drivers/usb/dwc3/dwc3-pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * dwc3-pci.c - PCI Specific glue layer
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/slab.h>
  14 #include <linux/pci.h>
  15 #include <linux/workqueue.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/gpio/consumer.h>
  19 #include <linux/gpio/machine.h>
  20 #include <linux/acpi.h>
  21 #include <linux/delay.h>
  22
  23 #define PCI_DEVICE_ID_INTEL_BYT                 0x0f37
  24 #define PCI_DEVICE_ID_INTEL_MRFLD               0x119e
  25 #define PCI_DEVICE_ID_INTEL_BSW                 0x22b7
  26 #define PCI_DEVICE_ID_INTEL_SPTLP               0x9d30
  27 #define PCI_DEVICE_ID_INTEL_SPTH                0xa130
  28 #define PCI_DEVICE_ID_INTEL_BXT                 0x0aaa
  29 #define PCI_DEVICE_ID_INTEL_BXT_M               0x1aaa
  30 #define PCI_DEVICE_ID_INTEL_APL                 0x5aaa
  31 #define PCI_DEVICE_ID_INTEL_KBP                 0xa2b0
  32 #define PCI_DEVICE_ID_INTEL_CMLLP               0x02ee
  33 #define PCI_DEVICE_ID_INTEL_CMLH                0x06ee
  34 #define PCI_DEVICE_ID_INTEL_GLK                 0x31aa
  35 #define PCI_DEVICE_ID_INTEL_CNPLP               0x9dee
  36 #define PCI_DEVICE_ID_INTEL_CNPH                0xa36e
  37 #define PCI_DEVICE_ID_INTEL_CNPV                0xa3b0
  38 #define PCI_DEVICE_ID_INTEL_ICLLP               0x34ee
  39 #define PCI_DEVICE_ID_INTEL_EHL                 0x4b7e
  40 #define PCI_DEVICE_ID_INTEL_TGPLP               0xa0ee
  41 #define PCI_DEVICE_ID_INTEL_TGPH                0x43ee
  42 #define PCI_DEVICE_ID_INTEL_JSP                 0x4dee
  43 #define PCI_DEVICE_ID_INTEL_ADLP                0x51ee
  44 #define PCI_DEVICE_ID_INTEL_ADLM                0x54ee
  45 #define PCI_DEVICE_ID_INTEL_ADLS                0x7ae1
  46 #define PCI_DEVICE_ID_INTEL_RPL                 0x460e
  47 #define PCI_DEVICE_ID_INTEL_RPLS                0x7a61
  48 #define PCI_DEVICE_ID_INTEL_MTLP                0x7ec1
  49 #define PCI_DEVICE_ID_INTEL_MTL                 0x7e7e
  50 #define PCI_DEVICE_ID_INTEL_TGL                 0x9a15
  51 #define PCI_DEVICE_ID_AMD_MR                    0x163a
  52
  53 #define PCI_INTEL_BXT_DSM_GUID          "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"
  54 #define PCI_INTEL_BXT_FUNC_PMU_PWR      4
  55 #define PCI_INTEL_BXT_STATE_D0          0
  56 #define PCI_INTEL_BXT_STATE_D3          3
  57
  58 #define GP_RWBAR                        1
  59 #define GP_RWREG1                       0xa0
  60 #define GP_RWREG1_ULPI_REFCLK_DISABLE   (1 << 17)
  61
  62 /**
  63  * struct dwc3_pci - Driver private structure
  64  * @dwc3: child dwc3 platform_device
  65  * @pci: our link to PCI bus
  66  * @guid: _DSM GUID
  67  * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM
  68  * @wakeup_work: work for asynchronous resume
  69  */
  70 struct dwc3_pci {
  71         struct platform_device *dwc3;
  72         struct pci_dev *pci;
  73
  74         guid_t guid;
  75
  76         unsigned int has_dsm_for_pm:1;
  77         struct work_struct wakeup_work;
  78 };
  79
  80 static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
  81 static const struct acpi_gpio_params cs_gpios = { 1, 0, false };
  82
  83 static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
  84         { "reset-gpios", &reset_gpios, 1 },
  85         { "cs-gpios", &cs_gpios, 1 },
  86         { },
  87 };
  88
  89 static struct gpiod_lookup_table platform_bytcr_gpios = {
  90         .dev_id         = "0000:00:16.0",
  91         .table          = {
  92                 GPIO_LOOKUP("INT33FC:00", 54, "cs", GPIO_ACTIVE_HIGH),
  93                 GPIO_LOOKUP("INT33FC:02", 14, "reset", GPIO_ACTIVE_HIGH),
  94                 {}
  95         },
  96 };
  97
  98 static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci)
  99 {
 100         void __iomem    *reg;
 101         u32             value;
 102
 103         reg = pcim_iomap(pci, GP_RWBAR, 0);
 104         if (!reg)
 105                 return -ENOMEM;
 106
 107         value = readl(reg + GP_RWREG1);
 108         if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE))
 109                 goto unmap; /* ULPI refclk already enabled */
 110
 111         value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE;
 112         writel(value, reg + GP_RWREG1);
 113         /* This comes from the Intel Android x86 tree w/o any explanation */
 114         msleep(100);
 115 unmap:
 116         pcim_iounmap(pci, reg);
 117         return 0;
 118 }
 119
 120 static const struct property_entry dwc3_pci_intel_properties[] = {
 121         PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
 122         PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
 123         {}
 124 };
 125
 126 static const struct property_entry dwc3_pci_intel_byt_properties[] = {
 127         PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
 128         PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
 129         PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
 130         {}
 131 };
 132
 133 static const struct property_entry dwc3_pci_mrfld_properties[] = {
 134         PROPERTY_ENTRY_STRING("dr_mode", "otg"),
 135         PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"),
 136         PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
 137         PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
 138         PROPERTY_ENTRY_BOOL("snps,usb2-gadget-lpm-disable"),
 139         PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
 140         {}
 141 };
 142
 143 static const struct property_entry dwc3_pci_amd_properties[] = {
 144         PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
 145         PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
 146         PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
 147         PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
 148         PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
 149         PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
 150         PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
 151         PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
 152         PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
 153         PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
 154         PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
 155         /* FIXME these quirks should be removed when AMD NL tapes out */
 156         PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
 157         PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
 158         PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
 159         PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
 160         {}
 161 };
 162
 163 static const struct property_entry dwc3_pci_mr_properties[] = {
 164         PROPERTY_ENTRY_STRING("dr_mode", "otg"),
 165         PROPERTY_ENTRY_BOOL("usb-role-switch"),
 166         PROPERTY_ENTRY_STRING("role-switch-default-mode", "host"),
 167         PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
 168         {}
 169 };
 170
 171 static const struct software_node dwc3_pci_intel_swnode = {
 172         .properties = dwc3_pci_intel_properties,
 173 };
 174
 175 static const struct software_node dwc3_pci_intel_byt_swnode = {
 176         .properties = dwc3_pci_intel_byt_properties,
 177 };
 178
 179 static const struct software_node dwc3_pci_intel_mrfld_swnode = {
 180         .properties = dwc3_pci_mrfld_properties,
 181 };
 182
 183 static const struct software_node dwc3_pci_amd_swnode = {
 184         .properties = dwc3_pci_amd_properties,
 185 };
 186
 187 static const struct software_node dwc3_pci_amd_mr_swnode = {
 188         .properties = dwc3_pci_mr_properties,
 189 };
 190
 191 static int dwc3_pci_quirks(struct dwc3_pci *dwc,
 192                            const struct software_node *swnode)
 193 {
 194         struct pci_dev                  *pdev = dwc->pci;
 195
 196         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 197                 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT ||
 198                     pdev->device == PCI_DEVICE_ID_INTEL_BXT_M ||
 199                     pdev->device == PCI_DEVICE_ID_INTEL_EHL) {
 200                         guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid);
 201                         dwc->has_dsm_for_pm = true;
 202                 }
 203
 204                 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
 205                         struct gpio_desc *gpio;
 206                         int ret;
 207
 208                         /* On BYT the FW does not always enable the refclock */
 209                         ret = dwc3_byt_enable_ulpi_refclock(pdev);
 210                         if (ret)
 211                                 return ret;
 212
 213                         ret = devm_acpi_dev_add_driver_gpios(&pdev->dev,
 214                                         acpi_dwc3_byt_gpios);
 215                         if (ret)
 216                                 dev_dbg(&pdev->dev, "failed to add mapping table\n");
 217
 218                         /*
 219                          * A lot of BYT devices lack ACPI resource entries for
 220                          * the GPIOs, add a fallback mapping to the reference
 221                          * design GPIOs which all boards seem to use.
 222                          */
 223                         gpiod_add_lookup_table(&platform_bytcr_gpios);
 224
 225                         /*
 226                          * These GPIOs will turn on the USB2 PHY. Note that we have to
 227                          * put the gpio descriptors again here because the phy driver
 228                          * might want to grab them, too.
 229                          */
 230                         gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW);
 231                         if (IS_ERR(gpio))
 232                                 return PTR_ERR(gpio);
 233
 234                         gpiod_set_value_cansleep(gpio, 1);
 235                         gpiod_put(gpio);
 236
 237                         gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
 238                         if (IS_ERR(gpio))
 239                                 return PTR_ERR(gpio);
 240
 241                         if (gpio) {
 242                                 gpiod_set_value_cansleep(gpio, 1);
 243                                 gpiod_put(gpio);
 244                                 usleep_range(10000, 11000);
 245                         }
 246                 }
 247         }
 248
 249         return device_add_software_node(&dwc->dwc3->dev, swnode);
 250 }
 251
 252 #ifdef CONFIG_PM
 253 static void dwc3_pci_resume_work(struct work_struct *work)
 254 {
 255         struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work);
 256         struct platform_device *dwc3 = dwc->dwc3;
 257         int ret;
 258
 259         ret = pm_runtime_get_sync(&dwc3->dev);
 260         if (ret < 0) {
 261                 pm_runtime_put_sync_autosuspend(&dwc3->dev);
 262                 return;
 263         }
 264
 265         pm_runtime_mark_last_busy(&dwc3->dev);
 266         pm_runtime_put_sync_autosuspend(&dwc3->dev);
 267 }
 268 #endif
 269
 270 static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
 271 {
 272         struct dwc3_pci         *dwc;
 273         struct resource         res[2];
 274         int                     ret;
 275         struct device           *dev = &pci->dev;
 276
 277         ret = pcim_enable_device(pci);
 278         if (ret) {
 279                 dev_err(dev, "failed to enable pci device\n");
 280                 return -ENODEV;
 281         }
 282
 283         pci_set_master(pci);
 284
 285         dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
 286         if (!dwc)
 287                 return -ENOMEM;
 288
 289         dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
 290         if (!dwc->dwc3)
 291                 return -ENOMEM;
 292
 293         memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
 294
 295         res[0].start    = pci_resource_start(pci, 0);
 296         res[0].end      = pci_resource_end(pci, 0);
 297         res[0].name     = "dwc_usb3";
 298         res[0].flags    = IORESOURCE_MEM;
 299
 300         res[1].start    = pci->irq;
 301         res[1].name     = "dwc_usb3";
 302         res[1].flags    = IORESOURCE_IRQ;
 303
 304         ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res));
 305         if (ret) {
 306                 dev_err(dev, "couldn't add resources to dwc3 device\n");
 307                 goto err;
 308         }
 309
 310         dwc->pci = pci;
 311         dwc->dwc3->dev.parent = dev;
 312         ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev));
 313
 314         ret = dwc3_pci_quirks(dwc, (void *)id->driver_data);
 315         if (ret)
 316                 goto err;
 317
 318         ret = platform_device_add(dwc->dwc3);
 319         if (ret) {
 320                 dev_err(dev, "failed to register dwc3 device\n");
 321                 goto err;
 322         }
 323
 324         device_init_wakeup(dev, true);
 325         pci_set_drvdata(pci, dwc);
 326         pm_runtime_put(dev);
 327 #ifdef CONFIG_PM
 328         INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work);
 329 #endif
 330
 331         return 0;
 332 err:
 333         device_remove_software_node(&dwc->dwc3->dev);
 334         platform_device_put(dwc->dwc3);
 335         return ret;
 336 }
 337
 338 static void dwc3_pci_remove(struct pci_dev *pci)
 339 {
 340         struct dwc3_pci         *dwc = pci_get_drvdata(pci);
 341         struct pci_dev          *pdev = dwc->pci;
 342
 343         if (pdev->device == PCI_DEVICE_ID_INTEL_BYT)
 344                 gpiod_remove_lookup_table(&platform_bytcr_gpios);
 345 #ifdef CONFIG_PM
 346         cancel_work_sync(&dwc->wakeup_work);
 347 #endif
 348         device_init_wakeup(&pci->dev, false);
 349         pm_runtime_get(&pci->dev);
 350         device_remove_software_node(&dwc->dwc3->dev);
 351         platform_device_unregister(dwc->dwc3);
 352 }
 353
 354 static const struct pci_device_id dwc3_pci_id_table[] = {
 355         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW),
 356           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 357
 358         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT),
 359           (kernel_ulong_t) &dwc3_pci_intel_byt_swnode, },
 360
 361         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD),
 362           (kernel_ulong_t) &dwc3_pci_intel_mrfld_swnode, },
 363
 364         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLLP),
 365           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 366
 367         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLH),
 368           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 369
 370         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP),
 371           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 372
 373         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH),
 374           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 375
 376         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT),
 377           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 378
 379         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M),
 380           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 381
 382         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL),
 383           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 384
 385         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP),
 386           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 387
 388         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK),
 389           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 390
 391         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP),
 392           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 393
 394         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH),
 395           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 396
 397         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPV),
 398           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 399
 400         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP),
 401           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 402
 403         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_EHL),
 404           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 405
 406         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPLP),
 407           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 408
 409         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPH),
 410           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 411
 412         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_JSP),
 413           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 414
 415         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLP),
 416           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 417
 418         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLM),
 419           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 420
 421         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLS),
 422           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 423
 424         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPL),
 425           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 426
 427         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPLS),
 428           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 429
 430         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTLP),
 431           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 432
 433         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL),
 434           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 435
 436         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL),
 437           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 438
 439         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB),
 440           (kernel_ulong_t) &dwc3_pci_amd_swnode, },
 441
 442         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_MR),
 443           (kernel_ulong_t)&dwc3_pci_amd_mr_swnode, },
 444
 445         {  }    /* Terminating Entry */
 446 };
 447 MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
 448
 449 #if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP)
 450 static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param)
 451 {
 452         union acpi_object *obj;
 453         union acpi_object tmp;
 454         union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);
 455
 456         if (!dwc->has_dsm_for_pm)
 457                 return 0;
 458
 459         tmp.type = ACPI_TYPE_INTEGER;
 460         tmp.integer.value = param;
 461
 462         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid,
 463                         1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4);
 464         if (!obj) {
 465                 dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n");
 466                 return -EIO;
 467         }
 468
 469         ACPI_FREE(obj);
 470
 471         return 0;
 472 }
 473 #endif /* CONFIG_PM || CONFIG_PM_SLEEP */
 474
 475 #ifdef CONFIG_PM
 476 static int dwc3_pci_runtime_suspend(struct device *dev)
 477 {
 478         struct dwc3_pci         *dwc = dev_get_drvdata(dev);
 479
 480         if (device_can_wakeup(dev))
 481                 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
 482
 483         return -EBUSY;
 484 }
 485
 486 static int dwc3_pci_runtime_resume(struct device *dev)
 487 {
 488         struct dwc3_pci         *dwc = dev_get_drvdata(dev);
 489         int                     ret;
 490
 491         ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
 492         if (ret)
 493                 return ret;
 494
 495         queue_work(pm_wq, &dwc->wakeup_work);
 496
 497         return 0;
 498 }
 499 #endif /* CONFIG_PM */
 500
 501 #ifdef CONFIG_PM_SLEEP
 502 static int dwc3_pci_suspend(struct device *dev)
 503 {
 504         struct dwc3_pci         *dwc = dev_get_drvdata(dev);
 505
 506         return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
 507 }
 508
 509 static int dwc3_pci_resume(struct device *dev)
 510 {
 511         struct dwc3_pci         *dwc = dev_get_drvdata(dev);
 512
 513         return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
 514 }
 515 #endif /* CONFIG_PM_SLEEP */
 516
 517 static const struct dev_pm_ops dwc3_pci_dev_pm_ops = {
 518         SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume)
 519         SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume,
 520                 NULL)
 521 };
 522
 523 static struct pci_driver dwc3_pci_driver = {
 524         .name           = "dwc3-pci",
 525         .id_table       = dwc3_pci_id_table,
 526         .probe          = dwc3_pci_probe,
 527         .remove         = dwc3_pci_remove,
 528         .driver         = {
 529                 .pm     = &dwc3_pci_dev_pm_ops,
 530         }
 531 };
 532
 533 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
 534 MODULE_LICENSE("GPL v2");
 535 MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
 536
 537 module_pci_driver(dwc3_pci_driver);