2 * dwc3-st.c Support for dwc3 platform devices on ST Microelectronics platforms
4 * This is a small driver for the dwc3 to provide the glue logic
5 * to configure the controller. Tested on STi platforms.
7 * Copyright (C) 2014 Stmicroelectronics
9 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
10 * Contributors: Aymen Bouattay <aymen.bouattay@st.com>
11 * Peter Griffin <peter.griffin@linaro.org>
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * Inspired by dwc3-omap.c and dwc3-exynos.c.
21 #include <linux/delay.h>
22 #include <linux/interrupt.h>
24 #include <linux/ioport.h>
25 #include <linux/kernel.h>
26 #include <linux/mfd/syscon.h>
27 #include <linux/module.h>
29 #include <linux/of_platform.h>
30 #include <linux/platform_device.h>
31 #include <linux/slab.h>
32 #include <linux/regmap.h>
33 #include <linux/reset.h>
34 #include <linux/usb/of.h>
40 #define CLKRST_CTRL 0x00
41 #define AUX_CLK_EN BIT(0)
42 #define SW_PIPEW_RESET_N BIT(4)
43 #define EXT_CFG_RESET_N BIT(8)
45 * 1'b0 : The host controller complies with the xHCI revision 0.96
46 * 1'b1 : The host controller complies with the xHCI revision 1.0
48 #define XHCI_REVISION BIT(12)
50 #define USB2_VBUS_MNGMNT_SEL1 0x2C
52 * For all fields in USB2_VBUS_MNGMNT_SEL1
53 * 2’b00 : Override value from Reg 0x30 is selected
54 * 2’b01 : utmiotg_<signal_name> from usb3_top is selected
55 * 2’b10 : pipew_<signal_name> from PIPEW instance is selected
56 * 2’b11 : value is 1'b0
58 #define USB2_VBUS_REG30 0x0
59 #define USB2_VBUS_UTMIOTG 0x1
60 #define USB2_VBUS_PIPEW 0x2
61 #define USB2_VBUS_ZERO 0x3
63 #define SEL_OVERRIDE_VBUSVALID(n) (n << 0)
64 #define SEL_OVERRIDE_POWERPRESENT(n) (n << 4)
65 #define SEL_OVERRIDE_BVALID(n) (n << 8)
67 /* Static DRD configuration */
68 #define USB3_CONTROL_MASK 0xf77
70 #define USB3_DEVICE_NOT_HOST BIT(0)
71 #define USB3_FORCE_VBUSVALID BIT(1)
72 #define USB3_DELAY_VBUSVALID BIT(2)
73 #define USB3_SEL_FORCE_OPMODE BIT(4)
74 #define USB3_FORCE_OPMODE(n) (n << 5)
75 #define USB3_SEL_FORCE_DPPULLDOWN2 BIT(8)
76 #define USB3_FORCE_DPPULLDOWN2 BIT(9)
77 #define USB3_SEL_FORCE_DMPULLDOWN2 BIT(10)
78 #define USB3_FORCE_DMPULLDOWN2 BIT(11)
81 * struct st_dwc3 - dwc3-st driver private structure
82 * @dev: device pointer
83 * @glue_base: ioaddr for the glue registers
84 * @regmap: regmap pointer for getting syscfg
85 * @syscfg_reg_off: usb syscfg control offset
86 * @dr_mode: drd static host/device config
87 * @rstc_pwrdn: rest controller for powerdown signal
88 * @rstc_rst: reset controller for softreset signal
93 void __iomem
*glue_base
;
94 struct regmap
*regmap
;
96 enum usb_dr_mode dr_mode
;
97 struct reset_control
*rstc_pwrdn
;
98 struct reset_control
*rstc_rst
;
101 static inline u32
st_dwc3_readl(void __iomem
*base
, u32 offset
)
103 return readl_relaxed(base
+ offset
);
106 static inline void st_dwc3_writel(void __iomem
*base
, u32 offset
, u32 value
)
108 writel_relaxed(value
, base
+ offset
);
112 * st_dwc3_drd_init: program the port
113 * @dwc3_data: driver private structure
114 * Description: this function is to program the port as either host or device
115 * according to the static configuration passed from devicetree.
116 * OTG and dual role are not yet supported!
118 static int st_dwc3_drd_init(struct st_dwc3
*dwc3_data
)
123 err
= regmap_read(dwc3_data
->regmap
, dwc3_data
->syscfg_reg_off
, &val
);
127 val
&= USB3_CONTROL_MASK
;
129 switch (dwc3_data
->dr_mode
) {
130 case USB_DR_MODE_PERIPHERAL
:
132 val
&= ~(USB3_FORCE_VBUSVALID
| USB3_DELAY_VBUSVALID
133 | USB3_SEL_FORCE_OPMODE
| USB3_FORCE_OPMODE(0x3)
134 | USB3_SEL_FORCE_DPPULLDOWN2
| USB3_FORCE_DPPULLDOWN2
135 | USB3_SEL_FORCE_DMPULLDOWN2
| USB3_FORCE_DMPULLDOWN2
);
137 val
|= USB3_DEVICE_NOT_HOST
;
140 case USB_DR_MODE_HOST
:
142 val
&= ~(USB3_DEVICE_NOT_HOST
| USB3_FORCE_VBUSVALID
143 | USB3_SEL_FORCE_OPMODE
| USB3_FORCE_OPMODE(0x3)
144 | USB3_SEL_FORCE_DPPULLDOWN2
| USB3_FORCE_DPPULLDOWN2
145 | USB3_SEL_FORCE_DMPULLDOWN2
| USB3_FORCE_DMPULLDOWN2
);
148 * USB3_DELAY_VBUSVALID is ANDed with USB_C_VBUSVALID. Thus,
149 * when set to ‘0‘, it can delay the arrival of VBUSVALID
150 * information to VBUSVLDEXT2 input of the pico PHY.
151 * We don't want to do that so we set the bit to '1'.
154 val
|= USB3_DELAY_VBUSVALID
;
158 dev_err(dwc3_data
->dev
, "Unsupported mode of operation %d\n",
163 return regmap_write(dwc3_data
->regmap
, dwc3_data
->syscfg_reg_off
, val
);
167 * st_dwc3_init: init the controller via glue logic
168 * @dwc3_data: driver private structure
170 static void st_dwc3_init(struct st_dwc3
*dwc3_data
)
172 u32 reg
= st_dwc3_readl(dwc3_data
->glue_base
, CLKRST_CTRL
);
174 reg
|= AUX_CLK_EN
| EXT_CFG_RESET_N
| XHCI_REVISION
;
175 reg
&= ~SW_PIPEW_RESET_N
;
176 st_dwc3_writel(dwc3_data
->glue_base
, CLKRST_CTRL
, reg
);
178 /* configure mux for vbus, powerpresent and bvalid signals */
179 reg
= st_dwc3_readl(dwc3_data
->glue_base
, USB2_VBUS_MNGMNT_SEL1
);
181 reg
|= SEL_OVERRIDE_VBUSVALID(USB2_VBUS_UTMIOTG
) |
182 SEL_OVERRIDE_POWERPRESENT(USB2_VBUS_UTMIOTG
) |
183 SEL_OVERRIDE_BVALID(USB2_VBUS_UTMIOTG
);
185 st_dwc3_writel(dwc3_data
->glue_base
, USB2_VBUS_MNGMNT_SEL1
, reg
);
187 reg
= st_dwc3_readl(dwc3_data
->glue_base
, CLKRST_CTRL
);
188 reg
|= SW_PIPEW_RESET_N
;
189 st_dwc3_writel(dwc3_data
->glue_base
, CLKRST_CTRL
, reg
);
192 static int st_dwc3_probe(struct platform_device
*pdev
)
194 struct st_dwc3
*dwc3_data
;
195 struct resource
*res
;
196 struct device
*dev
= &pdev
->dev
;
197 struct device_node
*node
= dev
->of_node
, *child
;
198 struct regmap
*regmap
;
201 dwc3_data
= devm_kzalloc(dev
, sizeof(*dwc3_data
), GFP_KERNEL
);
205 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "reg-glue");
206 dwc3_data
->glue_base
= devm_ioremap_resource(dev
, res
);
207 if (IS_ERR(dwc3_data
->glue_base
))
208 return PTR_ERR(dwc3_data
->glue_base
);
210 regmap
= syscon_regmap_lookup_by_phandle(node
, "st,syscfg");
212 return PTR_ERR(regmap
);
214 dma_set_coherent_mask(dev
, dev
->coherent_dma_mask
);
215 dwc3_data
->dev
= dev
;
216 dwc3_data
->regmap
= regmap
;
218 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "syscfg-reg");
221 goto undo_platform_dev_alloc
;
224 dwc3_data
->syscfg_reg_off
= res
->start
;
226 dev_vdbg(&pdev
->dev
, "glue-logic addr 0x%p, syscfg-reg offset 0x%x\n",
227 dwc3_data
->glue_base
, dwc3_data
->syscfg_reg_off
);
229 dwc3_data
->rstc_pwrdn
= devm_reset_control_get(dev
, "powerdown");
230 if (IS_ERR(dwc3_data
->rstc_pwrdn
)) {
231 dev_err(&pdev
->dev
, "could not get power controller\n");
232 ret
= PTR_ERR(dwc3_data
->rstc_pwrdn
);
233 goto undo_platform_dev_alloc
;
236 /* Manage PowerDown */
237 reset_control_deassert(dwc3_data
->rstc_pwrdn
);
239 dwc3_data
->rstc_rst
= devm_reset_control_get(dev
, "softreset");
240 if (IS_ERR(dwc3_data
->rstc_rst
)) {
241 dev_err(&pdev
->dev
, "could not get reset controller\n");
242 ret
= PTR_ERR(dwc3_data
->rstc_rst
);
246 /* Manage SoftReset */
247 reset_control_deassert(dwc3_data
->rstc_rst
);
249 child
= of_get_child_by_name(node
, "dwc3");
251 dev_err(&pdev
->dev
, "failed to find dwc3 core node\n");
256 dwc3_data
->dr_mode
= of_usb_get_dr_mode(child
);
258 /* Allocate and initialize the core */
259 ret
= of_platform_populate(node
, NULL
, NULL
, dev
);
261 dev_err(dev
, "failed to add dwc3 core\n");
266 * Configure the USB port as device or host according to the static
267 * configuration passed from DT.
268 * DRD is the only mode currently supported so this will be enhanced
269 * as soon as OTG is available.
271 ret
= st_dwc3_drd_init(dwc3_data
);
273 dev_err(dev
, "drd initialisation failed\n");
277 /* ST glue logic init */
278 st_dwc3_init(dwc3_data
);
280 platform_set_drvdata(pdev
, dwc3_data
);
284 reset_control_assert(dwc3_data
->rstc_rst
);
286 reset_control_assert(dwc3_data
->rstc_pwrdn
);
287 undo_platform_dev_alloc
:
288 platform_device_put(pdev
);
292 static int st_dwc3_remove(struct platform_device
*pdev
)
294 struct st_dwc3
*dwc3_data
= platform_get_drvdata(pdev
);
296 of_platform_depopulate(&pdev
->dev
);
298 reset_control_assert(dwc3_data
->rstc_pwrdn
);
299 reset_control_assert(dwc3_data
->rstc_rst
);
304 #ifdef CONFIG_PM_SLEEP
305 static int st_dwc3_suspend(struct device
*dev
)
307 struct st_dwc3
*dwc3_data
= dev_get_drvdata(dev
);
309 reset_control_assert(dwc3_data
->rstc_pwrdn
);
310 reset_control_assert(dwc3_data
->rstc_rst
);
312 pinctrl_pm_select_sleep_state(dev
);
317 static int st_dwc3_resume(struct device
*dev
)
319 struct st_dwc3
*dwc3_data
= dev_get_drvdata(dev
);
322 pinctrl_pm_select_default_state(dev
);
324 reset_control_deassert(dwc3_data
->rstc_pwrdn
);
325 reset_control_deassert(dwc3_data
->rstc_rst
);
327 ret
= st_dwc3_drd_init(dwc3_data
);
329 dev_err(dev
, "drd initialisation failed\n");
333 /* ST glue logic init */
334 st_dwc3_init(dwc3_data
);
338 #endif /* CONFIG_PM_SLEEP */
340 static SIMPLE_DEV_PM_OPS(st_dwc3_dev_pm_ops
, st_dwc3_suspend
, st_dwc3_resume
);
342 static const struct of_device_id st_dwc3_match
[] = {
343 { .compatible
= "st,stih407-dwc3" },
347 MODULE_DEVICE_TABLE(of
, st_dwc3_match
);
349 static struct platform_driver st_dwc3_driver
= {
350 .probe
= st_dwc3_probe
,
351 .remove
= st_dwc3_remove
,
353 .name
= "usb-st-dwc3",
354 .of_match_table
= st_dwc3_match
,
355 .pm
= &st_dwc3_dev_pm_ops
,
359 module_platform_driver(st_dwc3_driver
);
361 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
362 MODULE_DESCRIPTION("DesignWare USB3 STi Glue Layer");
363 MODULE_LICENSE("GPL v2");