1 // SPDX-License-Identifier: GPL-2.0
3 * dwc3-xilinx.c - Xilinx DWC3 controller specific glue driver
5 * Authors: Manish Narani <manish.narani@xilinx.com>
6 * Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
9 #include <linux/module.h>
10 #include <linux/kernel.h>
11 #include <linux/slab.h>
12 #include <linux/clk.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/of_platform.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/reset.h>
19 #include <linux/of_address.h>
20 #include <linux/delay.h>
21 #include <linux/firmware/xlnx-zynqmp.h>
24 #include <linux/phy/phy.h>
26 /* USB phy reset mask register */
27 #define XLNX_USB_PHY_RST_EN 0x001C
28 #define XLNX_PHY_RST_MASK 0x1
30 /* Xilinx USB 3.0 IP Register */
31 #define XLNX_USB_TRAFFIC_ROUTE_CONFIG 0x005C
32 #define XLNX_USB_TRAFFIC_ROUTE_FPD 0x1
34 /* Versal USB Reset ID */
35 #define VERSAL_USB_RESET_ID 0xC104036
37 #define XLNX_USB_FPD_PIPE_CLK 0x7c
38 #define PIPE_CLK_DESELECT 1
39 #define PIPE_CLK_SELECT 0
40 #define XLNX_USB_FPD_POWER_PRSNT 0x80
41 #define FPD_POWER_PRSNT_OPTION BIT(0)
45 struct clk_bulk_data
*clks
;
48 int (*pltfm_init
)(struct dwc3_xlnx
*data
);
51 static void dwc3_xlnx_mask_phy_rst(struct dwc3_xlnx
*priv_data
, bool mask
)
56 * Enable or disable ULPI PHY reset from USB Controller.
57 * This does not actually reset the phy, but just controls
58 * whether USB controller can or cannot reset ULPI PHY.
60 reg
= readl(priv_data
->regs
+ XLNX_USB_PHY_RST_EN
);
63 reg
&= ~XLNX_PHY_RST_MASK
;
65 reg
|= XLNX_PHY_RST_MASK
;
67 writel(reg
, priv_data
->regs
+ XLNX_USB_PHY_RST_EN
);
70 static int dwc3_xlnx_init_versal(struct dwc3_xlnx
*priv_data
)
72 struct device
*dev
= priv_data
->dev
;
75 dwc3_xlnx_mask_phy_rst(priv_data
, false);
77 /* Assert and De-assert reset */
78 ret
= zynqmp_pm_reset_assert(VERSAL_USB_RESET_ID
,
79 PM_RESET_ACTION_ASSERT
);
81 dev_err_probe(dev
, ret
, "failed to assert Reset\n");
85 ret
= zynqmp_pm_reset_assert(VERSAL_USB_RESET_ID
,
86 PM_RESET_ACTION_RELEASE
);
88 dev_err_probe(dev
, ret
, "failed to De-assert Reset\n");
92 dwc3_xlnx_mask_phy_rst(priv_data
, true);
97 static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx
*priv_data
)
99 struct device
*dev
= priv_data
->dev
;
100 struct reset_control
*crst
, *hibrst
, *apbrst
;
101 struct phy
*usb3_phy
;
105 usb3_phy
= devm_phy_optional_get(dev
, "usb3-phy");
106 if (IS_ERR(usb3_phy
)) {
107 ret
= PTR_ERR(usb3_phy
);
108 dev_err_probe(dev
, ret
,
109 "failed to get USB3 PHY\n");
114 * The following core resets are not required unless a USB3 PHY
115 * is used, and the subsequent register settings are not required
116 * unless a core reset is performed (they should be set properly
117 * by the first-stage boot loader, but may be reverted by a core
118 * reset). They may also break the configuration if USB3 is actually
119 * in use but the usb3-phy entry is missing from the device tree.
120 * Therefore, skip these operations in this case.
125 crst
= devm_reset_control_get_exclusive(dev
, "usb_crst");
128 dev_err_probe(dev
, ret
,
129 "failed to get core reset signal\n");
133 hibrst
= devm_reset_control_get_exclusive(dev
, "usb_hibrst");
134 if (IS_ERR(hibrst
)) {
135 ret
= PTR_ERR(hibrst
);
136 dev_err_probe(dev
, ret
,
137 "failed to get hibernation reset signal\n");
141 apbrst
= devm_reset_control_get_exclusive(dev
, "usb_apbrst");
142 if (IS_ERR(apbrst
)) {
143 ret
= PTR_ERR(apbrst
);
144 dev_err_probe(dev
, ret
,
145 "failed to get APB reset signal\n");
149 ret
= reset_control_assert(crst
);
151 dev_err(dev
, "Failed to assert core reset\n");
155 ret
= reset_control_assert(hibrst
);
157 dev_err(dev
, "Failed to assert hibernation reset\n");
161 ret
= reset_control_assert(apbrst
);
163 dev_err(dev
, "Failed to assert APB reset\n");
167 ret
= phy_init(usb3_phy
);
173 ret
= reset_control_deassert(apbrst
);
175 dev_err(dev
, "Failed to release APB reset\n");
179 /* Set PIPE Power Present signal in FPD Power Present Register*/
180 writel(FPD_POWER_PRSNT_OPTION
, priv_data
->regs
+ XLNX_USB_FPD_POWER_PRSNT
);
182 /* Set the PIPE Clock Select bit in FPD PIPE Clock register */
183 writel(PIPE_CLK_SELECT
, priv_data
->regs
+ XLNX_USB_FPD_PIPE_CLK
);
185 ret
= reset_control_deassert(crst
);
187 dev_err(dev
, "Failed to release core reset\n");
191 ret
= reset_control_deassert(hibrst
);
193 dev_err(dev
, "Failed to release hibernation reset\n");
197 ret
= phy_power_on(usb3_phy
);
205 * This routes the USB DMA traffic to go through FPD path instead
206 * of reaching DDR directly. This traffic routing is needed to
207 * make SMMU and CCI work with USB DMA.
209 if (of_dma_is_coherent(dev
->of_node
) || device_iommu_mapped(dev
)) {
210 reg
= readl(priv_data
->regs
+ XLNX_USB_TRAFFIC_ROUTE_CONFIG
);
211 reg
|= XLNX_USB_TRAFFIC_ROUTE_FPD
;
212 writel(reg
, priv_data
->regs
+ XLNX_USB_TRAFFIC_ROUTE_CONFIG
);
219 static const struct of_device_id dwc3_xlnx_of_match
[] = {
221 .compatible
= "xlnx,zynqmp-dwc3",
222 .data
= &dwc3_xlnx_init_zynqmp
,
225 .compatible
= "xlnx,versal-dwc3",
226 .data
= &dwc3_xlnx_init_versal
,
230 MODULE_DEVICE_TABLE(of
, dwc3_xlnx_of_match
);
232 static int dwc3_xlnx_probe(struct platform_device
*pdev
)
234 struct dwc3_xlnx
*priv_data
;
235 struct device
*dev
= &pdev
->dev
;
236 struct device_node
*np
= dev
->of_node
;
237 const struct of_device_id
*match
;
241 priv_data
= devm_kzalloc(dev
, sizeof(*priv_data
), GFP_KERNEL
);
245 regs
= devm_platform_ioremap_resource(pdev
, 0);
248 dev_err_probe(dev
, ret
, "failed to map registers\n");
252 match
= of_match_node(dwc3_xlnx_of_match
, pdev
->dev
.of_node
);
254 priv_data
->pltfm_init
= match
->data
;
255 priv_data
->regs
= regs
;
256 priv_data
->dev
= dev
;
258 platform_set_drvdata(pdev
, priv_data
);
260 ret
= devm_clk_bulk_get_all(priv_data
->dev
, &priv_data
->clks
);
264 priv_data
->num_clocks
= ret
;
266 ret
= clk_bulk_prepare_enable(priv_data
->num_clocks
, priv_data
->clks
);
270 ret
= priv_data
->pltfm_init(priv_data
);
274 ret
= of_platform_populate(np
, NULL
, NULL
, dev
);
278 pm_runtime_set_active(dev
);
279 pm_runtime_enable(dev
);
280 pm_suspend_ignore_children(dev
, false);
281 pm_runtime_get_sync(dev
);
286 clk_bulk_disable_unprepare(priv_data
->num_clocks
, priv_data
->clks
);
291 static int dwc3_xlnx_remove(struct platform_device
*pdev
)
293 struct dwc3_xlnx
*priv_data
= platform_get_drvdata(pdev
);
294 struct device
*dev
= &pdev
->dev
;
296 of_platform_depopulate(dev
);
298 clk_bulk_disable_unprepare(priv_data
->num_clocks
, priv_data
->clks
);
299 priv_data
->num_clocks
= 0;
301 pm_runtime_disable(dev
);
302 pm_runtime_put_noidle(dev
);
303 pm_runtime_set_suspended(dev
);
308 static int __maybe_unused
dwc3_xlnx_suspend_common(struct device
*dev
)
310 struct dwc3_xlnx
*priv_data
= dev_get_drvdata(dev
);
312 clk_bulk_disable(priv_data
->num_clocks
, priv_data
->clks
);
317 static int __maybe_unused
dwc3_xlnx_resume_common(struct device
*dev
)
319 struct dwc3_xlnx
*priv_data
= dev_get_drvdata(dev
);
321 return clk_bulk_enable(priv_data
->num_clocks
, priv_data
->clks
);
324 static int __maybe_unused
dwc3_xlnx_runtime_idle(struct device
*dev
)
326 pm_runtime_mark_last_busy(dev
);
327 pm_runtime_autosuspend(dev
);
332 static UNIVERSAL_DEV_PM_OPS(dwc3_xlnx_dev_pm_ops
, dwc3_xlnx_suspend_common
,
333 dwc3_xlnx_resume_common
, dwc3_xlnx_runtime_idle
);
335 static struct platform_driver dwc3_xlnx_driver
= {
336 .probe
= dwc3_xlnx_probe
,
337 .remove
= dwc3_xlnx_remove
,
339 .name
= "dwc3-xilinx",
340 .of_match_table
= dwc3_xlnx_of_match
,
341 .pm
= &dwc3_xlnx_dev_pm_ops
,
345 module_platform_driver(dwc3_xlnx_driver
);
347 MODULE_LICENSE("GPL v2");
348 MODULE_DESCRIPTION("Xilinx DWC3 controller specific glue driver");
349 MODULE_AUTHOR("Manish Narani <manish.narani@xilinx.com>");
350 MODULE_AUTHOR("Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>");