2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/slab.h>
21 #include <linux/spinlock.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/interrupt.h>
26 #include <linux/list.h>
27 #include <linux/dma-mapping.h>
29 #include <linux/usb/ch9.h>
30 #include <linux/usb/gadget.h>
31 #include <linux/usb/composite.h>
38 static void __dwc3_ep0_do_control_status(struct dwc3
*dwc
, struct dwc3_ep
*dep
);
39 static void __dwc3_ep0_do_control_data(struct dwc3
*dwc
,
40 struct dwc3_ep
*dep
, struct dwc3_request
*req
);
42 static int dwc3_ep0_start_trans(struct dwc3
*dwc
, u8 epnum
, dma_addr_t buf_dma
,
43 u32 len
, u32 type
, bool chain
)
45 struct dwc3_gadget_ep_cmd_params params
;
51 dep
= dwc
->eps
[epnum
];
52 if (dep
->flags
& DWC3_EP_BUSY
)
55 trb
= &dwc
->ep0_trb
[dep
->trb_enqueue
];
60 trb
->bpl
= lower_32_bits(buf_dma
);
61 trb
->bph
= upper_32_bits(buf_dma
);
65 trb
->ctrl
|= (DWC3_TRB_CTRL_HWO
66 | DWC3_TRB_CTRL_ISP_IMI
);
69 trb
->ctrl
|= DWC3_TRB_CTRL_CHN
;
71 trb
->ctrl
|= (DWC3_TRB_CTRL_IOC
77 memset(¶ms
, 0, sizeof(params
));
78 params
.param0
= upper_32_bits(dwc
->ep0_trb_addr
);
79 params
.param1
= lower_32_bits(dwc
->ep0_trb_addr
);
81 trace_dwc3_prepare_trb(dep
, trb
);
83 ret
= dwc3_send_gadget_ep_cmd(dep
, DWC3_DEPCMD_STARTTRANSFER
, ¶ms
);
87 dep
->flags
|= DWC3_EP_BUSY
;
88 dep
->resource_index
= dwc3_gadget_ep_get_transfer_index(dep
);
89 dwc
->ep0_next_event
= DWC3_EP0_COMPLETE
;
94 static int __dwc3_gadget_ep0_queue(struct dwc3_ep
*dep
,
95 struct dwc3_request
*req
)
97 struct dwc3
*dwc
= dep
->dwc
;
99 req
->request
.actual
= 0;
100 req
->request
.status
= -EINPROGRESS
;
101 req
->epnum
= dep
->number
;
103 list_add_tail(&req
->list
, &dep
->pending_list
);
106 * Gadget driver might not be quick enough to queue a request
107 * before we get a Transfer Not Ready event on this endpoint.
109 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
110 * flag is set, it's telling us that as soon as Gadget queues the
111 * required request, we should kick the transfer here because the
112 * IRQ we were waiting for is long gone.
114 if (dep
->flags
& DWC3_EP_PENDING_REQUEST
) {
117 direction
= !!(dep
->flags
& DWC3_EP0_DIR_IN
);
119 if (dwc
->ep0state
!= EP0_DATA_PHASE
) {
120 dev_WARN(dwc
->dev
, "Unexpected pending request\n");
124 __dwc3_ep0_do_control_data(dwc
, dwc
->eps
[direction
], req
);
126 dep
->flags
&= ~(DWC3_EP_PENDING_REQUEST
|
133 * In case gadget driver asked us to delay the STATUS phase,
136 if (dwc
->delayed_status
) {
139 direction
= !dwc
->ep0_expect_in
;
140 dwc
->delayed_status
= false;
141 usb_gadget_set_state(&dwc
->gadget
, USB_STATE_CONFIGURED
);
143 if (dwc
->ep0state
== EP0_STATUS_PHASE
)
144 __dwc3_ep0_do_control_status(dwc
, dwc
->eps
[direction
]);
150 * Unfortunately we have uncovered a limitation wrt the Data Phase.
152 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
153 * come before issueing Start Transfer command, but if we do, we will
154 * miss situations where the host starts another SETUP phase instead of
155 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
156 * Layer Compliance Suite.
158 * The problem surfaces due to the fact that in case of back-to-back
159 * SETUP packets there will be no XferNotReady(DATA) generated and we
160 * will be stuck waiting for XferNotReady(DATA) forever.
162 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
163 * it tells us to start Data Phase right away. It also mentions that if
164 * we receive a SETUP phase instead of the DATA phase, core will issue
165 * XferComplete for the DATA phase, before actually initiating it in
166 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
167 * can only be used to print some debugging logs, as the core expects
168 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
169 * just so it completes right away, without transferring anything and,
170 * only then, we can go back to the SETUP phase.
172 * Because of this scenario, SNPS decided to change the programming
173 * model of control transfers and support on-demand transfers only for
174 * the STATUS phase. To fix the issue we have now, we will always wait
175 * for gadget driver to queue the DATA phase's struct usb_request, then
176 * start it right away.
178 * If we're actually in a 2-stage transfer, we will wait for
179 * XferNotReady(STATUS).
181 if (dwc
->three_stage_setup
) {
184 direction
= dwc
->ep0_expect_in
;
185 dwc
->ep0state
= EP0_DATA_PHASE
;
187 __dwc3_ep0_do_control_data(dwc
, dwc
->eps
[direction
], req
);
189 dep
->flags
&= ~DWC3_EP0_DIR_IN
;
195 int dwc3_gadget_ep0_queue(struct usb_ep
*ep
, struct usb_request
*request
,
198 struct dwc3_request
*req
= to_dwc3_request(request
);
199 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
200 struct dwc3
*dwc
= dep
->dwc
;
206 spin_lock_irqsave(&dwc
->lock
, flags
);
207 if (!dep
->endpoint
.desc
) {
208 dev_err(dwc
->dev
, "%s: can't queue to disabled endpoint\n",
214 /* we share one TRB for ep0/1 */
215 if (!list_empty(&dep
->pending_list
)) {
220 ret
= __dwc3_gadget_ep0_queue(dep
, req
);
223 spin_unlock_irqrestore(&dwc
->lock
, flags
);
228 static void dwc3_ep0_stall_and_restart(struct dwc3
*dwc
)
232 /* reinitialize physical ep1 */
234 dep
->flags
= DWC3_EP_ENABLED
;
236 /* stall is always issued on EP0 */
238 __dwc3_gadget_ep_set_halt(dep
, 1, false);
239 dep
->flags
= DWC3_EP_ENABLED
;
240 dwc
->delayed_status
= false;
242 if (!list_empty(&dep
->pending_list
)) {
243 struct dwc3_request
*req
;
245 req
= next_request(&dep
->pending_list
);
246 dwc3_gadget_giveback(dep
, req
, -ECONNRESET
);
249 dwc
->ep0state
= EP0_SETUP_PHASE
;
250 dwc3_ep0_out_start(dwc
);
253 int __dwc3_gadget_ep0_set_halt(struct usb_ep
*ep
, int value
)
255 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
256 struct dwc3
*dwc
= dep
->dwc
;
258 dwc3_ep0_stall_and_restart(dwc
);
263 int dwc3_gadget_ep0_set_halt(struct usb_ep
*ep
, int value
)
265 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
266 struct dwc3
*dwc
= dep
->dwc
;
270 spin_lock_irqsave(&dwc
->lock
, flags
);
271 ret
= __dwc3_gadget_ep0_set_halt(ep
, value
);
272 spin_unlock_irqrestore(&dwc
->lock
, flags
);
277 void dwc3_ep0_out_start(struct dwc3
*dwc
)
281 complete(&dwc
->ep0_in_setup
);
283 ret
= dwc3_ep0_start_trans(dwc
, 0, dwc
->ctrl_req_addr
, 8,
284 DWC3_TRBCTL_CONTROL_SETUP
, false);
288 static struct dwc3_ep
*dwc3_wIndex_to_dep(struct dwc3
*dwc
, __le16 wIndex_le
)
291 u32 windex
= le16_to_cpu(wIndex_le
);
294 epnum
= (windex
& USB_ENDPOINT_NUMBER_MASK
) << 1;
295 if ((windex
& USB_ENDPOINT_DIR_MASK
) == USB_DIR_IN
)
298 dep
= dwc
->eps
[epnum
];
299 if (dep
->flags
& DWC3_EP_ENABLED
)
305 static void dwc3_ep0_status_cmpl(struct usb_ep
*ep
, struct usb_request
*req
)
311 static int dwc3_ep0_handle_status(struct dwc3
*dwc
,
312 struct usb_ctrlrequest
*ctrl
)
318 __le16
*response_pkt
;
320 recip
= ctrl
->bRequestType
& USB_RECIP_MASK
;
322 case USB_RECIP_DEVICE
:
324 * LTM will be set once we know how to set this in HW.
326 usb_status
|= dwc
->gadget
.is_selfpowered
;
328 if ((dwc
->speed
== DWC3_DSTS_SUPERSPEED
) ||
329 (dwc
->speed
== DWC3_DSTS_SUPERSPEED_PLUS
)) {
330 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
331 if (reg
& DWC3_DCTL_INITU1ENA
)
332 usb_status
|= 1 << USB_DEV_STAT_U1_ENABLED
;
333 if (reg
& DWC3_DCTL_INITU2ENA
)
334 usb_status
|= 1 << USB_DEV_STAT_U2_ENABLED
;
339 case USB_RECIP_INTERFACE
:
341 * Function Remote Wake Capable D0
342 * Function Remote Wakeup D1
346 case USB_RECIP_ENDPOINT
:
347 dep
= dwc3_wIndex_to_dep(dwc
, ctrl
->wIndex
);
351 if (dep
->flags
& DWC3_EP_STALL
)
352 usb_status
= 1 << USB_ENDPOINT_HALT
;
358 response_pkt
= (__le16
*) dwc
->setup_buf
;
359 *response_pkt
= cpu_to_le16(usb_status
);
362 dwc
->ep0_usb_req
.dep
= dep
;
363 dwc
->ep0_usb_req
.request
.length
= sizeof(*response_pkt
);
364 dwc
->ep0_usb_req
.request
.buf
= dwc
->setup_buf
;
365 dwc
->ep0_usb_req
.request
.complete
= dwc3_ep0_status_cmpl
;
367 return __dwc3_gadget_ep0_queue(dep
, &dwc
->ep0_usb_req
);
370 static int dwc3_ep0_handle_u1(struct dwc3
*dwc
, enum usb_device_state state
,
375 if (state
!= USB_STATE_CONFIGURED
)
377 if ((dwc
->speed
!= DWC3_DSTS_SUPERSPEED
) &&
378 (dwc
->speed
!= DWC3_DSTS_SUPERSPEED_PLUS
))
381 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
383 reg
|= DWC3_DCTL_INITU1ENA
;
385 reg
&= ~DWC3_DCTL_INITU1ENA
;
386 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
391 static int dwc3_ep0_handle_u2(struct dwc3
*dwc
, enum usb_device_state state
,
397 if (state
!= USB_STATE_CONFIGURED
)
399 if ((dwc
->speed
!= DWC3_DSTS_SUPERSPEED
) &&
400 (dwc
->speed
!= DWC3_DSTS_SUPERSPEED_PLUS
))
403 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
405 reg
|= DWC3_DCTL_INITU2ENA
;
407 reg
&= ~DWC3_DCTL_INITU2ENA
;
408 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
413 static int dwc3_ep0_handle_test(struct dwc3
*dwc
, enum usb_device_state state
,
416 if ((wIndex
& 0xff) != 0)
421 switch (wIndex
>> 8) {
427 dwc
->test_mode_nr
= wIndex
>> 8;
428 dwc
->test_mode
= true;
437 static int dwc3_ep0_handle_device(struct dwc3
*dwc
,
438 struct usb_ctrlrequest
*ctrl
, int set
)
440 enum usb_device_state state
;
445 wValue
= le16_to_cpu(ctrl
->wValue
);
446 wIndex
= le16_to_cpu(ctrl
->wIndex
);
447 state
= dwc
->gadget
.state
;
450 case USB_DEVICE_REMOTE_WAKEUP
:
453 * 9.4.1 says only only for SS, in AddressState only for
454 * default control pipe
456 case USB_DEVICE_U1_ENABLE
:
457 ret
= dwc3_ep0_handle_u1(dwc
, state
, set
);
459 case USB_DEVICE_U2_ENABLE
:
460 ret
= dwc3_ep0_handle_u2(dwc
, state
, set
);
462 case USB_DEVICE_LTM_ENABLE
:
465 case USB_DEVICE_TEST_MODE
:
466 ret
= dwc3_ep0_handle_test(dwc
, state
, wIndex
, set
);
475 static int dwc3_ep0_handle_intf(struct dwc3
*dwc
,
476 struct usb_ctrlrequest
*ctrl
, int set
)
478 enum usb_device_state state
;
483 wValue
= le16_to_cpu(ctrl
->wValue
);
484 wIndex
= le16_to_cpu(ctrl
->wIndex
);
485 state
= dwc
->gadget
.state
;
488 case USB_INTRF_FUNC_SUSPEND
:
490 * REVISIT: Ideally we would enable some low power mode here,
491 * however it's unclear what we should be doing here.
493 * For now, we're not doing anything, just making sure we return
494 * 0 so USB Command Verifier tests pass without any errors.
504 static int dwc3_ep0_handle_endpoint(struct dwc3
*dwc
,
505 struct usb_ctrlrequest
*ctrl
, int set
)
508 enum usb_device_state state
;
513 wValue
= le16_to_cpu(ctrl
->wValue
);
514 wIndex
= le16_to_cpu(ctrl
->wIndex
);
515 state
= dwc
->gadget
.state
;
518 case USB_ENDPOINT_HALT
:
519 dep
= dwc3_wIndex_to_dep(dwc
, ctrl
->wIndex
);
523 if (set
== 0 && (dep
->flags
& DWC3_EP_WEDGE
))
526 ret
= __dwc3_gadget_ep_set_halt(dep
, set
, true);
537 static int dwc3_ep0_handle_feature(struct dwc3
*dwc
,
538 struct usb_ctrlrequest
*ctrl
, int set
)
542 enum usb_device_state state
;
544 recip
= ctrl
->bRequestType
& USB_RECIP_MASK
;
545 state
= dwc
->gadget
.state
;
548 case USB_RECIP_DEVICE
:
549 ret
= dwc3_ep0_handle_device(dwc
, ctrl
, set
);
551 case USB_RECIP_INTERFACE
:
552 ret
= dwc3_ep0_handle_intf(dwc
, ctrl
, set
);
554 case USB_RECIP_ENDPOINT
:
555 ret
= dwc3_ep0_handle_endpoint(dwc
, ctrl
, set
);
564 static int dwc3_ep0_set_address(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
566 enum usb_device_state state
= dwc
->gadget
.state
;
570 addr
= le16_to_cpu(ctrl
->wValue
);
572 dev_err(dwc
->dev
, "invalid device address %d\n", addr
);
576 if (state
== USB_STATE_CONFIGURED
) {
577 dev_err(dwc
->dev
, "can't SetAddress() from Configured State\n");
581 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
582 reg
&= ~(DWC3_DCFG_DEVADDR_MASK
);
583 reg
|= DWC3_DCFG_DEVADDR(addr
);
584 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
587 usb_gadget_set_state(&dwc
->gadget
, USB_STATE_ADDRESS
);
589 usb_gadget_set_state(&dwc
->gadget
, USB_STATE_DEFAULT
);
594 static int dwc3_ep0_delegate_req(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
598 spin_unlock(&dwc
->lock
);
599 ret
= dwc
->gadget_driver
->setup(&dwc
->gadget
, ctrl
);
600 spin_lock(&dwc
->lock
);
604 static int dwc3_ep0_set_config(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
606 enum usb_device_state state
= dwc
->gadget
.state
;
611 cfg
= le16_to_cpu(ctrl
->wValue
);
614 case USB_STATE_DEFAULT
:
617 case USB_STATE_ADDRESS
:
618 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
619 /* if the cfg matches and the cfg is non zero */
620 if (cfg
&& (!ret
|| (ret
== USB_GADGET_DELAYED_STATUS
))) {
623 * only change state if set_config has already
624 * been processed. If gadget driver returns
625 * USB_GADGET_DELAYED_STATUS, we will wait
626 * to change the state on the next usb_ep_queue()
629 usb_gadget_set_state(&dwc
->gadget
,
630 USB_STATE_CONFIGURED
);
633 * Enable transition to U1/U2 state when
634 * nothing is pending from application.
636 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
637 reg
|= (DWC3_DCTL_ACCEPTU1ENA
| DWC3_DCTL_ACCEPTU2ENA
);
638 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
642 case USB_STATE_CONFIGURED
:
643 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
645 usb_gadget_set_state(&dwc
->gadget
,
654 static void dwc3_ep0_set_sel_cmpl(struct usb_ep
*ep
, struct usb_request
*req
)
656 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
657 struct dwc3
*dwc
= dep
->dwc
;
671 memcpy(&timing
, req
->buf
, sizeof(timing
));
673 dwc
->u1sel
= timing
.u1sel
;
674 dwc
->u1pel
= timing
.u1pel
;
675 dwc
->u2sel
= le16_to_cpu(timing
.u2sel
);
676 dwc
->u2pel
= le16_to_cpu(timing
.u2pel
);
678 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
679 if (reg
& DWC3_DCTL_INITU2ENA
)
681 if (reg
& DWC3_DCTL_INITU1ENA
)
685 * According to Synopsys Databook, if parameter is
686 * greater than 125, a value of zero should be
687 * programmed in the register.
692 /* now that we have the time, issue DGCMD Set Sel */
693 ret
= dwc3_send_gadget_generic_command(dwc
,
694 DWC3_DGCMD_SET_PERIODIC_PAR
, param
);
698 static int dwc3_ep0_set_sel(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
701 enum usb_device_state state
= dwc
->gadget
.state
;
705 if (state
== USB_STATE_DEFAULT
)
708 wValue
= le16_to_cpu(ctrl
->wValue
);
709 wLength
= le16_to_cpu(ctrl
->wLength
);
712 dev_err(dwc
->dev
, "Set SEL should be 6 bytes, got %d\n",
718 * To handle Set SEL we need to receive 6 bytes from Host. So let's
719 * queue a usb_request for 6 bytes.
721 * Remember, though, this controller can't handle non-wMaxPacketSize
722 * aligned transfers on the OUT direction, so we queue a request for
723 * wMaxPacketSize instead.
726 dwc
->ep0_usb_req
.dep
= dep
;
727 dwc
->ep0_usb_req
.request
.length
= dep
->endpoint
.maxpacket
;
728 dwc
->ep0_usb_req
.request
.buf
= dwc
->setup_buf
;
729 dwc
->ep0_usb_req
.request
.complete
= dwc3_ep0_set_sel_cmpl
;
731 return __dwc3_gadget_ep0_queue(dep
, &dwc
->ep0_usb_req
);
734 static int dwc3_ep0_set_isoch_delay(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
740 wValue
= le16_to_cpu(ctrl
->wValue
);
741 wLength
= le16_to_cpu(ctrl
->wLength
);
742 wIndex
= le16_to_cpu(ctrl
->wIndex
);
744 if (wIndex
|| wLength
)
748 * REVISIT It's unclear from Databook what to do with this
749 * value. For now, just cache it.
751 dwc
->isoch_delay
= wValue
;
756 static int dwc3_ep0_std_request(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
760 switch (ctrl
->bRequest
) {
761 case USB_REQ_GET_STATUS
:
762 ret
= dwc3_ep0_handle_status(dwc
, ctrl
);
764 case USB_REQ_CLEAR_FEATURE
:
765 ret
= dwc3_ep0_handle_feature(dwc
, ctrl
, 0);
767 case USB_REQ_SET_FEATURE
:
768 ret
= dwc3_ep0_handle_feature(dwc
, ctrl
, 1);
770 case USB_REQ_SET_ADDRESS
:
771 ret
= dwc3_ep0_set_address(dwc
, ctrl
);
773 case USB_REQ_SET_CONFIGURATION
:
774 ret
= dwc3_ep0_set_config(dwc
, ctrl
);
776 case USB_REQ_SET_SEL
:
777 ret
= dwc3_ep0_set_sel(dwc
, ctrl
);
779 case USB_REQ_SET_ISOCH_DELAY
:
780 ret
= dwc3_ep0_set_isoch_delay(dwc
, ctrl
);
783 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
790 static void dwc3_ep0_inspect_setup(struct dwc3
*dwc
,
791 const struct dwc3_event_depevt
*event
)
793 struct usb_ctrlrequest
*ctrl
= dwc
->ctrl_req
;
797 if (!dwc
->gadget_driver
)
800 trace_dwc3_ctrl_req(ctrl
);
802 len
= le16_to_cpu(ctrl
->wLength
);
804 dwc
->three_stage_setup
= false;
805 dwc
->ep0_expect_in
= false;
806 dwc
->ep0_next_event
= DWC3_EP0_NRDY_STATUS
;
808 dwc
->three_stage_setup
= true;
809 dwc
->ep0_expect_in
= !!(ctrl
->bRequestType
& USB_DIR_IN
);
810 dwc
->ep0_next_event
= DWC3_EP0_NRDY_DATA
;
813 if ((ctrl
->bRequestType
& USB_TYPE_MASK
) == USB_TYPE_STANDARD
)
814 ret
= dwc3_ep0_std_request(dwc
, ctrl
);
816 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
818 if (ret
== USB_GADGET_DELAYED_STATUS
)
819 dwc
->delayed_status
= true;
823 dwc3_ep0_stall_and_restart(dwc
);
826 static void dwc3_ep0_complete_data(struct dwc3
*dwc
,
827 const struct dwc3_event_depevt
*event
)
829 struct dwc3_request
*r
= NULL
;
830 struct usb_request
*ur
;
831 struct dwc3_trb
*trb
;
833 unsigned transfer_size
= 0;
835 unsigned remaining_ur_length
;
842 epnum
= event
->endpoint_number
;
845 dwc
->ep0_next_event
= DWC3_EP0_NRDY_STATUS
;
849 trace_dwc3_complete_trb(ep0
, trb
);
851 r
= next_request(&ep0
->pending_list
);
855 status
= DWC3_TRB_SIZE_TRBSTS(trb
->size
);
856 if (status
== DWC3_TRBSTS_SETUP_PENDING
) {
857 dwc
->setup_packet_pending
= true;
859 dwc3_gadget_giveback(ep0
, r
, -ECONNRESET
);
866 remaining_ur_length
= ur
->length
;
868 length
= trb
->size
& DWC3_TRB_SIZE_MASK
;
870 maxp
= ep0
->endpoint
.maxpacket
;
872 if (dwc
->ep0_bounced
) {
874 * Handle the first TRB before handling the bounce buffer if
875 * the request length is greater than the bounce buffer size
877 if (ur
->length
> DWC3_EP0_BOUNCE_SIZE
) {
878 transfer_size
= ALIGN(ur
->length
- maxp
, maxp
);
879 transferred
= transfer_size
- length
;
880 buf
= (u8
*)buf
+ transferred
;
881 ur
->actual
+= transferred
;
882 remaining_ur_length
-= transferred
;
885 length
= trb
->size
& DWC3_TRB_SIZE_MASK
;
887 ep0
->trb_enqueue
= 0;
890 transfer_size
= roundup((ur
->length
- transfer_size
),
893 transferred
= min_t(u32
, remaining_ur_length
,
894 transfer_size
- length
);
895 memcpy(buf
, dwc
->ep0_bounce
, transferred
);
897 transferred
= ur
->length
- length
;
900 ur
->actual
+= transferred
;
902 if ((epnum
& 1) && ur
->actual
< ur
->length
) {
903 /* for some reason we did not get everything out */
905 dwc3_ep0_stall_and_restart(dwc
);
907 dwc3_gadget_giveback(ep0
, r
, 0);
909 if (IS_ALIGNED(ur
->length
, ep0
->endpoint
.maxpacket
) &&
910 ur
->length
&& ur
->zero
) {
913 dwc
->ep0_next_event
= DWC3_EP0_COMPLETE
;
915 ret
= dwc3_ep0_start_trans(dwc
, epnum
,
916 dwc
->ctrl_req_addr
, 0,
917 DWC3_TRBCTL_CONTROL_DATA
, false);
923 static void dwc3_ep0_complete_status(struct dwc3
*dwc
,
924 const struct dwc3_event_depevt
*event
)
926 struct dwc3_request
*r
;
928 struct dwc3_trb
*trb
;
934 trace_dwc3_complete_trb(dep
, trb
);
936 if (!list_empty(&dep
->pending_list
)) {
937 r
= next_request(&dep
->pending_list
);
939 dwc3_gadget_giveback(dep
, r
, 0);
942 if (dwc
->test_mode
) {
945 ret
= dwc3_gadget_set_test_mode(dwc
, dwc
->test_mode_nr
);
947 dev_err(dwc
->dev
, "invalid test #%d\n",
949 dwc3_ep0_stall_and_restart(dwc
);
954 status
= DWC3_TRB_SIZE_TRBSTS(trb
->size
);
955 if (status
== DWC3_TRBSTS_SETUP_PENDING
)
956 dwc
->setup_packet_pending
= true;
958 dwc
->ep0state
= EP0_SETUP_PHASE
;
959 dwc3_ep0_out_start(dwc
);
962 static void dwc3_ep0_xfer_complete(struct dwc3
*dwc
,
963 const struct dwc3_event_depevt
*event
)
965 struct dwc3_ep
*dep
= dwc
->eps
[event
->endpoint_number
];
967 dep
->flags
&= ~DWC3_EP_BUSY
;
968 dep
->resource_index
= 0;
969 dwc
->setup_packet_pending
= false;
971 switch (dwc
->ep0state
) {
972 case EP0_SETUP_PHASE
:
973 dwc3_ep0_inspect_setup(dwc
, event
);
977 dwc3_ep0_complete_data(dwc
, event
);
980 case EP0_STATUS_PHASE
:
981 dwc3_ep0_complete_status(dwc
, event
);
984 WARN(true, "UNKNOWN ep0state %d\n", dwc
->ep0state
);
988 static void __dwc3_ep0_do_control_data(struct dwc3
*dwc
,
989 struct dwc3_ep
*dep
, struct dwc3_request
*req
)
993 req
->direction
= !!dep
->number
;
995 if (req
->request
.length
== 0) {
996 ret
= dwc3_ep0_start_trans(dwc
, dep
->number
,
997 dwc
->ctrl_req_addr
, 0,
998 DWC3_TRBCTL_CONTROL_DATA
, false);
999 } else if (!IS_ALIGNED(req
->request
.length
, dep
->endpoint
.maxpacket
)
1000 && (dep
->number
== 0)) {
1001 u32 transfer_size
= 0;
1004 ret
= usb_gadget_map_request_by_dev(dwc
->sysdev
,
1005 &req
->request
, dep
->number
);
1009 maxpacket
= dep
->endpoint
.maxpacket
;
1011 if (req
->request
.length
> DWC3_EP0_BOUNCE_SIZE
) {
1012 transfer_size
= ALIGN(req
->request
.length
- maxpacket
,
1014 ret
= dwc3_ep0_start_trans(dwc
, dep
->number
,
1017 DWC3_TRBCTL_CONTROL_DATA
,
1021 transfer_size
= roundup((req
->request
.length
- transfer_size
),
1024 dwc
->ep0_bounced
= true;
1026 ret
= dwc3_ep0_start_trans(dwc
, dep
->number
,
1027 dwc
->ep0_bounce_addr
, transfer_size
,
1028 DWC3_TRBCTL_CONTROL_DATA
, false);
1030 ret
= usb_gadget_map_request_by_dev(dwc
->sysdev
,
1031 &req
->request
, dep
->number
);
1035 ret
= dwc3_ep0_start_trans(dwc
, dep
->number
, req
->request
.dma
,
1036 req
->request
.length
, DWC3_TRBCTL_CONTROL_DATA
,
1043 static int dwc3_ep0_start_control_status(struct dwc3_ep
*dep
)
1045 struct dwc3
*dwc
= dep
->dwc
;
1048 type
= dwc
->three_stage_setup
? DWC3_TRBCTL_CONTROL_STATUS3
1049 : DWC3_TRBCTL_CONTROL_STATUS2
;
1051 return dwc3_ep0_start_trans(dwc
, dep
->number
,
1052 dwc
->ctrl_req_addr
, 0, type
, false);
1055 static void __dwc3_ep0_do_control_status(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
1057 WARN_ON(dwc3_ep0_start_control_status(dep
));
1060 static void dwc3_ep0_do_control_status(struct dwc3
*dwc
,
1061 const struct dwc3_event_depevt
*event
)
1063 struct dwc3_ep
*dep
= dwc
->eps
[event
->endpoint_number
];
1065 __dwc3_ep0_do_control_status(dwc
, dep
);
1068 static void dwc3_ep0_end_control_data(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
1070 struct dwc3_gadget_ep_cmd_params params
;
1074 if (!dep
->resource_index
)
1077 cmd
= DWC3_DEPCMD_ENDTRANSFER
;
1078 cmd
|= DWC3_DEPCMD_CMDIOC
;
1079 cmd
|= DWC3_DEPCMD_PARAM(dep
->resource_index
);
1080 memset(¶ms
, 0, sizeof(params
));
1081 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
1083 dep
->resource_index
= 0;
1086 static void dwc3_ep0_xfernotready(struct dwc3
*dwc
,
1087 const struct dwc3_event_depevt
*event
)
1089 switch (event
->status
) {
1090 case DEPEVT_STATUS_CONTROL_DATA
:
1092 * We already have a DATA transfer in the controller's cache,
1093 * if we receive a XferNotReady(DATA) we will ignore it, unless
1094 * it's for the wrong direction.
1096 * In that case, we must issue END_TRANSFER command to the Data
1097 * Phase we already have started and issue SetStall on the
1100 if (dwc
->ep0_expect_in
!= event
->endpoint_number
) {
1101 struct dwc3_ep
*dep
= dwc
->eps
[dwc
->ep0_expect_in
];
1103 dev_err(dwc
->dev
, "unexpected direction for Data Phase\n");
1104 dwc3_ep0_end_control_data(dwc
, dep
);
1105 dwc3_ep0_stall_and_restart(dwc
);
1111 case DEPEVT_STATUS_CONTROL_STATUS
:
1112 if (dwc
->ep0_next_event
!= DWC3_EP0_NRDY_STATUS
)
1115 dwc
->ep0state
= EP0_STATUS_PHASE
;
1117 if (dwc
->delayed_status
) {
1118 WARN_ON_ONCE(event
->endpoint_number
!= 1);
1122 dwc3_ep0_do_control_status(dwc
, event
);
1126 void dwc3_ep0_interrupt(struct dwc3
*dwc
,
1127 const struct dwc3_event_depevt
*event
)
1129 switch (event
->endpoint_event
) {
1130 case DWC3_DEPEVT_XFERCOMPLETE
:
1131 dwc3_ep0_xfer_complete(dwc
, event
);
1134 case DWC3_DEPEVT_XFERNOTREADY
:
1135 dwc3_ep0_xfernotready(dwc
, event
);
1138 case DWC3_DEPEVT_XFERINPROGRESS
:
1139 case DWC3_DEPEVT_RXTXFIFOEVT
:
1140 case DWC3_DEPEVT_STREAMEVT
:
1141 case DWC3_DEPEVT_EPCMDCMPLT
: