2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #include <linux/kernel.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42 #include <linux/platform_device.h>
43 #include <linux/pm_runtime.h>
44 #include <linux/interrupt.h>
46 #include <linux/list.h>
47 #include <linux/dma-mapping.h>
49 #include <linux/usb/ch9.h>
50 #include <linux/usb/gadget.h>
51 #include <linux/usb/composite.h>
57 static void dwc3_ep0_do_control_status(struct dwc3
*dwc
, u32 epnum
);
59 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state
)
68 case EP0_STATUS_PHASE
:
69 return "Status Phase";
75 static int dwc3_ep0_start_trans(struct dwc3
*dwc
, u8 epnum
, dma_addr_t buf_dma
,
78 struct dwc3_gadget_ep_cmd_params params
;
84 dep
= dwc
->eps
[epnum
];
85 if (dep
->flags
& DWC3_EP_BUSY
) {
86 dev_vdbg(dwc
->dev
, "%s: still busy\n", dep
->name
);
92 trb
->bpl
= lower_32_bits(buf_dma
);
93 trb
->bph
= upper_32_bits(buf_dma
);
97 trb
->ctrl
|= (DWC3_TRB_CTRL_HWO
100 | DWC3_TRB_CTRL_ISP_IMI
);
102 memset(¶ms
, 0, sizeof(params
));
103 params
.param0
= upper_32_bits(dwc
->ep0_trb_addr
);
104 params
.param1
= lower_32_bits(dwc
->ep0_trb_addr
);
106 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
107 DWC3_DEPCMD_STARTTRANSFER
, ¶ms
);
109 dev_dbg(dwc
->dev
, "failed to send STARTTRANSFER command\n");
113 dep
->flags
|= DWC3_EP_BUSY
;
114 dep
->res_trans_idx
= dwc3_gadget_ep_get_transfer_index(dwc
,
117 dwc
->ep0_next_event
= DWC3_EP0_COMPLETE
;
122 static int __dwc3_gadget_ep0_queue(struct dwc3_ep
*dep
,
123 struct dwc3_request
*req
)
125 struct dwc3
*dwc
= dep
->dwc
;
128 req
->request
.actual
= 0;
129 req
->request
.status
= -EINPROGRESS
;
130 req
->epnum
= dep
->number
;
132 list_add_tail(&req
->list
, &dep
->request_list
);
135 * Gadget driver might not be quick enough to queue a request
136 * before we get a Transfer Not Ready event on this endpoint.
138 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
139 * flag is set, it's telling us that as soon as Gadget queues the
140 * required request, we should kick the transfer here because the
141 * IRQ we were waiting for is long gone.
143 if (dep
->flags
& DWC3_EP_PENDING_REQUEST
) {
146 direction
= !!(dep
->flags
& DWC3_EP0_DIR_IN
);
148 if (dwc
->ep0state
!= EP0_DATA_PHASE
) {
149 dev_WARN(dwc
->dev
, "Unexpected pending request\n");
153 ret
= dwc3_ep0_start_trans(dwc
, direction
,
154 req
->request
.dma
, req
->request
.length
,
155 DWC3_TRBCTL_CONTROL_DATA
);
156 dep
->flags
&= ~(DWC3_EP_PENDING_REQUEST
|
158 } else if (dwc
->delayed_status
) {
159 dwc
->delayed_status
= false;
161 if (dwc
->ep0state
== EP0_STATUS_PHASE
)
162 dwc3_ep0_do_control_status(dwc
, 1);
164 dev_dbg(dwc
->dev
, "too early for delayed status\n");
170 int dwc3_gadget_ep0_queue(struct usb_ep
*ep
, struct usb_request
*request
,
173 struct dwc3_request
*req
= to_dwc3_request(request
);
174 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
175 struct dwc3
*dwc
= dep
->dwc
;
181 spin_lock_irqsave(&dwc
->lock
, flags
);
183 dev_dbg(dwc
->dev
, "trying to queue request %p to disabled %s\n",
189 /* we share one TRB for ep0/1 */
190 if (!list_empty(&dep
->request_list
)) {
195 dev_vdbg(dwc
->dev
, "queueing request %p to %s length %d, state '%s'\n",
196 request
, dep
->name
, request
->length
,
197 dwc3_ep0_state_string(dwc
->ep0state
));
199 ret
= __dwc3_gadget_ep0_queue(dep
, req
);
202 spin_unlock_irqrestore(&dwc
->lock
, flags
);
207 static void dwc3_ep0_stall_and_restart(struct dwc3
*dwc
)
209 struct dwc3_ep
*dep
= dwc
->eps
[0];
211 /* stall is always issued on EP0 */
212 __dwc3_gadget_ep_set_halt(dep
, 1);
213 dep
->flags
= DWC3_EP_ENABLED
;
214 dwc
->delayed_status
= false;
216 if (!list_empty(&dep
->request_list
)) {
217 struct dwc3_request
*req
;
219 req
= next_request(&dep
->request_list
);
220 dwc3_gadget_giveback(dep
, req
, -ECONNRESET
);
223 dwc
->ep0state
= EP0_SETUP_PHASE
;
224 dwc3_ep0_out_start(dwc
);
227 void dwc3_ep0_out_start(struct dwc3
*dwc
)
231 ret
= dwc3_ep0_start_trans(dwc
, 0, dwc
->ctrl_req_addr
, 8,
232 DWC3_TRBCTL_CONTROL_SETUP
);
236 static struct dwc3_ep
*dwc3_wIndex_to_dep(struct dwc3
*dwc
, __le16 wIndex_le
)
239 u32 windex
= le16_to_cpu(wIndex_le
);
242 epnum
= (windex
& USB_ENDPOINT_NUMBER_MASK
) << 1;
243 if ((windex
& USB_ENDPOINT_DIR_MASK
) == USB_DIR_IN
)
246 dep
= dwc
->eps
[epnum
];
247 if (dep
->flags
& DWC3_EP_ENABLED
)
253 static void dwc3_ep0_status_cmpl(struct usb_ep
*ep
, struct usb_request
*req
)
259 static int dwc3_ep0_handle_status(struct dwc3
*dwc
,
260 struct usb_ctrlrequest
*ctrl
)
265 __le16
*response_pkt
;
267 recip
= ctrl
->bRequestType
& USB_RECIP_MASK
;
269 case USB_RECIP_DEVICE
:
271 * We are self-powered. U1/U2/LTM will be set later
272 * once we handle this states. RemoteWakeup is 0 on SS
274 usb_status
|= dwc
->is_selfpowered
<< USB_DEVICE_SELF_POWERED
;
277 case USB_RECIP_INTERFACE
:
279 * Function Remote Wake Capable D0
280 * Function Remote Wakeup D1
284 case USB_RECIP_ENDPOINT
:
285 dep
= dwc3_wIndex_to_dep(dwc
, ctrl
->wIndex
);
289 if (dep
->flags
& DWC3_EP_STALL
)
290 usb_status
= 1 << USB_ENDPOINT_HALT
;
296 response_pkt
= (__le16
*) dwc
->setup_buf
;
297 *response_pkt
= cpu_to_le16(usb_status
);
300 dwc
->ep0_usb_req
.dep
= dep
;
301 dwc
->ep0_usb_req
.request
.length
= sizeof(*response_pkt
);
302 dwc
->ep0_usb_req
.request
.buf
= dwc
->setup_buf
;
303 dwc
->ep0_usb_req
.request
.complete
= dwc3_ep0_status_cmpl
;
305 return __dwc3_gadget_ep0_queue(dep
, &dwc
->ep0_usb_req
);
308 static int dwc3_ep0_handle_feature(struct dwc3
*dwc
,
309 struct usb_ctrlrequest
*ctrl
, int set
)
317 wValue
= le16_to_cpu(ctrl
->wValue
);
318 wIndex
= le16_to_cpu(ctrl
->wIndex
);
319 recip
= ctrl
->bRequestType
& USB_RECIP_MASK
;
321 case USB_RECIP_DEVICE
:
324 * 9.4.1 says only only for SS, in AddressState only for
325 * default control pipe
328 case USB_DEVICE_U1_ENABLE
:
329 case USB_DEVICE_U2_ENABLE
:
330 case USB_DEVICE_LTM_ENABLE
:
331 if (dwc
->dev_state
!= DWC3_CONFIGURED_STATE
)
333 if (dwc
->speed
!= DWC3_DSTS_SUPERSPEED
)
337 /* XXX add U[12] & LTM */
339 case USB_DEVICE_REMOTE_WAKEUP
:
341 case USB_DEVICE_U1_ENABLE
:
343 case USB_DEVICE_U2_ENABLE
:
345 case USB_DEVICE_LTM_ENABLE
:
348 case USB_DEVICE_TEST_MODE
:
349 if ((wIndex
& 0xff) != 0)
354 dwc
->test_mode_nr
= wIndex
>> 8;
355 dwc
->test_mode
= true;
359 case USB_RECIP_INTERFACE
:
361 case USB_INTRF_FUNC_SUSPEND
:
362 if (wIndex
& USB_INTRF_FUNC_SUSPEND_LP
)
363 /* XXX enable Low power suspend */
365 if (wIndex
& USB_INTRF_FUNC_SUSPEND_RW
)
366 /* XXX enable remote wakeup */
374 case USB_RECIP_ENDPOINT
:
376 case USB_ENDPOINT_HALT
:
377 dep
= dwc3_wIndex_to_dep(dwc
, wIndex
);
380 ret
= __dwc3_gadget_ep_set_halt(dep
, set
);
396 static int dwc3_ep0_set_address(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
401 addr
= le16_to_cpu(ctrl
->wValue
);
403 dev_dbg(dwc
->dev
, "invalid device address %d\n", addr
);
407 if (dwc
->dev_state
== DWC3_CONFIGURED_STATE
) {
408 dev_dbg(dwc
->dev
, "trying to set address when configured\n");
412 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
413 reg
&= ~(DWC3_DCFG_DEVADDR_MASK
);
414 reg
|= DWC3_DCFG_DEVADDR(addr
);
415 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
418 dwc
->dev_state
= DWC3_ADDRESS_STATE
;
420 dwc
->dev_state
= DWC3_DEFAULT_STATE
;
425 static int dwc3_ep0_delegate_req(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
429 spin_unlock(&dwc
->lock
);
430 ret
= dwc
->gadget_driver
->setup(&dwc
->gadget
, ctrl
);
431 spin_lock(&dwc
->lock
);
435 static int dwc3_ep0_set_config(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
440 dwc
->start_config_issued
= false;
441 cfg
= le16_to_cpu(ctrl
->wValue
);
443 switch (dwc
->dev_state
) {
444 case DWC3_DEFAULT_STATE
:
448 case DWC3_ADDRESS_STATE
:
449 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
450 /* if the cfg matches and the cfg is non zero */
451 if (cfg
&& (!ret
|| (ret
== USB_GADGET_DELAYED_STATUS
))) {
452 dwc
->dev_state
= DWC3_CONFIGURED_STATE
;
453 dwc
->resize_fifos
= true;
454 dev_dbg(dwc
->dev
, "resize fifos flag SET\n");
458 case DWC3_CONFIGURED_STATE
:
459 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
461 dwc
->dev_state
= DWC3_ADDRESS_STATE
;
469 static int dwc3_ep0_std_request(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
473 switch (ctrl
->bRequest
) {
474 case USB_REQ_GET_STATUS
:
475 dev_vdbg(dwc
->dev
, "USB_REQ_GET_STATUS\n");
476 ret
= dwc3_ep0_handle_status(dwc
, ctrl
);
478 case USB_REQ_CLEAR_FEATURE
:
479 dev_vdbg(dwc
->dev
, "USB_REQ_CLEAR_FEATURE\n");
480 ret
= dwc3_ep0_handle_feature(dwc
, ctrl
, 0);
482 case USB_REQ_SET_FEATURE
:
483 dev_vdbg(dwc
->dev
, "USB_REQ_SET_FEATURE\n");
484 ret
= dwc3_ep0_handle_feature(dwc
, ctrl
, 1);
486 case USB_REQ_SET_ADDRESS
:
487 dev_vdbg(dwc
->dev
, "USB_REQ_SET_ADDRESS\n");
488 ret
= dwc3_ep0_set_address(dwc
, ctrl
);
490 case USB_REQ_SET_CONFIGURATION
:
491 dev_vdbg(dwc
->dev
, "USB_REQ_SET_CONFIGURATION\n");
492 ret
= dwc3_ep0_set_config(dwc
, ctrl
);
495 dev_vdbg(dwc
->dev
, "Forwarding to gadget driver\n");
496 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
503 static void dwc3_ep0_inspect_setup(struct dwc3
*dwc
,
504 const struct dwc3_event_depevt
*event
)
506 struct usb_ctrlrequest
*ctrl
= dwc
->ctrl_req
;
510 if (!dwc
->gadget_driver
)
513 len
= le16_to_cpu(ctrl
->wLength
);
515 dwc
->three_stage_setup
= false;
516 dwc
->ep0_expect_in
= false;
517 dwc
->ep0_next_event
= DWC3_EP0_NRDY_STATUS
;
519 dwc
->three_stage_setup
= true;
520 dwc
->ep0_expect_in
= !!(ctrl
->bRequestType
& USB_DIR_IN
);
521 dwc
->ep0_next_event
= DWC3_EP0_NRDY_DATA
;
524 if ((ctrl
->bRequestType
& USB_TYPE_MASK
) == USB_TYPE_STANDARD
)
525 ret
= dwc3_ep0_std_request(dwc
, ctrl
);
527 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
529 if (ret
== USB_GADGET_DELAYED_STATUS
)
530 dwc
->delayed_status
= true;
536 dwc3_ep0_stall_and_restart(dwc
);
539 static void dwc3_ep0_complete_data(struct dwc3
*dwc
,
540 const struct dwc3_event_depevt
*event
)
542 struct dwc3_request
*r
= NULL
;
543 struct usb_request
*ur
;
544 struct dwc3_trb
*trb
;
550 epnum
= event
->endpoint_number
;
553 dwc
->ep0_next_event
= DWC3_EP0_NRDY_STATUS
;
555 r
= next_request(&ep0
->request_list
);
559 length
= trb
->size
& DWC3_TRB_SIZE_MASK
;
561 if (dwc
->ep0_bounced
) {
562 transferred
= min_t(u32
, ur
->length
,
563 ep0
->endpoint
.maxpacket
- length
);
564 memcpy(ur
->buf
, dwc
->ep0_bounce
, transferred
);
565 dwc
->ep0_bounced
= false;
567 transferred
= ur
->length
- length
;
568 ur
->actual
+= transferred
;
571 if ((epnum
& 1) && ur
->actual
< ur
->length
) {
572 /* for some reason we did not get everything out */
574 dwc3_ep0_stall_and_restart(dwc
);
577 * handle the case where we have to send a zero packet. This
578 * seems to be case when req.length > maxpacket. Could it be?
581 dwc3_gadget_giveback(ep0
, r
, 0);
585 static void dwc3_ep0_complete_req(struct dwc3
*dwc
,
586 const struct dwc3_event_depevt
*event
)
588 struct dwc3_request
*r
;
593 if (!list_empty(&dep
->request_list
)) {
594 r
= next_request(&dep
->request_list
);
596 dwc3_gadget_giveback(dep
, r
, 0);
599 if (dwc
->test_mode
) {
602 ret
= dwc3_gadget_set_test_mode(dwc
, dwc
->test_mode_nr
);
604 dev_dbg(dwc
->dev
, "Invalid Test #%d\n",
606 dwc3_ep0_stall_and_restart(dwc
);
610 dwc
->ep0state
= EP0_SETUP_PHASE
;
611 dwc3_ep0_out_start(dwc
);
614 static void dwc3_ep0_xfer_complete(struct dwc3
*dwc
,
615 const struct dwc3_event_depevt
*event
)
617 struct dwc3_ep
*dep
= dwc
->eps
[event
->endpoint_number
];
619 dep
->flags
&= ~DWC3_EP_BUSY
;
620 dep
->res_trans_idx
= 0;
621 dwc
->setup_packet_pending
= false;
623 switch (dwc
->ep0state
) {
624 case EP0_SETUP_PHASE
:
625 dev_vdbg(dwc
->dev
, "Inspecting Setup Bytes\n");
626 dwc3_ep0_inspect_setup(dwc
, event
);
630 dev_vdbg(dwc
->dev
, "Data Phase\n");
631 dwc3_ep0_complete_data(dwc
, event
);
634 case EP0_STATUS_PHASE
:
635 dev_vdbg(dwc
->dev
, "Status Phase\n");
636 dwc3_ep0_complete_req(dwc
, event
);
639 WARN(true, "UNKNOWN ep0state %d\n", dwc
->ep0state
);
643 static void dwc3_ep0_do_control_setup(struct dwc3
*dwc
,
644 const struct dwc3_event_depevt
*event
)
646 dwc3_ep0_out_start(dwc
);
649 static void dwc3_ep0_do_control_data(struct dwc3
*dwc
,
650 const struct dwc3_event_depevt
*event
)
653 struct dwc3_request
*req
;
658 if (list_empty(&dep
->request_list
)) {
659 dev_vdbg(dwc
->dev
, "pending request for EP0 Data phase\n");
660 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
662 if (event
->endpoint_number
)
663 dep
->flags
|= DWC3_EP0_DIR_IN
;
667 req
= next_request(&dep
->request_list
);
668 req
->direction
= !!event
->endpoint_number
;
670 if (req
->request
.length
== 0) {
671 ret
= dwc3_ep0_start_trans(dwc
, event
->endpoint_number
,
672 dwc
->ctrl_req_addr
, 0,
673 DWC3_TRBCTL_CONTROL_DATA
);
674 } else if ((req
->request
.length
% dep
->endpoint
.maxpacket
)
675 && (event
->endpoint_number
== 0)) {
676 ret
= usb_gadget_map_request(&dwc
->gadget
, &req
->request
,
677 event
->endpoint_number
);
679 dev_dbg(dwc
->dev
, "failed to map request\n");
683 WARN_ON(req
->request
.length
> dep
->endpoint
.maxpacket
);
685 dwc
->ep0_bounced
= true;
688 * REVISIT in case request length is bigger than EP0
689 * wMaxPacketSize, we will need two chained TRBs to handle
692 ret
= dwc3_ep0_start_trans(dwc
, event
->endpoint_number
,
693 dwc
->ep0_bounce_addr
, dep
->endpoint
.maxpacket
,
694 DWC3_TRBCTL_CONTROL_DATA
);
696 ret
= usb_gadget_map_request(&dwc
->gadget
, &req
->request
,
697 event
->endpoint_number
);
699 dev_dbg(dwc
->dev
, "failed to map request\n");
703 ret
= dwc3_ep0_start_trans(dwc
, event
->endpoint_number
,
704 req
->request
.dma
, req
->request
.length
,
705 DWC3_TRBCTL_CONTROL_DATA
);
711 static int dwc3_ep0_start_control_status(struct dwc3_ep
*dep
)
713 struct dwc3
*dwc
= dep
->dwc
;
716 type
= dwc
->three_stage_setup
? DWC3_TRBCTL_CONTROL_STATUS3
717 : DWC3_TRBCTL_CONTROL_STATUS2
;
719 return dwc3_ep0_start_trans(dwc
, dep
->number
,
720 dwc
->ctrl_req_addr
, 0, type
);
723 static void dwc3_ep0_do_control_status(struct dwc3
*dwc
, u32 epnum
)
725 struct dwc3_ep
*dep
= dwc
->eps
[epnum
];
727 if (dwc
->resize_fifos
) {
728 dev_dbg(dwc
->dev
, "starting to resize fifos\n");
729 dwc3_gadget_resize_tx_fifos(dwc
);
730 dwc
->resize_fifos
= 0;
733 WARN_ON(dwc3_ep0_start_control_status(dep
));
736 static void dwc3_ep0_xfernotready(struct dwc3
*dwc
,
737 const struct dwc3_event_depevt
*event
)
739 dwc
->setup_packet_pending
= true;
742 * This part is very tricky: If we has just handled
743 * XferNotReady(Setup) and we're now expecting a
744 * XferComplete but, instead, we receive another
745 * XferNotReady(Setup), we should STALL and restart
748 * In all other cases, we just continue waiting
749 * for the XferComplete event.
751 * We are a little bit unsafe here because we're
752 * not trying to ensure that last event was, indeed,
753 * XferNotReady(Setup).
755 * Still, we don't expect any condition where that
756 * should happen and, even if it does, it would be
757 * another error condition.
759 if (dwc
->ep0_next_event
== DWC3_EP0_COMPLETE
) {
760 switch (event
->status
) {
761 case DEPEVT_STATUS_CONTROL_SETUP
:
762 dev_vdbg(dwc
->dev
, "Unexpected XferNotReady(Setup)\n");
763 dwc3_ep0_stall_and_restart(dwc
);
765 case DEPEVT_STATUS_CONTROL_DATA
:
767 case DEPEVT_STATUS_CONTROL_STATUS
:
770 dev_vdbg(dwc
->dev
, "waiting for XferComplete\n");
776 switch (event
->status
) {
777 case DEPEVT_STATUS_CONTROL_SETUP
:
778 dev_vdbg(dwc
->dev
, "Control Setup\n");
780 dwc
->ep0state
= EP0_SETUP_PHASE
;
782 dwc3_ep0_do_control_setup(dwc
, event
);
785 case DEPEVT_STATUS_CONTROL_DATA
:
786 dev_vdbg(dwc
->dev
, "Control Data\n");
788 dwc
->ep0state
= EP0_DATA_PHASE
;
790 if (dwc
->ep0_next_event
!= DWC3_EP0_NRDY_DATA
) {
791 dev_vdbg(dwc
->dev
, "Expected %d got %d\n",
795 dwc3_ep0_stall_and_restart(dwc
);
800 * One of the possible error cases is when Host _does_
801 * request for Data Phase, but it does so on the wrong
804 * Here, we already know ep0_next_event is DATA (see above),
805 * so we only need to check for direction.
807 if (dwc
->ep0_expect_in
!= event
->endpoint_number
) {
808 dev_vdbg(dwc
->dev
, "Wrong direction for Data phase\n");
809 dwc3_ep0_stall_and_restart(dwc
);
813 dwc3_ep0_do_control_data(dwc
, event
);
816 case DEPEVT_STATUS_CONTROL_STATUS
:
817 dev_vdbg(dwc
->dev
, "Control Status\n");
819 dwc
->ep0state
= EP0_STATUS_PHASE
;
821 if (dwc
->ep0_next_event
!= DWC3_EP0_NRDY_STATUS
) {
822 dev_vdbg(dwc
->dev
, "Expected %d got %d\n",
824 DWC3_EP0_NRDY_STATUS
);
826 dwc3_ep0_stall_and_restart(dwc
);
830 if (dwc
->delayed_status
) {
831 WARN_ON_ONCE(event
->endpoint_number
!= 1);
832 dev_vdbg(dwc
->dev
, "Mass Storage delayed status\n");
836 dwc3_ep0_do_control_status(dwc
, event
->endpoint_number
);
840 void dwc3_ep0_interrupt(struct dwc3
*dwc
,
841 const struct dwc3_event_depevt
*event
)
843 u8 epnum
= event
->endpoint_number
;
845 dev_dbg(dwc
->dev
, "%s while ep%d%s in state '%s'\n",
846 dwc3_ep_event_string(event
->endpoint_event
),
847 epnum
>> 1, (epnum
& 1) ? "in" : "out",
848 dwc3_ep0_state_string(dwc
->ep0state
));
850 switch (event
->endpoint_event
) {
851 case DWC3_DEPEVT_XFERCOMPLETE
:
852 dwc3_ep0_xfer_complete(dwc
, event
);
855 case DWC3_DEPEVT_XFERNOTREADY
:
856 dwc3_ep0_xfernotready(dwc
, event
);
859 case DWC3_DEPEVT_XFERINPROGRESS
:
860 case DWC3_DEPEVT_RXTXFIFOEVT
:
861 case DWC3_DEPEVT_STREAMEVT
:
862 case DWC3_DEPEVT_EPCMDCMPLT
: