2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/interrupt.h>
27 #include <linux/list.h>
28 #include <linux/dma-mapping.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
47 int dwc3_gadget_set_test_mode(struct dwc3
*dwc
, int mode
)
51 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
52 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
66 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
78 int dwc3_gadget_get_link_state(struct dwc3
*dwc
)
82 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
84 return DWC3_DSTS_USBLNKST(reg
);
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
92 * Caller should take care of locking. This function will
93 * return 0 on success or -ETIMEDOUT.
95 int dwc3_gadget_set_link_state(struct dwc3
*dwc
, enum dwc3_link_state state
)
101 * Wait until device controller is ready. Only applies to 1.94a and
104 if (dwc
->revision
>= DWC3_REVISION_194A
) {
106 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
107 if (reg
& DWC3_DSTS_DCNRD
)
117 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
118 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
120 /* set requested state */
121 reg
|= DWC3_DCTL_ULSTCHNGREQ(state
);
122 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
128 if (dwc
->revision
>= DWC3_REVISION_194A
)
131 /* wait for a change in DSTS */
134 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
136 if (DWC3_DSTS_USBLNKST(reg
) == state
)
146 * dwc3_ep_inc_trb() - Increment a TRB index.
147 * @index - Pointer to the TRB index to increment.
149 * The index should never point to the link TRB. After incrementing,
150 * if it is point to the link TRB, wrap around to the beginning. The
151 * link TRB is always at the last TRB entry.
153 static void dwc3_ep_inc_trb(u8
*index
)
156 if (*index
== (DWC3_TRB_NUM
- 1))
160 static void dwc3_ep_inc_enq(struct dwc3_ep
*dep
)
162 dwc3_ep_inc_trb(&dep
->trb_enqueue
);
165 static void dwc3_ep_inc_deq(struct dwc3_ep
*dep
)
167 dwc3_ep_inc_trb(&dep
->trb_dequeue
);
170 void dwc3_gadget_giveback(struct dwc3_ep
*dep
, struct dwc3_request
*req
,
173 struct dwc3
*dwc
= dep
->dwc
;
175 req
->started
= false;
176 list_del(&req
->list
);
180 if (req
->request
.status
== -EINPROGRESS
)
181 req
->request
.status
= status
;
183 if (dwc
->ep0_bounced
&& dep
->number
<= 1)
184 dwc
->ep0_bounced
= false;
186 usb_gadget_unmap_request_by_dev(dwc
->sysdev
,
187 &req
->request
, req
->direction
);
189 trace_dwc3_gadget_giveback(req
);
191 spin_unlock(&dwc
->lock
);
192 usb_gadget_giveback_request(&dep
->endpoint
, &req
->request
);
193 spin_lock(&dwc
->lock
);
196 pm_runtime_put(dwc
->dev
);
199 int dwc3_send_gadget_generic_command(struct dwc3
*dwc
, unsigned cmd
, u32 param
)
206 dwc3_writel(dwc
->regs
, DWC3_DGCMDPAR
, param
);
207 dwc3_writel(dwc
->regs
, DWC3_DGCMD
, cmd
| DWC3_DGCMD_CMDACT
);
210 reg
= dwc3_readl(dwc
->regs
, DWC3_DGCMD
);
211 if (!(reg
& DWC3_DGCMD_CMDACT
)) {
212 status
= DWC3_DGCMD_STATUS(reg
);
224 trace_dwc3_gadget_generic_cmd(cmd
, param
, status
);
229 static int __dwc3_gadget_wakeup(struct dwc3
*dwc
);
231 int dwc3_send_gadget_ep_cmd(struct dwc3_ep
*dep
, unsigned cmd
,
232 struct dwc3_gadget_ep_cmd_params
*params
)
234 const struct usb_endpoint_descriptor
*desc
= dep
->endpoint
.desc
;
235 struct dwc3
*dwc
= dep
->dwc
;
244 * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
245 * we're issuing an endpoint command, we must check if
246 * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
248 * We will also set SUSPHY bit to what it was before returning as stated
249 * by the same section on Synopsys databook.
251 if (dwc
->gadget
.speed
<= USB_SPEED_HIGH
) {
252 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
253 if (unlikely(reg
& DWC3_GUSB2PHYCFG_SUSPHY
)) {
255 reg
&= ~DWC3_GUSB2PHYCFG_SUSPHY
;
256 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
260 if (DWC3_DEPCMD_CMD(cmd
) == DWC3_DEPCMD_STARTTRANSFER
) {
263 needs_wakeup
= (dwc
->link_state
== DWC3_LINK_STATE_U1
||
264 dwc
->link_state
== DWC3_LINK_STATE_U2
||
265 dwc
->link_state
== DWC3_LINK_STATE_U3
);
267 if (unlikely(needs_wakeup
)) {
268 ret
= __dwc3_gadget_wakeup(dwc
);
269 dev_WARN_ONCE(dwc
->dev
, ret
, "wakeup failed --> %d\n",
274 dwc3_writel(dep
->regs
, DWC3_DEPCMDPAR0
, params
->param0
);
275 dwc3_writel(dep
->regs
, DWC3_DEPCMDPAR1
, params
->param1
);
276 dwc3_writel(dep
->regs
, DWC3_DEPCMDPAR2
, params
->param2
);
279 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
280 * not relying on XferNotReady, we can make use of a special "No
281 * Response Update Transfer" command where we should clear both CmdAct
284 * With this, we don't need to wait for command completion and can
285 * straight away issue further commands to the endpoint.
287 * NOTICE: We're making an assumption that control endpoints will never
288 * make use of Update Transfer command. This is a safe assumption
289 * because we can never have more than one request at a time with
290 * Control Endpoints. If anybody changes that assumption, this chunk
291 * needs to be updated accordingly.
293 if (DWC3_DEPCMD_CMD(cmd
) == DWC3_DEPCMD_UPDATETRANSFER
&&
294 !usb_endpoint_xfer_isoc(desc
))
295 cmd
&= ~(DWC3_DEPCMD_CMDIOC
| DWC3_DEPCMD_CMDACT
);
297 cmd
|= DWC3_DEPCMD_CMDACT
;
299 dwc3_writel(dep
->regs
, DWC3_DEPCMD
, cmd
);
301 reg
= dwc3_readl(dep
->regs
, DWC3_DEPCMD
);
302 if (!(reg
& DWC3_DEPCMD_CMDACT
)) {
303 cmd_status
= DWC3_DEPCMD_STATUS(reg
);
305 switch (cmd_status
) {
309 case DEPEVT_TRANSFER_NO_RESOURCE
:
312 case DEPEVT_TRANSFER_BUS_EXPIRY
:
314 * SW issues START TRANSFER command to
315 * isochronous ep with future frame interval. If
316 * future interval time has already passed when
317 * core receives the command, it will respond
318 * with an error status of 'Bus Expiry'.
320 * Instead of always returning -EINVAL, let's
321 * give a hint to the gadget driver that this is
322 * the case by returning -EAGAIN.
327 dev_WARN(dwc
->dev
, "UNKNOWN cmd status\n");
336 cmd_status
= -ETIMEDOUT
;
339 trace_dwc3_gadget_ep_cmd(dep
, cmd
, params
, cmd_status
);
342 switch (DWC3_DEPCMD_CMD(cmd
)) {
343 case DWC3_DEPCMD_STARTTRANSFER
:
344 dep
->flags
|= DWC3_EP_TRANSFER_STARTED
;
346 case DWC3_DEPCMD_ENDTRANSFER
:
347 dep
->flags
&= ~DWC3_EP_TRANSFER_STARTED
;
355 if (unlikely(susphy
)) {
356 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
357 reg
|= DWC3_GUSB2PHYCFG_SUSPHY
;
358 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
364 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep
*dep
)
366 struct dwc3
*dwc
= dep
->dwc
;
367 struct dwc3_gadget_ep_cmd_params params
;
368 u32 cmd
= DWC3_DEPCMD_CLEARSTALL
;
371 * As of core revision 2.60a the recommended programming model
372 * is to set the ClearPendIN bit when issuing a Clear Stall EP
373 * command for IN endpoints. This is to prevent an issue where
374 * some (non-compliant) hosts may not send ACK TPs for pending
375 * IN transfers due to a mishandled error condition. Synopsys
378 if (dep
->direction
&& (dwc
->revision
>= DWC3_REVISION_260A
) &&
379 (dwc
->gadget
.speed
>= USB_SPEED_SUPER
))
380 cmd
|= DWC3_DEPCMD_CLEARPENDIN
;
382 memset(¶ms
, 0, sizeof(params
));
384 return dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
387 static dma_addr_t
dwc3_trb_dma_offset(struct dwc3_ep
*dep
,
388 struct dwc3_trb
*trb
)
390 u32 offset
= (char *) trb
- (char *) dep
->trb_pool
;
392 return dep
->trb_pool_dma
+ offset
;
395 static int dwc3_alloc_trb_pool(struct dwc3_ep
*dep
)
397 struct dwc3
*dwc
= dep
->dwc
;
402 dep
->trb_pool
= dma_alloc_coherent(dwc
->sysdev
,
403 sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
404 &dep
->trb_pool_dma
, GFP_KERNEL
);
405 if (!dep
->trb_pool
) {
406 dev_err(dep
->dwc
->dev
, "failed to allocate trb pool for %s\n",
414 static void dwc3_free_trb_pool(struct dwc3_ep
*dep
)
416 struct dwc3
*dwc
= dep
->dwc
;
418 dma_free_coherent(dwc
->sysdev
, sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
419 dep
->trb_pool
, dep
->trb_pool_dma
);
421 dep
->trb_pool
= NULL
;
422 dep
->trb_pool_dma
= 0;
425 static int dwc3_gadget_set_xfer_resource(struct dwc3
*dwc
, struct dwc3_ep
*dep
);
428 * dwc3_gadget_start_config - Configure EP resources
429 * @dwc: pointer to our controller context structure
430 * @dep: endpoint that is being enabled
432 * The assignment of transfer resources cannot perfectly follow the
433 * data book due to the fact that the controller driver does not have
434 * all knowledge of the configuration in advance. It is given this
435 * information piecemeal by the composite gadget framework after every
436 * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
437 * programming model in this scenario can cause errors. For two
440 * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
441 * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
442 * multiple interfaces.
444 * 2) The databook does not mention doing more DEPXFERCFG for new
445 * endpoint on alt setting (8.1.6).
447 * The following simplified method is used instead:
449 * All hardware endpoints can be assigned a transfer resource and this
450 * setting will stay persistent until either a core reset or
451 * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
452 * do DEPXFERCFG for every hardware endpoint as well. We are
453 * guaranteed that there are as many transfer resources as endpoints.
455 * This function is called for each endpoint when it is being enabled
456 * but is triggered only when called for EP0-out, which always happens
457 * first, and which should only happen in one of the above conditions.
459 static int dwc3_gadget_start_config(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
461 struct dwc3_gadget_ep_cmd_params params
;
469 memset(¶ms
, 0x00, sizeof(params
));
470 cmd
= DWC3_DEPCMD_DEPSTARTCFG
;
472 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
476 for (i
= 0; i
< DWC3_ENDPOINTS_NUM
; i
++) {
477 struct dwc3_ep
*dep
= dwc
->eps
[i
];
482 ret
= dwc3_gadget_set_xfer_resource(dwc
, dep
);
490 static int dwc3_gadget_set_ep_config(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
491 bool modify
, bool restore
)
493 const struct usb_ss_ep_comp_descriptor
*comp_desc
;
494 const struct usb_endpoint_descriptor
*desc
;
495 struct dwc3_gadget_ep_cmd_params params
;
497 if (dev_WARN_ONCE(dwc
->dev
, modify
&& restore
,
498 "Can't modify and restore\n"))
501 comp_desc
= dep
->endpoint
.comp_desc
;
502 desc
= dep
->endpoint
.desc
;
504 memset(¶ms
, 0x00, sizeof(params
));
506 params
.param0
= DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc
))
507 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc
));
509 /* Burst size is only needed in SuperSpeed mode */
510 if (dwc
->gadget
.speed
>= USB_SPEED_SUPER
) {
511 u32 burst
= dep
->endpoint
.maxburst
;
512 params
.param0
|= DWC3_DEPCFG_BURST_SIZE(burst
- 1);
516 params
.param0
|= DWC3_DEPCFG_ACTION_MODIFY
;
517 } else if (restore
) {
518 params
.param0
|= DWC3_DEPCFG_ACTION_RESTORE
;
519 params
.param2
|= dep
->saved_state
;
521 params
.param0
|= DWC3_DEPCFG_ACTION_INIT
;
524 if (usb_endpoint_xfer_control(desc
))
525 params
.param1
= DWC3_DEPCFG_XFER_COMPLETE_EN
;
527 if (dep
->number
<= 1 || usb_endpoint_xfer_isoc(desc
))
528 params
.param1
|= DWC3_DEPCFG_XFER_NOT_READY_EN
;
530 if (usb_ss_max_streams(comp_desc
) && usb_endpoint_xfer_bulk(desc
)) {
531 params
.param1
|= DWC3_DEPCFG_STREAM_CAPABLE
532 | DWC3_DEPCFG_STREAM_EVENT_EN
;
533 dep
->stream_capable
= true;
536 if (!usb_endpoint_xfer_control(desc
))
537 params
.param1
|= DWC3_DEPCFG_XFER_IN_PROGRESS_EN
;
540 * We are doing 1:1 mapping for endpoints, meaning
541 * Physical Endpoints 2 maps to Logical Endpoint 2 and
542 * so on. We consider the direction bit as part of the physical
543 * endpoint number. So USB endpoint 0x81 is 0x03.
545 params
.param1
|= DWC3_DEPCFG_EP_NUMBER(dep
->number
);
548 * We must use the lower 16 TX FIFOs even though
552 params
.param0
|= DWC3_DEPCFG_FIFO_NUMBER(dep
->number
>> 1);
554 if (desc
->bInterval
) {
555 params
.param1
|= DWC3_DEPCFG_BINTERVAL_M1(desc
->bInterval
- 1);
556 dep
->interval
= 1 << (desc
->bInterval
- 1);
559 return dwc3_send_gadget_ep_cmd(dep
, DWC3_DEPCMD_SETEPCONFIG
, ¶ms
);
562 static int dwc3_gadget_set_xfer_resource(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
564 struct dwc3_gadget_ep_cmd_params params
;
566 memset(¶ms
, 0x00, sizeof(params
));
568 params
.param0
= DWC3_DEPXFERCFG_NUM_XFER_RES(1);
570 return dwc3_send_gadget_ep_cmd(dep
, DWC3_DEPCMD_SETTRANSFRESOURCE
,
575 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
576 * @dep: endpoint to be initialized
577 * @desc: USB Endpoint Descriptor
579 * Caller should take care of locking
581 static int __dwc3_gadget_ep_enable(struct dwc3_ep
*dep
,
582 bool modify
, bool restore
)
584 const struct usb_endpoint_descriptor
*desc
= dep
->endpoint
.desc
;
585 struct dwc3
*dwc
= dep
->dwc
;
590 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
591 ret
= dwc3_gadget_start_config(dwc
, dep
);
596 ret
= dwc3_gadget_set_ep_config(dwc
, dep
, modify
, restore
);
600 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
601 struct dwc3_trb
*trb_st_hw
;
602 struct dwc3_trb
*trb_link
;
604 dep
->type
= usb_endpoint_type(desc
);
605 dep
->flags
|= DWC3_EP_ENABLED
;
606 dep
->flags
&= ~DWC3_EP_END_TRANSFER_PENDING
;
608 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
609 reg
|= DWC3_DALEPENA_EP(dep
->number
);
610 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
612 init_waitqueue_head(&dep
->wait_end_transfer
);
614 if (usb_endpoint_xfer_control(desc
))
617 /* Initialize the TRB ring */
618 dep
->trb_dequeue
= 0;
619 dep
->trb_enqueue
= 0;
620 memset(dep
->trb_pool
, 0,
621 sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
);
623 /* Link TRB. The HWO bit is never reset */
624 trb_st_hw
= &dep
->trb_pool
[0];
626 trb_link
= &dep
->trb_pool
[DWC3_TRB_NUM
- 1];
627 trb_link
->bpl
= lower_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
628 trb_link
->bph
= upper_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
629 trb_link
->ctrl
|= DWC3_TRBCTL_LINK_TRB
;
630 trb_link
->ctrl
|= DWC3_TRB_CTRL_HWO
;
634 * Issue StartTransfer here with no-op TRB so we can always rely on No
635 * Response Update Transfer command.
637 if (usb_endpoint_xfer_bulk(desc
)) {
638 struct dwc3_gadget_ep_cmd_params params
;
639 struct dwc3_trb
*trb
;
643 memset(¶ms
, 0, sizeof(params
));
644 trb
= &dep
->trb_pool
[0];
645 trb_dma
= dwc3_trb_dma_offset(dep
, trb
);
647 params
.param0
= upper_32_bits(trb_dma
);
648 params
.param1
= lower_32_bits(trb_dma
);
650 cmd
= DWC3_DEPCMD_STARTTRANSFER
;
652 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
656 dep
->flags
|= DWC3_EP_BUSY
;
658 dep
->resource_index
= dwc3_gadget_ep_get_transfer_index(dep
);
659 WARN_ON_ONCE(!dep
->resource_index
);
664 trace_dwc3_gadget_ep_enable(dep
);
669 static void dwc3_stop_active_transfer(struct dwc3
*dwc
, u32 epnum
, bool force
);
670 static void dwc3_remove_requests(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
672 struct dwc3_request
*req
;
674 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
676 /* - giveback all requests to gadget driver */
677 while (!list_empty(&dep
->started_list
)) {
678 req
= next_request(&dep
->started_list
);
680 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
683 while (!list_empty(&dep
->pending_list
)) {
684 req
= next_request(&dep
->pending_list
);
686 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
691 * __dwc3_gadget_ep_disable - Disables a HW endpoint
692 * @dep: the endpoint to disable
694 * This function also removes requests which are currently processed ny the
695 * hardware and those which are not yet scheduled.
696 * Caller should take care of locking.
698 static int __dwc3_gadget_ep_disable(struct dwc3_ep
*dep
)
700 struct dwc3
*dwc
= dep
->dwc
;
703 trace_dwc3_gadget_ep_disable(dep
);
705 dwc3_remove_requests(dwc
, dep
);
707 /* make sure HW endpoint isn't stalled */
708 if (dep
->flags
& DWC3_EP_STALL
)
709 __dwc3_gadget_ep_set_halt(dep
, 0, false);
711 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
712 reg
&= ~DWC3_DALEPENA_EP(dep
->number
);
713 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
715 dep
->stream_capable
= false;
717 dep
->flags
&= DWC3_EP_END_TRANSFER_PENDING
;
719 /* Clear out the ep descriptors for non-ep0 */
720 if (dep
->number
> 1) {
721 dep
->endpoint
.comp_desc
= NULL
;
722 dep
->endpoint
.desc
= NULL
;
728 /* -------------------------------------------------------------------------- */
730 static int dwc3_gadget_ep0_enable(struct usb_ep
*ep
,
731 const struct usb_endpoint_descriptor
*desc
)
736 static int dwc3_gadget_ep0_disable(struct usb_ep
*ep
)
741 /* -------------------------------------------------------------------------- */
743 static int dwc3_gadget_ep_enable(struct usb_ep
*ep
,
744 const struct usb_endpoint_descriptor
*desc
)
751 if (!ep
|| !desc
|| desc
->bDescriptorType
!= USB_DT_ENDPOINT
) {
752 pr_debug("dwc3: invalid parameters\n");
756 if (!desc
->wMaxPacketSize
) {
757 pr_debug("dwc3: missing wMaxPacketSize\n");
761 dep
= to_dwc3_ep(ep
);
764 if (dev_WARN_ONCE(dwc
->dev
, dep
->flags
& DWC3_EP_ENABLED
,
765 "%s is already enabled\n",
769 spin_lock_irqsave(&dwc
->lock
, flags
);
770 ret
= __dwc3_gadget_ep_enable(dep
, false, false);
771 spin_unlock_irqrestore(&dwc
->lock
, flags
);
776 static int dwc3_gadget_ep_disable(struct usb_ep
*ep
)
784 pr_debug("dwc3: invalid parameters\n");
788 dep
= to_dwc3_ep(ep
);
791 if (dev_WARN_ONCE(dwc
->dev
, !(dep
->flags
& DWC3_EP_ENABLED
),
792 "%s is already disabled\n",
796 spin_lock_irqsave(&dwc
->lock
, flags
);
797 ret
= __dwc3_gadget_ep_disable(dep
);
798 spin_unlock_irqrestore(&dwc
->lock
, flags
);
803 static struct usb_request
*dwc3_gadget_ep_alloc_request(struct usb_ep
*ep
,
806 struct dwc3_request
*req
;
807 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
809 req
= kzalloc(sizeof(*req
), gfp_flags
);
813 req
->epnum
= dep
->number
;
816 dep
->allocated_requests
++;
818 trace_dwc3_alloc_request(req
);
820 return &req
->request
;
823 static void dwc3_gadget_ep_free_request(struct usb_ep
*ep
,
824 struct usb_request
*request
)
826 struct dwc3_request
*req
= to_dwc3_request(request
);
827 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
829 dep
->allocated_requests
--;
830 trace_dwc3_free_request(req
);
834 static u32
dwc3_calc_trbs_left(struct dwc3_ep
*dep
);
837 * dwc3_prepare_one_trb - setup one TRB from one request
838 * @dep: endpoint for which this request is prepared
839 * @req: dwc3_request pointer
841 static void dwc3_prepare_one_trb(struct dwc3_ep
*dep
,
842 struct dwc3_request
*req
, dma_addr_t dma
,
843 unsigned length
, unsigned chain
, unsigned node
)
845 struct dwc3_trb
*trb
;
846 struct dwc3
*dwc
= dep
->dwc
;
847 struct usb_gadget
*gadget
= &dwc
->gadget
;
848 enum usb_device_speed speed
= gadget
->speed
;
850 trb
= &dep
->trb_pool
[dep
->trb_enqueue
];
853 dwc3_gadget_move_started_request(req
);
855 req
->trb_dma
= dwc3_trb_dma_offset(dep
, trb
);
856 dep
->queued_requests
++;
859 dwc3_ep_inc_enq(dep
);
861 trb
->size
= DWC3_TRB_SIZE_LENGTH(length
);
862 trb
->bpl
= lower_32_bits(dma
);
863 trb
->bph
= upper_32_bits(dma
);
865 switch (usb_endpoint_type(dep
->endpoint
.desc
)) {
866 case USB_ENDPOINT_XFER_CONTROL
:
867 trb
->ctrl
= DWC3_TRBCTL_CONTROL_SETUP
;
870 case USB_ENDPOINT_XFER_ISOC
:
872 trb
->ctrl
= DWC3_TRBCTL_ISOCHRONOUS_FIRST
;
874 if (speed
== USB_SPEED_HIGH
) {
875 struct usb_ep
*ep
= &dep
->endpoint
;
876 trb
->size
|= DWC3_TRB_SIZE_PCM1(ep
->mult
- 1);
879 trb
->ctrl
= DWC3_TRBCTL_ISOCHRONOUS
;
882 /* always enable Interrupt on Missed ISOC */
883 trb
->ctrl
|= DWC3_TRB_CTRL_ISP_IMI
;
886 case USB_ENDPOINT_XFER_BULK
:
887 case USB_ENDPOINT_XFER_INT
:
888 trb
->ctrl
= DWC3_TRBCTL_NORMAL
;
892 * This is only possible with faulty memory because we
893 * checked it already :)
895 dev_WARN(dwc
->dev
, "Unknown endpoint type %d\n",
896 usb_endpoint_type(dep
->endpoint
.desc
));
899 /* always enable Continue on Short Packet */
900 if (usb_endpoint_dir_out(dep
->endpoint
.desc
)) {
901 trb
->ctrl
|= DWC3_TRB_CTRL_CSP
;
903 if (req
->request
.short_not_ok
)
904 trb
->ctrl
|= DWC3_TRB_CTRL_ISP_IMI
;
907 if ((!req
->request
.no_interrupt
&& !chain
) ||
908 (dwc3_calc_trbs_left(dep
) == 0))
909 trb
->ctrl
|= DWC3_TRB_CTRL_IOC
;
912 trb
->ctrl
|= DWC3_TRB_CTRL_CHN
;
914 if (usb_endpoint_xfer_bulk(dep
->endpoint
.desc
) && dep
->stream_capable
)
915 trb
->ctrl
|= DWC3_TRB_CTRL_SID_SOFN(req
->request
.stream_id
);
917 trb
->ctrl
|= DWC3_TRB_CTRL_HWO
;
919 trace_dwc3_prepare_trb(dep
, trb
);
923 * dwc3_ep_prev_trb() - Returns the previous TRB in the ring
924 * @dep: The endpoint with the TRB ring
925 * @index: The index of the current TRB in the ring
927 * Returns the TRB prior to the one pointed to by the index. If the
928 * index is 0, we will wrap backwards, skip the link TRB, and return
929 * the one just before that.
931 static struct dwc3_trb
*dwc3_ep_prev_trb(struct dwc3_ep
*dep
, u8 index
)
936 tmp
= DWC3_TRB_NUM
- 1;
938 return &dep
->trb_pool
[tmp
- 1];
941 static u32
dwc3_calc_trbs_left(struct dwc3_ep
*dep
)
943 struct dwc3_trb
*tmp
;
944 struct dwc3
*dwc
= dep
->dwc
;
948 * If enqueue & dequeue are equal than it is either full or empty.
950 * One way to know for sure is if the TRB right before us has HWO bit
951 * set or not. If it has, then we're definitely full and can't fit any
952 * more transfers in our ring.
954 if (dep
->trb_enqueue
== dep
->trb_dequeue
) {
955 tmp
= dwc3_ep_prev_trb(dep
, dep
->trb_enqueue
);
956 if (dev_WARN_ONCE(dwc
->dev
, tmp
->ctrl
& DWC3_TRB_CTRL_HWO
,
957 "%s No TRBS left\n", dep
->name
))
960 return DWC3_TRB_NUM
- 1;
963 trbs_left
= dep
->trb_dequeue
- dep
->trb_enqueue
;
964 trbs_left
&= (DWC3_TRB_NUM
- 1);
966 if (dep
->trb_dequeue
< dep
->trb_enqueue
)
972 static void dwc3_prepare_one_trb_sg(struct dwc3_ep
*dep
,
973 struct dwc3_request
*req
)
975 struct scatterlist
*sg
= req
->sg
;
976 struct scatterlist
*s
;
981 for_each_sg(sg
, s
, req
->num_pending_sgs
, i
) {
982 unsigned chain
= true;
984 length
= sg_dma_len(s
);
985 dma
= sg_dma_address(s
);
990 dwc3_prepare_one_trb(dep
, req
, dma
, length
,
993 if (!dwc3_calc_trbs_left(dep
))
998 static void dwc3_prepare_one_trb_linear(struct dwc3_ep
*dep
,
999 struct dwc3_request
*req
)
1001 unsigned int length
;
1004 dma
= req
->request
.dma
;
1005 length
= req
->request
.length
;
1007 dwc3_prepare_one_trb(dep
, req
, dma
, length
,
1012 * dwc3_prepare_trbs - setup TRBs from requests
1013 * @dep: endpoint for which requests are being prepared
1015 * The function goes through the requests list and sets up TRBs for the
1016 * transfers. The function returns once there are no more TRBs available or
1017 * it runs out of requests.
1019 static void dwc3_prepare_trbs(struct dwc3_ep
*dep
)
1021 struct dwc3_request
*req
, *n
;
1023 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM
);
1025 if (!dwc3_calc_trbs_left(dep
))
1029 * We can get in a situation where there's a request in the started list
1030 * but there weren't enough TRBs to fully kick it in the first time
1031 * around, so it has been waiting for more TRBs to be freed up.
1033 * In that case, we should check if we have a request with pending_sgs
1034 * in the started list and prepare TRBs for that request first,
1035 * otherwise we will prepare TRBs completely out of order and that will
1038 list_for_each_entry(req
, &dep
->started_list
, list
) {
1039 if (req
->num_pending_sgs
> 0)
1040 dwc3_prepare_one_trb_sg(dep
, req
);
1042 if (!dwc3_calc_trbs_left(dep
))
1046 list_for_each_entry_safe(req
, n
, &dep
->pending_list
, list
) {
1047 if (req
->num_pending_sgs
> 0)
1048 dwc3_prepare_one_trb_sg(dep
, req
);
1050 dwc3_prepare_one_trb_linear(dep
, req
);
1052 if (!dwc3_calc_trbs_left(dep
))
1057 static int __dwc3_gadget_kick_transfer(struct dwc3_ep
*dep
, u16 cmd_param
)
1059 struct dwc3_gadget_ep_cmd_params params
;
1060 struct dwc3_request
*req
;
1065 starting
= !(dep
->flags
& DWC3_EP_BUSY
);
1067 dwc3_prepare_trbs(dep
);
1068 req
= next_request(&dep
->started_list
);
1070 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
1074 memset(¶ms
, 0, sizeof(params
));
1077 params
.param0
= upper_32_bits(req
->trb_dma
);
1078 params
.param1
= lower_32_bits(req
->trb_dma
);
1079 cmd
= DWC3_DEPCMD_STARTTRANSFER
|
1080 DWC3_DEPCMD_PARAM(cmd_param
);
1082 cmd
= DWC3_DEPCMD_UPDATETRANSFER
|
1083 DWC3_DEPCMD_PARAM(dep
->resource_index
);
1086 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
1089 * FIXME we need to iterate over the list of requests
1090 * here and stop, unmap, free and del each of the linked
1091 * requests instead of what we do now.
1094 memset(req
->trb
, 0, sizeof(struct dwc3_trb
));
1095 dep
->queued_requests
--;
1096 dwc3_gadget_giveback(dep
, req
, ret
);
1100 dep
->flags
|= DWC3_EP_BUSY
;
1103 dep
->resource_index
= dwc3_gadget_ep_get_transfer_index(dep
);
1104 WARN_ON_ONCE(!dep
->resource_index
);
1110 static int __dwc3_gadget_get_frame(struct dwc3
*dwc
)
1114 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1115 return DWC3_DSTS_SOFFN(reg
);
1118 static void __dwc3_gadget_start_isoc(struct dwc3
*dwc
,
1119 struct dwc3_ep
*dep
, u32 cur_uf
)
1123 if (list_empty(&dep
->pending_list
)) {
1124 dev_info(dwc
->dev
, "%s: ran out of requests\n",
1126 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
1130 /* 4 micro frames in the future */
1131 uf
= cur_uf
+ dep
->interval
* 4;
1133 __dwc3_gadget_kick_transfer(dep
, uf
);
1136 static void dwc3_gadget_start_isoc(struct dwc3
*dwc
,
1137 struct dwc3_ep
*dep
, const struct dwc3_event_depevt
*event
)
1141 mask
= ~(dep
->interval
- 1);
1142 cur_uf
= event
->parameters
& mask
;
1144 __dwc3_gadget_start_isoc(dwc
, dep
, cur_uf
);
1147 static int __dwc3_gadget_ep_queue(struct dwc3_ep
*dep
, struct dwc3_request
*req
)
1149 struct dwc3
*dwc
= dep
->dwc
;
1152 if (!dep
->endpoint
.desc
) {
1153 dev_err(dwc
->dev
, "%s: can't queue to disabled endpoint\n",
1158 if (WARN(req
->dep
!= dep
, "request %p belongs to '%s'\n",
1159 &req
->request
, req
->dep
->name
)) {
1160 dev_err(dwc
->dev
, "%s: request %p belongs to '%s'\n",
1161 dep
->name
, &req
->request
, req
->dep
->name
);
1165 pm_runtime_get(dwc
->dev
);
1167 req
->request
.actual
= 0;
1168 req
->request
.status
= -EINPROGRESS
;
1169 req
->direction
= dep
->direction
;
1170 req
->epnum
= dep
->number
;
1172 trace_dwc3_ep_queue(req
);
1174 ret
= usb_gadget_map_request_by_dev(dwc
->sysdev
, &req
->request
,
1179 req
->sg
= req
->request
.sg
;
1180 req
->num_pending_sgs
= req
->request
.num_mapped_sgs
;
1182 list_add_tail(&req
->list
, &dep
->pending_list
);
1185 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1186 * wait for a XferNotReady event so we will know what's the current
1187 * (micro-)frame number.
1189 * Without this trick, we are very, very likely gonna get Bus Expiry
1190 * errors which will force us issue EndTransfer command.
1192 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1193 if ((dep
->flags
& DWC3_EP_PENDING_REQUEST
)) {
1194 if (dep
->flags
& DWC3_EP_TRANSFER_STARTED
) {
1195 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
1196 dep
->flags
= DWC3_EP_ENABLED
;
1200 cur_uf
= __dwc3_gadget_get_frame(dwc
);
1201 __dwc3_gadget_start_isoc(dwc
, dep
, cur_uf
);
1202 dep
->flags
&= ~DWC3_EP_PENDING_REQUEST
;
1208 if (!dwc3_calc_trbs_left(dep
))
1211 ret
= __dwc3_gadget_kick_transfer(dep
, 0);
1218 static void __dwc3_gadget_ep_zlp_complete(struct usb_ep
*ep
,
1219 struct usb_request
*request
)
1221 dwc3_gadget_ep_free_request(ep
, request
);
1224 static int __dwc3_gadget_ep_queue_zlp(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
1226 struct dwc3_request
*req
;
1227 struct usb_request
*request
;
1228 struct usb_ep
*ep
= &dep
->endpoint
;
1230 request
= dwc3_gadget_ep_alloc_request(ep
, GFP_ATOMIC
);
1234 request
->length
= 0;
1235 request
->buf
= dwc
->zlp_buf
;
1236 request
->complete
= __dwc3_gadget_ep_zlp_complete
;
1238 req
= to_dwc3_request(request
);
1240 return __dwc3_gadget_ep_queue(dep
, req
);
1243 static int dwc3_gadget_ep_queue(struct usb_ep
*ep
, struct usb_request
*request
,
1246 struct dwc3_request
*req
= to_dwc3_request(request
);
1247 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1248 struct dwc3
*dwc
= dep
->dwc
;
1250 unsigned long flags
;
1254 spin_lock_irqsave(&dwc
->lock
, flags
);
1255 ret
= __dwc3_gadget_ep_queue(dep
, req
);
1258 * Okay, here's the thing, if gadget driver has requested for a ZLP by
1259 * setting request->zero, instead of doing magic, we will just queue an
1260 * extra usb_request ourselves so that it gets handled the same way as
1261 * any other request.
1263 if (ret
== 0 && request
->zero
&& request
->length
&&
1264 (request
->length
% ep
->maxpacket
== 0))
1265 ret
= __dwc3_gadget_ep_queue_zlp(dwc
, dep
);
1267 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1272 static int dwc3_gadget_ep_dequeue(struct usb_ep
*ep
,
1273 struct usb_request
*request
)
1275 struct dwc3_request
*req
= to_dwc3_request(request
);
1276 struct dwc3_request
*r
= NULL
;
1278 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1279 struct dwc3
*dwc
= dep
->dwc
;
1281 unsigned long flags
;
1284 trace_dwc3_ep_dequeue(req
);
1286 spin_lock_irqsave(&dwc
->lock
, flags
);
1288 list_for_each_entry(r
, &dep
->pending_list
, list
) {
1294 list_for_each_entry(r
, &dep
->started_list
, list
) {
1299 /* wait until it is processed */
1300 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
1303 dev_err(dwc
->dev
, "request %p was not queued to %s\n",
1310 /* giveback the request */
1311 dwc3_gadget_giveback(dep
, req
, -ECONNRESET
);
1314 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1319 int __dwc3_gadget_ep_set_halt(struct dwc3_ep
*dep
, int value
, int protocol
)
1321 struct dwc3_gadget_ep_cmd_params params
;
1322 struct dwc3
*dwc
= dep
->dwc
;
1325 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1326 dev_err(dwc
->dev
, "%s is of Isochronous type\n", dep
->name
);
1330 memset(¶ms
, 0x00, sizeof(params
));
1333 struct dwc3_trb
*trb
;
1335 unsigned transfer_in_flight
;
1338 if (dep
->number
> 1)
1339 trb
= dwc3_ep_prev_trb(dep
, dep
->trb_enqueue
);
1341 trb
= &dwc
->ep0_trb
[dep
->trb_enqueue
];
1343 transfer_in_flight
= trb
->ctrl
& DWC3_TRB_CTRL_HWO
;
1344 started
= !list_empty(&dep
->started_list
);
1346 if (!protocol
&& ((dep
->direction
&& transfer_in_flight
) ||
1347 (!dep
->direction
&& started
))) {
1351 ret
= dwc3_send_gadget_ep_cmd(dep
, DWC3_DEPCMD_SETSTALL
,
1354 dev_err(dwc
->dev
, "failed to set STALL on %s\n",
1357 dep
->flags
|= DWC3_EP_STALL
;
1360 ret
= dwc3_send_clear_stall_ep_cmd(dep
);
1362 dev_err(dwc
->dev
, "failed to clear STALL on %s\n",
1365 dep
->flags
&= ~(DWC3_EP_STALL
| DWC3_EP_WEDGE
);
1371 static int dwc3_gadget_ep_set_halt(struct usb_ep
*ep
, int value
)
1373 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1374 struct dwc3
*dwc
= dep
->dwc
;
1376 unsigned long flags
;
1380 spin_lock_irqsave(&dwc
->lock
, flags
);
1381 ret
= __dwc3_gadget_ep_set_halt(dep
, value
, false);
1382 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1387 static int dwc3_gadget_ep_set_wedge(struct usb_ep
*ep
)
1389 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1390 struct dwc3
*dwc
= dep
->dwc
;
1391 unsigned long flags
;
1394 spin_lock_irqsave(&dwc
->lock
, flags
);
1395 dep
->flags
|= DWC3_EP_WEDGE
;
1397 if (dep
->number
== 0 || dep
->number
== 1)
1398 ret
= __dwc3_gadget_ep0_set_halt(ep
, 1);
1400 ret
= __dwc3_gadget_ep_set_halt(dep
, 1, false);
1401 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1406 /* -------------------------------------------------------------------------- */
1408 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc
= {
1409 .bLength
= USB_DT_ENDPOINT_SIZE
,
1410 .bDescriptorType
= USB_DT_ENDPOINT
,
1411 .bmAttributes
= USB_ENDPOINT_XFER_CONTROL
,
1414 static const struct usb_ep_ops dwc3_gadget_ep0_ops
= {
1415 .enable
= dwc3_gadget_ep0_enable
,
1416 .disable
= dwc3_gadget_ep0_disable
,
1417 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1418 .free_request
= dwc3_gadget_ep_free_request
,
1419 .queue
= dwc3_gadget_ep0_queue
,
1420 .dequeue
= dwc3_gadget_ep_dequeue
,
1421 .set_halt
= dwc3_gadget_ep0_set_halt
,
1422 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1425 static const struct usb_ep_ops dwc3_gadget_ep_ops
= {
1426 .enable
= dwc3_gadget_ep_enable
,
1427 .disable
= dwc3_gadget_ep_disable
,
1428 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1429 .free_request
= dwc3_gadget_ep_free_request
,
1430 .queue
= dwc3_gadget_ep_queue
,
1431 .dequeue
= dwc3_gadget_ep_dequeue
,
1432 .set_halt
= dwc3_gadget_ep_set_halt
,
1433 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1436 /* -------------------------------------------------------------------------- */
1438 static int dwc3_gadget_get_frame(struct usb_gadget
*g
)
1440 struct dwc3
*dwc
= gadget_to_dwc(g
);
1442 return __dwc3_gadget_get_frame(dwc
);
1445 static int __dwc3_gadget_wakeup(struct dwc3
*dwc
)
1456 * According to the Databook Remote wakeup request should
1457 * be issued only when the device is in early suspend state.
1459 * We can check that via USB Link State bits in DSTS register.
1461 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1463 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
1464 if ((speed
== DWC3_DSTS_SUPERSPEED
) ||
1465 (speed
== DWC3_DSTS_SUPERSPEED_PLUS
))
1468 link_state
= DWC3_DSTS_USBLNKST(reg
);
1470 switch (link_state
) {
1471 case DWC3_LINK_STATE_RX_DET
: /* in HS, means Early Suspend */
1472 case DWC3_LINK_STATE_U3
: /* in HS, means SUSPEND */
1478 ret
= dwc3_gadget_set_link_state(dwc
, DWC3_LINK_STATE_RECOV
);
1480 dev_err(dwc
->dev
, "failed to put link in Recovery\n");
1484 /* Recent versions do this automatically */
1485 if (dwc
->revision
< DWC3_REVISION_194A
) {
1486 /* write zeroes to Link Change Request */
1487 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1488 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
1489 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1492 /* poll until Link State changes to ON */
1496 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1498 /* in HS, means ON */
1499 if (DWC3_DSTS_USBLNKST(reg
) == DWC3_LINK_STATE_U0
)
1503 if (DWC3_DSTS_USBLNKST(reg
) != DWC3_LINK_STATE_U0
) {
1504 dev_err(dwc
->dev
, "failed to send remote wakeup\n");
1511 static int dwc3_gadget_wakeup(struct usb_gadget
*g
)
1513 struct dwc3
*dwc
= gadget_to_dwc(g
);
1514 unsigned long flags
;
1517 spin_lock_irqsave(&dwc
->lock
, flags
);
1518 ret
= __dwc3_gadget_wakeup(dwc
);
1519 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1524 static int dwc3_gadget_set_selfpowered(struct usb_gadget
*g
,
1527 struct dwc3
*dwc
= gadget_to_dwc(g
);
1528 unsigned long flags
;
1530 spin_lock_irqsave(&dwc
->lock
, flags
);
1531 g
->is_selfpowered
= !!is_selfpowered
;
1532 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1537 static int dwc3_gadget_run_stop(struct dwc3
*dwc
, int is_on
, int suspend
)
1542 if (pm_runtime_suspended(dwc
->dev
))
1545 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1547 if (dwc
->revision
<= DWC3_REVISION_187A
) {
1548 reg
&= ~DWC3_DCTL_TRGTULST_MASK
;
1549 reg
|= DWC3_DCTL_TRGTULST_RX_DET
;
1552 if (dwc
->revision
>= DWC3_REVISION_194A
)
1553 reg
&= ~DWC3_DCTL_KEEP_CONNECT
;
1554 reg
|= DWC3_DCTL_RUN_STOP
;
1556 if (dwc
->has_hibernation
)
1557 reg
|= DWC3_DCTL_KEEP_CONNECT
;
1559 dwc
->pullups_connected
= true;
1561 reg
&= ~DWC3_DCTL_RUN_STOP
;
1563 if (dwc
->has_hibernation
&& !suspend
)
1564 reg
&= ~DWC3_DCTL_KEEP_CONNECT
;
1566 dwc
->pullups_connected
= false;
1569 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1572 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1573 reg
&= DWC3_DSTS_DEVCTRLHLT
;
1574 } while (--timeout
&& !(!is_on
^ !reg
));
1582 static int dwc3_gadget_pullup(struct usb_gadget
*g
, int is_on
)
1584 struct dwc3
*dwc
= gadget_to_dwc(g
);
1585 unsigned long flags
;
1591 * Per databook, when we want to stop the gadget, if a control transfer
1592 * is still in process, complete it and get the core into setup phase.
1594 if (!is_on
&& dwc
->ep0state
!= EP0_SETUP_PHASE
) {
1595 reinit_completion(&dwc
->ep0_in_setup
);
1597 ret
= wait_for_completion_timeout(&dwc
->ep0_in_setup
,
1598 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT
));
1600 dev_err(dwc
->dev
, "timed out waiting for SETUP phase\n");
1605 spin_lock_irqsave(&dwc
->lock
, flags
);
1606 ret
= dwc3_gadget_run_stop(dwc
, is_on
, false);
1607 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1612 static void dwc3_gadget_enable_irq(struct dwc3
*dwc
)
1616 /* Enable all but Start and End of Frame IRQs */
1617 reg
= (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN
|
1618 DWC3_DEVTEN_EVNTOVERFLOWEN
|
1619 DWC3_DEVTEN_CMDCMPLTEN
|
1620 DWC3_DEVTEN_ERRTICERREN
|
1621 DWC3_DEVTEN_WKUPEVTEN
|
1622 DWC3_DEVTEN_CONNECTDONEEN
|
1623 DWC3_DEVTEN_USBRSTEN
|
1624 DWC3_DEVTEN_DISCONNEVTEN
);
1626 if (dwc
->revision
< DWC3_REVISION_250A
)
1627 reg
|= DWC3_DEVTEN_ULSTCNGEN
;
1629 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, reg
);
1632 static void dwc3_gadget_disable_irq(struct dwc3
*dwc
)
1634 /* mask all interrupts */
1635 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, 0x00);
1638 static irqreturn_t
dwc3_interrupt(int irq
, void *_dwc
);
1639 static irqreturn_t
dwc3_thread_interrupt(int irq
, void *_dwc
);
1642 * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG
1643 * dwc: pointer to our context structure
1645 * The following looks like complex but it's actually very simple. In order to
1646 * calculate the number of packets we can burst at once on OUT transfers, we're
1647 * gonna use RxFIFO size.
1649 * To calculate RxFIFO size we need two numbers:
1650 * MDWIDTH = size, in bits, of the internal memory bus
1651 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1653 * Given these two numbers, the formula is simple:
1655 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1657 * 24 bytes is for 3x SETUP packets
1658 * 16 bytes is a clock domain crossing tolerance
1660 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1662 static void dwc3_gadget_setup_nump(struct dwc3
*dwc
)
1669 ram2_depth
= DWC3_GHWPARAMS7_RAM2_DEPTH(dwc
->hwparams
.hwparams7
);
1670 mdwidth
= DWC3_GHWPARAMS0_MDWIDTH(dwc
->hwparams
.hwparams0
);
1672 nump
= ((ram2_depth
* mdwidth
/ 8) - 24 - 16) / 1024;
1673 nump
= min_t(u32
, nump
, 16);
1676 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
1677 reg
&= ~DWC3_DCFG_NUMP_MASK
;
1678 reg
|= nump
<< DWC3_DCFG_NUMP_SHIFT
;
1679 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
1682 static int __dwc3_gadget_start(struct dwc3
*dwc
)
1684 struct dwc3_ep
*dep
;
1689 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1690 * the core supports IMOD, disable it.
1692 if (dwc
->imod_interval
) {
1693 dwc3_writel(dwc
->regs
, DWC3_DEV_IMOD(0), dwc
->imod_interval
);
1694 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB
);
1695 } else if (dwc3_has_imod(dwc
)) {
1696 dwc3_writel(dwc
->regs
, DWC3_DEV_IMOD(0), 0);
1699 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
1700 reg
&= ~(DWC3_DCFG_SPEED_MASK
);
1703 * WORKAROUND: DWC3 revision < 2.20a have an issue
1704 * which would cause metastability state on Run/Stop
1705 * bit if we try to force the IP to USB2-only mode.
1707 * Because of that, we cannot configure the IP to any
1708 * speed other than the SuperSpeed
1712 * STAR#9000525659: Clock Domain Crossing on DCTL in
1715 if (dwc
->revision
< DWC3_REVISION_220A
) {
1716 reg
|= DWC3_DCFG_SUPERSPEED
;
1718 switch (dwc
->maximum_speed
) {
1720 reg
|= DWC3_DCFG_LOWSPEED
;
1722 case USB_SPEED_FULL
:
1723 reg
|= DWC3_DCFG_FULLSPEED
;
1725 case USB_SPEED_HIGH
:
1726 reg
|= DWC3_DCFG_HIGHSPEED
;
1728 case USB_SPEED_SUPER_PLUS
:
1729 reg
|= DWC3_DCFG_SUPERSPEED_PLUS
;
1732 dev_err(dwc
->dev
, "invalid dwc->maximum_speed (%d)\n",
1733 dwc
->maximum_speed
);
1735 case USB_SPEED_SUPER
:
1736 reg
|= DWC3_DCFG_SUPERSPEED
;
1740 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
1743 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1744 * field instead of letting dwc3 itself calculate that automatically.
1746 * This way, we maximize the chances that we'll be able to get several
1747 * bursts of data without going through any sort of endpoint throttling.
1749 reg
= dwc3_readl(dwc
->regs
, DWC3_GRXTHRCFG
);
1750 reg
&= ~DWC3_GRXTHRCFG_PKTCNTSEL
;
1751 dwc3_writel(dwc
->regs
, DWC3_GRXTHRCFG
, reg
);
1753 dwc3_gadget_setup_nump(dwc
);
1755 /* Start with SuperSpeed Default */
1756 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
1759 ret
= __dwc3_gadget_ep_enable(dep
, false, false);
1761 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1766 ret
= __dwc3_gadget_ep_enable(dep
, false, false);
1768 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1772 /* begin to receive SETUP packets */
1773 dwc
->ep0state
= EP0_SETUP_PHASE
;
1774 dwc3_ep0_out_start(dwc
);
1776 dwc3_gadget_enable_irq(dwc
);
1781 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
1787 static int dwc3_gadget_start(struct usb_gadget
*g
,
1788 struct usb_gadget_driver
*driver
)
1790 struct dwc3
*dwc
= gadget_to_dwc(g
);
1791 unsigned long flags
;
1795 irq
= dwc
->irq_gadget
;
1796 ret
= request_threaded_irq(irq
, dwc3_interrupt
, dwc3_thread_interrupt
,
1797 IRQF_SHARED
, "dwc3", dwc
->ev_buf
);
1799 dev_err(dwc
->dev
, "failed to request irq #%d --> %d\n",
1804 spin_lock_irqsave(&dwc
->lock
, flags
);
1805 if (dwc
->gadget_driver
) {
1806 dev_err(dwc
->dev
, "%s is already bound to %s\n",
1808 dwc
->gadget_driver
->driver
.name
);
1813 dwc
->gadget_driver
= driver
;
1815 if (pm_runtime_active(dwc
->dev
))
1816 __dwc3_gadget_start(dwc
);
1818 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1823 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1830 static void __dwc3_gadget_stop(struct dwc3
*dwc
)
1832 dwc3_gadget_disable_irq(dwc
);
1833 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
1834 __dwc3_gadget_ep_disable(dwc
->eps
[1]);
1837 static int dwc3_gadget_stop(struct usb_gadget
*g
)
1839 struct dwc3
*dwc
= gadget_to_dwc(g
);
1840 unsigned long flags
;
1843 spin_lock_irqsave(&dwc
->lock
, flags
);
1845 if (pm_runtime_suspended(dwc
->dev
))
1848 __dwc3_gadget_stop(dwc
);
1850 for (epnum
= 2; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
1851 struct dwc3_ep
*dep
= dwc
->eps
[epnum
];
1856 if (!(dep
->flags
& DWC3_EP_END_TRANSFER_PENDING
))
1859 wait_event_lock_irq(dep
->wait_end_transfer
,
1860 !(dep
->flags
& DWC3_EP_END_TRANSFER_PENDING
),
1865 dwc
->gadget_driver
= NULL
;
1866 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1868 free_irq(dwc
->irq_gadget
, dwc
->ev_buf
);
1873 static const struct usb_gadget_ops dwc3_gadget_ops
= {
1874 .get_frame
= dwc3_gadget_get_frame
,
1875 .wakeup
= dwc3_gadget_wakeup
,
1876 .set_selfpowered
= dwc3_gadget_set_selfpowered
,
1877 .pullup
= dwc3_gadget_pullup
,
1878 .udc_start
= dwc3_gadget_start
,
1879 .udc_stop
= dwc3_gadget_stop
,
1882 /* -------------------------------------------------------------------------- */
1884 static int dwc3_gadget_init_hw_endpoints(struct dwc3
*dwc
,
1885 u8 num
, u32 direction
)
1887 struct dwc3_ep
*dep
;
1890 for (i
= 0; i
< num
; i
++) {
1891 u8 epnum
= (i
<< 1) | (direction
? 1 : 0);
1893 dep
= kzalloc(sizeof(*dep
), GFP_KERNEL
);
1898 dep
->number
= epnum
;
1899 dep
->direction
= !!direction
;
1900 dep
->regs
= dwc
->regs
+ DWC3_DEP_BASE(epnum
);
1901 dwc
->eps
[epnum
] = dep
;
1903 snprintf(dep
->name
, sizeof(dep
->name
), "ep%d%s", epnum
>> 1,
1904 (epnum
& 1) ? "in" : "out");
1906 dep
->endpoint
.name
= dep
->name
;
1908 if (!(dep
->number
> 1)) {
1909 dep
->endpoint
.desc
= &dwc3_gadget_ep0_desc
;
1910 dep
->endpoint
.comp_desc
= NULL
;
1913 spin_lock_init(&dep
->lock
);
1915 if (epnum
== 0 || epnum
== 1) {
1916 usb_ep_set_maxpacket_limit(&dep
->endpoint
, 512);
1917 dep
->endpoint
.maxburst
= 1;
1918 dep
->endpoint
.ops
= &dwc3_gadget_ep0_ops
;
1920 dwc
->gadget
.ep0
= &dep
->endpoint
;
1924 usb_ep_set_maxpacket_limit(&dep
->endpoint
, 1024);
1925 dep
->endpoint
.max_streams
= 15;
1926 dep
->endpoint
.ops
= &dwc3_gadget_ep_ops
;
1927 list_add_tail(&dep
->endpoint
.ep_list
,
1928 &dwc
->gadget
.ep_list
);
1930 ret
= dwc3_alloc_trb_pool(dep
);
1935 if (epnum
== 0 || epnum
== 1) {
1936 dep
->endpoint
.caps
.type_control
= true;
1938 dep
->endpoint
.caps
.type_iso
= true;
1939 dep
->endpoint
.caps
.type_bulk
= true;
1940 dep
->endpoint
.caps
.type_int
= true;
1943 dep
->endpoint
.caps
.dir_in
= !!direction
;
1944 dep
->endpoint
.caps
.dir_out
= !direction
;
1946 INIT_LIST_HEAD(&dep
->pending_list
);
1947 INIT_LIST_HEAD(&dep
->started_list
);
1953 static int dwc3_gadget_init_endpoints(struct dwc3
*dwc
)
1957 INIT_LIST_HEAD(&dwc
->gadget
.ep_list
);
1959 ret
= dwc3_gadget_init_hw_endpoints(dwc
, dwc
->num_out_eps
, 0);
1961 dev_err(dwc
->dev
, "failed to initialize OUT endpoints\n");
1965 ret
= dwc3_gadget_init_hw_endpoints(dwc
, dwc
->num_in_eps
, 1);
1967 dev_err(dwc
->dev
, "failed to initialize IN endpoints\n");
1974 static void dwc3_gadget_free_endpoints(struct dwc3
*dwc
)
1976 struct dwc3_ep
*dep
;
1979 for (epnum
= 0; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
1980 dep
= dwc
->eps
[epnum
];
1984 * Physical endpoints 0 and 1 are special; they form the
1985 * bi-directional USB endpoint 0.
1987 * For those two physical endpoints, we don't allocate a TRB
1988 * pool nor do we add them the endpoints list. Due to that, we
1989 * shouldn't do these two operations otherwise we would end up
1990 * with all sorts of bugs when removing dwc3.ko.
1992 if (epnum
!= 0 && epnum
!= 1) {
1993 dwc3_free_trb_pool(dep
);
1994 list_del(&dep
->endpoint
.ep_list
);
2001 /* -------------------------------------------------------------------------- */
2003 static int __dwc3_cleanup_done_trbs(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
2004 struct dwc3_request
*req
, struct dwc3_trb
*trb
,
2005 const struct dwc3_event_depevt
*event
, int status
,
2009 unsigned int s_pkt
= 0;
2010 unsigned int trb_status
;
2012 dwc3_ep_inc_deq(dep
);
2014 if (req
->trb
== trb
)
2015 dep
->queued_requests
--;
2017 trace_dwc3_complete_trb(dep
, trb
);
2020 * If we're in the middle of series of chained TRBs and we
2021 * receive a short transfer along the way, DWC3 will skip
2022 * through all TRBs including the last TRB in the chain (the
2023 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2024 * bit and SW has to do it manually.
2026 * We're going to do that here to avoid problems of HW trying
2027 * to use bogus TRBs for transfers.
2029 if (chain
&& (trb
->ctrl
& DWC3_TRB_CTRL_HWO
))
2030 trb
->ctrl
&= ~DWC3_TRB_CTRL_HWO
;
2032 if ((trb
->ctrl
& DWC3_TRB_CTRL_HWO
) && status
!= -ESHUTDOWN
)
2035 count
= trb
->size
& DWC3_TRB_SIZE_MASK
;
2036 req
->remaining
+= count
;
2038 if (dep
->direction
) {
2040 trb_status
= DWC3_TRB_SIZE_TRBSTS(trb
->size
);
2041 if (trb_status
== DWC3_TRBSTS_MISSED_ISOC
) {
2043 * If missed isoc occurred and there is
2044 * no request queued then issue END
2045 * TRANSFER, so that core generates
2046 * next xfernotready and we will issue
2047 * a fresh START TRANSFER.
2048 * If there are still queued request
2049 * then wait, do not issue either END
2050 * or UPDATE TRANSFER, just attach next
2051 * request in pending_list during
2052 * giveback.If any future queued request
2053 * is successfully transferred then we
2054 * will issue UPDATE TRANSFER for all
2055 * request in the pending_list.
2057 dep
->flags
|= DWC3_EP_MISSED_ISOC
;
2059 dev_err(dwc
->dev
, "incomplete IN transfer %s\n",
2061 status
= -ECONNRESET
;
2064 dep
->flags
&= ~DWC3_EP_MISSED_ISOC
;
2067 if (count
&& (event
->status
& DEPEVT_STATUS_SHORT
))
2071 if (s_pkt
&& !chain
)
2074 if ((event
->status
& DEPEVT_STATUS_IOC
) &&
2075 (trb
->ctrl
& DWC3_TRB_CTRL_IOC
))
2081 static int dwc3_cleanup_done_reqs(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
2082 const struct dwc3_event_depevt
*event
, int status
)
2084 struct dwc3_request
*req
, *n
;
2085 struct dwc3_trb
*trb
;
2089 list_for_each_entry_safe(req
, n
, &dep
->started_list
, list
) {
2093 length
= req
->request
.length
;
2094 chain
= req
->num_pending_sgs
> 0;
2096 struct scatterlist
*sg
= req
->sg
;
2097 struct scatterlist
*s
;
2098 unsigned int pending
= req
->num_pending_sgs
;
2101 for_each_sg(sg
, s
, pending
, i
) {
2102 trb
= &dep
->trb_pool
[dep
->trb_dequeue
];
2104 if (trb
->ctrl
& DWC3_TRB_CTRL_HWO
)
2107 req
->sg
= sg_next(s
);
2108 req
->num_pending_sgs
--;
2110 ret
= __dwc3_cleanup_done_trbs(dwc
, dep
, req
, trb
,
2111 event
, status
, chain
);
2116 trb
= &dep
->trb_pool
[dep
->trb_dequeue
];
2117 ret
= __dwc3_cleanup_done_trbs(dwc
, dep
, req
, trb
,
2118 event
, status
, chain
);
2121 req
->request
.actual
= length
- req
->remaining
;
2123 if ((req
->request
.actual
< length
) && req
->num_pending_sgs
)
2124 return __dwc3_gadget_kick_transfer(dep
, 0);
2126 dwc3_gadget_giveback(dep
, req
, status
);
2129 if ((event
->status
& DEPEVT_STATUS_IOC
) &&
2130 (trb
->ctrl
& DWC3_TRB_CTRL_IOC
))
2137 * Our endpoint might get disabled by another thread during
2138 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2139 * early on so DWC3_EP_BUSY flag gets cleared
2141 if (!dep
->endpoint
.desc
)
2144 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) &&
2145 list_empty(&dep
->started_list
)) {
2146 if (list_empty(&dep
->pending_list
)) {
2148 * If there is no entry in request list then do
2149 * not issue END TRANSFER now. Just set PENDING
2150 * flag, so that END TRANSFER is issued when an
2151 * entry is added into request list.
2153 dep
->flags
= DWC3_EP_PENDING_REQUEST
;
2155 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
2156 dep
->flags
= DWC3_EP_ENABLED
;
2161 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) && ioc
)
2167 static void dwc3_endpoint_transfer_complete(struct dwc3
*dwc
,
2168 struct dwc3_ep
*dep
, const struct dwc3_event_depevt
*event
)
2170 unsigned status
= 0;
2172 u32 is_xfer_complete
;
2174 is_xfer_complete
= (event
->endpoint_event
== DWC3_DEPEVT_XFERCOMPLETE
);
2176 if (event
->status
& DEPEVT_STATUS_BUSERR
)
2177 status
= -ECONNRESET
;
2179 clean_busy
= dwc3_cleanup_done_reqs(dwc
, dep
, event
, status
);
2180 if (clean_busy
&& (!dep
->endpoint
.desc
|| is_xfer_complete
||
2181 usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)))
2182 dep
->flags
&= ~DWC3_EP_BUSY
;
2185 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2186 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2188 if (dwc
->revision
< DWC3_REVISION_183A
) {
2192 for (i
= 0; i
< DWC3_ENDPOINTS_NUM
; i
++) {
2195 if (!(dep
->flags
& DWC3_EP_ENABLED
))
2198 if (!list_empty(&dep
->started_list
))
2202 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2204 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2210 * Our endpoint might get disabled by another thread during
2211 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2212 * early on so DWC3_EP_BUSY flag gets cleared
2214 if (!dep
->endpoint
.desc
)
2217 if (!usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
2220 ret
= __dwc3_gadget_kick_transfer(dep
, 0);
2221 if (!ret
|| ret
== -EBUSY
)
2226 static void dwc3_endpoint_interrupt(struct dwc3
*dwc
,
2227 const struct dwc3_event_depevt
*event
)
2229 struct dwc3_ep
*dep
;
2230 u8 epnum
= event
->endpoint_number
;
2233 dep
= dwc
->eps
[epnum
];
2235 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
2236 if (!(dep
->flags
& DWC3_EP_END_TRANSFER_PENDING
))
2239 /* Handle only EPCMDCMPLT when EP disabled */
2240 if (event
->endpoint_event
!= DWC3_DEPEVT_EPCMDCMPLT
)
2244 if (epnum
== 0 || epnum
== 1) {
2245 dwc3_ep0_interrupt(dwc
, event
);
2249 switch (event
->endpoint_event
) {
2250 case DWC3_DEPEVT_XFERCOMPLETE
:
2251 dep
->resource_index
= 0;
2253 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
2254 dev_err(dwc
->dev
, "XferComplete for Isochronous endpoint\n");
2258 dwc3_endpoint_transfer_complete(dwc
, dep
, event
);
2260 case DWC3_DEPEVT_XFERINPROGRESS
:
2261 dwc3_endpoint_transfer_complete(dwc
, dep
, event
);
2263 case DWC3_DEPEVT_XFERNOTREADY
:
2264 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
2265 dwc3_gadget_start_isoc(dwc
, dep
, event
);
2269 ret
= __dwc3_gadget_kick_transfer(dep
, 0);
2270 if (!ret
|| ret
== -EBUSY
)
2275 case DWC3_DEPEVT_STREAMEVT
:
2276 if (!usb_endpoint_xfer_bulk(dep
->endpoint
.desc
)) {
2277 dev_err(dwc
->dev
, "Stream event for non-Bulk %s\n",
2282 case DWC3_DEPEVT_EPCMDCMPLT
:
2283 cmd
= DEPEVT_PARAMETER_CMD(event
->parameters
);
2285 if (cmd
== DWC3_DEPCMD_ENDTRANSFER
) {
2286 dep
->flags
&= ~DWC3_EP_END_TRANSFER_PENDING
;
2287 wake_up(&dep
->wait_end_transfer
);
2290 case DWC3_DEPEVT_RXTXFIFOEVT
:
2295 static void dwc3_disconnect_gadget(struct dwc3
*dwc
)
2297 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->disconnect
) {
2298 spin_unlock(&dwc
->lock
);
2299 dwc
->gadget_driver
->disconnect(&dwc
->gadget
);
2300 spin_lock(&dwc
->lock
);
2304 static void dwc3_suspend_gadget(struct dwc3
*dwc
)
2306 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->suspend
) {
2307 spin_unlock(&dwc
->lock
);
2308 dwc
->gadget_driver
->suspend(&dwc
->gadget
);
2309 spin_lock(&dwc
->lock
);
2313 static void dwc3_resume_gadget(struct dwc3
*dwc
)
2315 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->resume
) {
2316 spin_unlock(&dwc
->lock
);
2317 dwc
->gadget_driver
->resume(&dwc
->gadget
);
2318 spin_lock(&dwc
->lock
);
2322 static void dwc3_reset_gadget(struct dwc3
*dwc
)
2324 if (!dwc
->gadget_driver
)
2327 if (dwc
->gadget
.speed
!= USB_SPEED_UNKNOWN
) {
2328 spin_unlock(&dwc
->lock
);
2329 usb_gadget_udc_reset(&dwc
->gadget
, dwc
->gadget_driver
);
2330 spin_lock(&dwc
->lock
);
2334 static void dwc3_stop_active_transfer(struct dwc3
*dwc
, u32 epnum
, bool force
)
2336 struct dwc3_ep
*dep
;
2337 struct dwc3_gadget_ep_cmd_params params
;
2341 dep
= dwc
->eps
[epnum
];
2343 if ((dep
->flags
& DWC3_EP_END_TRANSFER_PENDING
) ||
2344 !dep
->resource_index
)
2348 * NOTICE: We are violating what the Databook says about the
2349 * EndTransfer command. Ideally we would _always_ wait for the
2350 * EndTransfer Command Completion IRQ, but that's causing too
2351 * much trouble synchronizing between us and gadget driver.
2353 * We have discussed this with the IP Provider and it was
2354 * suggested to giveback all requests here, but give HW some
2355 * extra time to synchronize with the interconnect. We're using
2356 * an arbitrary 100us delay for that.
2358 * Note also that a similar handling was tested by Synopsys
2359 * (thanks a lot Paul) and nothing bad has come out of it.
2360 * In short, what we're doing is:
2362 * - Issue EndTransfer WITH CMDIOC bit set
2365 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2366 * supports a mode to work around the above limitation. The
2367 * software can poll the CMDACT bit in the DEPCMD register
2368 * after issuing a EndTransfer command. This mode is enabled
2369 * by writing GUCTL2[14]. This polling is already done in the
2370 * dwc3_send_gadget_ep_cmd() function so if the mode is
2371 * enabled, the EndTransfer command will have completed upon
2372 * returning from this function and we don't need to delay for
2375 * This mode is NOT available on the DWC_usb31 IP.
2378 cmd
= DWC3_DEPCMD_ENDTRANSFER
;
2379 cmd
|= force
? DWC3_DEPCMD_HIPRI_FORCERM
: 0;
2380 cmd
|= DWC3_DEPCMD_CMDIOC
;
2381 cmd
|= DWC3_DEPCMD_PARAM(dep
->resource_index
);
2382 memset(¶ms
, 0, sizeof(params
));
2383 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
2385 dep
->resource_index
= 0;
2386 dep
->flags
&= ~DWC3_EP_BUSY
;
2388 if (dwc3_is_usb31(dwc
) || dwc
->revision
< DWC3_REVISION_310A
) {
2389 dep
->flags
|= DWC3_EP_END_TRANSFER_PENDING
;
2394 static void dwc3_clear_stall_all_ep(struct dwc3
*dwc
)
2398 for (epnum
= 1; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
2399 struct dwc3_ep
*dep
;
2402 dep
= dwc
->eps
[epnum
];
2406 if (!(dep
->flags
& DWC3_EP_STALL
))
2409 dep
->flags
&= ~DWC3_EP_STALL
;
2411 ret
= dwc3_send_clear_stall_ep_cmd(dep
);
2416 static void dwc3_gadget_disconnect_interrupt(struct dwc3
*dwc
)
2420 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2421 reg
&= ~DWC3_DCTL_INITU1ENA
;
2422 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2424 reg
&= ~DWC3_DCTL_INITU2ENA
;
2425 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2427 dwc3_disconnect_gadget(dwc
);
2429 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2430 dwc
->setup_packet_pending
= false;
2431 usb_gadget_set_state(&dwc
->gadget
, USB_STATE_NOTATTACHED
);
2433 dwc
->connected
= false;
2436 static void dwc3_gadget_reset_interrupt(struct dwc3
*dwc
)
2440 dwc
->connected
= true;
2443 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2444 * would cause a missing Disconnect Event if there's a
2445 * pending Setup Packet in the FIFO.
2447 * There's no suggested workaround on the official Bug
2448 * report, which states that "unless the driver/application
2449 * is doing any special handling of a disconnect event,
2450 * there is no functional issue".
2452 * Unfortunately, it turns out that we _do_ some special
2453 * handling of a disconnect event, namely complete all
2454 * pending transfers, notify gadget driver of the
2455 * disconnection, and so on.
2457 * Our suggested workaround is to follow the Disconnect
2458 * Event steps here, instead, based on a setup_packet_pending
2459 * flag. Such flag gets set whenever we have a SETUP_PENDING
2460 * status for EP0 TRBs and gets cleared on XferComplete for the
2465 * STAR#9000466709: RTL: Device : Disconnect event not
2466 * generated if setup packet pending in FIFO
2468 if (dwc
->revision
< DWC3_REVISION_188A
) {
2469 if (dwc
->setup_packet_pending
)
2470 dwc3_gadget_disconnect_interrupt(dwc
);
2473 dwc3_reset_gadget(dwc
);
2475 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2476 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
2477 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2478 dwc
->test_mode
= false;
2479 dwc3_clear_stall_all_ep(dwc
);
2481 /* Reset device address to zero */
2482 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2483 reg
&= ~(DWC3_DCFG_DEVADDR_MASK
);
2484 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2487 static void dwc3_gadget_conndone_interrupt(struct dwc3
*dwc
)
2489 struct dwc3_ep
*dep
;
2494 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
2495 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
2499 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2500 * each time on Connect Done.
2502 * Currently we always use the reset value. If any platform
2503 * wants to set this to a different value, we need to add a
2504 * setting and update GCTL.RAMCLKSEL here.
2508 case DWC3_DSTS_SUPERSPEED_PLUS
:
2509 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
2510 dwc
->gadget
.ep0
->maxpacket
= 512;
2511 dwc
->gadget
.speed
= USB_SPEED_SUPER_PLUS
;
2513 case DWC3_DSTS_SUPERSPEED
:
2515 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2516 * would cause a missing USB3 Reset event.
2518 * In such situations, we should force a USB3 Reset
2519 * event by calling our dwc3_gadget_reset_interrupt()
2524 * STAR#9000483510: RTL: SS : USB3 reset event may
2525 * not be generated always when the link enters poll
2527 if (dwc
->revision
< DWC3_REVISION_190A
)
2528 dwc3_gadget_reset_interrupt(dwc
);
2530 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
2531 dwc
->gadget
.ep0
->maxpacket
= 512;
2532 dwc
->gadget
.speed
= USB_SPEED_SUPER
;
2534 case DWC3_DSTS_HIGHSPEED
:
2535 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2536 dwc
->gadget
.ep0
->maxpacket
= 64;
2537 dwc
->gadget
.speed
= USB_SPEED_HIGH
;
2539 case DWC3_DSTS_FULLSPEED
:
2540 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2541 dwc
->gadget
.ep0
->maxpacket
= 64;
2542 dwc
->gadget
.speed
= USB_SPEED_FULL
;
2544 case DWC3_DSTS_LOWSPEED
:
2545 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(8);
2546 dwc
->gadget
.ep0
->maxpacket
= 8;
2547 dwc
->gadget
.speed
= USB_SPEED_LOW
;
2551 /* Enable USB2 LPM Capability */
2553 if ((dwc
->revision
> DWC3_REVISION_194A
) &&
2554 (speed
!= DWC3_DSTS_SUPERSPEED
) &&
2555 (speed
!= DWC3_DSTS_SUPERSPEED_PLUS
)) {
2556 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2557 reg
|= DWC3_DCFG_LPM_CAP
;
2558 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2560 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2561 reg
&= ~(DWC3_DCTL_HIRD_THRES_MASK
| DWC3_DCTL_L1_HIBER_EN
);
2563 reg
|= DWC3_DCTL_HIRD_THRES(dwc
->hird_threshold
);
2566 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2567 * DCFG.LPMCap is set, core responses with an ACK and the
2568 * BESL value in the LPM token is less than or equal to LPM
2571 WARN_ONCE(dwc
->revision
< DWC3_REVISION_240A
2572 && dwc
->has_lpm_erratum
,
2573 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
2575 if (dwc
->has_lpm_erratum
&& dwc
->revision
>= DWC3_REVISION_240A
)
2576 reg
|= DWC3_DCTL_LPM_ERRATA(dwc
->lpm_nyet_threshold
);
2578 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2580 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2581 reg
&= ~DWC3_DCTL_HIRD_THRES_MASK
;
2582 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2586 ret
= __dwc3_gadget_ep_enable(dep
, true, false);
2588 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2593 ret
= __dwc3_gadget_ep_enable(dep
, true, false);
2595 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2600 * Configure PHY via GUSB3PIPECTLn if required.
2602 * Update GTXFIFOSIZn
2604 * In both cases reset values should be sufficient.
2608 static void dwc3_gadget_wakeup_interrupt(struct dwc3
*dwc
)
2611 * TODO take core out of low power mode when that's
2615 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->resume
) {
2616 spin_unlock(&dwc
->lock
);
2617 dwc
->gadget_driver
->resume(&dwc
->gadget
);
2618 spin_lock(&dwc
->lock
);
2622 static void dwc3_gadget_linksts_change_interrupt(struct dwc3
*dwc
,
2623 unsigned int evtinfo
)
2625 enum dwc3_link_state next
= evtinfo
& DWC3_LINK_STATE_MASK
;
2626 unsigned int pwropt
;
2629 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2630 * Hibernation mode enabled which would show up when device detects
2631 * host-initiated U3 exit.
2633 * In that case, device will generate a Link State Change Interrupt
2634 * from U3 to RESUME which is only necessary if Hibernation is
2637 * There are no functional changes due to such spurious event and we
2638 * just need to ignore it.
2642 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2645 pwropt
= DWC3_GHWPARAMS1_EN_PWROPT(dwc
->hwparams
.hwparams1
);
2646 if ((dwc
->revision
< DWC3_REVISION_250A
) &&
2647 (pwropt
!= DWC3_GHWPARAMS1_EN_PWROPT_HIB
)) {
2648 if ((dwc
->link_state
== DWC3_LINK_STATE_U3
) &&
2649 (next
== DWC3_LINK_STATE_RESUME
)) {
2655 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2656 * on the link partner, the USB session might do multiple entry/exit
2657 * of low power states before a transfer takes place.
2659 * Due to this problem, we might experience lower throughput. The
2660 * suggested workaround is to disable DCTL[12:9] bits if we're
2661 * transitioning from U1/U2 to U0 and enable those bits again
2662 * after a transfer completes and there are no pending transfers
2663 * on any of the enabled endpoints.
2665 * This is the first half of that workaround.
2669 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2670 * core send LGO_Ux entering U0
2672 if (dwc
->revision
< DWC3_REVISION_183A
) {
2673 if (next
== DWC3_LINK_STATE_U0
) {
2677 switch (dwc
->link_state
) {
2678 case DWC3_LINK_STATE_U1
:
2679 case DWC3_LINK_STATE_U2
:
2680 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2681 u1u2
= reg
& (DWC3_DCTL_INITU2ENA
2682 | DWC3_DCTL_ACCEPTU2ENA
2683 | DWC3_DCTL_INITU1ENA
2684 | DWC3_DCTL_ACCEPTU1ENA
);
2687 dwc
->u1u2
= reg
& u1u2
;
2691 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2701 case DWC3_LINK_STATE_U1
:
2702 if (dwc
->speed
== USB_SPEED_SUPER
)
2703 dwc3_suspend_gadget(dwc
);
2705 case DWC3_LINK_STATE_U2
:
2706 case DWC3_LINK_STATE_U3
:
2707 dwc3_suspend_gadget(dwc
);
2709 case DWC3_LINK_STATE_RESUME
:
2710 dwc3_resume_gadget(dwc
);
2717 dwc
->link_state
= next
;
2720 static void dwc3_gadget_suspend_interrupt(struct dwc3
*dwc
,
2721 unsigned int evtinfo
)
2723 enum dwc3_link_state next
= evtinfo
& DWC3_LINK_STATE_MASK
;
2725 if (dwc
->link_state
!= next
&& next
== DWC3_LINK_STATE_U3
)
2726 dwc3_suspend_gadget(dwc
);
2728 dwc
->link_state
= next
;
2731 static void dwc3_gadget_hibernation_interrupt(struct dwc3
*dwc
,
2732 unsigned int evtinfo
)
2734 unsigned int is_ss
= evtinfo
& BIT(4);
2737 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2738 * have a known issue which can cause USB CV TD.9.23 to fail
2741 * Because of this issue, core could generate bogus hibernation
2742 * events which SW needs to ignore.
2746 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2747 * Device Fallback from SuperSpeed
2749 if (is_ss
^ (dwc
->speed
== USB_SPEED_SUPER
))
2752 /* enter hibernation here */
2755 static void dwc3_gadget_interrupt(struct dwc3
*dwc
,
2756 const struct dwc3_event_devt
*event
)
2758 switch (event
->type
) {
2759 case DWC3_DEVICE_EVENT_DISCONNECT
:
2760 dwc3_gadget_disconnect_interrupt(dwc
);
2762 case DWC3_DEVICE_EVENT_RESET
:
2763 dwc3_gadget_reset_interrupt(dwc
);
2765 case DWC3_DEVICE_EVENT_CONNECT_DONE
:
2766 dwc3_gadget_conndone_interrupt(dwc
);
2768 case DWC3_DEVICE_EVENT_WAKEUP
:
2769 dwc3_gadget_wakeup_interrupt(dwc
);
2771 case DWC3_DEVICE_EVENT_HIBER_REQ
:
2772 if (dev_WARN_ONCE(dwc
->dev
, !dwc
->has_hibernation
,
2773 "unexpected hibernation event\n"))
2776 dwc3_gadget_hibernation_interrupt(dwc
, event
->event_info
);
2778 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE
:
2779 dwc3_gadget_linksts_change_interrupt(dwc
, event
->event_info
);
2781 case DWC3_DEVICE_EVENT_EOPF
:
2782 /* It changed to be suspend event for version 2.30a and above */
2783 if (dwc
->revision
>= DWC3_REVISION_230A
) {
2785 * Ignore suspend event until the gadget enters into
2786 * USB_STATE_CONFIGURED state.
2788 if (dwc
->gadget
.state
>= USB_STATE_CONFIGURED
)
2789 dwc3_gadget_suspend_interrupt(dwc
,
2793 case DWC3_DEVICE_EVENT_SOF
:
2794 case DWC3_DEVICE_EVENT_ERRATIC_ERROR
:
2795 case DWC3_DEVICE_EVENT_CMD_CMPL
:
2796 case DWC3_DEVICE_EVENT_OVERFLOW
:
2799 dev_WARN(dwc
->dev
, "UNKNOWN IRQ %d\n", event
->type
);
2803 static void dwc3_process_event_entry(struct dwc3
*dwc
,
2804 const union dwc3_event
*event
)
2806 trace_dwc3_event(event
->raw
, dwc
);
2808 /* Endpoint IRQ, handle it and return early */
2809 if (event
->type
.is_devspec
== 0) {
2811 return dwc3_endpoint_interrupt(dwc
, &event
->depevt
);
2814 switch (event
->type
.type
) {
2815 case DWC3_EVENT_TYPE_DEV
:
2816 dwc3_gadget_interrupt(dwc
, &event
->devt
);
2818 /* REVISIT what to do with Carkit and I2C events ? */
2820 dev_err(dwc
->dev
, "UNKNOWN IRQ type %d\n", event
->raw
);
2824 static irqreturn_t
dwc3_process_event_buf(struct dwc3_event_buffer
*evt
)
2826 struct dwc3
*dwc
= evt
->dwc
;
2827 irqreturn_t ret
= IRQ_NONE
;
2833 if (!(evt
->flags
& DWC3_EVENT_PENDING
))
2837 union dwc3_event event
;
2839 event
.raw
= *(u32
*) (evt
->cache
+ evt
->lpos
);
2841 dwc3_process_event_entry(dwc
, &event
);
2844 * FIXME we wrap around correctly to the next entry as
2845 * almost all entries are 4 bytes in size. There is one
2846 * entry which has 12 bytes which is a regular entry
2847 * followed by 8 bytes data. ATM I don't know how
2848 * things are organized if we get next to the a
2849 * boundary so I worry about that once we try to handle
2852 evt
->lpos
= (evt
->lpos
+ 4) % evt
->length
;
2857 evt
->flags
&= ~DWC3_EVENT_PENDING
;
2860 /* Unmask interrupt */
2861 reg
= dwc3_readl(dwc
->regs
, DWC3_GEVNTSIZ(0));
2862 reg
&= ~DWC3_GEVNTSIZ_INTMASK
;
2863 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(0), reg
);
2865 if (dwc
->imod_interval
) {
2866 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB
);
2867 dwc3_writel(dwc
->regs
, DWC3_DEV_IMOD(0), dwc
->imod_interval
);
2873 static irqreturn_t
dwc3_thread_interrupt(int irq
, void *_evt
)
2875 struct dwc3_event_buffer
*evt
= _evt
;
2876 struct dwc3
*dwc
= evt
->dwc
;
2877 unsigned long flags
;
2878 irqreturn_t ret
= IRQ_NONE
;
2880 spin_lock_irqsave(&dwc
->lock
, flags
);
2881 ret
= dwc3_process_event_buf(evt
);
2882 spin_unlock_irqrestore(&dwc
->lock
, flags
);
2887 static irqreturn_t
dwc3_check_event_buf(struct dwc3_event_buffer
*evt
)
2889 struct dwc3
*dwc
= evt
->dwc
;
2894 if (pm_runtime_suspended(dwc
->dev
)) {
2895 pm_runtime_get(dwc
->dev
);
2896 disable_irq_nosync(dwc
->irq_gadget
);
2897 dwc
->pending_events
= true;
2901 count
= dwc3_readl(dwc
->regs
, DWC3_GEVNTCOUNT(0));
2902 count
&= DWC3_GEVNTCOUNT_MASK
;
2907 evt
->flags
|= DWC3_EVENT_PENDING
;
2909 /* Mask interrupt */
2910 reg
= dwc3_readl(dwc
->regs
, DWC3_GEVNTSIZ(0));
2911 reg
|= DWC3_GEVNTSIZ_INTMASK
;
2912 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(0), reg
);
2914 amount
= min(count
, evt
->length
- evt
->lpos
);
2915 memcpy(evt
->cache
+ evt
->lpos
, evt
->buf
+ evt
->lpos
, amount
);
2918 memcpy(evt
->cache
, evt
->buf
, count
- amount
);
2920 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(0), count
);
2922 return IRQ_WAKE_THREAD
;
2925 static irqreturn_t
dwc3_interrupt(int irq
, void *_evt
)
2927 struct dwc3_event_buffer
*evt
= _evt
;
2929 return dwc3_check_event_buf(evt
);
2932 static int dwc3_gadget_get_irq(struct dwc3
*dwc
)
2934 struct platform_device
*dwc3_pdev
= to_platform_device(dwc
->dev
);
2937 irq
= platform_get_irq_byname(dwc3_pdev
, "peripheral");
2941 if (irq
== -EPROBE_DEFER
)
2944 irq
= platform_get_irq_byname(dwc3_pdev
, "dwc_usb3");
2948 if (irq
== -EPROBE_DEFER
)
2951 irq
= platform_get_irq(dwc3_pdev
, 0);
2955 if (irq
!= -EPROBE_DEFER
)
2956 dev_err(dwc
->dev
, "missing peripheral IRQ\n");
2966 * dwc3_gadget_init - Initializes gadget related registers
2967 * @dwc: pointer to our controller context structure
2969 * Returns 0 on success otherwise negative errno.
2971 int dwc3_gadget_init(struct dwc3
*dwc
)
2976 irq
= dwc3_gadget_get_irq(dwc
);
2982 dwc
->irq_gadget
= irq
;
2984 dwc
->ctrl_req
= dma_alloc_coherent(dwc
->sysdev
, sizeof(*dwc
->ctrl_req
),
2985 &dwc
->ctrl_req_addr
, GFP_KERNEL
);
2986 if (!dwc
->ctrl_req
) {
2987 dev_err(dwc
->dev
, "failed to allocate ctrl request\n");
2992 dwc
->ep0_trb
= dma_alloc_coherent(dwc
->sysdev
,
2993 sizeof(*dwc
->ep0_trb
) * 2,
2994 &dwc
->ep0_trb_addr
, GFP_KERNEL
);
2995 if (!dwc
->ep0_trb
) {
2996 dev_err(dwc
->dev
, "failed to allocate ep0 trb\n");
3001 dwc
->setup_buf
= kzalloc(DWC3_EP0_BOUNCE_SIZE
, GFP_KERNEL
);
3002 if (!dwc
->setup_buf
) {
3007 dwc
->ep0_bounce
= dma_alloc_coherent(dwc
->sysdev
,
3008 DWC3_EP0_BOUNCE_SIZE
, &dwc
->ep0_bounce_addr
,
3010 if (!dwc
->ep0_bounce
) {
3011 dev_err(dwc
->dev
, "failed to allocate ep0 bounce buffer\n");
3016 dwc
->zlp_buf
= kzalloc(DWC3_ZLP_BUF_SIZE
, GFP_KERNEL
);
3017 if (!dwc
->zlp_buf
) {
3022 init_completion(&dwc
->ep0_in_setup
);
3024 dwc
->gadget
.ops
= &dwc3_gadget_ops
;
3025 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
3026 dwc
->gadget
.sg_supported
= true;
3027 dwc
->gadget
.name
= "dwc3-gadget";
3028 dwc
->gadget
.is_otg
= dwc
->dr_mode
== USB_DR_MODE_OTG
;
3031 * FIXME We might be setting max_speed to <SUPER, however versions
3032 * <2.20a of dwc3 have an issue with metastability (documented
3033 * elsewhere in this driver) which tells us we can't set max speed to
3034 * anything lower than SUPER.
3036 * Because gadget.max_speed is only used by composite.c and function
3037 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3038 * to happen so we avoid sending SuperSpeed Capability descriptor
3039 * together with our BOS descriptor as that could confuse host into
3040 * thinking we can handle super speed.
3042 * Note that, in fact, we won't even support GetBOS requests when speed
3043 * is less than super speed because we don't have means, yet, to tell
3044 * composite.c that we are USB 2.0 + LPM ECN.
3046 if (dwc
->revision
< DWC3_REVISION_220A
)
3047 dev_info(dwc
->dev
, "changing max_speed on rev %08x\n",
3050 dwc
->gadget
.max_speed
= dwc
->maximum_speed
;
3053 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
3056 dwc
->gadget
.quirk_ep_out_aligned_size
= true;
3059 * REVISIT: Here we should clear all pending IRQs to be
3060 * sure we're starting from a well known location.
3063 ret
= dwc3_gadget_init_endpoints(dwc
);
3067 ret
= usb_add_gadget_udc(dwc
->dev
, &dwc
->gadget
);
3069 dev_err(dwc
->dev
, "failed to register udc\n");
3076 kfree(dwc
->zlp_buf
);
3079 dwc3_gadget_free_endpoints(dwc
);
3080 dma_free_coherent(dwc
->sysdev
, DWC3_EP0_BOUNCE_SIZE
,
3081 dwc
->ep0_bounce
, dwc
->ep0_bounce_addr
);
3084 kfree(dwc
->setup_buf
);
3087 dma_free_coherent(dwc
->sysdev
, sizeof(*dwc
->ep0_trb
) * 2,
3088 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
3091 dma_free_coherent(dwc
->sysdev
, sizeof(*dwc
->ctrl_req
),
3092 dwc
->ctrl_req
, dwc
->ctrl_req_addr
);
3098 /* -------------------------------------------------------------------------- */
3100 void dwc3_gadget_exit(struct dwc3
*dwc
)
3102 usb_del_gadget_udc(&dwc
->gadget
);
3104 dwc3_gadget_free_endpoints(dwc
);
3106 dma_free_coherent(dwc
->sysdev
, DWC3_EP0_BOUNCE_SIZE
,
3107 dwc
->ep0_bounce
, dwc
->ep0_bounce_addr
);
3109 kfree(dwc
->setup_buf
);
3110 kfree(dwc
->zlp_buf
);
3112 dma_free_coherent(dwc
->sysdev
, sizeof(*dwc
->ep0_trb
) * 2,
3113 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
3115 dma_free_coherent(dwc
->sysdev
, sizeof(*dwc
->ctrl_req
),
3116 dwc
->ctrl_req
, dwc
->ctrl_req_addr
);
3119 int dwc3_gadget_suspend(struct dwc3
*dwc
)
3123 if (!dwc
->gadget_driver
)
3126 ret
= dwc3_gadget_run_stop(dwc
, false, false);
3130 dwc3_disconnect_gadget(dwc
);
3131 __dwc3_gadget_stop(dwc
);
3136 int dwc3_gadget_resume(struct dwc3
*dwc
)
3140 if (!dwc
->gadget_driver
)
3143 ret
= __dwc3_gadget_start(dwc
);
3147 ret
= dwc3_gadget_run_stop(dwc
, true, false);
3154 __dwc3_gadget_stop(dwc
);
3160 void dwc3_gadget_process_pending_events(struct dwc3
*dwc
)
3162 if (dwc
->pending_events
) {
3163 dwc3_interrupt(dwc
->irq_gadget
, dwc
->ev_buf
);
3164 dwc
->pending_events
= false;
3165 enable_irq(dwc
->irq_gadget
);