2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/interrupt.h>
27 #include <linux/list.h>
28 #include <linux/dma-mapping.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
38 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
39 * @dwc: pointer to our context structure
40 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
42 * Caller should take care of locking. This function will
43 * return 0 on success or -EINVAL if wrong Test Selector
46 int dwc3_gadget_set_test_mode(struct dwc3
*dwc
, int mode
)
50 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
51 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
65 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
71 * dwc3_gadget_get_link_state - Gets current state of USB Link
72 * @dwc: pointer to our context structure
74 * Caller should take care of locking. This function will
75 * return the link state on success (>= 0) or -ETIMEDOUT.
77 int dwc3_gadget_get_link_state(struct dwc3
*dwc
)
81 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
83 return DWC3_DSTS_USBLNKST(reg
);
87 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
88 * @dwc: pointer to our context structure
89 * @state: the state to put link into
91 * Caller should take care of locking. This function will
92 * return 0 on success or -ETIMEDOUT.
94 int dwc3_gadget_set_link_state(struct dwc3
*dwc
, enum dwc3_link_state state
)
100 * Wait until device controller is ready. Only applies to 1.94a and
103 if (dwc
->revision
>= DWC3_REVISION_194A
) {
105 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
106 if (reg
& DWC3_DSTS_DCNRD
)
116 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
117 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
119 /* set requested state */
120 reg
|= DWC3_DCTL_ULSTCHNGREQ(state
);
121 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
124 * The following code is racy when called from dwc3_gadget_wakeup,
125 * and is not needed, at least on newer versions
127 if (dwc
->revision
>= DWC3_REVISION_194A
)
130 /* wait for a change in DSTS */
133 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
135 if (DWC3_DSTS_USBLNKST(reg
) == state
)
141 dev_vdbg(dwc
->dev
, "link state change request timed out\n");
147 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
148 * @dwc: pointer to our context structure
150 * This function will a best effort FIFO allocation in order
151 * to improve FIFO usage and throughput, while still allowing
152 * us to enable as many endpoints as possible.
154 * Keep in mind that this operation will be highly dependent
155 * on the configured size for RAM1 - which contains TxFifo -,
156 * the amount of endpoints enabled on coreConsultant tool, and
157 * the width of the Master Bus.
159 * In the ideal world, we would always be able to satisfy the
160 * following equation:
162 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
163 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
165 * Unfortunately, due to many variables that's not always the case.
167 int dwc3_gadget_resize_tx_fifos(struct dwc3
*dwc
)
169 int last_fifo_depth
= 0;
175 if (!dwc
->needs_fifo_resize
)
178 ram1_depth
= DWC3_RAM1_DEPTH(dwc
->hwparams
.hwparams7
);
179 mdwidth
= DWC3_MDWIDTH(dwc
->hwparams
.hwparams0
);
181 /* MDWIDTH is represented in bits, we need it in bytes */
185 * FIXME For now we will only allocate 1 wMaxPacketSize space
186 * for each enabled endpoint, later patches will come to
187 * improve this algorithm so that we better use the internal
190 for (num
= 0; num
< DWC3_ENDPOINTS_NUM
; num
++) {
191 struct dwc3_ep
*dep
= dwc
->eps
[num
];
192 int fifo_number
= dep
->number
>> 1;
196 if (!(dep
->number
& 1))
199 if (!(dep
->flags
& DWC3_EP_ENABLED
))
202 if (usb_endpoint_xfer_bulk(dep
->endpoint
.desc
)
203 || usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
207 * REVISIT: the following assumes we will always have enough
208 * space available on the FIFO RAM for all possible use cases.
209 * Make sure that's true somehow and change FIFO allocation
212 * If we have Bulk or Isochronous endpoints, we want
213 * them to be able to be very, very fast. So we're giving
214 * those endpoints a fifo_size which is enough for 3 full
217 tmp
= mult
* (dep
->endpoint
.maxpacket
+ mdwidth
);
220 fifo_size
= DIV_ROUND_UP(tmp
, mdwidth
);
222 fifo_size
|= (last_fifo_depth
<< 16);
224 dev_vdbg(dwc
->dev
, "%s: Fifo Addr %04x Size %d\n",
225 dep
->name
, last_fifo_depth
, fifo_size
& 0xffff);
227 dwc3_writel(dwc
->regs
, DWC3_GTXFIFOSIZ(fifo_number
),
230 last_fifo_depth
+= (fifo_size
& 0xffff);
236 void dwc3_gadget_giveback(struct dwc3_ep
*dep
, struct dwc3_request
*req
,
239 struct dwc3
*dwc
= dep
->dwc
;
247 * Skip LINK TRB. We can't use req->trb and check for
248 * DWC3_TRBCTL_LINK_TRB because it points the TRB we
249 * just completed (not the LINK TRB).
251 if (((dep
->busy_slot
& DWC3_TRB_MASK
) ==
253 usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
255 } while(++i
< req
->request
.num_mapped_sgs
);
258 list_del(&req
->list
);
261 if (req
->request
.status
== -EINPROGRESS
)
262 req
->request
.status
= status
;
264 if (dwc
->ep0_bounced
&& dep
->number
== 0)
265 dwc
->ep0_bounced
= false;
267 usb_gadget_unmap_request(&dwc
->gadget
, &req
->request
,
270 dev_dbg(dwc
->dev
, "request %p from %s completed %d/%d ===> %d\n",
271 req
, dep
->name
, req
->request
.actual
,
272 req
->request
.length
, status
);
274 spin_unlock(&dwc
->lock
);
275 req
->request
.complete(&dep
->endpoint
, &req
->request
);
276 spin_lock(&dwc
->lock
);
279 static const char *dwc3_gadget_ep_cmd_string(u8 cmd
)
282 case DWC3_DEPCMD_DEPSTARTCFG
:
283 return "Start New Configuration";
284 case DWC3_DEPCMD_ENDTRANSFER
:
285 return "End Transfer";
286 case DWC3_DEPCMD_UPDATETRANSFER
:
287 return "Update Transfer";
288 case DWC3_DEPCMD_STARTTRANSFER
:
289 return "Start Transfer";
290 case DWC3_DEPCMD_CLEARSTALL
:
291 return "Clear Stall";
292 case DWC3_DEPCMD_SETSTALL
:
294 case DWC3_DEPCMD_GETEPSTATE
:
295 return "Get Endpoint State";
296 case DWC3_DEPCMD_SETTRANSFRESOURCE
:
297 return "Set Endpoint Transfer Resource";
298 case DWC3_DEPCMD_SETEPCONFIG
:
299 return "Set Endpoint Configuration";
301 return "UNKNOWN command";
305 int dwc3_send_gadget_generic_command(struct dwc3
*dwc
, int cmd
, u32 param
)
310 dwc3_writel(dwc
->regs
, DWC3_DGCMDPAR
, param
);
311 dwc3_writel(dwc
->regs
, DWC3_DGCMD
, cmd
| DWC3_DGCMD_CMDACT
);
314 reg
= dwc3_readl(dwc
->regs
, DWC3_DGCMD
);
315 if (!(reg
& DWC3_DGCMD_CMDACT
)) {
316 dev_vdbg(dwc
->dev
, "Command Complete --> %d\n",
317 DWC3_DGCMD_STATUS(reg
));
322 * We can't sleep here, because it's also called from
332 int dwc3_send_gadget_ep_cmd(struct dwc3
*dwc
, unsigned ep
,
333 unsigned cmd
, struct dwc3_gadget_ep_cmd_params
*params
)
335 struct dwc3_ep
*dep
= dwc
->eps
[ep
];
339 dev_vdbg(dwc
->dev
, "%s: cmd '%s' params %08x %08x %08x\n",
341 dwc3_gadget_ep_cmd_string(cmd
), params
->param0
,
342 params
->param1
, params
->param2
);
344 dwc3_writel(dwc
->regs
, DWC3_DEPCMDPAR0(ep
), params
->param0
);
345 dwc3_writel(dwc
->regs
, DWC3_DEPCMDPAR1(ep
), params
->param1
);
346 dwc3_writel(dwc
->regs
, DWC3_DEPCMDPAR2(ep
), params
->param2
);
348 dwc3_writel(dwc
->regs
, DWC3_DEPCMD(ep
), cmd
| DWC3_DEPCMD_CMDACT
);
350 reg
= dwc3_readl(dwc
->regs
, DWC3_DEPCMD(ep
));
351 if (!(reg
& DWC3_DEPCMD_CMDACT
)) {
352 dev_vdbg(dwc
->dev
, "Command Complete --> %d\n",
353 DWC3_DEPCMD_STATUS(reg
));
358 * We can't sleep here, because it is also called from
369 static dma_addr_t
dwc3_trb_dma_offset(struct dwc3_ep
*dep
,
370 struct dwc3_trb
*trb
)
372 u32 offset
= (char *) trb
- (char *) dep
->trb_pool
;
374 return dep
->trb_pool_dma
+ offset
;
377 static int dwc3_alloc_trb_pool(struct dwc3_ep
*dep
)
379 struct dwc3
*dwc
= dep
->dwc
;
384 if (dep
->number
== 0 || dep
->number
== 1)
387 dep
->trb_pool
= dma_alloc_coherent(dwc
->dev
,
388 sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
389 &dep
->trb_pool_dma
, GFP_KERNEL
);
390 if (!dep
->trb_pool
) {
391 dev_err(dep
->dwc
->dev
, "failed to allocate trb pool for %s\n",
399 static void dwc3_free_trb_pool(struct dwc3_ep
*dep
)
401 struct dwc3
*dwc
= dep
->dwc
;
403 dma_free_coherent(dwc
->dev
, sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
404 dep
->trb_pool
, dep
->trb_pool_dma
);
406 dep
->trb_pool
= NULL
;
407 dep
->trb_pool_dma
= 0;
410 static int dwc3_gadget_start_config(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
412 struct dwc3_gadget_ep_cmd_params params
;
415 memset(¶ms
, 0x00, sizeof(params
));
417 if (dep
->number
!= 1) {
418 cmd
= DWC3_DEPCMD_DEPSTARTCFG
;
419 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
420 if (dep
->number
> 1) {
421 if (dwc
->start_config_issued
)
423 dwc
->start_config_issued
= true;
424 cmd
|= DWC3_DEPCMD_PARAM(2);
427 return dwc3_send_gadget_ep_cmd(dwc
, 0, cmd
, ¶ms
);
433 static int dwc3_gadget_set_ep_config(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
434 const struct usb_endpoint_descriptor
*desc
,
435 const struct usb_ss_ep_comp_descriptor
*comp_desc
,
436 bool ignore
, bool restore
)
438 struct dwc3_gadget_ep_cmd_params params
;
440 memset(¶ms
, 0x00, sizeof(params
));
442 params
.param0
= DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc
))
443 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc
));
445 /* Burst size is only needed in SuperSpeed mode */
446 if (dwc
->gadget
.speed
== USB_SPEED_SUPER
) {
447 u32 burst
= dep
->endpoint
.maxburst
- 1;
449 params
.param0
|= DWC3_DEPCFG_BURST_SIZE(burst
);
453 params
.param0
|= DWC3_DEPCFG_IGN_SEQ_NUM
;
456 params
.param0
|= DWC3_DEPCFG_ACTION_RESTORE
;
457 params
.param2
|= dep
->saved_state
;
460 params
.param1
= DWC3_DEPCFG_XFER_COMPLETE_EN
461 | DWC3_DEPCFG_XFER_NOT_READY_EN
;
463 if (usb_ss_max_streams(comp_desc
) && usb_endpoint_xfer_bulk(desc
)) {
464 params
.param1
|= DWC3_DEPCFG_STREAM_CAPABLE
465 | DWC3_DEPCFG_STREAM_EVENT_EN
;
466 dep
->stream_capable
= true;
469 if (usb_endpoint_xfer_isoc(desc
))
470 params
.param1
|= DWC3_DEPCFG_XFER_IN_PROGRESS_EN
;
473 * We are doing 1:1 mapping for endpoints, meaning
474 * Physical Endpoints 2 maps to Logical Endpoint 2 and
475 * so on. We consider the direction bit as part of the physical
476 * endpoint number. So USB endpoint 0x81 is 0x03.
478 params
.param1
|= DWC3_DEPCFG_EP_NUMBER(dep
->number
);
481 * We must use the lower 16 TX FIFOs even though
485 params
.param0
|= DWC3_DEPCFG_FIFO_NUMBER(dep
->number
>> 1);
487 if (desc
->bInterval
) {
488 params
.param1
|= DWC3_DEPCFG_BINTERVAL_M1(desc
->bInterval
- 1);
489 dep
->interval
= 1 << (desc
->bInterval
- 1);
492 return dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
493 DWC3_DEPCMD_SETEPCONFIG
, ¶ms
);
496 static int dwc3_gadget_set_xfer_resource(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
498 struct dwc3_gadget_ep_cmd_params params
;
500 memset(¶ms
, 0x00, sizeof(params
));
502 params
.param0
= DWC3_DEPXFERCFG_NUM_XFER_RES(1);
504 return dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
505 DWC3_DEPCMD_SETTRANSFRESOURCE
, ¶ms
);
509 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
510 * @dep: endpoint to be initialized
511 * @desc: USB Endpoint Descriptor
513 * Caller should take care of locking
515 static int __dwc3_gadget_ep_enable(struct dwc3_ep
*dep
,
516 const struct usb_endpoint_descriptor
*desc
,
517 const struct usb_ss_ep_comp_descriptor
*comp_desc
,
518 bool ignore
, bool restore
)
520 struct dwc3
*dwc
= dep
->dwc
;
524 dev_vdbg(dwc
->dev
, "Enabling %s\n", dep
->name
);
526 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
527 ret
= dwc3_gadget_start_config(dwc
, dep
);
532 ret
= dwc3_gadget_set_ep_config(dwc
, dep
, desc
, comp_desc
, ignore
,
537 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
538 struct dwc3_trb
*trb_st_hw
;
539 struct dwc3_trb
*trb_link
;
541 ret
= dwc3_gadget_set_xfer_resource(dwc
, dep
);
545 dep
->endpoint
.desc
= desc
;
546 dep
->comp_desc
= comp_desc
;
547 dep
->type
= usb_endpoint_type(desc
);
548 dep
->flags
|= DWC3_EP_ENABLED
;
550 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
551 reg
|= DWC3_DALEPENA_EP(dep
->number
);
552 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
554 if (!usb_endpoint_xfer_isoc(desc
))
557 memset(&trb_link
, 0, sizeof(trb_link
));
559 /* Link TRB for ISOC. The HWO bit is never reset */
560 trb_st_hw
= &dep
->trb_pool
[0];
562 trb_link
= &dep
->trb_pool
[DWC3_TRB_NUM
- 1];
564 trb_link
->bpl
= lower_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
565 trb_link
->bph
= upper_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
566 trb_link
->ctrl
|= DWC3_TRBCTL_LINK_TRB
;
567 trb_link
->ctrl
|= DWC3_TRB_CTRL_HWO
;
573 static void dwc3_stop_active_transfer(struct dwc3
*dwc
, u32 epnum
, bool force
);
574 static void dwc3_remove_requests(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
576 struct dwc3_request
*req
;
578 if (!list_empty(&dep
->req_queued
)) {
579 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
581 /* - giveback all requests to gadget driver */
582 while (!list_empty(&dep
->req_queued
)) {
583 req
= next_request(&dep
->req_queued
);
585 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
589 while (!list_empty(&dep
->request_list
)) {
590 req
= next_request(&dep
->request_list
);
592 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
597 * __dwc3_gadget_ep_disable - Disables a HW endpoint
598 * @dep: the endpoint to disable
600 * This function also removes requests which are currently processed ny the
601 * hardware and those which are not yet scheduled.
602 * Caller should take care of locking.
604 static int __dwc3_gadget_ep_disable(struct dwc3_ep
*dep
)
606 struct dwc3
*dwc
= dep
->dwc
;
609 dwc3_remove_requests(dwc
, dep
);
611 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
612 reg
&= ~DWC3_DALEPENA_EP(dep
->number
);
613 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
615 dep
->stream_capable
= false;
616 dep
->endpoint
.desc
= NULL
;
617 dep
->comp_desc
= NULL
;
624 /* -------------------------------------------------------------------------- */
626 static int dwc3_gadget_ep0_enable(struct usb_ep
*ep
,
627 const struct usb_endpoint_descriptor
*desc
)
632 static int dwc3_gadget_ep0_disable(struct usb_ep
*ep
)
637 /* -------------------------------------------------------------------------- */
639 static int dwc3_gadget_ep_enable(struct usb_ep
*ep
,
640 const struct usb_endpoint_descriptor
*desc
)
647 if (!ep
|| !desc
|| desc
->bDescriptorType
!= USB_DT_ENDPOINT
) {
648 pr_debug("dwc3: invalid parameters\n");
652 if (!desc
->wMaxPacketSize
) {
653 pr_debug("dwc3: missing wMaxPacketSize\n");
657 dep
= to_dwc3_ep(ep
);
660 if (dep
->flags
& DWC3_EP_ENABLED
) {
661 dev_WARN_ONCE(dwc
->dev
, true, "%s is already enabled\n",
666 switch (usb_endpoint_type(desc
)) {
667 case USB_ENDPOINT_XFER_CONTROL
:
668 strlcat(dep
->name
, "-control", sizeof(dep
->name
));
670 case USB_ENDPOINT_XFER_ISOC
:
671 strlcat(dep
->name
, "-isoc", sizeof(dep
->name
));
673 case USB_ENDPOINT_XFER_BULK
:
674 strlcat(dep
->name
, "-bulk", sizeof(dep
->name
));
676 case USB_ENDPOINT_XFER_INT
:
677 strlcat(dep
->name
, "-int", sizeof(dep
->name
));
680 dev_err(dwc
->dev
, "invalid endpoint transfer type\n");
683 spin_lock_irqsave(&dwc
->lock
, flags
);
684 ret
= __dwc3_gadget_ep_enable(dep
, desc
, ep
->comp_desc
, false, false);
685 spin_unlock_irqrestore(&dwc
->lock
, flags
);
690 static int dwc3_gadget_ep_disable(struct usb_ep
*ep
)
698 pr_debug("dwc3: invalid parameters\n");
702 dep
= to_dwc3_ep(ep
);
705 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
706 dev_WARN_ONCE(dwc
->dev
, true, "%s is already disabled\n",
711 snprintf(dep
->name
, sizeof(dep
->name
), "ep%d%s",
713 (dep
->number
& 1) ? "in" : "out");
715 spin_lock_irqsave(&dwc
->lock
, flags
);
716 ret
= __dwc3_gadget_ep_disable(dep
);
717 spin_unlock_irqrestore(&dwc
->lock
, flags
);
722 static struct usb_request
*dwc3_gadget_ep_alloc_request(struct usb_ep
*ep
,
725 struct dwc3_request
*req
;
726 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
727 struct dwc3
*dwc
= dep
->dwc
;
729 req
= kzalloc(sizeof(*req
), gfp_flags
);
731 dev_err(dwc
->dev
, "not enough memory\n");
735 req
->epnum
= dep
->number
;
738 return &req
->request
;
741 static void dwc3_gadget_ep_free_request(struct usb_ep
*ep
,
742 struct usb_request
*request
)
744 struct dwc3_request
*req
= to_dwc3_request(request
);
750 * dwc3_prepare_one_trb - setup one TRB from one request
751 * @dep: endpoint for which this request is prepared
752 * @req: dwc3_request pointer
754 static void dwc3_prepare_one_trb(struct dwc3_ep
*dep
,
755 struct dwc3_request
*req
, dma_addr_t dma
,
756 unsigned length
, unsigned last
, unsigned chain
, unsigned node
)
758 struct dwc3
*dwc
= dep
->dwc
;
759 struct dwc3_trb
*trb
;
761 dev_vdbg(dwc
->dev
, "%s: req %p dma %08llx length %d%s%s\n",
762 dep
->name
, req
, (unsigned long long) dma
,
763 length
, last
? " last" : "",
764 chain
? " chain" : "");
766 /* Skip the LINK-TRB on ISOC */
767 if (((dep
->free_slot
& DWC3_TRB_MASK
) == DWC3_TRB_NUM
- 1) &&
768 usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
771 trb
= &dep
->trb_pool
[dep
->free_slot
& DWC3_TRB_MASK
];
774 dwc3_gadget_move_request_queued(req
);
776 req
->trb_dma
= dwc3_trb_dma_offset(dep
, trb
);
777 req
->start_slot
= dep
->free_slot
& DWC3_TRB_MASK
;
782 trb
->size
= DWC3_TRB_SIZE_LENGTH(length
);
783 trb
->bpl
= lower_32_bits(dma
);
784 trb
->bph
= upper_32_bits(dma
);
786 switch (usb_endpoint_type(dep
->endpoint
.desc
)) {
787 case USB_ENDPOINT_XFER_CONTROL
:
788 trb
->ctrl
= DWC3_TRBCTL_CONTROL_SETUP
;
791 case USB_ENDPOINT_XFER_ISOC
:
793 trb
->ctrl
= DWC3_TRBCTL_ISOCHRONOUS_FIRST
;
795 trb
->ctrl
= DWC3_TRBCTL_ISOCHRONOUS
;
798 case USB_ENDPOINT_XFER_BULK
:
799 case USB_ENDPOINT_XFER_INT
:
800 trb
->ctrl
= DWC3_TRBCTL_NORMAL
;
804 * This is only possible with faulty memory because we
805 * checked it already :)
810 if (!req
->request
.no_interrupt
&& !chain
)
811 trb
->ctrl
|= DWC3_TRB_CTRL_IOC
;
813 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
814 trb
->ctrl
|= DWC3_TRB_CTRL_ISP_IMI
;
815 trb
->ctrl
|= DWC3_TRB_CTRL_CSP
;
817 trb
->ctrl
|= DWC3_TRB_CTRL_LST
;
821 trb
->ctrl
|= DWC3_TRB_CTRL_CHN
;
823 if (usb_endpoint_xfer_bulk(dep
->endpoint
.desc
) && dep
->stream_capable
)
824 trb
->ctrl
|= DWC3_TRB_CTRL_SID_SOFN(req
->request
.stream_id
);
826 trb
->ctrl
|= DWC3_TRB_CTRL_HWO
;
830 * dwc3_prepare_trbs - setup TRBs from requests
831 * @dep: endpoint for which requests are being prepared
832 * @starting: true if the endpoint is idle and no requests are queued.
834 * The function goes through the requests list and sets up TRBs for the
835 * transfers. The function returns once there are no more TRBs available or
836 * it runs out of requests.
838 static void dwc3_prepare_trbs(struct dwc3_ep
*dep
, bool starting
)
840 struct dwc3_request
*req
, *n
;
843 unsigned int last_one
= 0;
845 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM
);
847 /* the first request must not be queued */
848 trbs_left
= (dep
->busy_slot
- dep
->free_slot
) & DWC3_TRB_MASK
;
850 /* Can't wrap around on a non-isoc EP since there's no link TRB */
851 if (!usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
852 max
= DWC3_TRB_NUM
- (dep
->free_slot
& DWC3_TRB_MASK
);
858 * If busy & slot are equal than it is either full or empty. If we are
859 * starting to process requests then we are empty. Otherwise we are
860 * full and don't do anything
865 trbs_left
= DWC3_TRB_NUM
;
867 * In case we start from scratch, we queue the ISOC requests
868 * starting from slot 1. This is done because we use ring
869 * buffer and have no LST bit to stop us. Instead, we place
870 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
871 * after the first request so we start at slot 1 and have
872 * 7 requests proceed before we hit the first IOC.
873 * Other transfer types don't use the ring buffer and are
874 * processed from the first TRB until the last one. Since we
875 * don't wrap around we have to start at the beginning.
877 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
886 /* The last TRB is a link TRB, not used for xfer */
887 if ((trbs_left
<= 1) && usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
890 list_for_each_entry_safe(req
, n
, &dep
->request_list
, list
) {
895 if (req
->request
.num_mapped_sgs
> 0) {
896 struct usb_request
*request
= &req
->request
;
897 struct scatterlist
*sg
= request
->sg
;
898 struct scatterlist
*s
;
901 for_each_sg(sg
, s
, request
->num_mapped_sgs
, i
) {
902 unsigned chain
= true;
904 length
= sg_dma_len(s
);
905 dma
= sg_dma_address(s
);
907 if (i
== (request
->num_mapped_sgs
- 1) ||
909 if (list_is_last(&req
->list
,
922 dwc3_prepare_one_trb(dep
, req
, dma
, length
,
929 dma
= req
->request
.dma
;
930 length
= req
->request
.length
;
936 /* Is this the last request? */
937 if (list_is_last(&req
->list
, &dep
->request_list
))
940 dwc3_prepare_one_trb(dep
, req
, dma
, length
,
949 static int __dwc3_gadget_kick_transfer(struct dwc3_ep
*dep
, u16 cmd_param
,
952 struct dwc3_gadget_ep_cmd_params params
;
953 struct dwc3_request
*req
;
954 struct dwc3
*dwc
= dep
->dwc
;
958 if (start_new
&& (dep
->flags
& DWC3_EP_BUSY
)) {
959 dev_vdbg(dwc
->dev
, "%s: endpoint busy\n", dep
->name
);
962 dep
->flags
&= ~DWC3_EP_PENDING_REQUEST
;
965 * If we are getting here after a short-out-packet we don't enqueue any
966 * new requests as we try to set the IOC bit only on the last request.
969 if (list_empty(&dep
->req_queued
))
970 dwc3_prepare_trbs(dep
, start_new
);
972 /* req points to the first request which will be sent */
973 req
= next_request(&dep
->req_queued
);
975 dwc3_prepare_trbs(dep
, start_new
);
978 * req points to the first request where HWO changed from 0 to 1
980 req
= next_request(&dep
->req_queued
);
983 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
987 memset(¶ms
, 0, sizeof(params
));
990 params
.param0
= upper_32_bits(req
->trb_dma
);
991 params
.param1
= lower_32_bits(req
->trb_dma
);
992 cmd
= DWC3_DEPCMD_STARTTRANSFER
;
994 cmd
= DWC3_DEPCMD_UPDATETRANSFER
;
997 cmd
|= DWC3_DEPCMD_PARAM(cmd_param
);
998 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
, cmd
, ¶ms
);
1000 dev_dbg(dwc
->dev
, "failed to send STARTTRANSFER command\n");
1003 * FIXME we need to iterate over the list of requests
1004 * here and stop, unmap, free and del each of the linked
1005 * requests instead of what we do now.
1007 usb_gadget_unmap_request(&dwc
->gadget
, &req
->request
,
1009 list_del(&req
->list
);
1013 dep
->flags
|= DWC3_EP_BUSY
;
1016 dep
->resource_index
= dwc3_gadget_ep_get_transfer_index(dwc
,
1018 WARN_ON_ONCE(!dep
->resource_index
);
1024 static void __dwc3_gadget_start_isoc(struct dwc3
*dwc
,
1025 struct dwc3_ep
*dep
, u32 cur_uf
)
1029 if (list_empty(&dep
->request_list
)) {
1030 dev_vdbg(dwc
->dev
, "ISOC ep %s run out for requests.\n",
1032 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
1036 /* 4 micro frames in the future */
1037 uf
= cur_uf
+ dep
->interval
* 4;
1039 __dwc3_gadget_kick_transfer(dep
, uf
, 1);
1042 static void dwc3_gadget_start_isoc(struct dwc3
*dwc
,
1043 struct dwc3_ep
*dep
, const struct dwc3_event_depevt
*event
)
1047 mask
= ~(dep
->interval
- 1);
1048 cur_uf
= event
->parameters
& mask
;
1050 __dwc3_gadget_start_isoc(dwc
, dep
, cur_uf
);
1053 static int __dwc3_gadget_ep_queue(struct dwc3_ep
*dep
, struct dwc3_request
*req
)
1055 struct dwc3
*dwc
= dep
->dwc
;
1058 req
->request
.actual
= 0;
1059 req
->request
.status
= -EINPROGRESS
;
1060 req
->direction
= dep
->direction
;
1061 req
->epnum
= dep
->number
;
1064 * We only add to our list of requests now and
1065 * start consuming the list once we get XferNotReady
1068 * That way, we avoid doing anything that we don't need
1069 * to do now and defer it until the point we receive a
1070 * particular token from the Host side.
1072 * This will also avoid Host cancelling URBs due to too
1075 ret
= usb_gadget_map_request(&dwc
->gadget
, &req
->request
,
1080 list_add_tail(&req
->list
, &dep
->request_list
);
1083 * There are a few special cases:
1085 * 1. XferNotReady with empty list of requests. We need to kick the
1086 * transfer here in that situation, otherwise we will be NAKing
1087 * forever. If we get XferNotReady before gadget driver has a
1088 * chance to queue a request, we will ACK the IRQ but won't be
1089 * able to receive the data until the next request is queued.
1090 * The following code is handling exactly that.
1093 if (dep
->flags
& DWC3_EP_PENDING_REQUEST
) {
1095 * If xfernotready is already elapsed and it is a case
1096 * of isoc transfer, then issue END TRANSFER, so that
1097 * you can receive xfernotready again and can have
1098 * notion of current microframe.
1100 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1101 if (list_empty(&dep
->req_queued
)) {
1102 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
1103 dep
->flags
= DWC3_EP_ENABLED
;
1108 ret
= __dwc3_gadget_kick_transfer(dep
, 0, true);
1109 if (ret
&& ret
!= -EBUSY
)
1110 dev_dbg(dwc
->dev
, "%s: failed to kick transfers\n",
1116 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1117 * kick the transfer here after queuing a request, otherwise the
1118 * core may not see the modified TRB(s).
1120 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) &&
1121 (dep
->flags
& DWC3_EP_BUSY
) &&
1122 !(dep
->flags
& DWC3_EP_MISSED_ISOC
)) {
1123 WARN_ON_ONCE(!dep
->resource_index
);
1124 ret
= __dwc3_gadget_kick_transfer(dep
, dep
->resource_index
,
1126 if (ret
&& ret
!= -EBUSY
)
1127 dev_dbg(dwc
->dev
, "%s: failed to kick transfers\n",
1133 * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1134 * right away, otherwise host will not know we have streams to be
1137 if (dep
->stream_capable
) {
1140 ret
= __dwc3_gadget_kick_transfer(dep
, 0, true);
1141 if (ret
&& ret
!= -EBUSY
) {
1142 struct dwc3
*dwc
= dep
->dwc
;
1144 dev_dbg(dwc
->dev
, "%s: failed to kick transfers\n",
1152 static int dwc3_gadget_ep_queue(struct usb_ep
*ep
, struct usb_request
*request
,
1155 struct dwc3_request
*req
= to_dwc3_request(request
);
1156 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1157 struct dwc3
*dwc
= dep
->dwc
;
1159 unsigned long flags
;
1163 if (!dep
->endpoint
.desc
) {
1164 dev_dbg(dwc
->dev
, "trying to queue request %p to disabled %s\n",
1169 dev_vdbg(dwc
->dev
, "queing request %p to %s length %d\n",
1170 request
, ep
->name
, request
->length
);
1172 spin_lock_irqsave(&dwc
->lock
, flags
);
1173 ret
= __dwc3_gadget_ep_queue(dep
, req
);
1174 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1179 static int dwc3_gadget_ep_dequeue(struct usb_ep
*ep
,
1180 struct usb_request
*request
)
1182 struct dwc3_request
*req
= to_dwc3_request(request
);
1183 struct dwc3_request
*r
= NULL
;
1185 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1186 struct dwc3
*dwc
= dep
->dwc
;
1188 unsigned long flags
;
1191 spin_lock_irqsave(&dwc
->lock
, flags
);
1193 list_for_each_entry(r
, &dep
->request_list
, list
) {
1199 list_for_each_entry(r
, &dep
->req_queued
, list
) {
1204 /* wait until it is processed */
1205 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
1208 dev_err(dwc
->dev
, "request %p was not queued to %s\n",
1215 /* giveback the request */
1216 dwc3_gadget_giveback(dep
, req
, -ECONNRESET
);
1219 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1224 int __dwc3_gadget_ep_set_halt(struct dwc3_ep
*dep
, int value
)
1226 struct dwc3_gadget_ep_cmd_params params
;
1227 struct dwc3
*dwc
= dep
->dwc
;
1230 memset(¶ms
, 0x00, sizeof(params
));
1233 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
1234 DWC3_DEPCMD_SETSTALL
, ¶ms
);
1236 dev_err(dwc
->dev
, "failed to %s STALL on %s\n",
1237 value
? "set" : "clear",
1240 dep
->flags
|= DWC3_EP_STALL
;
1242 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
1243 DWC3_DEPCMD_CLEARSTALL
, ¶ms
);
1245 dev_err(dwc
->dev
, "failed to %s STALL on %s\n",
1246 value
? "set" : "clear",
1249 dep
->flags
&= ~(DWC3_EP_STALL
| DWC3_EP_WEDGE
);
1255 static int dwc3_gadget_ep_set_halt(struct usb_ep
*ep
, int value
)
1257 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1258 struct dwc3
*dwc
= dep
->dwc
;
1260 unsigned long flags
;
1264 spin_lock_irqsave(&dwc
->lock
, flags
);
1266 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1267 dev_err(dwc
->dev
, "%s is of Isochronous type\n", dep
->name
);
1272 ret
= __dwc3_gadget_ep_set_halt(dep
, value
);
1274 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1279 static int dwc3_gadget_ep_set_wedge(struct usb_ep
*ep
)
1281 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1282 struct dwc3
*dwc
= dep
->dwc
;
1283 unsigned long flags
;
1285 spin_lock_irqsave(&dwc
->lock
, flags
);
1286 dep
->flags
|= DWC3_EP_WEDGE
;
1287 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1289 if (dep
->number
== 0 || dep
->number
== 1)
1290 return dwc3_gadget_ep0_set_halt(ep
, 1);
1292 return dwc3_gadget_ep_set_halt(ep
, 1);
1295 /* -------------------------------------------------------------------------- */
1297 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc
= {
1298 .bLength
= USB_DT_ENDPOINT_SIZE
,
1299 .bDescriptorType
= USB_DT_ENDPOINT
,
1300 .bmAttributes
= USB_ENDPOINT_XFER_CONTROL
,
1303 static const struct usb_ep_ops dwc3_gadget_ep0_ops
= {
1304 .enable
= dwc3_gadget_ep0_enable
,
1305 .disable
= dwc3_gadget_ep0_disable
,
1306 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1307 .free_request
= dwc3_gadget_ep_free_request
,
1308 .queue
= dwc3_gadget_ep0_queue
,
1309 .dequeue
= dwc3_gadget_ep_dequeue
,
1310 .set_halt
= dwc3_gadget_ep0_set_halt
,
1311 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1314 static const struct usb_ep_ops dwc3_gadget_ep_ops
= {
1315 .enable
= dwc3_gadget_ep_enable
,
1316 .disable
= dwc3_gadget_ep_disable
,
1317 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1318 .free_request
= dwc3_gadget_ep_free_request
,
1319 .queue
= dwc3_gadget_ep_queue
,
1320 .dequeue
= dwc3_gadget_ep_dequeue
,
1321 .set_halt
= dwc3_gadget_ep_set_halt
,
1322 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1325 /* -------------------------------------------------------------------------- */
1327 static int dwc3_gadget_get_frame(struct usb_gadget
*g
)
1329 struct dwc3
*dwc
= gadget_to_dwc(g
);
1332 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1333 return DWC3_DSTS_SOFFN(reg
);
1336 static int dwc3_gadget_wakeup(struct usb_gadget
*g
)
1338 struct dwc3
*dwc
= gadget_to_dwc(g
);
1340 unsigned long timeout
;
1341 unsigned long flags
;
1350 spin_lock_irqsave(&dwc
->lock
, flags
);
1353 * According to the Databook Remote wakeup request should
1354 * be issued only when the device is in early suspend state.
1356 * We can check that via USB Link State bits in DSTS register.
1358 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1360 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
1361 if (speed
== DWC3_DSTS_SUPERSPEED
) {
1362 dev_dbg(dwc
->dev
, "no wakeup on SuperSpeed\n");
1367 link_state
= DWC3_DSTS_USBLNKST(reg
);
1369 switch (link_state
) {
1370 case DWC3_LINK_STATE_RX_DET
: /* in HS, means Early Suspend */
1371 case DWC3_LINK_STATE_U3
: /* in HS, means SUSPEND */
1374 dev_dbg(dwc
->dev
, "can't wakeup from link state %d\n",
1380 ret
= dwc3_gadget_set_link_state(dwc
, DWC3_LINK_STATE_RECOV
);
1382 dev_err(dwc
->dev
, "failed to put link in Recovery\n");
1386 /* Recent versions do this automatically */
1387 if (dwc
->revision
< DWC3_REVISION_194A
) {
1388 /* write zeroes to Link Change Request */
1389 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1390 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
1391 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1394 /* poll until Link State changes to ON */
1395 timeout
= jiffies
+ msecs_to_jiffies(100);
1397 while (!time_after(jiffies
, timeout
)) {
1398 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1400 /* in HS, means ON */
1401 if (DWC3_DSTS_USBLNKST(reg
) == DWC3_LINK_STATE_U0
)
1405 if (DWC3_DSTS_USBLNKST(reg
) != DWC3_LINK_STATE_U0
) {
1406 dev_err(dwc
->dev
, "failed to send remote wakeup\n");
1411 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1416 static int dwc3_gadget_set_selfpowered(struct usb_gadget
*g
,
1419 struct dwc3
*dwc
= gadget_to_dwc(g
);
1420 unsigned long flags
;
1422 spin_lock_irqsave(&dwc
->lock
, flags
);
1423 dwc
->is_selfpowered
= !!is_selfpowered
;
1424 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1429 static int dwc3_gadget_run_stop(struct dwc3
*dwc
, int is_on
, int suspend
)
1434 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1436 if (dwc
->revision
<= DWC3_REVISION_187A
) {
1437 reg
&= ~DWC3_DCTL_TRGTULST_MASK
;
1438 reg
|= DWC3_DCTL_TRGTULST_RX_DET
;
1441 if (dwc
->revision
>= DWC3_REVISION_194A
)
1442 reg
&= ~DWC3_DCTL_KEEP_CONNECT
;
1443 reg
|= DWC3_DCTL_RUN_STOP
;
1445 if (dwc
->has_hibernation
)
1446 reg
|= DWC3_DCTL_KEEP_CONNECT
;
1448 dwc
->pullups_connected
= true;
1450 reg
&= ~DWC3_DCTL_RUN_STOP
;
1452 if (dwc
->has_hibernation
&& !suspend
)
1453 reg
&= ~DWC3_DCTL_KEEP_CONNECT
;
1455 dwc
->pullups_connected
= false;
1458 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1461 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1463 if (!(reg
& DWC3_DSTS_DEVCTRLHLT
))
1466 if (reg
& DWC3_DSTS_DEVCTRLHLT
)
1475 dev_vdbg(dwc
->dev
, "gadget %s data soft-%s\n",
1477 ? dwc
->gadget_driver
->function
: "no-function",
1478 is_on
? "connect" : "disconnect");
1483 static int dwc3_gadget_pullup(struct usb_gadget
*g
, int is_on
)
1485 struct dwc3
*dwc
= gadget_to_dwc(g
);
1486 unsigned long flags
;
1491 spin_lock_irqsave(&dwc
->lock
, flags
);
1492 ret
= dwc3_gadget_run_stop(dwc
, is_on
, false);
1493 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1498 static void dwc3_gadget_enable_irq(struct dwc3
*dwc
)
1502 /* Enable all but Start and End of Frame IRQs */
1503 reg
= (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN
|
1504 DWC3_DEVTEN_EVNTOVERFLOWEN
|
1505 DWC3_DEVTEN_CMDCMPLTEN
|
1506 DWC3_DEVTEN_ERRTICERREN
|
1507 DWC3_DEVTEN_WKUPEVTEN
|
1508 DWC3_DEVTEN_ULSTCNGEN
|
1509 DWC3_DEVTEN_CONNECTDONEEN
|
1510 DWC3_DEVTEN_USBRSTEN
|
1511 DWC3_DEVTEN_DISCONNEVTEN
);
1513 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, reg
);
1516 static void dwc3_gadget_disable_irq(struct dwc3
*dwc
)
1518 /* mask all interrupts */
1519 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, 0x00);
1522 static irqreturn_t
dwc3_interrupt(int irq
, void *_dwc
);
1523 static irqreturn_t
dwc3_thread_interrupt(int irq
, void *_dwc
);
1525 static int dwc3_gadget_start(struct usb_gadget
*g
,
1526 struct usb_gadget_driver
*driver
)
1528 struct dwc3
*dwc
= gadget_to_dwc(g
);
1529 struct dwc3_ep
*dep
;
1530 unsigned long flags
;
1535 irq
= platform_get_irq(to_platform_device(dwc
->dev
), 0);
1536 ret
= request_threaded_irq(irq
, dwc3_interrupt
, dwc3_thread_interrupt
,
1537 IRQF_SHARED
, "dwc3", dwc
);
1539 dev_err(dwc
->dev
, "failed to request irq #%d --> %d\n",
1544 spin_lock_irqsave(&dwc
->lock
, flags
);
1546 if (dwc
->gadget_driver
) {
1547 dev_err(dwc
->dev
, "%s is already bound to %s\n",
1549 dwc
->gadget_driver
->driver
.name
);
1554 dwc
->gadget_driver
= driver
;
1556 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
1557 reg
&= ~(DWC3_DCFG_SPEED_MASK
);
1560 * WORKAROUND: DWC3 revision < 2.20a have an issue
1561 * which would cause metastability state on Run/Stop
1562 * bit if we try to force the IP to USB2-only mode.
1564 * Because of that, we cannot configure the IP to any
1565 * speed other than the SuperSpeed
1569 * STAR#9000525659: Clock Domain Crossing on DCTL in
1572 if (dwc
->revision
< DWC3_REVISION_220A
) {
1573 reg
|= DWC3_DCFG_SUPERSPEED
;
1575 switch (dwc
->maximum_speed
) {
1577 reg
|= DWC3_DSTS_LOWSPEED
;
1579 case USB_SPEED_FULL
:
1580 reg
|= DWC3_DSTS_FULLSPEED1
;
1582 case USB_SPEED_HIGH
:
1583 reg
|= DWC3_DSTS_HIGHSPEED
;
1585 case USB_SPEED_SUPER
: /* FALLTHROUGH */
1586 case USB_SPEED_UNKNOWN
: /* FALTHROUGH */
1588 reg
|= DWC3_DSTS_SUPERSPEED
;
1591 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
1593 dwc
->start_config_issued
= false;
1595 /* Start with SuperSpeed Default */
1596 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
1599 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, false,
1602 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1607 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, false,
1610 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1614 /* begin to receive SETUP packets */
1615 dwc
->ep0state
= EP0_SETUP_PHASE
;
1616 dwc3_ep0_out_start(dwc
);
1618 dwc3_gadget_enable_irq(dwc
);
1620 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1625 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
1628 dwc
->gadget_driver
= NULL
;
1631 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1639 static int dwc3_gadget_stop(struct usb_gadget
*g
,
1640 struct usb_gadget_driver
*driver
)
1642 struct dwc3
*dwc
= gadget_to_dwc(g
);
1643 unsigned long flags
;
1646 spin_lock_irqsave(&dwc
->lock
, flags
);
1648 dwc3_gadget_disable_irq(dwc
);
1649 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
1650 __dwc3_gadget_ep_disable(dwc
->eps
[1]);
1652 dwc
->gadget_driver
= NULL
;
1654 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1656 irq
= platform_get_irq(to_platform_device(dwc
->dev
), 0);
1662 static const struct usb_gadget_ops dwc3_gadget_ops
= {
1663 .get_frame
= dwc3_gadget_get_frame
,
1664 .wakeup
= dwc3_gadget_wakeup
,
1665 .set_selfpowered
= dwc3_gadget_set_selfpowered
,
1666 .pullup
= dwc3_gadget_pullup
,
1667 .udc_start
= dwc3_gadget_start
,
1668 .udc_stop
= dwc3_gadget_stop
,
1671 /* -------------------------------------------------------------------------- */
1673 static int dwc3_gadget_init_hw_endpoints(struct dwc3
*dwc
,
1674 u8 num
, u32 direction
)
1676 struct dwc3_ep
*dep
;
1679 for (i
= 0; i
< num
; i
++) {
1680 u8 epnum
= (i
<< 1) | (!!direction
);
1682 dep
= kzalloc(sizeof(*dep
), GFP_KERNEL
);
1684 dev_err(dwc
->dev
, "can't allocate endpoint %d\n",
1690 dep
->number
= epnum
;
1691 dep
->direction
= !!direction
;
1692 dwc
->eps
[epnum
] = dep
;
1694 snprintf(dep
->name
, sizeof(dep
->name
), "ep%d%s", epnum
>> 1,
1695 (epnum
& 1) ? "in" : "out");
1697 dep
->endpoint
.name
= dep
->name
;
1699 dev_vdbg(dwc
->dev
, "initializing %s\n", dep
->name
);
1701 if (epnum
== 0 || epnum
== 1) {
1702 usb_ep_set_maxpacket_limit(&dep
->endpoint
, 512);
1703 dep
->endpoint
.maxburst
= 1;
1704 dep
->endpoint
.ops
= &dwc3_gadget_ep0_ops
;
1706 dwc
->gadget
.ep0
= &dep
->endpoint
;
1710 usb_ep_set_maxpacket_limit(&dep
->endpoint
, 1024);
1711 dep
->endpoint
.max_streams
= 15;
1712 dep
->endpoint
.ops
= &dwc3_gadget_ep_ops
;
1713 list_add_tail(&dep
->endpoint
.ep_list
,
1714 &dwc
->gadget
.ep_list
);
1716 ret
= dwc3_alloc_trb_pool(dep
);
1721 INIT_LIST_HEAD(&dep
->request_list
);
1722 INIT_LIST_HEAD(&dep
->req_queued
);
1728 static int dwc3_gadget_init_endpoints(struct dwc3
*dwc
)
1732 INIT_LIST_HEAD(&dwc
->gadget
.ep_list
);
1734 ret
= dwc3_gadget_init_hw_endpoints(dwc
, dwc
->num_out_eps
, 0);
1736 dev_vdbg(dwc
->dev
, "failed to allocate OUT endpoints\n");
1740 ret
= dwc3_gadget_init_hw_endpoints(dwc
, dwc
->num_in_eps
, 1);
1742 dev_vdbg(dwc
->dev
, "failed to allocate IN endpoints\n");
1749 static void dwc3_gadget_free_endpoints(struct dwc3
*dwc
)
1751 struct dwc3_ep
*dep
;
1754 for (epnum
= 0; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
1755 dep
= dwc
->eps
[epnum
];
1759 * Physical endpoints 0 and 1 are special; they form the
1760 * bi-directional USB endpoint 0.
1762 * For those two physical endpoints, we don't allocate a TRB
1763 * pool nor do we add them the endpoints list. Due to that, we
1764 * shouldn't do these two operations otherwise we would end up
1765 * with all sorts of bugs when removing dwc3.ko.
1767 if (epnum
!= 0 && epnum
!= 1) {
1768 dwc3_free_trb_pool(dep
);
1769 list_del(&dep
->endpoint
.ep_list
);
1776 /* -------------------------------------------------------------------------- */
1778 static int __dwc3_cleanup_done_trbs(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
1779 struct dwc3_request
*req
, struct dwc3_trb
*trb
,
1780 const struct dwc3_event_depevt
*event
, int status
)
1783 unsigned int s_pkt
= 0;
1784 unsigned int trb_status
;
1786 if ((trb
->ctrl
& DWC3_TRB_CTRL_HWO
) && status
!= -ESHUTDOWN
)
1788 * We continue despite the error. There is not much we
1789 * can do. If we don't clean it up we loop forever. If
1790 * we skip the TRB then it gets overwritten after a
1791 * while since we use them in a ring buffer. A BUG()
1792 * would help. Lets hope that if this occurs, someone
1793 * fixes the root cause instead of looking away :)
1795 dev_err(dwc
->dev
, "%s's TRB (%p) still owned by HW\n",
1797 count
= trb
->size
& DWC3_TRB_SIZE_MASK
;
1799 if (dep
->direction
) {
1801 trb_status
= DWC3_TRB_SIZE_TRBSTS(trb
->size
);
1802 if (trb_status
== DWC3_TRBSTS_MISSED_ISOC
) {
1803 dev_dbg(dwc
->dev
, "incomplete IN transfer %s\n",
1806 * If missed isoc occurred and there is
1807 * no request queued then issue END
1808 * TRANSFER, so that core generates
1809 * next xfernotready and we will issue
1810 * a fresh START TRANSFER.
1811 * If there are still queued request
1812 * then wait, do not issue either END
1813 * or UPDATE TRANSFER, just attach next
1814 * request in request_list during
1815 * giveback.If any future queued request
1816 * is successfully transferred then we
1817 * will issue UPDATE TRANSFER for all
1818 * request in the request_list.
1820 dep
->flags
|= DWC3_EP_MISSED_ISOC
;
1822 dev_err(dwc
->dev
, "incomplete IN transfer %s\n",
1824 status
= -ECONNRESET
;
1827 dep
->flags
&= ~DWC3_EP_MISSED_ISOC
;
1830 if (count
&& (event
->status
& DEPEVT_STATUS_SHORT
))
1835 * We assume here we will always receive the entire data block
1836 * which we should receive. Meaning, if we program RX to
1837 * receive 4K but we receive only 2K, we assume that's all we
1838 * should receive and we simply bounce the request back to the
1839 * gadget driver for further processing.
1841 req
->request
.actual
+= req
->request
.length
- count
;
1844 if ((event
->status
& DEPEVT_STATUS_LST
) &&
1845 (trb
->ctrl
& (DWC3_TRB_CTRL_LST
|
1846 DWC3_TRB_CTRL_HWO
)))
1848 if ((event
->status
& DEPEVT_STATUS_IOC
) &&
1849 (trb
->ctrl
& DWC3_TRB_CTRL_IOC
))
1854 static int dwc3_cleanup_done_reqs(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
1855 const struct dwc3_event_depevt
*event
, int status
)
1857 struct dwc3_request
*req
;
1858 struct dwc3_trb
*trb
;
1864 req
= next_request(&dep
->req_queued
);
1871 slot
= req
->start_slot
+ i
;
1872 if ((slot
== DWC3_TRB_NUM
- 1) &&
1873 usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
1875 slot
%= DWC3_TRB_NUM
;
1876 trb
= &dep
->trb_pool
[slot
];
1878 ret
= __dwc3_cleanup_done_trbs(dwc
, dep
, req
, trb
,
1882 }while (++i
< req
->request
.num_mapped_sgs
);
1884 dwc3_gadget_giveback(dep
, req
, status
);
1890 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) &&
1891 list_empty(&dep
->req_queued
)) {
1892 if (list_empty(&dep
->request_list
)) {
1894 * If there is no entry in request list then do
1895 * not issue END TRANSFER now. Just set PENDING
1896 * flag, so that END TRANSFER is issued when an
1897 * entry is added into request list.
1899 dep
->flags
= DWC3_EP_PENDING_REQUEST
;
1901 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
1902 dep
->flags
= DWC3_EP_ENABLED
;
1910 static void dwc3_endpoint_transfer_complete(struct dwc3
*dwc
,
1911 struct dwc3_ep
*dep
, const struct dwc3_event_depevt
*event
,
1914 unsigned status
= 0;
1917 if (event
->status
& DEPEVT_STATUS_BUSERR
)
1918 status
= -ECONNRESET
;
1920 clean_busy
= dwc3_cleanup_done_reqs(dwc
, dep
, event
, status
);
1922 dep
->flags
&= ~DWC3_EP_BUSY
;
1925 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1926 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1928 if (dwc
->revision
< DWC3_REVISION_183A
) {
1932 for (i
= 0; i
< DWC3_ENDPOINTS_NUM
; i
++) {
1935 if (!(dep
->flags
& DWC3_EP_ENABLED
))
1938 if (!list_empty(&dep
->req_queued
))
1942 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1944 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1950 static void dwc3_endpoint_interrupt(struct dwc3
*dwc
,
1951 const struct dwc3_event_depevt
*event
)
1953 struct dwc3_ep
*dep
;
1954 u8 epnum
= event
->endpoint_number
;
1956 dep
= dwc
->eps
[epnum
];
1958 if (!(dep
->flags
& DWC3_EP_ENABLED
))
1961 dev_vdbg(dwc
->dev
, "%s: %s\n", dep
->name
,
1962 dwc3_ep_event_string(event
->endpoint_event
));
1964 if (epnum
== 0 || epnum
== 1) {
1965 dwc3_ep0_interrupt(dwc
, event
);
1969 switch (event
->endpoint_event
) {
1970 case DWC3_DEPEVT_XFERCOMPLETE
:
1971 dep
->resource_index
= 0;
1973 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1974 dev_dbg(dwc
->dev
, "%s is an Isochronous endpoint\n",
1979 dwc3_endpoint_transfer_complete(dwc
, dep
, event
, 1);
1981 case DWC3_DEPEVT_XFERINPROGRESS
:
1982 if (!usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1983 dev_dbg(dwc
->dev
, "%s is not an Isochronous endpoint\n",
1988 dwc3_endpoint_transfer_complete(dwc
, dep
, event
, 0);
1990 case DWC3_DEPEVT_XFERNOTREADY
:
1991 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1992 dwc3_gadget_start_isoc(dwc
, dep
, event
);
1996 dev_vdbg(dwc
->dev
, "%s: reason %s\n",
1997 dep
->name
, event
->status
&
1998 DEPEVT_STATUS_TRANSFER_ACTIVE
2000 : "Transfer Not Active");
2002 ret
= __dwc3_gadget_kick_transfer(dep
, 0, 1);
2003 if (!ret
|| ret
== -EBUSY
)
2006 dev_dbg(dwc
->dev
, "%s: failed to kick transfers\n",
2011 case DWC3_DEPEVT_STREAMEVT
:
2012 if (!usb_endpoint_xfer_bulk(dep
->endpoint
.desc
)) {
2013 dev_err(dwc
->dev
, "Stream event for non-Bulk %s\n",
2018 switch (event
->status
) {
2019 case DEPEVT_STREAMEVT_FOUND
:
2020 dev_vdbg(dwc
->dev
, "Stream %d found and started\n",
2024 case DEPEVT_STREAMEVT_NOTFOUND
:
2027 dev_dbg(dwc
->dev
, "Couldn't find suitable stream\n");
2030 case DWC3_DEPEVT_RXTXFIFOEVT
:
2031 dev_dbg(dwc
->dev
, "%s FIFO Overrun\n", dep
->name
);
2033 case DWC3_DEPEVT_EPCMDCMPLT
:
2034 dev_vdbg(dwc
->dev
, "Endpoint Command Complete\n");
2039 static void dwc3_disconnect_gadget(struct dwc3
*dwc
)
2041 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->disconnect
) {
2042 spin_unlock(&dwc
->lock
);
2043 dwc
->gadget_driver
->disconnect(&dwc
->gadget
);
2044 spin_lock(&dwc
->lock
);
2048 static void dwc3_suspend_gadget(struct dwc3
*dwc
)
2050 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->suspend
) {
2051 spin_unlock(&dwc
->lock
);
2052 dwc
->gadget_driver
->suspend(&dwc
->gadget
);
2053 spin_lock(&dwc
->lock
);
2057 static void dwc3_resume_gadget(struct dwc3
*dwc
)
2059 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->resume
) {
2060 spin_unlock(&dwc
->lock
);
2061 dwc
->gadget_driver
->resume(&dwc
->gadget
);
2062 spin_lock(&dwc
->lock
);
2066 static void dwc3_stop_active_transfer(struct dwc3
*dwc
, u32 epnum
, bool force
)
2068 struct dwc3_ep
*dep
;
2069 struct dwc3_gadget_ep_cmd_params params
;
2073 dep
= dwc
->eps
[epnum
];
2075 if (!dep
->resource_index
)
2079 * NOTICE: We are violating what the Databook says about the
2080 * EndTransfer command. Ideally we would _always_ wait for the
2081 * EndTransfer Command Completion IRQ, but that's causing too
2082 * much trouble synchronizing between us and gadget driver.
2084 * We have discussed this with the IP Provider and it was
2085 * suggested to giveback all requests here, but give HW some
2086 * extra time to synchronize with the interconnect. We're using
2087 * an arbitraty 100us delay for that.
2089 * Note also that a similar handling was tested by Synopsys
2090 * (thanks a lot Paul) and nothing bad has come out of it.
2091 * In short, what we're doing is:
2093 * - Issue EndTransfer WITH CMDIOC bit set
2097 cmd
= DWC3_DEPCMD_ENDTRANSFER
;
2098 cmd
|= force
? DWC3_DEPCMD_HIPRI_FORCERM
: 0;
2099 cmd
|= DWC3_DEPCMD_CMDIOC
;
2100 cmd
|= DWC3_DEPCMD_PARAM(dep
->resource_index
);
2101 memset(¶ms
, 0, sizeof(params
));
2102 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
, cmd
, ¶ms
);
2104 dep
->resource_index
= 0;
2105 dep
->flags
&= ~DWC3_EP_BUSY
;
2109 static void dwc3_stop_active_transfers(struct dwc3
*dwc
)
2113 for (epnum
= 2; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
2114 struct dwc3_ep
*dep
;
2116 dep
= dwc
->eps
[epnum
];
2120 if (!(dep
->flags
& DWC3_EP_ENABLED
))
2123 dwc3_remove_requests(dwc
, dep
);
2127 static void dwc3_clear_stall_all_ep(struct dwc3
*dwc
)
2131 for (epnum
= 1; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
2132 struct dwc3_ep
*dep
;
2133 struct dwc3_gadget_ep_cmd_params params
;
2136 dep
= dwc
->eps
[epnum
];
2140 if (!(dep
->flags
& DWC3_EP_STALL
))
2143 dep
->flags
&= ~DWC3_EP_STALL
;
2145 memset(¶ms
, 0, sizeof(params
));
2146 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
2147 DWC3_DEPCMD_CLEARSTALL
, ¶ms
);
2152 static void dwc3_gadget_disconnect_interrupt(struct dwc3
*dwc
)
2156 dev_vdbg(dwc
->dev
, "%s\n", __func__
);
2158 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2159 reg
&= ~DWC3_DCTL_INITU1ENA
;
2160 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2162 reg
&= ~DWC3_DCTL_INITU2ENA
;
2163 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2165 dwc3_disconnect_gadget(dwc
);
2166 dwc
->start_config_issued
= false;
2168 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2169 dwc
->setup_packet_pending
= false;
2172 static void dwc3_gadget_reset_interrupt(struct dwc3
*dwc
)
2176 dev_vdbg(dwc
->dev
, "%s\n", __func__
);
2179 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2180 * would cause a missing Disconnect Event if there's a
2181 * pending Setup Packet in the FIFO.
2183 * There's no suggested workaround on the official Bug
2184 * report, which states that "unless the driver/application
2185 * is doing any special handling of a disconnect event,
2186 * there is no functional issue".
2188 * Unfortunately, it turns out that we _do_ some special
2189 * handling of a disconnect event, namely complete all
2190 * pending transfers, notify gadget driver of the
2191 * disconnection, and so on.
2193 * Our suggested workaround is to follow the Disconnect
2194 * Event steps here, instead, based on a setup_packet_pending
2195 * flag. Such flag gets set whenever we have a XferNotReady
2196 * event on EP0 and gets cleared on XferComplete for the
2201 * STAR#9000466709: RTL: Device : Disconnect event not
2202 * generated if setup packet pending in FIFO
2204 if (dwc
->revision
< DWC3_REVISION_188A
) {
2205 if (dwc
->setup_packet_pending
)
2206 dwc3_gadget_disconnect_interrupt(dwc
);
2209 /* after reset -> Default State */
2210 usb_gadget_set_state(&dwc
->gadget
, USB_STATE_DEFAULT
);
2212 if (dwc
->gadget
.speed
!= USB_SPEED_UNKNOWN
)
2213 dwc3_disconnect_gadget(dwc
);
2215 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2216 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
2217 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2218 dwc
->test_mode
= false;
2220 dwc3_stop_active_transfers(dwc
);
2221 dwc3_clear_stall_all_ep(dwc
);
2222 dwc
->start_config_issued
= false;
2224 /* Reset device address to zero */
2225 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2226 reg
&= ~(DWC3_DCFG_DEVADDR_MASK
);
2227 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2230 static void dwc3_update_ram_clk_sel(struct dwc3
*dwc
, u32 speed
)
2233 u32 usb30_clock
= DWC3_GCTL_CLK_BUS
;
2236 * We change the clock only at SS but I dunno why I would want to do
2237 * this. Maybe it becomes part of the power saving plan.
2240 if (speed
!= DWC3_DSTS_SUPERSPEED
)
2244 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2245 * each time on Connect Done.
2250 reg
= dwc3_readl(dwc
->regs
, DWC3_GCTL
);
2251 reg
|= DWC3_GCTL_RAMCLKSEL(usb30_clock
);
2252 dwc3_writel(dwc
->regs
, DWC3_GCTL
, reg
);
2255 static void dwc3_gadget_conndone_interrupt(struct dwc3
*dwc
)
2257 struct dwc3_ep
*dep
;
2262 dev_vdbg(dwc
->dev
, "%s\n", __func__
);
2264 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
2265 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
2268 dwc3_update_ram_clk_sel(dwc
, speed
);
2271 case DWC3_DCFG_SUPERSPEED
:
2273 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2274 * would cause a missing USB3 Reset event.
2276 * In such situations, we should force a USB3 Reset
2277 * event by calling our dwc3_gadget_reset_interrupt()
2282 * STAR#9000483510: RTL: SS : USB3 reset event may
2283 * not be generated always when the link enters poll
2285 if (dwc
->revision
< DWC3_REVISION_190A
)
2286 dwc3_gadget_reset_interrupt(dwc
);
2288 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
2289 dwc
->gadget
.ep0
->maxpacket
= 512;
2290 dwc
->gadget
.speed
= USB_SPEED_SUPER
;
2292 case DWC3_DCFG_HIGHSPEED
:
2293 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2294 dwc
->gadget
.ep0
->maxpacket
= 64;
2295 dwc
->gadget
.speed
= USB_SPEED_HIGH
;
2297 case DWC3_DCFG_FULLSPEED2
:
2298 case DWC3_DCFG_FULLSPEED1
:
2299 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2300 dwc
->gadget
.ep0
->maxpacket
= 64;
2301 dwc
->gadget
.speed
= USB_SPEED_FULL
;
2303 case DWC3_DCFG_LOWSPEED
:
2304 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(8);
2305 dwc
->gadget
.ep0
->maxpacket
= 8;
2306 dwc
->gadget
.speed
= USB_SPEED_LOW
;
2310 /* Enable USB2 LPM Capability */
2312 if ((dwc
->revision
> DWC3_REVISION_194A
)
2313 && (speed
!= DWC3_DCFG_SUPERSPEED
)) {
2314 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2315 reg
|= DWC3_DCFG_LPM_CAP
;
2316 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2318 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2319 reg
&= ~(DWC3_DCTL_HIRD_THRES_MASK
| DWC3_DCTL_L1_HIBER_EN
);
2322 * TODO: This should be configurable. For now using
2323 * maximum allowed HIRD threshold value of 0b1100
2325 reg
|= DWC3_DCTL_HIRD_THRES(12);
2327 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2329 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2330 reg
&= ~DWC3_DCTL_HIRD_THRES_MASK
;
2331 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2335 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, true,
2338 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2343 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, true,
2346 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2351 * Configure PHY via GUSB3PIPECTLn if required.
2353 * Update GTXFIFOSIZn
2355 * In both cases reset values should be sufficient.
2359 static void dwc3_gadget_wakeup_interrupt(struct dwc3
*dwc
)
2361 dev_vdbg(dwc
->dev
, "%s\n", __func__
);
2364 * TODO take core out of low power mode when that's
2368 dwc
->gadget_driver
->resume(&dwc
->gadget
);
2371 static void dwc3_gadget_linksts_change_interrupt(struct dwc3
*dwc
,
2372 unsigned int evtinfo
)
2374 enum dwc3_link_state next
= evtinfo
& DWC3_LINK_STATE_MASK
;
2375 unsigned int pwropt
;
2378 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2379 * Hibernation mode enabled which would show up when device detects
2380 * host-initiated U3 exit.
2382 * In that case, device will generate a Link State Change Interrupt
2383 * from U3 to RESUME which is only necessary if Hibernation is
2386 * There are no functional changes due to such spurious event and we
2387 * just need to ignore it.
2391 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2394 pwropt
= DWC3_GHWPARAMS1_EN_PWROPT(dwc
->hwparams
.hwparams1
);
2395 if ((dwc
->revision
< DWC3_REVISION_250A
) &&
2396 (pwropt
!= DWC3_GHWPARAMS1_EN_PWROPT_HIB
)) {
2397 if ((dwc
->link_state
== DWC3_LINK_STATE_U3
) &&
2398 (next
== DWC3_LINK_STATE_RESUME
)) {
2399 dev_vdbg(dwc
->dev
, "ignoring transition U3 -> Resume\n");
2405 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2406 * on the link partner, the USB session might do multiple entry/exit
2407 * of low power states before a transfer takes place.
2409 * Due to this problem, we might experience lower throughput. The
2410 * suggested workaround is to disable DCTL[12:9] bits if we're
2411 * transitioning from U1/U2 to U0 and enable those bits again
2412 * after a transfer completes and there are no pending transfers
2413 * on any of the enabled endpoints.
2415 * This is the first half of that workaround.
2419 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2420 * core send LGO_Ux entering U0
2422 if (dwc
->revision
< DWC3_REVISION_183A
) {
2423 if (next
== DWC3_LINK_STATE_U0
) {
2427 switch (dwc
->link_state
) {
2428 case DWC3_LINK_STATE_U1
:
2429 case DWC3_LINK_STATE_U2
:
2430 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2431 u1u2
= reg
& (DWC3_DCTL_INITU2ENA
2432 | DWC3_DCTL_ACCEPTU2ENA
2433 | DWC3_DCTL_INITU1ENA
2434 | DWC3_DCTL_ACCEPTU1ENA
);
2437 dwc
->u1u2
= reg
& u1u2
;
2441 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2450 dwc
->link_state
= next
;
2453 case DWC3_LINK_STATE_U1
:
2454 if (dwc
->speed
== USB_SPEED_SUPER
)
2455 dwc3_suspend_gadget(dwc
);
2457 case DWC3_LINK_STATE_U2
:
2458 case DWC3_LINK_STATE_U3
:
2459 dwc3_suspend_gadget(dwc
);
2461 case DWC3_LINK_STATE_RESUME
:
2462 dwc3_resume_gadget(dwc
);
2469 dev_vdbg(dwc
->dev
, "%s link %d\n", __func__
, dwc
->link_state
);
2472 static void dwc3_gadget_hibernation_interrupt(struct dwc3
*dwc
,
2473 unsigned int evtinfo
)
2475 unsigned int is_ss
= evtinfo
& BIT(4);
2478 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2479 * have a known issue which can cause USB CV TD.9.23 to fail
2482 * Because of this issue, core could generate bogus hibernation
2483 * events which SW needs to ignore.
2487 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2488 * Device Fallback from SuperSpeed
2490 if (is_ss
^ (dwc
->speed
== USB_SPEED_SUPER
))
2493 /* enter hibernation here */
2496 static void dwc3_gadget_interrupt(struct dwc3
*dwc
,
2497 const struct dwc3_event_devt
*event
)
2499 switch (event
->type
) {
2500 case DWC3_DEVICE_EVENT_DISCONNECT
:
2501 dwc3_gadget_disconnect_interrupt(dwc
);
2503 case DWC3_DEVICE_EVENT_RESET
:
2504 dwc3_gadget_reset_interrupt(dwc
);
2506 case DWC3_DEVICE_EVENT_CONNECT_DONE
:
2507 dwc3_gadget_conndone_interrupt(dwc
);
2509 case DWC3_DEVICE_EVENT_WAKEUP
:
2510 dwc3_gadget_wakeup_interrupt(dwc
);
2512 case DWC3_DEVICE_EVENT_HIBER_REQ
:
2513 if (dev_WARN_ONCE(dwc
->dev
, !dwc
->has_hibernation
,
2514 "unexpected hibernation event\n"))
2517 dwc3_gadget_hibernation_interrupt(dwc
, event
->event_info
);
2519 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE
:
2520 dwc3_gadget_linksts_change_interrupt(dwc
, event
->event_info
);
2522 case DWC3_DEVICE_EVENT_EOPF
:
2523 dev_vdbg(dwc
->dev
, "End of Periodic Frame\n");
2525 case DWC3_DEVICE_EVENT_SOF
:
2526 dev_vdbg(dwc
->dev
, "Start of Periodic Frame\n");
2528 case DWC3_DEVICE_EVENT_ERRATIC_ERROR
:
2529 dev_vdbg(dwc
->dev
, "Erratic Error\n");
2531 case DWC3_DEVICE_EVENT_CMD_CMPL
:
2532 dev_vdbg(dwc
->dev
, "Command Complete\n");
2534 case DWC3_DEVICE_EVENT_OVERFLOW
:
2535 dev_vdbg(dwc
->dev
, "Overflow\n");
2538 dev_dbg(dwc
->dev
, "UNKNOWN IRQ %d\n", event
->type
);
2542 static void dwc3_process_event_entry(struct dwc3
*dwc
,
2543 const union dwc3_event
*event
)
2545 /* Endpoint IRQ, handle it and return early */
2546 if (event
->type
.is_devspec
== 0) {
2548 return dwc3_endpoint_interrupt(dwc
, &event
->depevt
);
2551 switch (event
->type
.type
) {
2552 case DWC3_EVENT_TYPE_DEV
:
2553 dwc3_gadget_interrupt(dwc
, &event
->devt
);
2555 /* REVISIT what to do with Carkit and I2C events ? */
2557 dev_err(dwc
->dev
, "UNKNOWN IRQ type %d\n", event
->raw
);
2561 static irqreturn_t
dwc3_process_event_buf(struct dwc3
*dwc
, u32 buf
)
2563 struct dwc3_event_buffer
*evt
;
2564 irqreturn_t ret
= IRQ_NONE
;
2568 evt
= dwc
->ev_buffs
[buf
];
2571 if (!(evt
->flags
& DWC3_EVENT_PENDING
))
2575 union dwc3_event event
;
2577 event
.raw
= *(u32
*) (evt
->buf
+ evt
->lpos
);
2579 dwc3_process_event_entry(dwc
, &event
);
2582 * FIXME we wrap around correctly to the next entry as
2583 * almost all entries are 4 bytes in size. There is one
2584 * entry which has 12 bytes which is a regular entry
2585 * followed by 8 bytes data. ATM I don't know how
2586 * things are organized if we get next to the a
2587 * boundary so I worry about that once we try to handle
2590 evt
->lpos
= (evt
->lpos
+ 4) % DWC3_EVENT_BUFFERS_SIZE
;
2593 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(buf
), 4);
2597 evt
->flags
&= ~DWC3_EVENT_PENDING
;
2600 /* Unmask interrupt */
2601 reg
= dwc3_readl(dwc
->regs
, DWC3_GEVNTSIZ(buf
));
2602 reg
&= ~DWC3_GEVNTSIZ_INTMASK
;
2603 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(buf
), reg
);
2608 static irqreturn_t
dwc3_thread_interrupt(int irq
, void *_dwc
)
2610 struct dwc3
*dwc
= _dwc
;
2611 unsigned long flags
;
2612 irqreturn_t ret
= IRQ_NONE
;
2615 spin_lock_irqsave(&dwc
->lock
, flags
);
2617 for (i
= 0; i
< dwc
->num_event_buffers
; i
++)
2618 ret
|= dwc3_process_event_buf(dwc
, i
);
2620 spin_unlock_irqrestore(&dwc
->lock
, flags
);
2625 static irqreturn_t
dwc3_check_event_buf(struct dwc3
*dwc
, u32 buf
)
2627 struct dwc3_event_buffer
*evt
;
2631 evt
= dwc
->ev_buffs
[buf
];
2633 count
= dwc3_readl(dwc
->regs
, DWC3_GEVNTCOUNT(buf
));
2634 count
&= DWC3_GEVNTCOUNT_MASK
;
2639 evt
->flags
|= DWC3_EVENT_PENDING
;
2641 /* Mask interrupt */
2642 reg
= dwc3_readl(dwc
->regs
, DWC3_GEVNTSIZ(buf
));
2643 reg
|= DWC3_GEVNTSIZ_INTMASK
;
2644 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(buf
), reg
);
2646 return IRQ_WAKE_THREAD
;
2649 static irqreturn_t
dwc3_interrupt(int irq
, void *_dwc
)
2651 struct dwc3
*dwc
= _dwc
;
2653 irqreturn_t ret
= IRQ_NONE
;
2655 spin_lock(&dwc
->lock
);
2657 for (i
= 0; i
< dwc
->num_event_buffers
; i
++) {
2660 status
= dwc3_check_event_buf(dwc
, i
);
2661 if (status
== IRQ_WAKE_THREAD
)
2665 spin_unlock(&dwc
->lock
);
2671 * dwc3_gadget_init - Initializes gadget related registers
2672 * @dwc: pointer to our controller context structure
2674 * Returns 0 on success otherwise negative errno.
2676 int dwc3_gadget_init(struct dwc3
*dwc
)
2680 dwc
->ctrl_req
= dma_alloc_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
2681 &dwc
->ctrl_req_addr
, GFP_KERNEL
);
2682 if (!dwc
->ctrl_req
) {
2683 dev_err(dwc
->dev
, "failed to allocate ctrl request\n");
2688 dwc
->ep0_trb
= dma_alloc_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
),
2689 &dwc
->ep0_trb_addr
, GFP_KERNEL
);
2690 if (!dwc
->ep0_trb
) {
2691 dev_err(dwc
->dev
, "failed to allocate ep0 trb\n");
2696 dwc
->setup_buf
= kzalloc(DWC3_EP0_BOUNCE_SIZE
, GFP_KERNEL
);
2697 if (!dwc
->setup_buf
) {
2698 dev_err(dwc
->dev
, "failed to allocate setup buffer\n");
2703 dwc
->ep0_bounce
= dma_alloc_coherent(dwc
->dev
,
2704 DWC3_EP0_BOUNCE_SIZE
, &dwc
->ep0_bounce_addr
,
2706 if (!dwc
->ep0_bounce
) {
2707 dev_err(dwc
->dev
, "failed to allocate ep0 bounce buffer\n");
2712 dwc
->gadget
.ops
= &dwc3_gadget_ops
;
2713 dwc
->gadget
.max_speed
= USB_SPEED_SUPER
;
2714 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2715 dwc
->gadget
.sg_supported
= true;
2716 dwc
->gadget
.name
= "dwc3-gadget";
2719 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2722 dwc
->gadget
.quirk_ep_out_aligned_size
= true;
2725 * REVISIT: Here we should clear all pending IRQs to be
2726 * sure we're starting from a well known location.
2729 ret
= dwc3_gadget_init_endpoints(dwc
);
2733 ret
= usb_add_gadget_udc(dwc
->dev
, &dwc
->gadget
);
2735 dev_err(dwc
->dev
, "failed to register udc\n");
2742 dwc3_gadget_free_endpoints(dwc
);
2743 dma_free_coherent(dwc
->dev
, DWC3_EP0_BOUNCE_SIZE
,
2744 dwc
->ep0_bounce
, dwc
->ep0_bounce_addr
);
2747 kfree(dwc
->setup_buf
);
2750 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
),
2751 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
2754 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
2755 dwc
->ctrl_req
, dwc
->ctrl_req_addr
);
2761 /* -------------------------------------------------------------------------- */
2763 void dwc3_gadget_exit(struct dwc3
*dwc
)
2765 usb_del_gadget_udc(&dwc
->gadget
);
2767 dwc3_gadget_free_endpoints(dwc
);
2769 dma_free_coherent(dwc
->dev
, DWC3_EP0_BOUNCE_SIZE
,
2770 dwc
->ep0_bounce
, dwc
->ep0_bounce_addr
);
2772 kfree(dwc
->setup_buf
);
2774 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
),
2775 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
2777 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
2778 dwc
->ctrl_req
, dwc
->ctrl_req_addr
);
2781 int dwc3_gadget_prepare(struct dwc3
*dwc
)
2783 if (dwc
->pullups_connected
) {
2784 dwc3_gadget_disable_irq(dwc
);
2785 dwc3_gadget_run_stop(dwc
, true, true);
2791 void dwc3_gadget_complete(struct dwc3
*dwc
)
2793 if (dwc
->pullups_connected
) {
2794 dwc3_gadget_enable_irq(dwc
);
2795 dwc3_gadget_run_stop(dwc
, true, false);
2799 int dwc3_gadget_suspend(struct dwc3
*dwc
)
2801 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
2802 __dwc3_gadget_ep_disable(dwc
->eps
[1]);
2804 dwc
->dcfg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2809 int dwc3_gadget_resume(struct dwc3
*dwc
)
2811 struct dwc3_ep
*dep
;
2814 /* Start with SuperSpeed Default */
2815 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
2818 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, false,
2824 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, false,
2829 /* begin to receive SETUP packets */
2830 dwc
->ep0state
= EP0_SETUP_PHASE
;
2831 dwc3_ep0_out_start(dwc
);
2833 dwc3_writel(dwc
->regs
, DWC3_DCFG
, dwc
->dcfg
);
2838 __dwc3_gadget_ep_disable(dwc
->eps
[0]);