2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/interrupt.h>
27 #include <linux/list.h>
28 #include <linux/dma-mapping.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
47 int dwc3_gadget_set_test_mode(struct dwc3
*dwc
, int mode
)
51 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
52 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
66 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
78 int dwc3_gadget_get_link_state(struct dwc3
*dwc
)
82 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
84 return DWC3_DSTS_USBLNKST(reg
);
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
92 * Caller should take care of locking. This function will
93 * return 0 on success or -ETIMEDOUT.
95 int dwc3_gadget_set_link_state(struct dwc3
*dwc
, enum dwc3_link_state state
)
101 * Wait until device controller is ready. Only applies to 1.94a and
104 if (dwc
->revision
>= DWC3_REVISION_194A
) {
106 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
107 if (reg
& DWC3_DSTS_DCNRD
)
117 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
118 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
120 /* set requested state */
121 reg
|= DWC3_DCTL_ULSTCHNGREQ(state
);
122 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
128 if (dwc
->revision
>= DWC3_REVISION_194A
)
131 /* wait for a change in DSTS */
134 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
136 if (DWC3_DSTS_USBLNKST(reg
) == state
)
142 dwc3_trace(trace_dwc3_gadget
,
143 "link state change request timed out");
149 * dwc3_ep_inc_trb() - Increment a TRB index.
150 * @index - Pointer to the TRB index to increment.
152 * The index should never point to the link TRB. After incrementing,
153 * if it is point to the link TRB, wrap around to the beginning. The
154 * link TRB is always at the last TRB entry.
156 static void dwc3_ep_inc_trb(u8
*index
)
159 if (*index
== (DWC3_TRB_NUM
- 1))
163 static void dwc3_ep_inc_enq(struct dwc3_ep
*dep
)
165 dwc3_ep_inc_trb(&dep
->trb_enqueue
);
168 static void dwc3_ep_inc_deq(struct dwc3_ep
*dep
)
170 dwc3_ep_inc_trb(&dep
->trb_dequeue
);
173 void dwc3_gadget_giveback(struct dwc3_ep
*dep
, struct dwc3_request
*req
,
176 struct dwc3
*dwc
= dep
->dwc
;
178 req
->started
= false;
179 list_del(&req
->list
);
182 if (req
->request
.status
== -EINPROGRESS
)
183 req
->request
.status
= status
;
185 if (dwc
->ep0_bounced
&& dep
->number
== 0)
186 dwc
->ep0_bounced
= false;
188 usb_gadget_unmap_request(&dwc
->gadget
, &req
->request
,
191 trace_dwc3_gadget_giveback(req
);
193 spin_unlock(&dwc
->lock
);
194 usb_gadget_giveback_request(&dep
->endpoint
, &req
->request
);
195 spin_lock(&dwc
->lock
);
198 pm_runtime_put(dwc
->dev
);
201 int dwc3_send_gadget_generic_command(struct dwc3
*dwc
, unsigned cmd
, u32 param
)
208 dwc3_writel(dwc
->regs
, DWC3_DGCMDPAR
, param
);
209 dwc3_writel(dwc
->regs
, DWC3_DGCMD
, cmd
| DWC3_DGCMD_CMDACT
);
212 reg
= dwc3_readl(dwc
->regs
, DWC3_DGCMD
);
213 if (!(reg
& DWC3_DGCMD_CMDACT
)) {
214 status
= DWC3_DGCMD_STATUS(reg
);
226 trace_dwc3_gadget_generic_cmd(cmd
, param
, status
);
231 static int __dwc3_gadget_wakeup(struct dwc3
*dwc
);
233 int dwc3_send_gadget_ep_cmd(struct dwc3_ep
*dep
, unsigned cmd
,
234 struct dwc3_gadget_ep_cmd_params
*params
)
236 struct dwc3
*dwc
= dep
->dwc
;
245 * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
246 * we're issuing an endpoint command, we must check if
247 * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
249 * We will also set SUSPHY bit to what it was before returning as stated
250 * by the same section on Synopsys databook.
252 if (dwc
->gadget
.speed
<= USB_SPEED_HIGH
) {
253 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
254 if (unlikely(reg
& DWC3_GUSB2PHYCFG_SUSPHY
)) {
256 reg
&= ~DWC3_GUSB2PHYCFG_SUSPHY
;
257 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
261 if (DWC3_DEPCMD_CMD(cmd
) == DWC3_DEPCMD_STARTTRANSFER
) {
264 needs_wakeup
= (dwc
->link_state
== DWC3_LINK_STATE_U1
||
265 dwc
->link_state
== DWC3_LINK_STATE_U2
||
266 dwc
->link_state
== DWC3_LINK_STATE_U3
);
268 if (unlikely(needs_wakeup
)) {
269 ret
= __dwc3_gadget_wakeup(dwc
);
270 dev_WARN_ONCE(dwc
->dev
, ret
, "wakeup failed --> %d\n",
275 dwc3_writel(dep
->regs
, DWC3_DEPCMDPAR0
, params
->param0
);
276 dwc3_writel(dep
->regs
, DWC3_DEPCMDPAR1
, params
->param1
);
277 dwc3_writel(dep
->regs
, DWC3_DEPCMDPAR2
, params
->param2
);
279 dwc3_writel(dep
->regs
, DWC3_DEPCMD
, cmd
| DWC3_DEPCMD_CMDACT
);
281 reg
= dwc3_readl(dep
->regs
, DWC3_DEPCMD
);
282 if (!(reg
& DWC3_DEPCMD_CMDACT
)) {
283 cmd_status
= DWC3_DEPCMD_STATUS(reg
);
285 switch (cmd_status
) {
289 case DEPEVT_TRANSFER_NO_RESOURCE
:
292 case DEPEVT_TRANSFER_BUS_EXPIRY
:
294 * SW issues START TRANSFER command to
295 * isochronous ep with future frame interval. If
296 * future interval time has already passed when
297 * core receives the command, it will respond
298 * with an error status of 'Bus Expiry'.
300 * Instead of always returning -EINVAL, let's
301 * give a hint to the gadget driver that this is
302 * the case by returning -EAGAIN.
307 dev_WARN(dwc
->dev
, "UNKNOWN cmd status\n");
316 cmd_status
= -ETIMEDOUT
;
319 trace_dwc3_gadget_ep_cmd(dep
, cmd
, params
, cmd_status
);
321 if (unlikely(susphy
)) {
322 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
323 reg
|= DWC3_GUSB2PHYCFG_SUSPHY
;
324 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
330 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep
*dep
)
332 struct dwc3
*dwc
= dep
->dwc
;
333 struct dwc3_gadget_ep_cmd_params params
;
334 u32 cmd
= DWC3_DEPCMD_CLEARSTALL
;
337 * As of core revision 2.60a the recommended programming model
338 * is to set the ClearPendIN bit when issuing a Clear Stall EP
339 * command for IN endpoints. This is to prevent an issue where
340 * some (non-compliant) hosts may not send ACK TPs for pending
341 * IN transfers due to a mishandled error condition. Synopsys
344 if (dep
->direction
&& (dwc
->revision
>= DWC3_REVISION_260A
) &&
345 (dwc
->gadget
.speed
>= USB_SPEED_SUPER
))
346 cmd
|= DWC3_DEPCMD_CLEARPENDIN
;
348 memset(¶ms
, 0, sizeof(params
));
350 return dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
353 static dma_addr_t
dwc3_trb_dma_offset(struct dwc3_ep
*dep
,
354 struct dwc3_trb
*trb
)
356 u32 offset
= (char *) trb
- (char *) dep
->trb_pool
;
358 return dep
->trb_pool_dma
+ offset
;
361 static int dwc3_alloc_trb_pool(struct dwc3_ep
*dep
)
363 struct dwc3
*dwc
= dep
->dwc
;
368 dep
->trb_pool
= dma_alloc_coherent(dwc
->dev
,
369 sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
370 &dep
->trb_pool_dma
, GFP_KERNEL
);
371 if (!dep
->trb_pool
) {
372 dev_err(dep
->dwc
->dev
, "failed to allocate trb pool for %s\n",
380 static void dwc3_free_trb_pool(struct dwc3_ep
*dep
)
382 struct dwc3
*dwc
= dep
->dwc
;
384 dma_free_coherent(dwc
->dev
, sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
385 dep
->trb_pool
, dep
->trb_pool_dma
);
387 dep
->trb_pool
= NULL
;
388 dep
->trb_pool_dma
= 0;
391 static int dwc3_gadget_set_xfer_resource(struct dwc3
*dwc
, struct dwc3_ep
*dep
);
394 * dwc3_gadget_start_config - Configure EP resources
395 * @dwc: pointer to our controller context structure
396 * @dep: endpoint that is being enabled
398 * The assignment of transfer resources cannot perfectly follow the
399 * data book due to the fact that the controller driver does not have
400 * all knowledge of the configuration in advance. It is given this
401 * information piecemeal by the composite gadget framework after every
402 * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
403 * programming model in this scenario can cause errors. For two
406 * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
407 * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
408 * multiple interfaces.
410 * 2) The databook does not mention doing more DEPXFERCFG for new
411 * endpoint on alt setting (8.1.6).
413 * The following simplified method is used instead:
415 * All hardware endpoints can be assigned a transfer resource and this
416 * setting will stay persistent until either a core reset or
417 * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
418 * do DEPXFERCFG for every hardware endpoint as well. We are
419 * guaranteed that there are as many transfer resources as endpoints.
421 * This function is called for each endpoint when it is being enabled
422 * but is triggered only when called for EP0-out, which always happens
423 * first, and which should only happen in one of the above conditions.
425 static int dwc3_gadget_start_config(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
427 struct dwc3_gadget_ep_cmd_params params
;
435 memset(¶ms
, 0x00, sizeof(params
));
436 cmd
= DWC3_DEPCMD_DEPSTARTCFG
;
438 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
442 for (i
= 0; i
< DWC3_ENDPOINTS_NUM
; i
++) {
443 struct dwc3_ep
*dep
= dwc
->eps
[i
];
448 ret
= dwc3_gadget_set_xfer_resource(dwc
, dep
);
456 static int dwc3_gadget_set_ep_config(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
457 const struct usb_endpoint_descriptor
*desc
,
458 const struct usb_ss_ep_comp_descriptor
*comp_desc
,
459 bool modify
, bool restore
)
461 struct dwc3_gadget_ep_cmd_params params
;
463 if (dev_WARN_ONCE(dwc
->dev
, modify
&& restore
,
464 "Can't modify and restore\n"))
467 memset(¶ms
, 0x00, sizeof(params
));
469 params
.param0
= DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc
))
470 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc
));
472 /* Burst size is only needed in SuperSpeed mode */
473 if (dwc
->gadget
.speed
>= USB_SPEED_SUPER
) {
474 u32 burst
= dep
->endpoint
.maxburst
;
475 params
.param0
|= DWC3_DEPCFG_BURST_SIZE(burst
- 1);
479 params
.param0
|= DWC3_DEPCFG_ACTION_MODIFY
;
480 } else if (restore
) {
481 params
.param0
|= DWC3_DEPCFG_ACTION_RESTORE
;
482 params
.param2
|= dep
->saved_state
;
484 params
.param0
|= DWC3_DEPCFG_ACTION_INIT
;
487 if (usb_endpoint_xfer_control(desc
))
488 params
.param1
= DWC3_DEPCFG_XFER_COMPLETE_EN
;
490 if (dep
->number
<= 1 || usb_endpoint_xfer_isoc(desc
))
491 params
.param1
|= DWC3_DEPCFG_XFER_NOT_READY_EN
;
493 if (usb_ss_max_streams(comp_desc
) && usb_endpoint_xfer_bulk(desc
)) {
494 params
.param1
|= DWC3_DEPCFG_STREAM_CAPABLE
495 | DWC3_DEPCFG_STREAM_EVENT_EN
;
496 dep
->stream_capable
= true;
499 if (!usb_endpoint_xfer_control(desc
))
500 params
.param1
|= DWC3_DEPCFG_XFER_IN_PROGRESS_EN
;
503 * We are doing 1:1 mapping for endpoints, meaning
504 * Physical Endpoints 2 maps to Logical Endpoint 2 and
505 * so on. We consider the direction bit as part of the physical
506 * endpoint number. So USB endpoint 0x81 is 0x03.
508 params
.param1
|= DWC3_DEPCFG_EP_NUMBER(dep
->number
);
511 * We must use the lower 16 TX FIFOs even though
515 params
.param0
|= DWC3_DEPCFG_FIFO_NUMBER(dep
->number
>> 1);
517 if (desc
->bInterval
) {
518 params
.param1
|= DWC3_DEPCFG_BINTERVAL_M1(desc
->bInterval
- 1);
519 dep
->interval
= 1 << (desc
->bInterval
- 1);
522 return dwc3_send_gadget_ep_cmd(dep
, DWC3_DEPCMD_SETEPCONFIG
, ¶ms
);
525 static int dwc3_gadget_set_xfer_resource(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
527 struct dwc3_gadget_ep_cmd_params params
;
529 memset(¶ms
, 0x00, sizeof(params
));
531 params
.param0
= DWC3_DEPXFERCFG_NUM_XFER_RES(1);
533 return dwc3_send_gadget_ep_cmd(dep
, DWC3_DEPCMD_SETTRANSFRESOURCE
,
538 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
539 * @dep: endpoint to be initialized
540 * @desc: USB Endpoint Descriptor
542 * Caller should take care of locking
544 static int __dwc3_gadget_ep_enable(struct dwc3_ep
*dep
,
545 const struct usb_endpoint_descriptor
*desc
,
546 const struct usb_ss_ep_comp_descriptor
*comp_desc
,
547 bool modify
, bool restore
)
549 struct dwc3
*dwc
= dep
->dwc
;
553 dwc3_trace(trace_dwc3_gadget
, "Enabling %s", dep
->name
);
555 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
556 ret
= dwc3_gadget_start_config(dwc
, dep
);
561 ret
= dwc3_gadget_set_ep_config(dwc
, dep
, desc
, comp_desc
, modify
,
566 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
567 struct dwc3_trb
*trb_st_hw
;
568 struct dwc3_trb
*trb_link
;
570 dep
->endpoint
.desc
= desc
;
571 dep
->comp_desc
= comp_desc
;
572 dep
->type
= usb_endpoint_type(desc
);
573 dep
->flags
|= DWC3_EP_ENABLED
;
575 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
576 reg
|= DWC3_DALEPENA_EP(dep
->number
);
577 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
579 if (usb_endpoint_xfer_control(desc
))
582 /* Initialize the TRB ring */
583 dep
->trb_dequeue
= 0;
584 dep
->trb_enqueue
= 0;
585 memset(dep
->trb_pool
, 0,
586 sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
);
588 /* Link TRB. The HWO bit is never reset */
589 trb_st_hw
= &dep
->trb_pool
[0];
591 trb_link
= &dep
->trb_pool
[DWC3_TRB_NUM
- 1];
592 trb_link
->bpl
= lower_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
593 trb_link
->bph
= upper_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
594 trb_link
->ctrl
|= DWC3_TRBCTL_LINK_TRB
;
595 trb_link
->ctrl
|= DWC3_TRB_CTRL_HWO
;
601 static void dwc3_stop_active_transfer(struct dwc3
*dwc
, u32 epnum
, bool force
);
602 static void dwc3_remove_requests(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
604 struct dwc3_request
*req
;
606 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
608 /* - giveback all requests to gadget driver */
609 while (!list_empty(&dep
->started_list
)) {
610 req
= next_request(&dep
->started_list
);
612 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
615 while (!list_empty(&dep
->pending_list
)) {
616 req
= next_request(&dep
->pending_list
);
618 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
623 * __dwc3_gadget_ep_disable - Disables a HW endpoint
624 * @dep: the endpoint to disable
626 * This function also removes requests which are currently processed ny the
627 * hardware and those which are not yet scheduled.
628 * Caller should take care of locking.
630 static int __dwc3_gadget_ep_disable(struct dwc3_ep
*dep
)
632 struct dwc3
*dwc
= dep
->dwc
;
635 dwc3_trace(trace_dwc3_gadget
, "Disabling %s", dep
->name
);
637 dwc3_remove_requests(dwc
, dep
);
639 /* make sure HW endpoint isn't stalled */
640 if (dep
->flags
& DWC3_EP_STALL
)
641 __dwc3_gadget_ep_set_halt(dep
, 0, false);
643 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
644 reg
&= ~DWC3_DALEPENA_EP(dep
->number
);
645 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
647 dep
->stream_capable
= false;
648 dep
->endpoint
.desc
= NULL
;
649 dep
->comp_desc
= NULL
;
656 /* -------------------------------------------------------------------------- */
658 static int dwc3_gadget_ep0_enable(struct usb_ep
*ep
,
659 const struct usb_endpoint_descriptor
*desc
)
664 static int dwc3_gadget_ep0_disable(struct usb_ep
*ep
)
669 /* -------------------------------------------------------------------------- */
671 static int dwc3_gadget_ep_enable(struct usb_ep
*ep
,
672 const struct usb_endpoint_descriptor
*desc
)
679 if (!ep
|| !desc
|| desc
->bDescriptorType
!= USB_DT_ENDPOINT
) {
680 pr_debug("dwc3: invalid parameters\n");
684 if (!desc
->wMaxPacketSize
) {
685 pr_debug("dwc3: missing wMaxPacketSize\n");
689 dep
= to_dwc3_ep(ep
);
692 if (dev_WARN_ONCE(dwc
->dev
, dep
->flags
& DWC3_EP_ENABLED
,
693 "%s is already enabled\n",
697 spin_lock_irqsave(&dwc
->lock
, flags
);
698 ret
= __dwc3_gadget_ep_enable(dep
, desc
, ep
->comp_desc
, false, false);
699 spin_unlock_irqrestore(&dwc
->lock
, flags
);
704 static int dwc3_gadget_ep_disable(struct usb_ep
*ep
)
712 pr_debug("dwc3: invalid parameters\n");
716 dep
= to_dwc3_ep(ep
);
719 if (dev_WARN_ONCE(dwc
->dev
, !(dep
->flags
& DWC3_EP_ENABLED
),
720 "%s is already disabled\n",
724 spin_lock_irqsave(&dwc
->lock
, flags
);
725 ret
= __dwc3_gadget_ep_disable(dep
);
726 spin_unlock_irqrestore(&dwc
->lock
, flags
);
731 static struct usb_request
*dwc3_gadget_ep_alloc_request(struct usb_ep
*ep
,
734 struct dwc3_request
*req
;
735 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
737 req
= kzalloc(sizeof(*req
), gfp_flags
);
741 req
->epnum
= dep
->number
;
744 dep
->allocated_requests
++;
746 trace_dwc3_alloc_request(req
);
748 return &req
->request
;
751 static void dwc3_gadget_ep_free_request(struct usb_ep
*ep
,
752 struct usb_request
*request
)
754 struct dwc3_request
*req
= to_dwc3_request(request
);
755 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
757 dep
->allocated_requests
--;
758 trace_dwc3_free_request(req
);
762 static u32
dwc3_calc_trbs_left(struct dwc3_ep
*dep
);
765 * dwc3_prepare_one_trb - setup one TRB from one request
766 * @dep: endpoint for which this request is prepared
767 * @req: dwc3_request pointer
769 static void dwc3_prepare_one_trb(struct dwc3_ep
*dep
,
770 struct dwc3_request
*req
, dma_addr_t dma
,
771 unsigned length
, unsigned chain
, unsigned node
)
773 struct dwc3_trb
*trb
;
774 struct dwc3
*dwc
= dep
->dwc
;
775 struct usb_gadget
*gadget
= &dwc
->gadget
;
776 enum usb_device_speed speed
= gadget
->speed
;
778 dwc3_trace(trace_dwc3_gadget
, "%s: req %p dma %08llx length %d%s",
779 dep
->name
, req
, (unsigned long long) dma
,
780 length
, chain
? " chain" : "");
782 trb
= &dep
->trb_pool
[dep
->trb_enqueue
];
785 dwc3_gadget_move_started_request(req
);
787 req
->trb_dma
= dwc3_trb_dma_offset(dep
, trb
);
788 req
->first_trb_index
= dep
->trb_enqueue
;
789 dep
->queued_requests
++;
792 dwc3_ep_inc_enq(dep
);
794 trb
->size
= DWC3_TRB_SIZE_LENGTH(length
);
795 trb
->bpl
= lower_32_bits(dma
);
796 trb
->bph
= upper_32_bits(dma
);
798 switch (usb_endpoint_type(dep
->endpoint
.desc
)) {
799 case USB_ENDPOINT_XFER_CONTROL
:
800 trb
->ctrl
= DWC3_TRBCTL_CONTROL_SETUP
;
803 case USB_ENDPOINT_XFER_ISOC
:
805 trb
->ctrl
= DWC3_TRBCTL_ISOCHRONOUS_FIRST
;
807 if (speed
== USB_SPEED_HIGH
) {
808 struct usb_ep
*ep
= &dep
->endpoint
;
809 trb
->size
|= DWC3_TRB_SIZE_PCM1(ep
->mult
- 1);
812 trb
->ctrl
= DWC3_TRBCTL_ISOCHRONOUS
;
815 /* always enable Interrupt on Missed ISOC */
816 trb
->ctrl
|= DWC3_TRB_CTRL_ISP_IMI
;
819 case USB_ENDPOINT_XFER_BULK
:
820 case USB_ENDPOINT_XFER_INT
:
821 trb
->ctrl
= DWC3_TRBCTL_NORMAL
;
825 * This is only possible with faulty memory because we
826 * checked it already :)
831 /* always enable Continue on Short Packet */
832 trb
->ctrl
|= DWC3_TRB_CTRL_CSP
;
834 if ((!req
->request
.no_interrupt
&& !chain
) ||
835 (dwc3_calc_trbs_left(dep
) == 0))
836 trb
->ctrl
|= DWC3_TRB_CTRL_IOC
| DWC3_TRB_CTRL_ISP_IMI
;
839 trb
->ctrl
|= DWC3_TRB_CTRL_CHN
;
841 if (usb_endpoint_xfer_bulk(dep
->endpoint
.desc
) && dep
->stream_capable
)
842 trb
->ctrl
|= DWC3_TRB_CTRL_SID_SOFN(req
->request
.stream_id
);
844 trb
->ctrl
|= DWC3_TRB_CTRL_HWO
;
846 trace_dwc3_prepare_trb(dep
, trb
);
850 * dwc3_ep_prev_trb() - Returns the previous TRB in the ring
851 * @dep: The endpoint with the TRB ring
852 * @index: The index of the current TRB in the ring
854 * Returns the TRB prior to the one pointed to by the index. If the
855 * index is 0, we will wrap backwards, skip the link TRB, and return
856 * the one just before that.
858 static struct dwc3_trb
*dwc3_ep_prev_trb(struct dwc3_ep
*dep
, u8 index
)
863 tmp
= DWC3_TRB_NUM
- 1;
865 return &dep
->trb_pool
[tmp
- 1];
868 static u32
dwc3_calc_trbs_left(struct dwc3_ep
*dep
)
870 struct dwc3_trb
*tmp
;
874 * If enqueue & dequeue are equal than it is either full or empty.
876 * One way to know for sure is if the TRB right before us has HWO bit
877 * set or not. If it has, then we're definitely full and can't fit any
878 * more transfers in our ring.
880 if (dep
->trb_enqueue
== dep
->trb_dequeue
) {
881 tmp
= dwc3_ep_prev_trb(dep
, dep
->trb_enqueue
);
882 if (tmp
->ctrl
& DWC3_TRB_CTRL_HWO
)
885 return DWC3_TRB_NUM
- 1;
888 trbs_left
= dep
->trb_dequeue
- dep
->trb_enqueue
;
889 trbs_left
&= (DWC3_TRB_NUM
- 1);
891 if (dep
->trb_dequeue
< dep
->trb_enqueue
)
897 static void dwc3_prepare_one_trb_sg(struct dwc3_ep
*dep
,
898 struct dwc3_request
*req
)
900 struct scatterlist
*sg
= req
->sg
;
901 struct scatterlist
*s
;
906 for_each_sg(sg
, s
, req
->num_pending_sgs
, i
) {
907 unsigned chain
= true;
909 length
= sg_dma_len(s
);
910 dma
= sg_dma_address(s
);
915 dwc3_prepare_one_trb(dep
, req
, dma
, length
,
918 if (!dwc3_calc_trbs_left(dep
))
923 static void dwc3_prepare_one_trb_linear(struct dwc3_ep
*dep
,
924 struct dwc3_request
*req
)
929 dma
= req
->request
.dma
;
930 length
= req
->request
.length
;
932 dwc3_prepare_one_trb(dep
, req
, dma
, length
,
937 * dwc3_prepare_trbs - setup TRBs from requests
938 * @dep: endpoint for which requests are being prepared
940 * The function goes through the requests list and sets up TRBs for the
941 * transfers. The function returns once there are no more TRBs available or
942 * it runs out of requests.
944 static void dwc3_prepare_trbs(struct dwc3_ep
*dep
)
946 struct dwc3_request
*req
, *n
;
948 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM
);
950 if (!dwc3_calc_trbs_left(dep
))
953 list_for_each_entry_safe(req
, n
, &dep
->pending_list
, list
) {
954 if (req
->num_pending_sgs
> 0)
955 dwc3_prepare_one_trb_sg(dep
, req
);
957 dwc3_prepare_one_trb_linear(dep
, req
);
959 if (!dwc3_calc_trbs_left(dep
))
964 static int __dwc3_gadget_kick_transfer(struct dwc3_ep
*dep
, u16 cmd_param
)
966 struct dwc3_gadget_ep_cmd_params params
;
967 struct dwc3_request
*req
;
968 struct dwc3
*dwc
= dep
->dwc
;
973 starting
= !(dep
->flags
& DWC3_EP_BUSY
);
975 dwc3_prepare_trbs(dep
);
976 req
= next_request(&dep
->started_list
);
978 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
982 memset(¶ms
, 0, sizeof(params
));
985 params
.param0
= upper_32_bits(req
->trb_dma
);
986 params
.param1
= lower_32_bits(req
->trb_dma
);
987 cmd
= DWC3_DEPCMD_STARTTRANSFER
|
988 DWC3_DEPCMD_PARAM(cmd_param
);
990 cmd
= DWC3_DEPCMD_UPDATETRANSFER
|
991 DWC3_DEPCMD_PARAM(dep
->resource_index
);
994 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
997 * FIXME we need to iterate over the list of requests
998 * here and stop, unmap, free and del each of the linked
999 * requests instead of what we do now.
1001 usb_gadget_unmap_request(&dwc
->gadget
, &req
->request
,
1003 list_del(&req
->list
);
1007 dep
->flags
|= DWC3_EP_BUSY
;
1010 dep
->resource_index
= dwc3_gadget_ep_get_transfer_index(dep
);
1011 WARN_ON_ONCE(!dep
->resource_index
);
1017 static void __dwc3_gadget_start_isoc(struct dwc3
*dwc
,
1018 struct dwc3_ep
*dep
, u32 cur_uf
)
1022 if (list_empty(&dep
->pending_list
)) {
1023 dwc3_trace(trace_dwc3_gadget
,
1024 "ISOC ep %s run out for requests",
1026 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
1030 /* 4 micro frames in the future */
1031 uf
= cur_uf
+ dep
->interval
* 4;
1033 __dwc3_gadget_kick_transfer(dep
, uf
);
1036 static void dwc3_gadget_start_isoc(struct dwc3
*dwc
,
1037 struct dwc3_ep
*dep
, const struct dwc3_event_depevt
*event
)
1041 mask
= ~(dep
->interval
- 1);
1042 cur_uf
= event
->parameters
& mask
;
1044 __dwc3_gadget_start_isoc(dwc
, dep
, cur_uf
);
1047 static int __dwc3_gadget_ep_queue(struct dwc3_ep
*dep
, struct dwc3_request
*req
)
1049 struct dwc3
*dwc
= dep
->dwc
;
1052 if (!dep
->endpoint
.desc
) {
1053 dwc3_trace(trace_dwc3_gadget
,
1054 "trying to queue request %p to disabled %s",
1055 &req
->request
, dep
->endpoint
.name
);
1059 if (WARN(req
->dep
!= dep
, "request %p belongs to '%s'\n",
1060 &req
->request
, req
->dep
->name
)) {
1061 dwc3_trace(trace_dwc3_gadget
, "request %p belongs to '%s'",
1062 &req
->request
, req
->dep
->name
);
1066 pm_runtime_get(dwc
->dev
);
1068 req
->request
.actual
= 0;
1069 req
->request
.status
= -EINPROGRESS
;
1070 req
->direction
= dep
->direction
;
1071 req
->epnum
= dep
->number
;
1073 trace_dwc3_ep_queue(req
);
1075 ret
= usb_gadget_map_request(&dwc
->gadget
, &req
->request
,
1080 req
->sg
= req
->request
.sg
;
1081 req
->num_pending_sgs
= req
->request
.num_mapped_sgs
;
1083 list_add_tail(&req
->list
, &dep
->pending_list
);
1086 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1087 * wait for a XferNotReady event so we will know what's the current
1088 * (micro-)frame number.
1090 * Without this trick, we are very, very likely gonna get Bus Expiry
1091 * errors which will force us issue EndTransfer command.
1093 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1094 if ((dep
->flags
& DWC3_EP_PENDING_REQUEST
) &&
1095 list_empty(&dep
->started_list
)) {
1096 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
1097 dep
->flags
= DWC3_EP_ENABLED
;
1102 if (!dwc3_calc_trbs_left(dep
))
1105 ret
= __dwc3_gadget_kick_transfer(dep
, 0);
1106 if (ret
&& ret
!= -EBUSY
)
1107 dwc3_trace(trace_dwc3_gadget
,
1108 "%s: failed to kick transfers",
1116 static void __dwc3_gadget_ep_zlp_complete(struct usb_ep
*ep
,
1117 struct usb_request
*request
)
1119 dwc3_gadget_ep_free_request(ep
, request
);
1122 static int __dwc3_gadget_ep_queue_zlp(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
1124 struct dwc3_request
*req
;
1125 struct usb_request
*request
;
1126 struct usb_ep
*ep
= &dep
->endpoint
;
1128 dwc3_trace(trace_dwc3_gadget
, "queueing ZLP");
1129 request
= dwc3_gadget_ep_alloc_request(ep
, GFP_ATOMIC
);
1133 request
->length
= 0;
1134 request
->buf
= dwc
->zlp_buf
;
1135 request
->complete
= __dwc3_gadget_ep_zlp_complete
;
1137 req
= to_dwc3_request(request
);
1139 return __dwc3_gadget_ep_queue(dep
, req
);
1142 static int dwc3_gadget_ep_queue(struct usb_ep
*ep
, struct usb_request
*request
,
1145 struct dwc3_request
*req
= to_dwc3_request(request
);
1146 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1147 struct dwc3
*dwc
= dep
->dwc
;
1149 unsigned long flags
;
1153 spin_lock_irqsave(&dwc
->lock
, flags
);
1154 ret
= __dwc3_gadget_ep_queue(dep
, req
);
1157 * Okay, here's the thing, if gadget driver has requested for a ZLP by
1158 * setting request->zero, instead of doing magic, we will just queue an
1159 * extra usb_request ourselves so that it gets handled the same way as
1160 * any other request.
1162 if (ret
== 0 && request
->zero
&& request
->length
&&
1163 (request
->length
% ep
->maxpacket
== 0))
1164 ret
= __dwc3_gadget_ep_queue_zlp(dwc
, dep
);
1166 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1171 static int dwc3_gadget_ep_dequeue(struct usb_ep
*ep
,
1172 struct usb_request
*request
)
1174 struct dwc3_request
*req
= to_dwc3_request(request
);
1175 struct dwc3_request
*r
= NULL
;
1177 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1178 struct dwc3
*dwc
= dep
->dwc
;
1180 unsigned long flags
;
1183 trace_dwc3_ep_dequeue(req
);
1185 spin_lock_irqsave(&dwc
->lock
, flags
);
1187 list_for_each_entry(r
, &dep
->pending_list
, list
) {
1193 list_for_each_entry(r
, &dep
->started_list
, list
) {
1198 /* wait until it is processed */
1199 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
1202 dev_err(dwc
->dev
, "request %p was not queued to %s\n",
1209 /* giveback the request */
1210 dwc3_gadget_giveback(dep
, req
, -ECONNRESET
);
1213 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1218 int __dwc3_gadget_ep_set_halt(struct dwc3_ep
*dep
, int value
, int protocol
)
1220 struct dwc3_gadget_ep_cmd_params params
;
1221 struct dwc3
*dwc
= dep
->dwc
;
1224 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1225 dev_err(dwc
->dev
, "%s is of Isochronous type\n", dep
->name
);
1229 memset(¶ms
, 0x00, sizeof(params
));
1232 struct dwc3_trb
*trb
;
1234 unsigned transfer_in_flight
;
1237 if (dep
->number
> 1)
1238 trb
= dwc3_ep_prev_trb(dep
, dep
->trb_enqueue
);
1240 trb
= &dwc
->ep0_trb
[dep
->trb_enqueue
];
1242 transfer_in_flight
= trb
->ctrl
& DWC3_TRB_CTRL_HWO
;
1243 started
= !list_empty(&dep
->started_list
);
1245 if (!protocol
&& ((dep
->direction
&& transfer_in_flight
) ||
1246 (!dep
->direction
&& started
))) {
1247 dwc3_trace(trace_dwc3_gadget
,
1248 "%s: pending request, cannot halt",
1253 ret
= dwc3_send_gadget_ep_cmd(dep
, DWC3_DEPCMD_SETSTALL
,
1256 dev_err(dwc
->dev
, "failed to set STALL on %s\n",
1259 dep
->flags
|= DWC3_EP_STALL
;
1262 ret
= dwc3_send_clear_stall_ep_cmd(dep
);
1264 dev_err(dwc
->dev
, "failed to clear STALL on %s\n",
1267 dep
->flags
&= ~(DWC3_EP_STALL
| DWC3_EP_WEDGE
);
1273 static int dwc3_gadget_ep_set_halt(struct usb_ep
*ep
, int value
)
1275 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1276 struct dwc3
*dwc
= dep
->dwc
;
1278 unsigned long flags
;
1282 spin_lock_irqsave(&dwc
->lock
, flags
);
1283 ret
= __dwc3_gadget_ep_set_halt(dep
, value
, false);
1284 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1289 static int dwc3_gadget_ep_set_wedge(struct usb_ep
*ep
)
1291 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1292 struct dwc3
*dwc
= dep
->dwc
;
1293 unsigned long flags
;
1296 spin_lock_irqsave(&dwc
->lock
, flags
);
1297 dep
->flags
|= DWC3_EP_WEDGE
;
1299 if (dep
->number
== 0 || dep
->number
== 1)
1300 ret
= __dwc3_gadget_ep0_set_halt(ep
, 1);
1302 ret
= __dwc3_gadget_ep_set_halt(dep
, 1, false);
1303 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1308 /* -------------------------------------------------------------------------- */
1310 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc
= {
1311 .bLength
= USB_DT_ENDPOINT_SIZE
,
1312 .bDescriptorType
= USB_DT_ENDPOINT
,
1313 .bmAttributes
= USB_ENDPOINT_XFER_CONTROL
,
1316 static const struct usb_ep_ops dwc3_gadget_ep0_ops
= {
1317 .enable
= dwc3_gadget_ep0_enable
,
1318 .disable
= dwc3_gadget_ep0_disable
,
1319 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1320 .free_request
= dwc3_gadget_ep_free_request
,
1321 .queue
= dwc3_gadget_ep0_queue
,
1322 .dequeue
= dwc3_gadget_ep_dequeue
,
1323 .set_halt
= dwc3_gadget_ep0_set_halt
,
1324 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1327 static const struct usb_ep_ops dwc3_gadget_ep_ops
= {
1328 .enable
= dwc3_gadget_ep_enable
,
1329 .disable
= dwc3_gadget_ep_disable
,
1330 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1331 .free_request
= dwc3_gadget_ep_free_request
,
1332 .queue
= dwc3_gadget_ep_queue
,
1333 .dequeue
= dwc3_gadget_ep_dequeue
,
1334 .set_halt
= dwc3_gadget_ep_set_halt
,
1335 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1338 /* -------------------------------------------------------------------------- */
1340 static int dwc3_gadget_get_frame(struct usb_gadget
*g
)
1342 struct dwc3
*dwc
= gadget_to_dwc(g
);
1345 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1346 return DWC3_DSTS_SOFFN(reg
);
1349 static int __dwc3_gadget_wakeup(struct dwc3
*dwc
)
1360 * According to the Databook Remote wakeup request should
1361 * be issued only when the device is in early suspend state.
1363 * We can check that via USB Link State bits in DSTS register.
1365 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1367 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
1368 if ((speed
== DWC3_DSTS_SUPERSPEED
) ||
1369 (speed
== DWC3_DSTS_SUPERSPEED_PLUS
)) {
1370 dwc3_trace(trace_dwc3_gadget
, "no wakeup on SuperSpeed");
1374 link_state
= DWC3_DSTS_USBLNKST(reg
);
1376 switch (link_state
) {
1377 case DWC3_LINK_STATE_RX_DET
: /* in HS, means Early Suspend */
1378 case DWC3_LINK_STATE_U3
: /* in HS, means SUSPEND */
1381 dwc3_trace(trace_dwc3_gadget
,
1382 "can't wakeup from '%s'",
1383 dwc3_gadget_link_string(link_state
));
1387 ret
= dwc3_gadget_set_link_state(dwc
, DWC3_LINK_STATE_RECOV
);
1389 dev_err(dwc
->dev
, "failed to put link in Recovery\n");
1393 /* Recent versions do this automatically */
1394 if (dwc
->revision
< DWC3_REVISION_194A
) {
1395 /* write zeroes to Link Change Request */
1396 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1397 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
1398 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1401 /* poll until Link State changes to ON */
1405 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1407 /* in HS, means ON */
1408 if (DWC3_DSTS_USBLNKST(reg
) == DWC3_LINK_STATE_U0
)
1412 if (DWC3_DSTS_USBLNKST(reg
) != DWC3_LINK_STATE_U0
) {
1413 dev_err(dwc
->dev
, "failed to send remote wakeup\n");
1420 static int dwc3_gadget_wakeup(struct usb_gadget
*g
)
1422 struct dwc3
*dwc
= gadget_to_dwc(g
);
1423 unsigned long flags
;
1426 spin_lock_irqsave(&dwc
->lock
, flags
);
1427 ret
= __dwc3_gadget_wakeup(dwc
);
1428 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1433 static int dwc3_gadget_set_selfpowered(struct usb_gadget
*g
,
1436 struct dwc3
*dwc
= gadget_to_dwc(g
);
1437 unsigned long flags
;
1439 spin_lock_irqsave(&dwc
->lock
, flags
);
1440 g
->is_selfpowered
= !!is_selfpowered
;
1441 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1446 static int dwc3_gadget_run_stop(struct dwc3
*dwc
, int is_on
, int suspend
)
1451 if (pm_runtime_suspended(dwc
->dev
))
1454 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1456 if (dwc
->revision
<= DWC3_REVISION_187A
) {
1457 reg
&= ~DWC3_DCTL_TRGTULST_MASK
;
1458 reg
|= DWC3_DCTL_TRGTULST_RX_DET
;
1461 if (dwc
->revision
>= DWC3_REVISION_194A
)
1462 reg
&= ~DWC3_DCTL_KEEP_CONNECT
;
1463 reg
|= DWC3_DCTL_RUN_STOP
;
1465 if (dwc
->has_hibernation
)
1466 reg
|= DWC3_DCTL_KEEP_CONNECT
;
1468 dwc
->pullups_connected
= true;
1470 reg
&= ~DWC3_DCTL_RUN_STOP
;
1472 if (dwc
->has_hibernation
&& !suspend
)
1473 reg
&= ~DWC3_DCTL_KEEP_CONNECT
;
1475 dwc
->pullups_connected
= false;
1478 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1481 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1482 reg
&= DWC3_DSTS_DEVCTRLHLT
;
1483 } while (--timeout
&& !(!is_on
^ !reg
));
1488 dwc3_trace(trace_dwc3_gadget
, "gadget %s data soft-%s",
1490 ? dwc
->gadget_driver
->function
: "no-function",
1491 is_on
? "connect" : "disconnect");
1496 static int dwc3_gadget_pullup(struct usb_gadget
*g
, int is_on
)
1498 struct dwc3
*dwc
= gadget_to_dwc(g
);
1499 unsigned long flags
;
1504 spin_lock_irqsave(&dwc
->lock
, flags
);
1505 ret
= dwc3_gadget_run_stop(dwc
, is_on
, false);
1506 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1511 static void dwc3_gadget_enable_irq(struct dwc3
*dwc
)
1515 /* Enable all but Start and End of Frame IRQs */
1516 reg
= (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN
|
1517 DWC3_DEVTEN_EVNTOVERFLOWEN
|
1518 DWC3_DEVTEN_CMDCMPLTEN
|
1519 DWC3_DEVTEN_ERRTICERREN
|
1520 DWC3_DEVTEN_WKUPEVTEN
|
1521 DWC3_DEVTEN_ULSTCNGEN
|
1522 DWC3_DEVTEN_CONNECTDONEEN
|
1523 DWC3_DEVTEN_USBRSTEN
|
1524 DWC3_DEVTEN_DISCONNEVTEN
);
1526 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, reg
);
1529 static void dwc3_gadget_disable_irq(struct dwc3
*dwc
)
1531 /* mask all interrupts */
1532 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, 0x00);
1535 static irqreturn_t
dwc3_interrupt(int irq
, void *_dwc
);
1536 static irqreturn_t
dwc3_thread_interrupt(int irq
, void *_dwc
);
1539 * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG
1540 * dwc: pointer to our context structure
1542 * The following looks like complex but it's actually very simple. In order to
1543 * calculate the number of packets we can burst at once on OUT transfers, we're
1544 * gonna use RxFIFO size.
1546 * To calculate RxFIFO size we need two numbers:
1547 * MDWIDTH = size, in bits, of the internal memory bus
1548 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1550 * Given these two numbers, the formula is simple:
1552 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1554 * 24 bytes is for 3x SETUP packets
1555 * 16 bytes is a clock domain crossing tolerance
1557 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1559 static void dwc3_gadget_setup_nump(struct dwc3
*dwc
)
1566 ram2_depth
= DWC3_GHWPARAMS7_RAM2_DEPTH(dwc
->hwparams
.hwparams7
);
1567 mdwidth
= DWC3_GHWPARAMS0_MDWIDTH(dwc
->hwparams
.hwparams0
);
1569 nump
= ((ram2_depth
* mdwidth
/ 8) - 24 - 16) / 1024;
1570 nump
= min_t(u32
, nump
, 16);
1573 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
1574 reg
&= ~DWC3_DCFG_NUMP_MASK
;
1575 reg
|= nump
<< DWC3_DCFG_NUMP_SHIFT
;
1576 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
1579 static int __dwc3_gadget_start(struct dwc3
*dwc
)
1581 struct dwc3_ep
*dep
;
1585 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
1586 reg
&= ~(DWC3_DCFG_SPEED_MASK
);
1589 * WORKAROUND: DWC3 revision < 2.20a have an issue
1590 * which would cause metastability state on Run/Stop
1591 * bit if we try to force the IP to USB2-only mode.
1593 * Because of that, we cannot configure the IP to any
1594 * speed other than the SuperSpeed
1598 * STAR#9000525659: Clock Domain Crossing on DCTL in
1601 if (dwc
->revision
< DWC3_REVISION_220A
) {
1602 reg
|= DWC3_DCFG_SUPERSPEED
;
1604 switch (dwc
->maximum_speed
) {
1606 reg
|= DWC3_DCFG_LOWSPEED
;
1608 case USB_SPEED_FULL
:
1609 reg
|= DWC3_DCFG_FULLSPEED1
;
1611 case USB_SPEED_HIGH
:
1612 reg
|= DWC3_DCFG_HIGHSPEED
;
1614 case USB_SPEED_SUPER_PLUS
:
1615 reg
|= DWC3_DCFG_SUPERSPEED_PLUS
;
1618 dev_err(dwc
->dev
, "invalid dwc->maximum_speed (%d)\n",
1619 dwc
->maximum_speed
);
1621 case USB_SPEED_SUPER
:
1622 reg
|= DWC3_DCFG_SUPERSPEED
;
1626 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
1629 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1630 * field instead of letting dwc3 itself calculate that automatically.
1632 * This way, we maximize the chances that we'll be able to get several
1633 * bursts of data without going through any sort of endpoint throttling.
1635 reg
= dwc3_readl(dwc
->regs
, DWC3_GRXTHRCFG
);
1636 reg
&= ~DWC3_GRXTHRCFG_PKTCNTSEL
;
1637 dwc3_writel(dwc
->regs
, DWC3_GRXTHRCFG
, reg
);
1639 dwc3_gadget_setup_nump(dwc
);
1641 /* Start with SuperSpeed Default */
1642 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
1645 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, false,
1648 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1653 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, false,
1656 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1660 /* begin to receive SETUP packets */
1661 dwc
->ep0state
= EP0_SETUP_PHASE
;
1662 dwc3_ep0_out_start(dwc
);
1664 dwc3_gadget_enable_irq(dwc
);
1669 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
1675 static int dwc3_gadget_start(struct usb_gadget
*g
,
1676 struct usb_gadget_driver
*driver
)
1678 struct dwc3
*dwc
= gadget_to_dwc(g
);
1679 unsigned long flags
;
1683 irq
= dwc
->irq_gadget
;
1684 ret
= request_threaded_irq(irq
, dwc3_interrupt
, dwc3_thread_interrupt
,
1685 IRQF_SHARED
, "dwc3", dwc
->ev_buf
);
1687 dev_err(dwc
->dev
, "failed to request irq #%d --> %d\n",
1692 spin_lock_irqsave(&dwc
->lock
, flags
);
1693 if (dwc
->gadget_driver
) {
1694 dev_err(dwc
->dev
, "%s is already bound to %s\n",
1696 dwc
->gadget_driver
->driver
.name
);
1701 dwc
->gadget_driver
= driver
;
1703 if (pm_runtime_active(dwc
->dev
))
1704 __dwc3_gadget_start(dwc
);
1706 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1711 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1718 static void __dwc3_gadget_stop(struct dwc3
*dwc
)
1720 if (pm_runtime_suspended(dwc
->dev
))
1723 dwc3_gadget_disable_irq(dwc
);
1724 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
1725 __dwc3_gadget_ep_disable(dwc
->eps
[1]);
1728 static int dwc3_gadget_stop(struct usb_gadget
*g
)
1730 struct dwc3
*dwc
= gadget_to_dwc(g
);
1731 unsigned long flags
;
1733 spin_lock_irqsave(&dwc
->lock
, flags
);
1734 __dwc3_gadget_stop(dwc
);
1735 dwc
->gadget_driver
= NULL
;
1736 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1738 free_irq(dwc
->irq_gadget
, dwc
->ev_buf
);
1743 static const struct usb_gadget_ops dwc3_gadget_ops
= {
1744 .get_frame
= dwc3_gadget_get_frame
,
1745 .wakeup
= dwc3_gadget_wakeup
,
1746 .set_selfpowered
= dwc3_gadget_set_selfpowered
,
1747 .pullup
= dwc3_gadget_pullup
,
1748 .udc_start
= dwc3_gadget_start
,
1749 .udc_stop
= dwc3_gadget_stop
,
1752 /* -------------------------------------------------------------------------- */
1754 static int dwc3_gadget_init_hw_endpoints(struct dwc3
*dwc
,
1755 u8 num
, u32 direction
)
1757 struct dwc3_ep
*dep
;
1760 for (i
= 0; i
< num
; i
++) {
1761 u8 epnum
= (i
<< 1) | (direction
? 1 : 0);
1763 dep
= kzalloc(sizeof(*dep
), GFP_KERNEL
);
1768 dep
->number
= epnum
;
1769 dep
->direction
= !!direction
;
1770 dep
->regs
= dwc
->regs
+ DWC3_DEP_BASE(epnum
);
1771 dwc
->eps
[epnum
] = dep
;
1773 snprintf(dep
->name
, sizeof(dep
->name
), "ep%d%s", epnum
>> 1,
1774 (epnum
& 1) ? "in" : "out");
1776 dep
->endpoint
.name
= dep
->name
;
1777 spin_lock_init(&dep
->lock
);
1779 dwc3_trace(trace_dwc3_gadget
, "initializing %s", dep
->name
);
1781 if (epnum
== 0 || epnum
== 1) {
1782 usb_ep_set_maxpacket_limit(&dep
->endpoint
, 512);
1783 dep
->endpoint
.maxburst
= 1;
1784 dep
->endpoint
.ops
= &dwc3_gadget_ep0_ops
;
1786 dwc
->gadget
.ep0
= &dep
->endpoint
;
1790 usb_ep_set_maxpacket_limit(&dep
->endpoint
, 1024);
1791 dep
->endpoint
.max_streams
= 15;
1792 dep
->endpoint
.ops
= &dwc3_gadget_ep_ops
;
1793 list_add_tail(&dep
->endpoint
.ep_list
,
1794 &dwc
->gadget
.ep_list
);
1796 ret
= dwc3_alloc_trb_pool(dep
);
1801 if (epnum
== 0 || epnum
== 1) {
1802 dep
->endpoint
.caps
.type_control
= true;
1804 dep
->endpoint
.caps
.type_iso
= true;
1805 dep
->endpoint
.caps
.type_bulk
= true;
1806 dep
->endpoint
.caps
.type_int
= true;
1809 dep
->endpoint
.caps
.dir_in
= !!direction
;
1810 dep
->endpoint
.caps
.dir_out
= !direction
;
1812 INIT_LIST_HEAD(&dep
->pending_list
);
1813 INIT_LIST_HEAD(&dep
->started_list
);
1819 static int dwc3_gadget_init_endpoints(struct dwc3
*dwc
)
1823 INIT_LIST_HEAD(&dwc
->gadget
.ep_list
);
1825 ret
= dwc3_gadget_init_hw_endpoints(dwc
, dwc
->num_out_eps
, 0);
1827 dwc3_trace(trace_dwc3_gadget
,
1828 "failed to allocate OUT endpoints");
1832 ret
= dwc3_gadget_init_hw_endpoints(dwc
, dwc
->num_in_eps
, 1);
1834 dwc3_trace(trace_dwc3_gadget
,
1835 "failed to allocate IN endpoints");
1842 static void dwc3_gadget_free_endpoints(struct dwc3
*dwc
)
1844 struct dwc3_ep
*dep
;
1847 for (epnum
= 0; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
1848 dep
= dwc
->eps
[epnum
];
1852 * Physical endpoints 0 and 1 are special; they form the
1853 * bi-directional USB endpoint 0.
1855 * For those two physical endpoints, we don't allocate a TRB
1856 * pool nor do we add them the endpoints list. Due to that, we
1857 * shouldn't do these two operations otherwise we would end up
1858 * with all sorts of bugs when removing dwc3.ko.
1860 if (epnum
!= 0 && epnum
!= 1) {
1861 dwc3_free_trb_pool(dep
);
1862 list_del(&dep
->endpoint
.ep_list
);
1869 /* -------------------------------------------------------------------------- */
1871 static int __dwc3_cleanup_done_trbs(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
1872 struct dwc3_request
*req
, struct dwc3_trb
*trb
,
1873 const struct dwc3_event_depevt
*event
, int status
,
1877 unsigned int s_pkt
= 0;
1878 unsigned int trb_status
;
1880 dwc3_ep_inc_deq(dep
);
1882 if (req
->trb
== trb
)
1883 dep
->queued_requests
--;
1885 trace_dwc3_complete_trb(dep
, trb
);
1888 * If we're in the middle of series of chained TRBs and we
1889 * receive a short transfer along the way, DWC3 will skip
1890 * through all TRBs including the last TRB in the chain (the
1891 * where CHN bit is zero. DWC3 will also avoid clearing HWO
1892 * bit and SW has to do it manually.
1894 * We're going to do that here to avoid problems of HW trying
1895 * to use bogus TRBs for transfers.
1897 if (chain
&& (trb
->ctrl
& DWC3_TRB_CTRL_HWO
))
1898 trb
->ctrl
&= ~DWC3_TRB_CTRL_HWO
;
1900 if ((trb
->ctrl
& DWC3_TRB_CTRL_HWO
) && status
!= -ESHUTDOWN
)
1903 count
= trb
->size
& DWC3_TRB_SIZE_MASK
;
1904 req
->request
.actual
+= count
;
1906 if (dep
->direction
) {
1908 trb_status
= DWC3_TRB_SIZE_TRBSTS(trb
->size
);
1909 if (trb_status
== DWC3_TRBSTS_MISSED_ISOC
) {
1910 dwc3_trace(trace_dwc3_gadget
,
1911 "%s: incomplete IN transfer",
1914 * If missed isoc occurred and there is
1915 * no request queued then issue END
1916 * TRANSFER, so that core generates
1917 * next xfernotready and we will issue
1918 * a fresh START TRANSFER.
1919 * If there are still queued request
1920 * then wait, do not issue either END
1921 * or UPDATE TRANSFER, just attach next
1922 * request in pending_list during
1923 * giveback.If any future queued request
1924 * is successfully transferred then we
1925 * will issue UPDATE TRANSFER for all
1926 * request in the pending_list.
1928 dep
->flags
|= DWC3_EP_MISSED_ISOC
;
1930 dev_err(dwc
->dev
, "incomplete IN transfer %s\n",
1932 status
= -ECONNRESET
;
1935 dep
->flags
&= ~DWC3_EP_MISSED_ISOC
;
1938 if (count
&& (event
->status
& DEPEVT_STATUS_SHORT
))
1942 if (s_pkt
&& !chain
)
1945 if ((event
->status
& DEPEVT_STATUS_IOC
) &&
1946 (trb
->ctrl
& DWC3_TRB_CTRL_IOC
))
1952 static int dwc3_cleanup_done_reqs(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
1953 const struct dwc3_event_depevt
*event
, int status
)
1955 struct dwc3_request
*req
, *n
;
1956 struct dwc3_trb
*trb
;
1960 list_for_each_entry_safe(req
, n
, &dep
->started_list
, list
) {
1965 length
= req
->request
.length
;
1966 chain
= req
->num_pending_sgs
> 0;
1968 struct scatterlist
*sg
= req
->sg
;
1969 struct scatterlist
*s
;
1970 unsigned int pending
= req
->num_pending_sgs
;
1973 for_each_sg(sg
, s
, pending
, i
) {
1974 trb
= &dep
->trb_pool
[dep
->trb_dequeue
];
1976 req
->sg
= sg_next(s
);
1977 req
->num_pending_sgs
--;
1979 ret
= __dwc3_cleanup_done_trbs(dwc
, dep
, req
, trb
,
1980 event
, status
, chain
);
1985 trb
= &dep
->trb_pool
[dep
->trb_dequeue
];
1986 ret
= __dwc3_cleanup_done_trbs(dwc
, dep
, req
, trb
,
1987 event
, status
, chain
);
1991 * We assume here we will always receive the entire data block
1992 * which we should receive. Meaning, if we program RX to
1993 * receive 4K but we receive only 2K, we assume that's all we
1994 * should receive and we simply bounce the request back to the
1995 * gadget driver for further processing.
1997 actual
= length
- req
->request
.actual
;
1998 req
->request
.actual
= actual
;
2000 if (ret
&& chain
&& (actual
< length
) && req
->num_pending_sgs
)
2001 return __dwc3_gadget_kick_transfer(dep
, 0);
2003 dwc3_gadget_giveback(dep
, req
, status
);
2006 if ((event
->status
& DEPEVT_STATUS_IOC
) &&
2007 (trb
->ctrl
& DWC3_TRB_CTRL_IOC
))
2014 * Our endpoint might get disabled by another thread during
2015 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2016 * early on so DWC3_EP_BUSY flag gets cleared
2018 if (!dep
->endpoint
.desc
)
2021 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) &&
2022 list_empty(&dep
->started_list
)) {
2023 if (list_empty(&dep
->pending_list
)) {
2025 * If there is no entry in request list then do
2026 * not issue END TRANSFER now. Just set PENDING
2027 * flag, so that END TRANSFER is issued when an
2028 * entry is added into request list.
2030 dep
->flags
= DWC3_EP_PENDING_REQUEST
;
2032 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
2033 dep
->flags
= DWC3_EP_ENABLED
;
2038 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) && ioc
)
2044 static void dwc3_endpoint_transfer_complete(struct dwc3
*dwc
,
2045 struct dwc3_ep
*dep
, const struct dwc3_event_depevt
*event
)
2047 unsigned status
= 0;
2049 u32 is_xfer_complete
;
2051 is_xfer_complete
= (event
->endpoint_event
== DWC3_DEPEVT_XFERCOMPLETE
);
2053 if (event
->status
& DEPEVT_STATUS_BUSERR
)
2054 status
= -ECONNRESET
;
2056 clean_busy
= dwc3_cleanup_done_reqs(dwc
, dep
, event
, status
);
2057 if (clean_busy
&& (!dep
->endpoint
.desc
|| is_xfer_complete
||
2058 usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)))
2059 dep
->flags
&= ~DWC3_EP_BUSY
;
2062 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2063 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2065 if (dwc
->revision
< DWC3_REVISION_183A
) {
2069 for (i
= 0; i
< DWC3_ENDPOINTS_NUM
; i
++) {
2072 if (!(dep
->flags
& DWC3_EP_ENABLED
))
2075 if (!list_empty(&dep
->started_list
))
2079 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2081 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2087 * Our endpoint might get disabled by another thread during
2088 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2089 * early on so DWC3_EP_BUSY flag gets cleared
2091 if (!dep
->endpoint
.desc
)
2094 if (!usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
2097 ret
= __dwc3_gadget_kick_transfer(dep
, 0);
2098 if (!ret
|| ret
== -EBUSY
)
2103 static void dwc3_endpoint_interrupt(struct dwc3
*dwc
,
2104 const struct dwc3_event_depevt
*event
)
2106 struct dwc3_ep
*dep
;
2107 u8 epnum
= event
->endpoint_number
;
2109 dep
= dwc
->eps
[epnum
];
2111 if (!(dep
->flags
& DWC3_EP_ENABLED
))
2114 if (epnum
== 0 || epnum
== 1) {
2115 dwc3_ep0_interrupt(dwc
, event
);
2119 switch (event
->endpoint_event
) {
2120 case DWC3_DEPEVT_XFERCOMPLETE
:
2121 dep
->resource_index
= 0;
2123 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
2124 dwc3_trace(trace_dwc3_gadget
,
2125 "%s is an Isochronous endpoint",
2130 dwc3_endpoint_transfer_complete(dwc
, dep
, event
);
2132 case DWC3_DEPEVT_XFERINPROGRESS
:
2133 dwc3_endpoint_transfer_complete(dwc
, dep
, event
);
2135 case DWC3_DEPEVT_XFERNOTREADY
:
2136 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
2137 dwc3_gadget_start_isoc(dwc
, dep
, event
);
2142 active
= event
->status
& DEPEVT_STATUS_TRANSFER_ACTIVE
;
2144 dwc3_trace(trace_dwc3_gadget
, "%s: reason %s",
2145 dep
->name
, active
? "Transfer Active"
2146 : "Transfer Not Active");
2148 ret
= __dwc3_gadget_kick_transfer(dep
, 0);
2149 if (!ret
|| ret
== -EBUSY
)
2152 dwc3_trace(trace_dwc3_gadget
,
2153 "%s: failed to kick transfers",
2158 case DWC3_DEPEVT_STREAMEVT
:
2159 if (!usb_endpoint_xfer_bulk(dep
->endpoint
.desc
)) {
2160 dev_err(dwc
->dev
, "Stream event for non-Bulk %s\n",
2165 switch (event
->status
) {
2166 case DEPEVT_STREAMEVT_FOUND
:
2167 dwc3_trace(trace_dwc3_gadget
,
2168 "Stream %d found and started",
2172 case DEPEVT_STREAMEVT_NOTFOUND
:
2175 dwc3_trace(trace_dwc3_gadget
,
2176 "unable to find suitable stream");
2179 case DWC3_DEPEVT_RXTXFIFOEVT
:
2180 dwc3_trace(trace_dwc3_gadget
, "%s FIFO Overrun", dep
->name
);
2182 case DWC3_DEPEVT_EPCMDCMPLT
:
2183 dwc3_trace(trace_dwc3_gadget
, "Endpoint Command Complete");
2188 static void dwc3_disconnect_gadget(struct dwc3
*dwc
)
2190 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->disconnect
) {
2191 spin_unlock(&dwc
->lock
);
2192 dwc
->gadget_driver
->disconnect(&dwc
->gadget
);
2193 spin_lock(&dwc
->lock
);
2197 static void dwc3_suspend_gadget(struct dwc3
*dwc
)
2199 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->suspend
) {
2200 spin_unlock(&dwc
->lock
);
2201 dwc
->gadget_driver
->suspend(&dwc
->gadget
);
2202 spin_lock(&dwc
->lock
);
2206 static void dwc3_resume_gadget(struct dwc3
*dwc
)
2208 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->resume
) {
2209 spin_unlock(&dwc
->lock
);
2210 dwc
->gadget_driver
->resume(&dwc
->gadget
);
2211 spin_lock(&dwc
->lock
);
2215 static void dwc3_reset_gadget(struct dwc3
*dwc
)
2217 if (!dwc
->gadget_driver
)
2220 if (dwc
->gadget
.speed
!= USB_SPEED_UNKNOWN
) {
2221 spin_unlock(&dwc
->lock
);
2222 usb_gadget_udc_reset(&dwc
->gadget
, dwc
->gadget_driver
);
2223 spin_lock(&dwc
->lock
);
2227 static void dwc3_stop_active_transfer(struct dwc3
*dwc
, u32 epnum
, bool force
)
2229 struct dwc3_ep
*dep
;
2230 struct dwc3_gadget_ep_cmd_params params
;
2234 dep
= dwc
->eps
[epnum
];
2236 if (!dep
->resource_index
)
2240 * NOTICE: We are violating what the Databook says about the
2241 * EndTransfer command. Ideally we would _always_ wait for the
2242 * EndTransfer Command Completion IRQ, but that's causing too
2243 * much trouble synchronizing between us and gadget driver.
2245 * We have discussed this with the IP Provider and it was
2246 * suggested to giveback all requests here, but give HW some
2247 * extra time to synchronize with the interconnect. We're using
2248 * an arbitrary 100us delay for that.
2250 * Note also that a similar handling was tested by Synopsys
2251 * (thanks a lot Paul) and nothing bad has come out of it.
2252 * In short, what we're doing is:
2254 * - Issue EndTransfer WITH CMDIOC bit set
2257 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2258 * supports a mode to work around the above limitation. The
2259 * software can poll the CMDACT bit in the DEPCMD register
2260 * after issuing a EndTransfer command. This mode is enabled
2261 * by writing GUCTL2[14]. This polling is already done in the
2262 * dwc3_send_gadget_ep_cmd() function so if the mode is
2263 * enabled, the EndTransfer command will have completed upon
2264 * returning from this function and we don't need to delay for
2267 * This mode is NOT available on the DWC_usb31 IP.
2270 cmd
= DWC3_DEPCMD_ENDTRANSFER
;
2271 cmd
|= force
? DWC3_DEPCMD_HIPRI_FORCERM
: 0;
2272 cmd
|= DWC3_DEPCMD_CMDIOC
;
2273 cmd
|= DWC3_DEPCMD_PARAM(dep
->resource_index
);
2274 memset(¶ms
, 0, sizeof(params
));
2275 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
2277 dep
->resource_index
= 0;
2278 dep
->flags
&= ~DWC3_EP_BUSY
;
2280 if (dwc3_is_usb31(dwc
) || dwc
->revision
< DWC3_REVISION_310A
)
2284 static void dwc3_stop_active_transfers(struct dwc3
*dwc
)
2288 for (epnum
= 2; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
2289 struct dwc3_ep
*dep
;
2291 dep
= dwc
->eps
[epnum
];
2295 if (!(dep
->flags
& DWC3_EP_ENABLED
))
2298 dwc3_remove_requests(dwc
, dep
);
2302 static void dwc3_clear_stall_all_ep(struct dwc3
*dwc
)
2306 for (epnum
= 1; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
2307 struct dwc3_ep
*dep
;
2310 dep
= dwc
->eps
[epnum
];
2314 if (!(dep
->flags
& DWC3_EP_STALL
))
2317 dep
->flags
&= ~DWC3_EP_STALL
;
2319 ret
= dwc3_send_clear_stall_ep_cmd(dep
);
2324 static void dwc3_gadget_disconnect_interrupt(struct dwc3
*dwc
)
2328 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2329 reg
&= ~DWC3_DCTL_INITU1ENA
;
2330 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2332 reg
&= ~DWC3_DCTL_INITU2ENA
;
2333 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2335 dwc3_disconnect_gadget(dwc
);
2337 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2338 dwc
->setup_packet_pending
= false;
2339 usb_gadget_set_state(&dwc
->gadget
, USB_STATE_NOTATTACHED
);
2341 dwc
->connected
= false;
2344 static void dwc3_gadget_reset_interrupt(struct dwc3
*dwc
)
2348 dwc
->connected
= true;
2351 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2352 * would cause a missing Disconnect Event if there's a
2353 * pending Setup Packet in the FIFO.
2355 * There's no suggested workaround on the official Bug
2356 * report, which states that "unless the driver/application
2357 * is doing any special handling of a disconnect event,
2358 * there is no functional issue".
2360 * Unfortunately, it turns out that we _do_ some special
2361 * handling of a disconnect event, namely complete all
2362 * pending transfers, notify gadget driver of the
2363 * disconnection, and so on.
2365 * Our suggested workaround is to follow the Disconnect
2366 * Event steps here, instead, based on a setup_packet_pending
2367 * flag. Such flag gets set whenever we have a SETUP_PENDING
2368 * status for EP0 TRBs and gets cleared on XferComplete for the
2373 * STAR#9000466709: RTL: Device : Disconnect event not
2374 * generated if setup packet pending in FIFO
2376 if (dwc
->revision
< DWC3_REVISION_188A
) {
2377 if (dwc
->setup_packet_pending
)
2378 dwc3_gadget_disconnect_interrupt(dwc
);
2381 dwc3_reset_gadget(dwc
);
2383 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2384 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
2385 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2386 dwc
->test_mode
= false;
2388 dwc3_stop_active_transfers(dwc
);
2389 dwc3_clear_stall_all_ep(dwc
);
2391 /* Reset device address to zero */
2392 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2393 reg
&= ~(DWC3_DCFG_DEVADDR_MASK
);
2394 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2397 static void dwc3_update_ram_clk_sel(struct dwc3
*dwc
, u32 speed
)
2400 u32 usb30_clock
= DWC3_GCTL_CLK_BUS
;
2403 * We change the clock only at SS but I dunno why I would want to do
2404 * this. Maybe it becomes part of the power saving plan.
2407 if ((speed
!= DWC3_DSTS_SUPERSPEED
) &&
2408 (speed
!= DWC3_DSTS_SUPERSPEED_PLUS
))
2412 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2413 * each time on Connect Done.
2418 reg
= dwc3_readl(dwc
->regs
, DWC3_GCTL
);
2419 reg
|= DWC3_GCTL_RAMCLKSEL(usb30_clock
);
2420 dwc3_writel(dwc
->regs
, DWC3_GCTL
, reg
);
2423 static void dwc3_gadget_conndone_interrupt(struct dwc3
*dwc
)
2425 struct dwc3_ep
*dep
;
2430 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
2431 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
2434 dwc3_update_ram_clk_sel(dwc
, speed
);
2437 case DWC3_DSTS_SUPERSPEED_PLUS
:
2438 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
2439 dwc
->gadget
.ep0
->maxpacket
= 512;
2440 dwc
->gadget
.speed
= USB_SPEED_SUPER_PLUS
;
2442 case DWC3_DSTS_SUPERSPEED
:
2444 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2445 * would cause a missing USB3 Reset event.
2447 * In such situations, we should force a USB3 Reset
2448 * event by calling our dwc3_gadget_reset_interrupt()
2453 * STAR#9000483510: RTL: SS : USB3 reset event may
2454 * not be generated always when the link enters poll
2456 if (dwc
->revision
< DWC3_REVISION_190A
)
2457 dwc3_gadget_reset_interrupt(dwc
);
2459 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
2460 dwc
->gadget
.ep0
->maxpacket
= 512;
2461 dwc
->gadget
.speed
= USB_SPEED_SUPER
;
2463 case DWC3_DSTS_HIGHSPEED
:
2464 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2465 dwc
->gadget
.ep0
->maxpacket
= 64;
2466 dwc
->gadget
.speed
= USB_SPEED_HIGH
;
2468 case DWC3_DSTS_FULLSPEED2
:
2469 case DWC3_DSTS_FULLSPEED1
:
2470 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2471 dwc
->gadget
.ep0
->maxpacket
= 64;
2472 dwc
->gadget
.speed
= USB_SPEED_FULL
;
2474 case DWC3_DSTS_LOWSPEED
:
2475 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(8);
2476 dwc
->gadget
.ep0
->maxpacket
= 8;
2477 dwc
->gadget
.speed
= USB_SPEED_LOW
;
2481 /* Enable USB2 LPM Capability */
2483 if ((dwc
->revision
> DWC3_REVISION_194A
) &&
2484 (speed
!= DWC3_DSTS_SUPERSPEED
) &&
2485 (speed
!= DWC3_DSTS_SUPERSPEED_PLUS
)) {
2486 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2487 reg
|= DWC3_DCFG_LPM_CAP
;
2488 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2490 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2491 reg
&= ~(DWC3_DCTL_HIRD_THRES_MASK
| DWC3_DCTL_L1_HIBER_EN
);
2493 reg
|= DWC3_DCTL_HIRD_THRES(dwc
->hird_threshold
);
2496 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2497 * DCFG.LPMCap is set, core responses with an ACK and the
2498 * BESL value in the LPM token is less than or equal to LPM
2501 WARN_ONCE(dwc
->revision
< DWC3_REVISION_240A
2502 && dwc
->has_lpm_erratum
,
2503 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2505 if (dwc
->has_lpm_erratum
&& dwc
->revision
>= DWC3_REVISION_240A
)
2506 reg
|= DWC3_DCTL_LPM_ERRATA(dwc
->lpm_nyet_threshold
);
2508 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2510 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2511 reg
&= ~DWC3_DCTL_HIRD_THRES_MASK
;
2512 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2516 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, true,
2519 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2524 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, true,
2527 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2532 * Configure PHY via GUSB3PIPECTLn if required.
2534 * Update GTXFIFOSIZn
2536 * In both cases reset values should be sufficient.
2540 static void dwc3_gadget_wakeup_interrupt(struct dwc3
*dwc
)
2543 * TODO take core out of low power mode when that's
2547 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->resume
) {
2548 spin_unlock(&dwc
->lock
);
2549 dwc
->gadget_driver
->resume(&dwc
->gadget
);
2550 spin_lock(&dwc
->lock
);
2554 static void dwc3_gadget_linksts_change_interrupt(struct dwc3
*dwc
,
2555 unsigned int evtinfo
)
2557 enum dwc3_link_state next
= evtinfo
& DWC3_LINK_STATE_MASK
;
2558 unsigned int pwropt
;
2561 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2562 * Hibernation mode enabled which would show up when device detects
2563 * host-initiated U3 exit.
2565 * In that case, device will generate a Link State Change Interrupt
2566 * from U3 to RESUME which is only necessary if Hibernation is
2569 * There are no functional changes due to such spurious event and we
2570 * just need to ignore it.
2574 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2577 pwropt
= DWC3_GHWPARAMS1_EN_PWROPT(dwc
->hwparams
.hwparams1
);
2578 if ((dwc
->revision
< DWC3_REVISION_250A
) &&
2579 (pwropt
!= DWC3_GHWPARAMS1_EN_PWROPT_HIB
)) {
2580 if ((dwc
->link_state
== DWC3_LINK_STATE_U3
) &&
2581 (next
== DWC3_LINK_STATE_RESUME
)) {
2582 dwc3_trace(trace_dwc3_gadget
,
2583 "ignoring transition U3 -> Resume");
2589 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2590 * on the link partner, the USB session might do multiple entry/exit
2591 * of low power states before a transfer takes place.
2593 * Due to this problem, we might experience lower throughput. The
2594 * suggested workaround is to disable DCTL[12:9] bits if we're
2595 * transitioning from U1/U2 to U0 and enable those bits again
2596 * after a transfer completes and there are no pending transfers
2597 * on any of the enabled endpoints.
2599 * This is the first half of that workaround.
2603 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2604 * core send LGO_Ux entering U0
2606 if (dwc
->revision
< DWC3_REVISION_183A
) {
2607 if (next
== DWC3_LINK_STATE_U0
) {
2611 switch (dwc
->link_state
) {
2612 case DWC3_LINK_STATE_U1
:
2613 case DWC3_LINK_STATE_U2
:
2614 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2615 u1u2
= reg
& (DWC3_DCTL_INITU2ENA
2616 | DWC3_DCTL_ACCEPTU2ENA
2617 | DWC3_DCTL_INITU1ENA
2618 | DWC3_DCTL_ACCEPTU1ENA
);
2621 dwc
->u1u2
= reg
& u1u2
;
2625 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2635 case DWC3_LINK_STATE_U1
:
2636 if (dwc
->speed
== USB_SPEED_SUPER
)
2637 dwc3_suspend_gadget(dwc
);
2639 case DWC3_LINK_STATE_U2
:
2640 case DWC3_LINK_STATE_U3
:
2641 dwc3_suspend_gadget(dwc
);
2643 case DWC3_LINK_STATE_RESUME
:
2644 dwc3_resume_gadget(dwc
);
2651 dwc
->link_state
= next
;
2654 static void dwc3_gadget_suspend_interrupt(struct dwc3
*dwc
,
2655 unsigned int evtinfo
)
2657 enum dwc3_link_state next
= evtinfo
& DWC3_LINK_STATE_MASK
;
2659 if (dwc
->link_state
!= next
&& next
== DWC3_LINK_STATE_U3
)
2660 dwc3_suspend_gadget(dwc
);
2662 dwc
->link_state
= next
;
2665 static void dwc3_gadget_hibernation_interrupt(struct dwc3
*dwc
,
2666 unsigned int evtinfo
)
2668 unsigned int is_ss
= evtinfo
& BIT(4);
2671 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2672 * have a known issue which can cause USB CV TD.9.23 to fail
2675 * Because of this issue, core could generate bogus hibernation
2676 * events which SW needs to ignore.
2680 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2681 * Device Fallback from SuperSpeed
2683 if (is_ss
^ (dwc
->speed
== USB_SPEED_SUPER
))
2686 /* enter hibernation here */
2689 static void dwc3_gadget_interrupt(struct dwc3
*dwc
,
2690 const struct dwc3_event_devt
*event
)
2692 switch (event
->type
) {
2693 case DWC3_DEVICE_EVENT_DISCONNECT
:
2694 dwc3_gadget_disconnect_interrupt(dwc
);
2696 case DWC3_DEVICE_EVENT_RESET
:
2697 dwc3_gadget_reset_interrupt(dwc
);
2699 case DWC3_DEVICE_EVENT_CONNECT_DONE
:
2700 dwc3_gadget_conndone_interrupt(dwc
);
2702 case DWC3_DEVICE_EVENT_WAKEUP
:
2703 dwc3_gadget_wakeup_interrupt(dwc
);
2705 case DWC3_DEVICE_EVENT_HIBER_REQ
:
2706 if (dev_WARN_ONCE(dwc
->dev
, !dwc
->has_hibernation
,
2707 "unexpected hibernation event\n"))
2710 dwc3_gadget_hibernation_interrupt(dwc
, event
->event_info
);
2712 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE
:
2713 dwc3_gadget_linksts_change_interrupt(dwc
, event
->event_info
);
2715 case DWC3_DEVICE_EVENT_EOPF
:
2716 /* It changed to be suspend event for version 2.30a and above */
2717 if (dwc
->revision
< DWC3_REVISION_230A
) {
2718 dwc3_trace(trace_dwc3_gadget
, "End of Periodic Frame");
2720 dwc3_trace(trace_dwc3_gadget
, "U3/L1-L2 Suspend Event");
2723 * Ignore suspend event until the gadget enters into
2724 * USB_STATE_CONFIGURED state.
2726 if (dwc
->gadget
.state
>= USB_STATE_CONFIGURED
)
2727 dwc3_gadget_suspend_interrupt(dwc
,
2731 case DWC3_DEVICE_EVENT_SOF
:
2732 dwc3_trace(trace_dwc3_gadget
, "Start of Periodic Frame");
2734 case DWC3_DEVICE_EVENT_ERRATIC_ERROR
:
2735 dwc3_trace(trace_dwc3_gadget
, "Erratic Error");
2737 case DWC3_DEVICE_EVENT_CMD_CMPL
:
2738 dwc3_trace(trace_dwc3_gadget
, "Command Complete");
2740 case DWC3_DEVICE_EVENT_OVERFLOW
:
2741 dwc3_trace(trace_dwc3_gadget
, "Overflow");
2744 dev_WARN(dwc
->dev
, "UNKNOWN IRQ %d\n", event
->type
);
2748 static void dwc3_process_event_entry(struct dwc3
*dwc
,
2749 const union dwc3_event
*event
)
2751 trace_dwc3_event(event
->raw
);
2753 /* Endpoint IRQ, handle it and return early */
2754 if (event
->type
.is_devspec
== 0) {
2756 return dwc3_endpoint_interrupt(dwc
, &event
->depevt
);
2759 switch (event
->type
.type
) {
2760 case DWC3_EVENT_TYPE_DEV
:
2761 dwc3_gadget_interrupt(dwc
, &event
->devt
);
2763 /* REVISIT what to do with Carkit and I2C events ? */
2765 dev_err(dwc
->dev
, "UNKNOWN IRQ type %d\n", event
->raw
);
2769 static irqreturn_t
dwc3_process_event_buf(struct dwc3_event_buffer
*evt
)
2771 struct dwc3
*dwc
= evt
->dwc
;
2772 irqreturn_t ret
= IRQ_NONE
;
2778 if (!(evt
->flags
& DWC3_EVENT_PENDING
))
2782 union dwc3_event event
;
2784 event
.raw
= *(u32
*) (evt
->buf
+ evt
->lpos
);
2786 dwc3_process_event_entry(dwc
, &event
);
2789 * FIXME we wrap around correctly to the next entry as
2790 * almost all entries are 4 bytes in size. There is one
2791 * entry which has 12 bytes which is a regular entry
2792 * followed by 8 bytes data. ATM I don't know how
2793 * things are organized if we get next to the a
2794 * boundary so I worry about that once we try to handle
2797 evt
->lpos
= (evt
->lpos
+ 4) % DWC3_EVENT_BUFFERS_SIZE
;
2800 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(0), 4);
2804 evt
->flags
&= ~DWC3_EVENT_PENDING
;
2807 /* Unmask interrupt */
2808 reg
= dwc3_readl(dwc
->regs
, DWC3_GEVNTSIZ(0));
2809 reg
&= ~DWC3_GEVNTSIZ_INTMASK
;
2810 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(0), reg
);
2815 static irqreturn_t
dwc3_thread_interrupt(int irq
, void *_evt
)
2817 struct dwc3_event_buffer
*evt
= _evt
;
2818 struct dwc3
*dwc
= evt
->dwc
;
2819 unsigned long flags
;
2820 irqreturn_t ret
= IRQ_NONE
;
2822 spin_lock_irqsave(&dwc
->lock
, flags
);
2823 ret
= dwc3_process_event_buf(evt
);
2824 spin_unlock_irqrestore(&dwc
->lock
, flags
);
2829 static irqreturn_t
dwc3_check_event_buf(struct dwc3_event_buffer
*evt
)
2831 struct dwc3
*dwc
= evt
->dwc
;
2835 if (pm_runtime_suspended(dwc
->dev
)) {
2836 pm_runtime_get(dwc
->dev
);
2837 disable_irq_nosync(dwc
->irq_gadget
);
2838 dwc
->pending_events
= true;
2842 count
= dwc3_readl(dwc
->regs
, DWC3_GEVNTCOUNT(0));
2843 count
&= DWC3_GEVNTCOUNT_MASK
;
2848 evt
->flags
|= DWC3_EVENT_PENDING
;
2850 /* Mask interrupt */
2851 reg
= dwc3_readl(dwc
->regs
, DWC3_GEVNTSIZ(0));
2852 reg
|= DWC3_GEVNTSIZ_INTMASK
;
2853 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(0), reg
);
2855 return IRQ_WAKE_THREAD
;
2858 static irqreturn_t
dwc3_interrupt(int irq
, void *_evt
)
2860 struct dwc3_event_buffer
*evt
= _evt
;
2862 return dwc3_check_event_buf(evt
);
2866 * dwc3_gadget_init - Initializes gadget related registers
2867 * @dwc: pointer to our controller context structure
2869 * Returns 0 on success otherwise negative errno.
2871 int dwc3_gadget_init(struct dwc3
*dwc
)
2874 struct platform_device
*dwc3_pdev
= to_platform_device(dwc
->dev
);
2876 irq
= platform_get_irq_byname(dwc3_pdev
, "peripheral");
2877 if (irq
== -EPROBE_DEFER
)
2881 irq
= platform_get_irq_byname(dwc3_pdev
, "dwc_usb3");
2882 if (irq
== -EPROBE_DEFER
)
2886 irq
= platform_get_irq(dwc3_pdev
, 0);
2888 if (irq
!= -EPROBE_DEFER
) {
2890 "missing peripheral IRQ\n");
2899 dwc
->irq_gadget
= irq
;
2901 dwc
->ctrl_req
= dma_alloc_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
2902 &dwc
->ctrl_req_addr
, GFP_KERNEL
);
2903 if (!dwc
->ctrl_req
) {
2904 dev_err(dwc
->dev
, "failed to allocate ctrl request\n");
2909 dwc
->ep0_trb
= dma_alloc_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
) * 2,
2910 &dwc
->ep0_trb_addr
, GFP_KERNEL
);
2911 if (!dwc
->ep0_trb
) {
2912 dev_err(dwc
->dev
, "failed to allocate ep0 trb\n");
2917 dwc
->setup_buf
= kzalloc(DWC3_EP0_BOUNCE_SIZE
, GFP_KERNEL
);
2918 if (!dwc
->setup_buf
) {
2923 dwc
->ep0_bounce
= dma_alloc_coherent(dwc
->dev
,
2924 DWC3_EP0_BOUNCE_SIZE
, &dwc
->ep0_bounce_addr
,
2926 if (!dwc
->ep0_bounce
) {
2927 dev_err(dwc
->dev
, "failed to allocate ep0 bounce buffer\n");
2932 dwc
->zlp_buf
= kzalloc(DWC3_ZLP_BUF_SIZE
, GFP_KERNEL
);
2933 if (!dwc
->zlp_buf
) {
2938 dwc
->gadget
.ops
= &dwc3_gadget_ops
;
2939 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2940 dwc
->gadget
.sg_supported
= true;
2941 dwc
->gadget
.name
= "dwc3-gadget";
2942 dwc
->gadget
.is_otg
= dwc
->dr_mode
== USB_DR_MODE_OTG
;
2945 * FIXME We might be setting max_speed to <SUPER, however versions
2946 * <2.20a of dwc3 have an issue with metastability (documented
2947 * elsewhere in this driver) which tells us we can't set max speed to
2948 * anything lower than SUPER.
2950 * Because gadget.max_speed is only used by composite.c and function
2951 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2952 * to happen so we avoid sending SuperSpeed Capability descriptor
2953 * together with our BOS descriptor as that could confuse host into
2954 * thinking we can handle super speed.
2956 * Note that, in fact, we won't even support GetBOS requests when speed
2957 * is less than super speed because we don't have means, yet, to tell
2958 * composite.c that we are USB 2.0 + LPM ECN.
2960 if (dwc
->revision
< DWC3_REVISION_220A
)
2961 dwc3_trace(trace_dwc3_gadget
,
2962 "Changing max_speed on rev %08x",
2965 dwc
->gadget
.max_speed
= dwc
->maximum_speed
;
2968 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2971 dwc
->gadget
.quirk_ep_out_aligned_size
= true;
2974 * REVISIT: Here we should clear all pending IRQs to be
2975 * sure we're starting from a well known location.
2978 ret
= dwc3_gadget_init_endpoints(dwc
);
2982 ret
= usb_add_gadget_udc(dwc
->dev
, &dwc
->gadget
);
2984 dev_err(dwc
->dev
, "failed to register udc\n");
2991 kfree(dwc
->zlp_buf
);
2994 dwc3_gadget_free_endpoints(dwc
);
2995 dma_free_coherent(dwc
->dev
, DWC3_EP0_BOUNCE_SIZE
,
2996 dwc
->ep0_bounce
, dwc
->ep0_bounce_addr
);
2999 kfree(dwc
->setup_buf
);
3002 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
) * 2,
3003 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
3006 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
3007 dwc
->ctrl_req
, dwc
->ctrl_req_addr
);
3013 /* -------------------------------------------------------------------------- */
3015 void dwc3_gadget_exit(struct dwc3
*dwc
)
3017 usb_del_gadget_udc(&dwc
->gadget
);
3019 dwc3_gadget_free_endpoints(dwc
);
3021 dma_free_coherent(dwc
->dev
, DWC3_EP0_BOUNCE_SIZE
,
3022 dwc
->ep0_bounce
, dwc
->ep0_bounce_addr
);
3024 kfree(dwc
->setup_buf
);
3025 kfree(dwc
->zlp_buf
);
3027 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
) * 2,
3028 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
3030 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
3031 dwc
->ctrl_req
, dwc
->ctrl_req_addr
);
3034 int dwc3_gadget_suspend(struct dwc3
*dwc
)
3038 if (!dwc
->gadget_driver
)
3041 ret
= dwc3_gadget_run_stop(dwc
, false, false);
3045 dwc3_disconnect_gadget(dwc
);
3046 __dwc3_gadget_stop(dwc
);
3051 int dwc3_gadget_resume(struct dwc3
*dwc
)
3055 if (!dwc
->gadget_driver
)
3058 ret
= __dwc3_gadget_start(dwc
);
3062 ret
= dwc3_gadget_run_stop(dwc
, true, false);
3069 __dwc3_gadget_stop(dwc
);
3075 void dwc3_gadget_process_pending_events(struct dwc3
*dwc
)
3077 if (dwc
->pending_events
) {
3078 dwc3_interrupt(dwc
->irq_gadget
, dwc
->ev_buf
);
3079 dwc
->pending_events
= false;
3080 enable_irq(dwc
->irq_gadget
);