2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/interrupt.h>
27 #include <linux/list.h>
28 #include <linux/dma-mapping.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
47 int dwc3_gadget_set_test_mode(struct dwc3
*dwc
, int mode
)
51 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
52 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
66 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
78 int dwc3_gadget_get_link_state(struct dwc3
*dwc
)
82 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
84 return DWC3_DSTS_USBLNKST(reg
);
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
92 * Caller should take care of locking. This function will
93 * return 0 on success or -ETIMEDOUT.
95 int dwc3_gadget_set_link_state(struct dwc3
*dwc
, enum dwc3_link_state state
)
101 * Wait until device controller is ready. Only applies to 1.94a and
104 if (dwc
->revision
>= DWC3_REVISION_194A
) {
106 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
107 if (reg
& DWC3_DSTS_DCNRD
)
117 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
118 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
120 /* set requested state */
121 reg
|= DWC3_DCTL_ULSTCHNGREQ(state
);
122 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
128 if (dwc
->revision
>= DWC3_REVISION_194A
)
131 /* wait for a change in DSTS */
134 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
136 if (DWC3_DSTS_USBLNKST(reg
) == state
)
142 dwc3_trace(trace_dwc3_gadget
,
143 "link state change request timed out");
148 static void dwc3_ep_inc_enq(struct dwc3_ep
*dep
)
151 dep
->trb_enqueue
%= DWC3_TRB_NUM
;
154 static void dwc3_ep_inc_deq(struct dwc3_ep
*dep
)
157 dep
->trb_dequeue
%= DWC3_TRB_NUM
;
160 static int dwc3_ep_is_last_trb(unsigned int index
)
162 return index
== DWC3_TRB_NUM
- 1;
165 void dwc3_gadget_giveback(struct dwc3_ep
*dep
, struct dwc3_request
*req
,
168 struct dwc3
*dwc
= dep
->dwc
;
174 dwc3_ep_inc_deq(dep
);
176 * Skip LINK TRB. We can't use req->trb and check for
177 * DWC3_TRBCTL_LINK_TRB because it points the TRB we
178 * just completed (not the LINK TRB).
180 if (dwc3_ep_is_last_trb(dep
->trb_dequeue
))
181 dwc3_ep_inc_deq(dep
);
182 } while(++i
< req
->request
.num_mapped_sgs
);
183 req
->started
= false;
185 list_del(&req
->list
);
188 if (req
->request
.status
== -EINPROGRESS
)
189 req
->request
.status
= status
;
191 if (dwc
->ep0_bounced
&& dep
->number
== 0)
192 dwc
->ep0_bounced
= false;
194 usb_gadget_unmap_request(&dwc
->gadget
, &req
->request
,
197 trace_dwc3_gadget_giveback(req
);
199 spin_unlock(&dwc
->lock
);
200 usb_gadget_giveback_request(&dep
->endpoint
, &req
->request
);
201 spin_lock(&dwc
->lock
);
204 pm_runtime_put(dwc
->dev
);
207 int dwc3_send_gadget_generic_command(struct dwc3
*dwc
, unsigned cmd
, u32 param
)
212 trace_dwc3_gadget_generic_cmd(cmd
, param
);
214 dwc3_writel(dwc
->regs
, DWC3_DGCMDPAR
, param
);
215 dwc3_writel(dwc
->regs
, DWC3_DGCMD
, cmd
| DWC3_DGCMD_CMDACT
);
218 reg
= dwc3_readl(dwc
->regs
, DWC3_DGCMD
);
219 if (!(reg
& DWC3_DGCMD_CMDACT
)) {
220 dwc3_trace(trace_dwc3_gadget
,
221 "Command Complete --> %d",
222 DWC3_DGCMD_STATUS(reg
));
223 if (DWC3_DGCMD_STATUS(reg
))
229 * We can't sleep here, because it's also called from
234 dwc3_trace(trace_dwc3_gadget
,
235 "Command Timed Out");
242 static int __dwc3_gadget_wakeup(struct dwc3
*dwc
);
244 int dwc3_send_gadget_ep_cmd(struct dwc3_ep
*dep
, unsigned cmd
,
245 struct dwc3_gadget_ep_cmd_params
*params
)
247 struct dwc3
*dwc
= dep
->dwc
;
254 trace_dwc3_gadget_ep_cmd(dep
, cmd
, params
);
257 * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
258 * we're issuing an endpoint command, we must check if
259 * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
261 * We will also set SUSPHY bit to what it was before returning as stated
262 * by the same section on Synopsys databook.
264 if (dwc
->gadget
.speed
<= USB_SPEED_HIGH
) {
265 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
266 if (unlikely(reg
& DWC3_GUSB2PHYCFG_SUSPHY
)) {
268 reg
&= ~DWC3_GUSB2PHYCFG_SUSPHY
;
269 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
273 if (cmd
== DWC3_DEPCMD_STARTTRANSFER
) {
276 needs_wakeup
= (dwc
->link_state
== DWC3_LINK_STATE_U1
||
277 dwc
->link_state
== DWC3_LINK_STATE_U2
||
278 dwc
->link_state
== DWC3_LINK_STATE_U3
);
280 if (unlikely(needs_wakeup
)) {
281 ret
= __dwc3_gadget_wakeup(dwc
);
282 dev_WARN_ONCE(dwc
->dev
, ret
, "wakeup failed --> %d\n",
287 dwc3_writel(dep
->regs
, DWC3_DEPCMDPAR0
, params
->param0
);
288 dwc3_writel(dep
->regs
, DWC3_DEPCMDPAR1
, params
->param1
);
289 dwc3_writel(dep
->regs
, DWC3_DEPCMDPAR2
, params
->param2
);
291 dwc3_writel(dep
->regs
, DWC3_DEPCMD
, cmd
| DWC3_DEPCMD_CMDACT
);
293 reg
= dwc3_readl(dep
->regs
, DWC3_DEPCMD
);
294 if (!(reg
& DWC3_DEPCMD_CMDACT
)) {
295 int cmd_status
= DWC3_DEPCMD_STATUS(reg
);
297 dwc3_trace(trace_dwc3_gadget
,
298 "Command Complete --> %d",
301 switch (cmd_status
) {
305 case DEPEVT_TRANSFER_NO_RESOURCE
:
306 dwc3_trace(trace_dwc3_gadget
, "%s: no resource available");
309 case DEPEVT_TRANSFER_BUS_EXPIRY
:
311 * SW issues START TRANSFER command to
312 * isochronous ep with future frame interval. If
313 * future interval time has already passed when
314 * core receives the command, it will respond
315 * with an error status of 'Bus Expiry'.
317 * Instead of always returning -EINVAL, let's
318 * give a hint to the gadget driver that this is
319 * the case by returning -EAGAIN.
321 dwc3_trace(trace_dwc3_gadget
, "%s: bus expiry");
325 dev_WARN(dwc
->dev
, "UNKNOWN cmd status\n");
332 * We can't sleep here, because it is also called from
337 dwc3_trace(trace_dwc3_gadget
,
338 "Command Timed Out");
344 if (unlikely(susphy
)) {
345 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
346 reg
|= DWC3_GUSB2PHYCFG_SUSPHY
;
347 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
353 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep
*dep
)
355 struct dwc3
*dwc
= dep
->dwc
;
356 struct dwc3_gadget_ep_cmd_params params
;
357 u32 cmd
= DWC3_DEPCMD_CLEARSTALL
;
360 * As of core revision 2.60a the recommended programming model
361 * is to set the ClearPendIN bit when issuing a Clear Stall EP
362 * command for IN endpoints. This is to prevent an issue where
363 * some (non-compliant) hosts may not send ACK TPs for pending
364 * IN transfers due to a mishandled error condition. Synopsys
367 if (dep
->direction
&& (dwc
->revision
>= DWC3_REVISION_260A
))
368 cmd
|= DWC3_DEPCMD_CLEARPENDIN
;
370 memset(¶ms
, 0, sizeof(params
));
372 return dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
375 static dma_addr_t
dwc3_trb_dma_offset(struct dwc3_ep
*dep
,
376 struct dwc3_trb
*trb
)
378 u32 offset
= (char *) trb
- (char *) dep
->trb_pool
;
380 return dep
->trb_pool_dma
+ offset
;
383 static int dwc3_alloc_trb_pool(struct dwc3_ep
*dep
)
385 struct dwc3
*dwc
= dep
->dwc
;
390 dep
->trb_pool
= dma_alloc_coherent(dwc
->dev
,
391 sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
392 &dep
->trb_pool_dma
, GFP_KERNEL
);
393 if (!dep
->trb_pool
) {
394 dev_err(dep
->dwc
->dev
, "failed to allocate trb pool for %s\n",
402 static void dwc3_free_trb_pool(struct dwc3_ep
*dep
)
404 struct dwc3
*dwc
= dep
->dwc
;
406 dma_free_coherent(dwc
->dev
, sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
407 dep
->trb_pool
, dep
->trb_pool_dma
);
409 dep
->trb_pool
= NULL
;
410 dep
->trb_pool_dma
= 0;
413 static int dwc3_gadget_set_xfer_resource(struct dwc3
*dwc
, struct dwc3_ep
*dep
);
416 * dwc3_gadget_start_config - Configure EP resources
417 * @dwc: pointer to our controller context structure
418 * @dep: endpoint that is being enabled
420 * The assignment of transfer resources cannot perfectly follow the
421 * data book due to the fact that the controller driver does not have
422 * all knowledge of the configuration in advance. It is given this
423 * information piecemeal by the composite gadget framework after every
424 * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
425 * programming model in this scenario can cause errors. For two
428 * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
429 * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
430 * multiple interfaces.
432 * 2) The databook does not mention doing more DEPXFERCFG for new
433 * endpoint on alt setting (8.1.6).
435 * The following simplified method is used instead:
437 * All hardware endpoints can be assigned a transfer resource and this
438 * setting will stay persistent until either a core reset or
439 * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
440 * do DEPXFERCFG for every hardware endpoint as well. We are
441 * guaranteed that there are as many transfer resources as endpoints.
443 * This function is called for each endpoint when it is being enabled
444 * but is triggered only when called for EP0-out, which always happens
445 * first, and which should only happen in one of the above conditions.
447 static int dwc3_gadget_start_config(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
449 struct dwc3_gadget_ep_cmd_params params
;
457 memset(¶ms
, 0x00, sizeof(params
));
458 cmd
= DWC3_DEPCMD_DEPSTARTCFG
;
460 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
464 for (i
= 0; i
< DWC3_ENDPOINTS_NUM
; i
++) {
465 struct dwc3_ep
*dep
= dwc
->eps
[i
];
470 ret
= dwc3_gadget_set_xfer_resource(dwc
, dep
);
478 static int dwc3_gadget_set_ep_config(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
479 const struct usb_endpoint_descriptor
*desc
,
480 const struct usb_ss_ep_comp_descriptor
*comp_desc
,
481 bool ignore
, bool restore
)
483 struct dwc3_gadget_ep_cmd_params params
;
485 memset(¶ms
, 0x00, sizeof(params
));
487 params
.param0
= DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc
))
488 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc
));
490 /* Burst size is only needed in SuperSpeed mode */
491 if (dwc
->gadget
.speed
>= USB_SPEED_SUPER
) {
492 u32 burst
= dep
->endpoint
.maxburst
;
493 params
.param0
|= DWC3_DEPCFG_BURST_SIZE(burst
- 1);
497 params
.param0
|= DWC3_DEPCFG_IGN_SEQ_NUM
;
500 params
.param0
|= DWC3_DEPCFG_ACTION_RESTORE
;
501 params
.param2
|= dep
->saved_state
;
504 params
.param1
= DWC3_DEPCFG_XFER_COMPLETE_EN
505 | DWC3_DEPCFG_XFER_NOT_READY_EN
;
507 if (usb_ss_max_streams(comp_desc
) && usb_endpoint_xfer_bulk(desc
)) {
508 params
.param1
|= DWC3_DEPCFG_STREAM_CAPABLE
509 | DWC3_DEPCFG_STREAM_EVENT_EN
;
510 dep
->stream_capable
= true;
513 if (!usb_endpoint_xfer_control(desc
))
514 params
.param1
|= DWC3_DEPCFG_XFER_IN_PROGRESS_EN
;
517 * We are doing 1:1 mapping for endpoints, meaning
518 * Physical Endpoints 2 maps to Logical Endpoint 2 and
519 * so on. We consider the direction bit as part of the physical
520 * endpoint number. So USB endpoint 0x81 is 0x03.
522 params
.param1
|= DWC3_DEPCFG_EP_NUMBER(dep
->number
);
525 * We must use the lower 16 TX FIFOs even though
529 params
.param0
|= DWC3_DEPCFG_FIFO_NUMBER(dep
->number
>> 1);
531 if (desc
->bInterval
) {
532 params
.param1
|= DWC3_DEPCFG_BINTERVAL_M1(desc
->bInterval
- 1);
533 dep
->interval
= 1 << (desc
->bInterval
- 1);
536 return dwc3_send_gadget_ep_cmd(dep
, DWC3_DEPCMD_SETEPCONFIG
, ¶ms
);
539 static int dwc3_gadget_set_xfer_resource(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
541 struct dwc3_gadget_ep_cmd_params params
;
543 memset(¶ms
, 0x00, sizeof(params
));
545 params
.param0
= DWC3_DEPXFERCFG_NUM_XFER_RES(1);
547 return dwc3_send_gadget_ep_cmd(dep
, DWC3_DEPCMD_SETTRANSFRESOURCE
,
552 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
553 * @dep: endpoint to be initialized
554 * @desc: USB Endpoint Descriptor
556 * Caller should take care of locking
558 static int __dwc3_gadget_ep_enable(struct dwc3_ep
*dep
,
559 const struct usb_endpoint_descriptor
*desc
,
560 const struct usb_ss_ep_comp_descriptor
*comp_desc
,
561 bool ignore
, bool restore
)
563 struct dwc3
*dwc
= dep
->dwc
;
567 dwc3_trace(trace_dwc3_gadget
, "Enabling %s", dep
->name
);
569 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
570 ret
= dwc3_gadget_start_config(dwc
, dep
);
575 ret
= dwc3_gadget_set_ep_config(dwc
, dep
, desc
, comp_desc
, ignore
,
580 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
581 struct dwc3_trb
*trb_st_hw
;
582 struct dwc3_trb
*trb_link
;
584 dep
->endpoint
.desc
= desc
;
585 dep
->comp_desc
= comp_desc
;
586 dep
->type
= usb_endpoint_type(desc
);
587 dep
->flags
|= DWC3_EP_ENABLED
;
589 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
590 reg
|= DWC3_DALEPENA_EP(dep
->number
);
591 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
593 if (usb_endpoint_xfer_control(desc
))
596 /* Link TRB. The HWO bit is never reset */
597 trb_st_hw
= &dep
->trb_pool
[0];
599 trb_link
= &dep
->trb_pool
[DWC3_TRB_NUM
- 1];
600 memset(trb_link
, 0, sizeof(*trb_link
));
602 trb_link
->bpl
= lower_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
603 trb_link
->bph
= upper_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
604 trb_link
->ctrl
|= DWC3_TRBCTL_LINK_TRB
;
605 trb_link
->ctrl
|= DWC3_TRB_CTRL_HWO
;
609 switch (usb_endpoint_type(desc
)) {
610 case USB_ENDPOINT_XFER_CONTROL
:
611 /* don't change name */
613 case USB_ENDPOINT_XFER_ISOC
:
614 strlcat(dep
->name
, "-isoc", sizeof(dep
->name
));
616 case USB_ENDPOINT_XFER_BULK
:
617 strlcat(dep
->name
, "-bulk", sizeof(dep
->name
));
619 case USB_ENDPOINT_XFER_INT
:
620 strlcat(dep
->name
, "-int", sizeof(dep
->name
));
623 dev_err(dwc
->dev
, "invalid endpoint transfer type\n");
629 static void dwc3_stop_active_transfer(struct dwc3
*dwc
, u32 epnum
, bool force
);
630 static void dwc3_remove_requests(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
632 struct dwc3_request
*req
;
634 if (!list_empty(&dep
->started_list
)) {
635 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
637 /* - giveback all requests to gadget driver */
638 while (!list_empty(&dep
->started_list
)) {
639 req
= next_request(&dep
->started_list
);
641 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
645 while (!list_empty(&dep
->pending_list
)) {
646 req
= next_request(&dep
->pending_list
);
648 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
653 * __dwc3_gadget_ep_disable - Disables a HW endpoint
654 * @dep: the endpoint to disable
656 * This function also removes requests which are currently processed ny the
657 * hardware and those which are not yet scheduled.
658 * Caller should take care of locking.
660 static int __dwc3_gadget_ep_disable(struct dwc3_ep
*dep
)
662 struct dwc3
*dwc
= dep
->dwc
;
665 dwc3_trace(trace_dwc3_gadget
, "Disabling %s", dep
->name
);
667 dwc3_remove_requests(dwc
, dep
);
669 /* make sure HW endpoint isn't stalled */
670 if (dep
->flags
& DWC3_EP_STALL
)
671 __dwc3_gadget_ep_set_halt(dep
, 0, false);
673 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
674 reg
&= ~DWC3_DALEPENA_EP(dep
->number
);
675 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
677 dep
->stream_capable
= false;
678 dep
->endpoint
.desc
= NULL
;
679 dep
->comp_desc
= NULL
;
683 snprintf(dep
->name
, sizeof(dep
->name
), "ep%d%s",
685 (dep
->number
& 1) ? "in" : "out");
690 /* -------------------------------------------------------------------------- */
692 static int dwc3_gadget_ep0_enable(struct usb_ep
*ep
,
693 const struct usb_endpoint_descriptor
*desc
)
698 static int dwc3_gadget_ep0_disable(struct usb_ep
*ep
)
703 /* -------------------------------------------------------------------------- */
705 static int dwc3_gadget_ep_enable(struct usb_ep
*ep
,
706 const struct usb_endpoint_descriptor
*desc
)
713 if (!ep
|| !desc
|| desc
->bDescriptorType
!= USB_DT_ENDPOINT
) {
714 pr_debug("dwc3: invalid parameters\n");
718 if (!desc
->wMaxPacketSize
) {
719 pr_debug("dwc3: missing wMaxPacketSize\n");
723 dep
= to_dwc3_ep(ep
);
726 if (dev_WARN_ONCE(dwc
->dev
, dep
->flags
& DWC3_EP_ENABLED
,
727 "%s is already enabled\n",
731 spin_lock_irqsave(&dwc
->lock
, flags
);
732 ret
= __dwc3_gadget_ep_enable(dep
, desc
, ep
->comp_desc
, false, false);
733 spin_unlock_irqrestore(&dwc
->lock
, flags
);
738 static int dwc3_gadget_ep_disable(struct usb_ep
*ep
)
746 pr_debug("dwc3: invalid parameters\n");
750 dep
= to_dwc3_ep(ep
);
753 if (dev_WARN_ONCE(dwc
->dev
, !(dep
->flags
& DWC3_EP_ENABLED
),
754 "%s is already disabled\n",
758 spin_lock_irqsave(&dwc
->lock
, flags
);
759 ret
= __dwc3_gadget_ep_disable(dep
);
760 spin_unlock_irqrestore(&dwc
->lock
, flags
);
765 static struct usb_request
*dwc3_gadget_ep_alloc_request(struct usb_ep
*ep
,
768 struct dwc3_request
*req
;
769 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
771 req
= kzalloc(sizeof(*req
), gfp_flags
);
775 req
->epnum
= dep
->number
;
778 trace_dwc3_alloc_request(req
);
780 return &req
->request
;
783 static void dwc3_gadget_ep_free_request(struct usb_ep
*ep
,
784 struct usb_request
*request
)
786 struct dwc3_request
*req
= to_dwc3_request(request
);
788 trace_dwc3_free_request(req
);
793 * dwc3_prepare_one_trb - setup one TRB from one request
794 * @dep: endpoint for which this request is prepared
795 * @req: dwc3_request pointer
797 static void dwc3_prepare_one_trb(struct dwc3_ep
*dep
,
798 struct dwc3_request
*req
, dma_addr_t dma
,
799 unsigned length
, unsigned last
, unsigned chain
, unsigned node
)
801 struct dwc3_trb
*trb
;
803 dwc3_trace(trace_dwc3_gadget
, "%s: req %p dma %08llx length %d%s%s",
804 dep
->name
, req
, (unsigned long long) dma
,
805 length
, last
? " last" : "",
806 chain
? " chain" : "");
809 trb
= &dep
->trb_pool
[dep
->trb_enqueue
];
812 dwc3_gadget_move_started_request(req
);
814 req
->trb_dma
= dwc3_trb_dma_offset(dep
, trb
);
815 req
->first_trb_index
= dep
->trb_enqueue
;
818 dwc3_ep_inc_enq(dep
);
819 /* Skip the LINK-TRB */
820 if (dwc3_ep_is_last_trb(dep
->trb_enqueue
))
821 dwc3_ep_inc_enq(dep
);
823 trb
->size
= DWC3_TRB_SIZE_LENGTH(length
);
824 trb
->bpl
= lower_32_bits(dma
);
825 trb
->bph
= upper_32_bits(dma
);
827 switch (usb_endpoint_type(dep
->endpoint
.desc
)) {
828 case USB_ENDPOINT_XFER_CONTROL
:
829 trb
->ctrl
= DWC3_TRBCTL_CONTROL_SETUP
;
832 case USB_ENDPOINT_XFER_ISOC
:
834 trb
->ctrl
= DWC3_TRBCTL_ISOCHRONOUS_FIRST
;
836 trb
->ctrl
= DWC3_TRBCTL_ISOCHRONOUS
;
838 /* always enable Interrupt on Missed ISOC */
839 trb
->ctrl
|= DWC3_TRB_CTRL_ISP_IMI
;
842 case USB_ENDPOINT_XFER_BULK
:
843 case USB_ENDPOINT_XFER_INT
:
844 trb
->ctrl
= DWC3_TRBCTL_NORMAL
;
848 * This is only possible with faulty memory because we
849 * checked it already :)
854 /* always enable Continue on Short Packet */
855 trb
->ctrl
|= DWC3_TRB_CTRL_CSP
;
857 if (!req
->request
.no_interrupt
&& !chain
)
858 trb
->ctrl
|= DWC3_TRB_CTRL_IOC
| DWC3_TRB_CTRL_ISP_IMI
;
861 trb
->ctrl
|= DWC3_TRB_CTRL_LST
;
864 trb
->ctrl
|= DWC3_TRB_CTRL_CHN
;
866 if (usb_endpoint_xfer_bulk(dep
->endpoint
.desc
) && dep
->stream_capable
)
867 trb
->ctrl
|= DWC3_TRB_CTRL_SID_SOFN(req
->request
.stream_id
);
869 trb
->ctrl
|= DWC3_TRB_CTRL_HWO
;
871 trace_dwc3_prepare_trb(dep
, trb
);
874 static u32
dwc3_calc_trbs_left(struct dwc3_ep
*dep
)
876 struct dwc3_trb
*tmp
;
879 * If enqueue & dequeue are equal than it is either full or empty.
881 * One way to know for sure is if the TRB right before us has HWO bit
882 * set or not. If it has, then we're definitely full and can't fit any
883 * more transfers in our ring.
885 if (dep
->trb_enqueue
== dep
->trb_dequeue
) {
886 /* If we're full, enqueue/dequeue are > 0 */
887 if (dep
->trb_enqueue
) {
888 tmp
= &dep
->trb_pool
[dep
->trb_enqueue
- 1];
889 if (tmp
->ctrl
& DWC3_TRB_CTRL_HWO
)
893 return DWC3_TRB_NUM
- 1;
896 return dep
->trb_dequeue
- dep
->trb_enqueue
;
899 static void dwc3_prepare_one_trb_sg(struct dwc3_ep
*dep
,
900 struct dwc3_request
*req
, unsigned int trbs_left
)
902 struct usb_request
*request
= &req
->request
;
903 struct scatterlist
*sg
= request
->sg
;
904 struct scatterlist
*s
;
905 unsigned int last
= false;
910 for_each_sg(sg
, s
, request
->num_mapped_sgs
, i
) {
911 unsigned chain
= true;
913 length
= sg_dma_len(s
);
914 dma
= sg_dma_address(s
);
917 if (list_is_last(&req
->list
, &dep
->pending_list
))
929 dwc3_prepare_one_trb(dep
, req
, dma
, length
,
937 static void dwc3_prepare_one_trb_linear(struct dwc3_ep
*dep
,
938 struct dwc3_request
*req
, unsigned int trbs_left
)
940 unsigned int last
= false;
944 dma
= req
->request
.dma
;
945 length
= req
->request
.length
;
950 /* Is this the last request? */
951 if (list_is_last(&req
->list
, &dep
->pending_list
))
954 dwc3_prepare_one_trb(dep
, req
, dma
, length
,
959 * dwc3_prepare_trbs - setup TRBs from requests
960 * @dep: endpoint for which requests are being prepared
962 * The function goes through the requests list and sets up TRBs for the
963 * transfers. The function returns once there are no more TRBs available or
964 * it runs out of requests.
966 static void dwc3_prepare_trbs(struct dwc3_ep
*dep
)
968 struct dwc3_request
*req
, *n
;
971 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM
);
973 trbs_left
= dwc3_calc_trbs_left(dep
);
975 list_for_each_entry_safe(req
, n
, &dep
->pending_list
, list
) {
976 if (req
->request
.num_mapped_sgs
> 0)
977 dwc3_prepare_one_trb_sg(dep
, req
, trbs_left
--);
979 dwc3_prepare_one_trb_linear(dep
, req
, trbs_left
--);
986 static int __dwc3_gadget_kick_transfer(struct dwc3_ep
*dep
, u16 cmd_param
)
988 struct dwc3_gadget_ep_cmd_params params
;
989 struct dwc3_request
*req
;
990 struct dwc3
*dwc
= dep
->dwc
;
995 starting
= !(dep
->flags
& DWC3_EP_BUSY
);
997 dwc3_prepare_trbs(dep
);
998 req
= next_request(&dep
->started_list
);
1000 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
1004 memset(¶ms
, 0, sizeof(params
));
1007 params
.param0
= upper_32_bits(req
->trb_dma
);
1008 params
.param1
= lower_32_bits(req
->trb_dma
);
1009 cmd
= DWC3_DEPCMD_STARTTRANSFER
;
1011 cmd
= DWC3_DEPCMD_UPDATETRANSFER
;
1014 cmd
|= DWC3_DEPCMD_PARAM(cmd_param
);
1015 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
1018 * FIXME we need to iterate over the list of requests
1019 * here and stop, unmap, free and del each of the linked
1020 * requests instead of what we do now.
1022 usb_gadget_unmap_request(&dwc
->gadget
, &req
->request
,
1024 list_del(&req
->list
);
1028 dep
->flags
|= DWC3_EP_BUSY
;
1031 dep
->resource_index
= dwc3_gadget_ep_get_transfer_index(dep
);
1032 WARN_ON_ONCE(!dep
->resource_index
);
1038 static void __dwc3_gadget_start_isoc(struct dwc3
*dwc
,
1039 struct dwc3_ep
*dep
, u32 cur_uf
)
1043 if (list_empty(&dep
->pending_list
)) {
1044 dwc3_trace(trace_dwc3_gadget
,
1045 "ISOC ep %s run out for requests",
1047 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
1051 /* 4 micro frames in the future */
1052 uf
= cur_uf
+ dep
->interval
* 4;
1054 __dwc3_gadget_kick_transfer(dep
, uf
);
1057 static void dwc3_gadget_start_isoc(struct dwc3
*dwc
,
1058 struct dwc3_ep
*dep
, const struct dwc3_event_depevt
*event
)
1062 mask
= ~(dep
->interval
- 1);
1063 cur_uf
= event
->parameters
& mask
;
1065 __dwc3_gadget_start_isoc(dwc
, dep
, cur_uf
);
1068 static int __dwc3_gadget_ep_queue(struct dwc3_ep
*dep
, struct dwc3_request
*req
)
1070 struct dwc3
*dwc
= dep
->dwc
;
1073 if (!dep
->endpoint
.desc
) {
1074 dwc3_trace(trace_dwc3_gadget
,
1075 "trying to queue request %p to disabled %s\n",
1076 &req
->request
, dep
->endpoint
.name
);
1080 if (WARN(req
->dep
!= dep
, "request %p belongs to '%s'\n",
1081 &req
->request
, req
->dep
->name
)) {
1082 dwc3_trace(trace_dwc3_gadget
, "request %p belongs to '%s'\n",
1083 &req
->request
, req
->dep
->name
);
1087 pm_runtime_get(dwc
->dev
);
1089 req
->request
.actual
= 0;
1090 req
->request
.status
= -EINPROGRESS
;
1091 req
->direction
= dep
->direction
;
1092 req
->epnum
= dep
->number
;
1094 trace_dwc3_ep_queue(req
);
1097 * We only add to our list of requests now and
1098 * start consuming the list once we get XferNotReady
1101 * That way, we avoid doing anything that we don't need
1102 * to do now and defer it until the point we receive a
1103 * particular token from the Host side.
1105 * This will also avoid Host cancelling URBs due to too
1108 ret
= usb_gadget_map_request(&dwc
->gadget
, &req
->request
,
1113 list_add_tail(&req
->list
, &dep
->pending_list
);
1116 * If there are no pending requests and the endpoint isn't already
1117 * busy, we will just start the request straight away.
1119 * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1120 * little bit faster.
1122 if (!usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) &&
1123 !usb_endpoint_xfer_int(dep
->endpoint
.desc
) &&
1124 !(dep
->flags
& DWC3_EP_BUSY
)) {
1125 ret
= __dwc3_gadget_kick_transfer(dep
, 0);
1130 * There are a few special cases:
1132 * 1. XferNotReady with empty list of requests. We need to kick the
1133 * transfer here in that situation, otherwise we will be NAKing
1134 * forever. If we get XferNotReady before gadget driver has a
1135 * chance to queue a request, we will ACK the IRQ but won't be
1136 * able to receive the data until the next request is queued.
1137 * The following code is handling exactly that.
1140 if (dep
->flags
& DWC3_EP_PENDING_REQUEST
) {
1142 * If xfernotready is already elapsed and it is a case
1143 * of isoc transfer, then issue END TRANSFER, so that
1144 * you can receive xfernotready again and can have
1145 * notion of current microframe.
1147 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1148 if (list_empty(&dep
->started_list
)) {
1149 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
1150 dep
->flags
= DWC3_EP_ENABLED
;
1155 ret
= __dwc3_gadget_kick_transfer(dep
, 0);
1157 dep
->flags
&= ~DWC3_EP_PENDING_REQUEST
;
1163 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1164 * kick the transfer here after queuing a request, otherwise the
1165 * core may not see the modified TRB(s).
1167 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) &&
1168 (dep
->flags
& DWC3_EP_BUSY
) &&
1169 !(dep
->flags
& DWC3_EP_MISSED_ISOC
)) {
1170 WARN_ON_ONCE(!dep
->resource_index
);
1171 ret
= __dwc3_gadget_kick_transfer(dep
, dep
->resource_index
);
1176 * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1177 * right away, otherwise host will not know we have streams to be
1180 if (dep
->stream_capable
)
1181 ret
= __dwc3_gadget_kick_transfer(dep
, 0);
1184 if (ret
&& ret
!= -EBUSY
)
1185 dwc3_trace(trace_dwc3_gadget
,
1186 "%s: failed to kick transfers\n",
1194 static void __dwc3_gadget_ep_zlp_complete(struct usb_ep
*ep
,
1195 struct usb_request
*request
)
1197 dwc3_gadget_ep_free_request(ep
, request
);
1200 static int __dwc3_gadget_ep_queue_zlp(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
1202 struct dwc3_request
*req
;
1203 struct usb_request
*request
;
1204 struct usb_ep
*ep
= &dep
->endpoint
;
1206 dwc3_trace(trace_dwc3_gadget
, "queueing ZLP\n");
1207 request
= dwc3_gadget_ep_alloc_request(ep
, GFP_ATOMIC
);
1211 request
->length
= 0;
1212 request
->buf
= dwc
->zlp_buf
;
1213 request
->complete
= __dwc3_gadget_ep_zlp_complete
;
1215 req
= to_dwc3_request(request
);
1217 return __dwc3_gadget_ep_queue(dep
, req
);
1220 static int dwc3_gadget_ep_queue(struct usb_ep
*ep
, struct usb_request
*request
,
1223 struct dwc3_request
*req
= to_dwc3_request(request
);
1224 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1225 struct dwc3
*dwc
= dep
->dwc
;
1227 unsigned long flags
;
1231 spin_lock_irqsave(&dwc
->lock
, flags
);
1232 ret
= __dwc3_gadget_ep_queue(dep
, req
);
1235 * Okay, here's the thing, if gadget driver has requested for a ZLP by
1236 * setting request->zero, instead of doing magic, we will just queue an
1237 * extra usb_request ourselves so that it gets handled the same way as
1238 * any other request.
1240 if (ret
== 0 && request
->zero
&& request
->length
&&
1241 (request
->length
% ep
->maxpacket
== 0))
1242 ret
= __dwc3_gadget_ep_queue_zlp(dwc
, dep
);
1244 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1249 static int dwc3_gadget_ep_dequeue(struct usb_ep
*ep
,
1250 struct usb_request
*request
)
1252 struct dwc3_request
*req
= to_dwc3_request(request
);
1253 struct dwc3_request
*r
= NULL
;
1255 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1256 struct dwc3
*dwc
= dep
->dwc
;
1258 unsigned long flags
;
1261 trace_dwc3_ep_dequeue(req
);
1263 spin_lock_irqsave(&dwc
->lock
, flags
);
1265 list_for_each_entry(r
, &dep
->pending_list
, list
) {
1271 list_for_each_entry(r
, &dep
->started_list
, list
) {
1276 /* wait until it is processed */
1277 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
1280 dev_err(dwc
->dev
, "request %p was not queued to %s\n",
1287 /* giveback the request */
1288 dwc3_gadget_giveback(dep
, req
, -ECONNRESET
);
1291 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1296 int __dwc3_gadget_ep_set_halt(struct dwc3_ep
*dep
, int value
, int protocol
)
1298 struct dwc3_gadget_ep_cmd_params params
;
1299 struct dwc3
*dwc
= dep
->dwc
;
1302 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1303 dev_err(dwc
->dev
, "%s is of Isochronous type\n", dep
->name
);
1307 memset(¶ms
, 0x00, sizeof(params
));
1310 if (!protocol
&& ((dep
->direction
&& dep
->flags
& DWC3_EP_BUSY
) ||
1311 (!list_empty(&dep
->started_list
) ||
1312 !list_empty(&dep
->pending_list
)))) {
1313 dwc3_trace(trace_dwc3_gadget
,
1314 "%s: pending request, cannot halt",
1319 ret
= dwc3_send_gadget_ep_cmd(dep
, DWC3_DEPCMD_SETSTALL
,
1322 dev_err(dwc
->dev
, "failed to set STALL on %s\n",
1325 dep
->flags
|= DWC3_EP_STALL
;
1328 ret
= dwc3_send_clear_stall_ep_cmd(dep
);
1330 dev_err(dwc
->dev
, "failed to clear STALL on %s\n",
1333 dep
->flags
&= ~(DWC3_EP_STALL
| DWC3_EP_WEDGE
);
1339 static int dwc3_gadget_ep_set_halt(struct usb_ep
*ep
, int value
)
1341 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1342 struct dwc3
*dwc
= dep
->dwc
;
1344 unsigned long flags
;
1348 spin_lock_irqsave(&dwc
->lock
, flags
);
1349 ret
= __dwc3_gadget_ep_set_halt(dep
, value
, false);
1350 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1355 static int dwc3_gadget_ep_set_wedge(struct usb_ep
*ep
)
1357 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1358 struct dwc3
*dwc
= dep
->dwc
;
1359 unsigned long flags
;
1362 spin_lock_irqsave(&dwc
->lock
, flags
);
1363 dep
->flags
|= DWC3_EP_WEDGE
;
1365 if (dep
->number
== 0 || dep
->number
== 1)
1366 ret
= __dwc3_gadget_ep0_set_halt(ep
, 1);
1368 ret
= __dwc3_gadget_ep_set_halt(dep
, 1, false);
1369 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1374 /* -------------------------------------------------------------------------- */
1376 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc
= {
1377 .bLength
= USB_DT_ENDPOINT_SIZE
,
1378 .bDescriptorType
= USB_DT_ENDPOINT
,
1379 .bmAttributes
= USB_ENDPOINT_XFER_CONTROL
,
1382 static const struct usb_ep_ops dwc3_gadget_ep0_ops
= {
1383 .enable
= dwc3_gadget_ep0_enable
,
1384 .disable
= dwc3_gadget_ep0_disable
,
1385 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1386 .free_request
= dwc3_gadget_ep_free_request
,
1387 .queue
= dwc3_gadget_ep0_queue
,
1388 .dequeue
= dwc3_gadget_ep_dequeue
,
1389 .set_halt
= dwc3_gadget_ep0_set_halt
,
1390 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1393 static const struct usb_ep_ops dwc3_gadget_ep_ops
= {
1394 .enable
= dwc3_gadget_ep_enable
,
1395 .disable
= dwc3_gadget_ep_disable
,
1396 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1397 .free_request
= dwc3_gadget_ep_free_request
,
1398 .queue
= dwc3_gadget_ep_queue
,
1399 .dequeue
= dwc3_gadget_ep_dequeue
,
1400 .set_halt
= dwc3_gadget_ep_set_halt
,
1401 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1404 /* -------------------------------------------------------------------------- */
1406 static int dwc3_gadget_get_frame(struct usb_gadget
*g
)
1408 struct dwc3
*dwc
= gadget_to_dwc(g
);
1411 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1412 return DWC3_DSTS_SOFFN(reg
);
1415 static int __dwc3_gadget_wakeup(struct dwc3
*dwc
)
1417 unsigned long timeout
;
1426 * According to the Databook Remote wakeup request should
1427 * be issued only when the device is in early suspend state.
1429 * We can check that via USB Link State bits in DSTS register.
1431 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1433 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
1434 if ((speed
== DWC3_DSTS_SUPERSPEED
) ||
1435 (speed
== DWC3_DSTS_SUPERSPEED_PLUS
)) {
1436 dwc3_trace(trace_dwc3_gadget
, "no wakeup on SuperSpeed\n");
1440 link_state
= DWC3_DSTS_USBLNKST(reg
);
1442 switch (link_state
) {
1443 case DWC3_LINK_STATE_RX_DET
: /* in HS, means Early Suspend */
1444 case DWC3_LINK_STATE_U3
: /* in HS, means SUSPEND */
1447 dwc3_trace(trace_dwc3_gadget
,
1448 "can't wakeup from '%s'\n",
1449 dwc3_gadget_link_string(link_state
));
1453 ret
= dwc3_gadget_set_link_state(dwc
, DWC3_LINK_STATE_RECOV
);
1455 dev_err(dwc
->dev
, "failed to put link in Recovery\n");
1459 /* Recent versions do this automatically */
1460 if (dwc
->revision
< DWC3_REVISION_194A
) {
1461 /* write zeroes to Link Change Request */
1462 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1463 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
1464 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1467 /* poll until Link State changes to ON */
1468 timeout
= jiffies
+ msecs_to_jiffies(100);
1470 while (!time_after(jiffies
, timeout
)) {
1471 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1473 /* in HS, means ON */
1474 if (DWC3_DSTS_USBLNKST(reg
) == DWC3_LINK_STATE_U0
)
1478 if (DWC3_DSTS_USBLNKST(reg
) != DWC3_LINK_STATE_U0
) {
1479 dev_err(dwc
->dev
, "failed to send remote wakeup\n");
1486 static int dwc3_gadget_wakeup(struct usb_gadget
*g
)
1488 struct dwc3
*dwc
= gadget_to_dwc(g
);
1489 unsigned long flags
;
1492 spin_lock_irqsave(&dwc
->lock
, flags
);
1493 ret
= __dwc3_gadget_wakeup(dwc
);
1494 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1499 static int dwc3_gadget_set_selfpowered(struct usb_gadget
*g
,
1502 struct dwc3
*dwc
= gadget_to_dwc(g
);
1503 unsigned long flags
;
1505 spin_lock_irqsave(&dwc
->lock
, flags
);
1506 g
->is_selfpowered
= !!is_selfpowered
;
1507 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1512 static int dwc3_gadget_run_stop(struct dwc3
*dwc
, int is_on
, int suspend
)
1517 if (pm_runtime_suspended(dwc
->dev
))
1520 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1522 if (dwc
->revision
<= DWC3_REVISION_187A
) {
1523 reg
&= ~DWC3_DCTL_TRGTULST_MASK
;
1524 reg
|= DWC3_DCTL_TRGTULST_RX_DET
;
1527 if (dwc
->revision
>= DWC3_REVISION_194A
)
1528 reg
&= ~DWC3_DCTL_KEEP_CONNECT
;
1529 reg
|= DWC3_DCTL_RUN_STOP
;
1531 if (dwc
->has_hibernation
)
1532 reg
|= DWC3_DCTL_KEEP_CONNECT
;
1534 dwc
->pullups_connected
= true;
1536 reg
&= ~DWC3_DCTL_RUN_STOP
;
1538 if (dwc
->has_hibernation
&& !suspend
)
1539 reg
&= ~DWC3_DCTL_KEEP_CONNECT
;
1541 dwc
->pullups_connected
= false;
1544 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1547 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1549 if (!(reg
& DWC3_DSTS_DEVCTRLHLT
))
1552 if (reg
& DWC3_DSTS_DEVCTRLHLT
)
1561 dwc3_trace(trace_dwc3_gadget
, "gadget %s data soft-%s",
1563 ? dwc
->gadget_driver
->function
: "no-function",
1564 is_on
? "connect" : "disconnect");
1569 static int dwc3_gadget_pullup(struct usb_gadget
*g
, int is_on
)
1571 struct dwc3
*dwc
= gadget_to_dwc(g
);
1572 unsigned long flags
;
1577 spin_lock_irqsave(&dwc
->lock
, flags
);
1578 ret
= dwc3_gadget_run_stop(dwc
, is_on
, false);
1579 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1584 static void dwc3_gadget_enable_irq(struct dwc3
*dwc
)
1588 /* Enable all but Start and End of Frame IRQs */
1589 reg
= (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN
|
1590 DWC3_DEVTEN_EVNTOVERFLOWEN
|
1591 DWC3_DEVTEN_CMDCMPLTEN
|
1592 DWC3_DEVTEN_ERRTICERREN
|
1593 DWC3_DEVTEN_WKUPEVTEN
|
1594 DWC3_DEVTEN_ULSTCNGEN
|
1595 DWC3_DEVTEN_CONNECTDONEEN
|
1596 DWC3_DEVTEN_USBRSTEN
|
1597 DWC3_DEVTEN_DISCONNEVTEN
);
1599 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, reg
);
1602 static void dwc3_gadget_disable_irq(struct dwc3
*dwc
)
1604 /* mask all interrupts */
1605 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, 0x00);
1608 static irqreturn_t
dwc3_interrupt(int irq
, void *_dwc
);
1609 static irqreturn_t
dwc3_thread_interrupt(int irq
, void *_dwc
);
1612 * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG
1613 * dwc: pointer to our context structure
1615 * The following looks like complex but it's actually very simple. In order to
1616 * calculate the number of packets we can burst at once on OUT transfers, we're
1617 * gonna use RxFIFO size.
1619 * To calculate RxFIFO size we need two numbers:
1620 * MDWIDTH = size, in bits, of the internal memory bus
1621 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1623 * Given these two numbers, the formula is simple:
1625 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1627 * 24 bytes is for 3x SETUP packets
1628 * 16 bytes is a clock domain crossing tolerance
1630 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1632 static void dwc3_gadget_setup_nump(struct dwc3
*dwc
)
1639 ram2_depth
= DWC3_GHWPARAMS7_RAM2_DEPTH(dwc
->hwparams
.hwparams7
);
1640 mdwidth
= DWC3_GHWPARAMS0_MDWIDTH(dwc
->hwparams
.hwparams0
);
1642 nump
= ((ram2_depth
* mdwidth
/ 8) - 24 - 16) / 1024;
1643 nump
= min_t(u32
, nump
, 16);
1646 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
1647 reg
&= ~DWC3_DCFG_NUMP_MASK
;
1648 reg
|= nump
<< DWC3_DCFG_NUMP_SHIFT
;
1649 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
1652 static int __dwc3_gadget_start(struct dwc3
*dwc
)
1654 struct dwc3_ep
*dep
;
1658 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
1659 reg
&= ~(DWC3_DCFG_SPEED_MASK
);
1662 * WORKAROUND: DWC3 revision < 2.20a have an issue
1663 * which would cause metastability state on Run/Stop
1664 * bit if we try to force the IP to USB2-only mode.
1666 * Because of that, we cannot configure the IP to any
1667 * speed other than the SuperSpeed
1671 * STAR#9000525659: Clock Domain Crossing on DCTL in
1674 if (dwc
->revision
< DWC3_REVISION_220A
) {
1675 reg
|= DWC3_DCFG_SUPERSPEED
;
1677 switch (dwc
->maximum_speed
) {
1679 reg
|= DWC3_DSTS_LOWSPEED
;
1681 case USB_SPEED_FULL
:
1682 reg
|= DWC3_DSTS_FULLSPEED1
;
1684 case USB_SPEED_HIGH
:
1685 reg
|= DWC3_DSTS_HIGHSPEED
;
1687 case USB_SPEED_SUPER_PLUS
:
1688 reg
|= DWC3_DSTS_SUPERSPEED_PLUS
;
1691 dev_err(dwc
->dev
, "invalid dwc->maximum_speed (%d)\n",
1692 dwc
->maximum_speed
);
1694 case USB_SPEED_SUPER
:
1695 reg
|= DWC3_DCFG_SUPERSPEED
;
1699 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
1702 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1703 * field instead of letting dwc3 itself calculate that automatically.
1705 * This way, we maximize the chances that we'll be able to get several
1706 * bursts of data without going through any sort of endpoint throttling.
1708 reg
= dwc3_readl(dwc
->regs
, DWC3_GRXTHRCFG
);
1709 reg
&= ~DWC3_GRXTHRCFG_PKTCNTSEL
;
1710 dwc3_writel(dwc
->regs
, DWC3_GRXTHRCFG
, reg
);
1712 dwc3_gadget_setup_nump(dwc
);
1714 /* Start with SuperSpeed Default */
1715 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
1718 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, false,
1721 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1726 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, false,
1729 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1733 /* begin to receive SETUP packets */
1734 dwc
->ep0state
= EP0_SETUP_PHASE
;
1735 dwc3_ep0_out_start(dwc
);
1737 dwc3_gadget_enable_irq(dwc
);
1742 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
1748 static int dwc3_gadget_start(struct usb_gadget
*g
,
1749 struct usb_gadget_driver
*driver
)
1751 struct dwc3
*dwc
= gadget_to_dwc(g
);
1752 unsigned long flags
;
1756 irq
= platform_get_irq(to_platform_device(dwc
->dev
), 0);
1757 ret
= request_threaded_irq(irq
, dwc3_interrupt
, dwc3_thread_interrupt
,
1758 IRQF_SHARED
, "dwc3", dwc
->ev_buf
);
1760 dev_err(dwc
->dev
, "failed to request irq #%d --> %d\n",
1764 dwc
->irq_gadget
= irq
;
1766 spin_lock_irqsave(&dwc
->lock
, flags
);
1767 if (dwc
->gadget_driver
) {
1768 dev_err(dwc
->dev
, "%s is already bound to %s\n",
1770 dwc
->gadget_driver
->driver
.name
);
1775 dwc
->gadget_driver
= driver
;
1777 if (pm_runtime_active(dwc
->dev
))
1778 __dwc3_gadget_start(dwc
);
1780 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1785 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1792 static void __dwc3_gadget_stop(struct dwc3
*dwc
)
1794 dwc3_gadget_disable_irq(dwc
);
1795 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
1796 __dwc3_gadget_ep_disable(dwc
->eps
[1]);
1799 static int dwc3_gadget_stop(struct usb_gadget
*g
)
1801 struct dwc3
*dwc
= gadget_to_dwc(g
);
1802 unsigned long flags
;
1804 spin_lock_irqsave(&dwc
->lock
, flags
);
1805 __dwc3_gadget_stop(dwc
);
1806 dwc
->gadget_driver
= NULL
;
1807 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1809 free_irq(dwc
->irq_gadget
, dwc
->ev_buf
);
1814 static const struct usb_gadget_ops dwc3_gadget_ops
= {
1815 .get_frame
= dwc3_gadget_get_frame
,
1816 .wakeup
= dwc3_gadget_wakeup
,
1817 .set_selfpowered
= dwc3_gadget_set_selfpowered
,
1818 .pullup
= dwc3_gadget_pullup
,
1819 .udc_start
= dwc3_gadget_start
,
1820 .udc_stop
= dwc3_gadget_stop
,
1823 /* -------------------------------------------------------------------------- */
1825 static int dwc3_gadget_init_hw_endpoints(struct dwc3
*dwc
,
1826 u8 num
, u32 direction
)
1828 struct dwc3_ep
*dep
;
1831 for (i
= 0; i
< num
; i
++) {
1832 u8 epnum
= (i
<< 1) | (!!direction
);
1834 dep
= kzalloc(sizeof(*dep
), GFP_KERNEL
);
1839 dep
->number
= epnum
;
1840 dep
->direction
= !!direction
;
1841 dep
->regs
= dwc
->regs
+ DWC3_DEP_BASE(epnum
);
1842 dwc
->eps
[epnum
] = dep
;
1844 snprintf(dep
->name
, sizeof(dep
->name
), "ep%d%s", epnum
>> 1,
1845 (epnum
& 1) ? "in" : "out");
1847 dep
->endpoint
.name
= dep
->name
;
1848 spin_lock_init(&dep
->lock
);
1850 dwc3_trace(trace_dwc3_gadget
, "initializing %s", dep
->name
);
1852 if (epnum
== 0 || epnum
== 1) {
1853 usb_ep_set_maxpacket_limit(&dep
->endpoint
, 512);
1854 dep
->endpoint
.maxburst
= 1;
1855 dep
->endpoint
.ops
= &dwc3_gadget_ep0_ops
;
1857 dwc
->gadget
.ep0
= &dep
->endpoint
;
1861 usb_ep_set_maxpacket_limit(&dep
->endpoint
, 1024);
1862 dep
->endpoint
.max_streams
= 15;
1863 dep
->endpoint
.ops
= &dwc3_gadget_ep_ops
;
1864 list_add_tail(&dep
->endpoint
.ep_list
,
1865 &dwc
->gadget
.ep_list
);
1867 ret
= dwc3_alloc_trb_pool(dep
);
1872 if (epnum
== 0 || epnum
== 1) {
1873 dep
->endpoint
.caps
.type_control
= true;
1875 dep
->endpoint
.caps
.type_iso
= true;
1876 dep
->endpoint
.caps
.type_bulk
= true;
1877 dep
->endpoint
.caps
.type_int
= true;
1880 dep
->endpoint
.caps
.dir_in
= !!direction
;
1881 dep
->endpoint
.caps
.dir_out
= !direction
;
1883 INIT_LIST_HEAD(&dep
->pending_list
);
1884 INIT_LIST_HEAD(&dep
->started_list
);
1890 static int dwc3_gadget_init_endpoints(struct dwc3
*dwc
)
1894 INIT_LIST_HEAD(&dwc
->gadget
.ep_list
);
1896 ret
= dwc3_gadget_init_hw_endpoints(dwc
, dwc
->num_out_eps
, 0);
1898 dwc3_trace(trace_dwc3_gadget
,
1899 "failed to allocate OUT endpoints");
1903 ret
= dwc3_gadget_init_hw_endpoints(dwc
, dwc
->num_in_eps
, 1);
1905 dwc3_trace(trace_dwc3_gadget
,
1906 "failed to allocate IN endpoints");
1913 static void dwc3_gadget_free_endpoints(struct dwc3
*dwc
)
1915 struct dwc3_ep
*dep
;
1918 for (epnum
= 0; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
1919 dep
= dwc
->eps
[epnum
];
1923 * Physical endpoints 0 and 1 are special; they form the
1924 * bi-directional USB endpoint 0.
1926 * For those two physical endpoints, we don't allocate a TRB
1927 * pool nor do we add them the endpoints list. Due to that, we
1928 * shouldn't do these two operations otherwise we would end up
1929 * with all sorts of bugs when removing dwc3.ko.
1931 if (epnum
!= 0 && epnum
!= 1) {
1932 dwc3_free_trb_pool(dep
);
1933 list_del(&dep
->endpoint
.ep_list
);
1940 /* -------------------------------------------------------------------------- */
1942 static int __dwc3_cleanup_done_trbs(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
1943 struct dwc3_request
*req
, struct dwc3_trb
*trb
,
1944 const struct dwc3_event_depevt
*event
, int status
)
1947 unsigned int s_pkt
= 0;
1948 unsigned int trb_status
;
1950 trace_dwc3_complete_trb(dep
, trb
);
1952 if ((trb
->ctrl
& DWC3_TRB_CTRL_HWO
) && status
!= -ESHUTDOWN
)
1954 * We continue despite the error. There is not much we
1955 * can do. If we don't clean it up we loop forever. If
1956 * we skip the TRB then it gets overwritten after a
1957 * while since we use them in a ring buffer. A BUG()
1958 * would help. Lets hope that if this occurs, someone
1959 * fixes the root cause instead of looking away :)
1961 dev_err(dwc
->dev
, "%s's TRB (%p) still owned by HW\n",
1963 count
= trb
->size
& DWC3_TRB_SIZE_MASK
;
1965 if (dep
->direction
) {
1967 trb_status
= DWC3_TRB_SIZE_TRBSTS(trb
->size
);
1968 if (trb_status
== DWC3_TRBSTS_MISSED_ISOC
) {
1969 dwc3_trace(trace_dwc3_gadget
,
1970 "%s: incomplete IN transfer\n",
1973 * If missed isoc occurred and there is
1974 * no request queued then issue END
1975 * TRANSFER, so that core generates
1976 * next xfernotready and we will issue
1977 * a fresh START TRANSFER.
1978 * If there are still queued request
1979 * then wait, do not issue either END
1980 * or UPDATE TRANSFER, just attach next
1981 * request in pending_list during
1982 * giveback.If any future queued request
1983 * is successfully transferred then we
1984 * will issue UPDATE TRANSFER for all
1985 * request in the pending_list.
1987 dep
->flags
|= DWC3_EP_MISSED_ISOC
;
1989 dev_err(dwc
->dev
, "incomplete IN transfer %s\n",
1991 status
= -ECONNRESET
;
1994 dep
->flags
&= ~DWC3_EP_MISSED_ISOC
;
1997 if (count
&& (event
->status
& DEPEVT_STATUS_SHORT
))
2002 * We assume here we will always receive the entire data block
2003 * which we should receive. Meaning, if we program RX to
2004 * receive 4K but we receive only 2K, we assume that's all we
2005 * should receive and we simply bounce the request back to the
2006 * gadget driver for further processing.
2008 req
->request
.actual
+= req
->request
.length
- count
;
2011 if ((event
->status
& DEPEVT_STATUS_LST
) &&
2012 (trb
->ctrl
& (DWC3_TRB_CTRL_LST
|
2013 DWC3_TRB_CTRL_HWO
)))
2015 if ((event
->status
& DEPEVT_STATUS_IOC
) &&
2016 (trb
->ctrl
& DWC3_TRB_CTRL_IOC
))
2021 static int dwc3_cleanup_done_reqs(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
2022 const struct dwc3_event_depevt
*event
, int status
)
2024 struct dwc3_request
*req
;
2025 struct dwc3_trb
*trb
;
2031 req
= next_request(&dep
->started_list
);
2032 if (WARN_ON_ONCE(!req
))
2037 slot
= req
->first_trb_index
+ i
;
2038 if (slot
== DWC3_TRB_NUM
- 1)
2040 slot
%= DWC3_TRB_NUM
;
2041 trb
= &dep
->trb_pool
[slot
];
2043 ret
= __dwc3_cleanup_done_trbs(dwc
, dep
, req
, trb
,
2047 } while (++i
< req
->request
.num_mapped_sgs
);
2049 dwc3_gadget_giveback(dep
, req
, status
);
2056 * Our endpoint might get disabled by another thread during
2057 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2058 * early on so DWC3_EP_BUSY flag gets cleared
2060 if (!dep
->endpoint
.desc
)
2063 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) &&
2064 list_empty(&dep
->started_list
)) {
2065 if (list_empty(&dep
->pending_list
)) {
2067 * If there is no entry in request list then do
2068 * not issue END TRANSFER now. Just set PENDING
2069 * flag, so that END TRANSFER is issued when an
2070 * entry is added into request list.
2072 dep
->flags
= DWC3_EP_PENDING_REQUEST
;
2074 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
2075 dep
->flags
= DWC3_EP_ENABLED
;
2080 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
2081 if ((event
->status
& DEPEVT_STATUS_IOC
) &&
2082 (trb
->ctrl
& DWC3_TRB_CTRL_IOC
))
2087 static void dwc3_endpoint_transfer_complete(struct dwc3
*dwc
,
2088 struct dwc3_ep
*dep
, const struct dwc3_event_depevt
*event
)
2090 unsigned status
= 0;
2092 u32 is_xfer_complete
;
2094 is_xfer_complete
= (event
->endpoint_event
== DWC3_DEPEVT_XFERCOMPLETE
);
2096 if (event
->status
& DEPEVT_STATUS_BUSERR
)
2097 status
= -ECONNRESET
;
2099 clean_busy
= dwc3_cleanup_done_reqs(dwc
, dep
, event
, status
);
2100 if (clean_busy
&& (!dep
->endpoint
.desc
|| is_xfer_complete
||
2101 usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)))
2102 dep
->flags
&= ~DWC3_EP_BUSY
;
2105 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2106 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2108 if (dwc
->revision
< DWC3_REVISION_183A
) {
2112 for (i
= 0; i
< DWC3_ENDPOINTS_NUM
; i
++) {
2115 if (!(dep
->flags
& DWC3_EP_ENABLED
))
2118 if (!list_empty(&dep
->started_list
))
2122 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2124 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2130 * Our endpoint might get disabled by another thread during
2131 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2132 * early on so DWC3_EP_BUSY flag gets cleared
2134 if (!dep
->endpoint
.desc
)
2137 if (!usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
2140 ret
= __dwc3_gadget_kick_transfer(dep
, 0);
2141 if (!ret
|| ret
== -EBUSY
)
2146 static void dwc3_endpoint_interrupt(struct dwc3
*dwc
,
2147 const struct dwc3_event_depevt
*event
)
2149 struct dwc3_ep
*dep
;
2150 u8 epnum
= event
->endpoint_number
;
2152 dep
= dwc
->eps
[epnum
];
2154 if (!(dep
->flags
& DWC3_EP_ENABLED
))
2157 if (epnum
== 0 || epnum
== 1) {
2158 dwc3_ep0_interrupt(dwc
, event
);
2162 switch (event
->endpoint_event
) {
2163 case DWC3_DEPEVT_XFERCOMPLETE
:
2164 dep
->resource_index
= 0;
2166 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
2167 dwc3_trace(trace_dwc3_gadget
,
2168 "%s is an Isochronous endpoint\n",
2173 dwc3_endpoint_transfer_complete(dwc
, dep
, event
);
2175 case DWC3_DEPEVT_XFERINPROGRESS
:
2176 dwc3_endpoint_transfer_complete(dwc
, dep
, event
);
2178 case DWC3_DEPEVT_XFERNOTREADY
:
2179 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
2180 dwc3_gadget_start_isoc(dwc
, dep
, event
);
2185 active
= event
->status
& DEPEVT_STATUS_TRANSFER_ACTIVE
;
2187 dwc3_trace(trace_dwc3_gadget
, "%s: reason %s",
2188 dep
->name
, active
? "Transfer Active"
2189 : "Transfer Not Active");
2191 ret
= __dwc3_gadget_kick_transfer(dep
, 0);
2192 if (!ret
|| ret
== -EBUSY
)
2195 dwc3_trace(trace_dwc3_gadget
,
2196 "%s: failed to kick transfers\n",
2201 case DWC3_DEPEVT_STREAMEVT
:
2202 if (!usb_endpoint_xfer_bulk(dep
->endpoint
.desc
)) {
2203 dev_err(dwc
->dev
, "Stream event for non-Bulk %s\n",
2208 switch (event
->status
) {
2209 case DEPEVT_STREAMEVT_FOUND
:
2210 dwc3_trace(trace_dwc3_gadget
,
2211 "Stream %d found and started",
2215 case DEPEVT_STREAMEVT_NOTFOUND
:
2218 dwc3_trace(trace_dwc3_gadget
,
2219 "unable to find suitable stream\n");
2222 case DWC3_DEPEVT_RXTXFIFOEVT
:
2223 dwc3_trace(trace_dwc3_gadget
, "%s FIFO Overrun\n", dep
->name
);
2225 case DWC3_DEPEVT_EPCMDCMPLT
:
2226 dwc3_trace(trace_dwc3_gadget
, "Endpoint Command Complete");
2231 static void dwc3_disconnect_gadget(struct dwc3
*dwc
)
2233 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->disconnect
) {
2234 spin_unlock(&dwc
->lock
);
2235 dwc
->gadget_driver
->disconnect(&dwc
->gadget
);
2236 spin_lock(&dwc
->lock
);
2240 static void dwc3_suspend_gadget(struct dwc3
*dwc
)
2242 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->suspend
) {
2243 spin_unlock(&dwc
->lock
);
2244 dwc
->gadget_driver
->suspend(&dwc
->gadget
);
2245 spin_lock(&dwc
->lock
);
2249 static void dwc3_resume_gadget(struct dwc3
*dwc
)
2251 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->resume
) {
2252 spin_unlock(&dwc
->lock
);
2253 dwc
->gadget_driver
->resume(&dwc
->gadget
);
2254 spin_lock(&dwc
->lock
);
2258 static void dwc3_reset_gadget(struct dwc3
*dwc
)
2260 if (!dwc
->gadget_driver
)
2263 if (dwc
->gadget
.speed
!= USB_SPEED_UNKNOWN
) {
2264 spin_unlock(&dwc
->lock
);
2265 usb_gadget_udc_reset(&dwc
->gadget
, dwc
->gadget_driver
);
2266 spin_lock(&dwc
->lock
);
2270 static void dwc3_stop_active_transfer(struct dwc3
*dwc
, u32 epnum
, bool force
)
2272 struct dwc3_ep
*dep
;
2273 struct dwc3_gadget_ep_cmd_params params
;
2277 dep
= dwc
->eps
[epnum
];
2279 if (!dep
->resource_index
)
2283 * NOTICE: We are violating what the Databook says about the
2284 * EndTransfer command. Ideally we would _always_ wait for the
2285 * EndTransfer Command Completion IRQ, but that's causing too
2286 * much trouble synchronizing between us and gadget driver.
2288 * We have discussed this with the IP Provider and it was
2289 * suggested to giveback all requests here, but give HW some
2290 * extra time to synchronize with the interconnect. We're using
2291 * an arbitrary 100us delay for that.
2293 * Note also that a similar handling was tested by Synopsys
2294 * (thanks a lot Paul) and nothing bad has come out of it.
2295 * In short, what we're doing is:
2297 * - Issue EndTransfer WITH CMDIOC bit set
2301 cmd
= DWC3_DEPCMD_ENDTRANSFER
;
2302 cmd
|= force
? DWC3_DEPCMD_HIPRI_FORCERM
: 0;
2303 cmd
|= DWC3_DEPCMD_CMDIOC
;
2304 cmd
|= DWC3_DEPCMD_PARAM(dep
->resource_index
);
2305 memset(¶ms
, 0, sizeof(params
));
2306 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
2308 dep
->resource_index
= 0;
2309 dep
->flags
&= ~DWC3_EP_BUSY
;
2313 static void dwc3_stop_active_transfers(struct dwc3
*dwc
)
2317 for (epnum
= 2; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
2318 struct dwc3_ep
*dep
;
2320 dep
= dwc
->eps
[epnum
];
2324 if (!(dep
->flags
& DWC3_EP_ENABLED
))
2327 dwc3_remove_requests(dwc
, dep
);
2331 static void dwc3_clear_stall_all_ep(struct dwc3
*dwc
)
2335 for (epnum
= 1; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
2336 struct dwc3_ep
*dep
;
2339 dep
= dwc
->eps
[epnum
];
2343 if (!(dep
->flags
& DWC3_EP_STALL
))
2346 dep
->flags
&= ~DWC3_EP_STALL
;
2348 ret
= dwc3_send_clear_stall_ep_cmd(dep
);
2353 static void dwc3_gadget_disconnect_interrupt(struct dwc3
*dwc
)
2357 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2358 reg
&= ~DWC3_DCTL_INITU1ENA
;
2359 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2361 reg
&= ~DWC3_DCTL_INITU2ENA
;
2362 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2364 dwc3_disconnect_gadget(dwc
);
2366 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2367 dwc
->setup_packet_pending
= false;
2368 usb_gadget_set_state(&dwc
->gadget
, USB_STATE_NOTATTACHED
);
2370 dwc
->connected
= false;
2373 static void dwc3_gadget_reset_interrupt(struct dwc3
*dwc
)
2377 dwc
->connected
= true;
2380 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2381 * would cause a missing Disconnect Event if there's a
2382 * pending Setup Packet in the FIFO.
2384 * There's no suggested workaround on the official Bug
2385 * report, which states that "unless the driver/application
2386 * is doing any special handling of a disconnect event,
2387 * there is no functional issue".
2389 * Unfortunately, it turns out that we _do_ some special
2390 * handling of a disconnect event, namely complete all
2391 * pending transfers, notify gadget driver of the
2392 * disconnection, and so on.
2394 * Our suggested workaround is to follow the Disconnect
2395 * Event steps here, instead, based on a setup_packet_pending
2396 * flag. Such flag gets set whenever we have a SETUP_PENDING
2397 * status for EP0 TRBs and gets cleared on XferComplete for the
2402 * STAR#9000466709: RTL: Device : Disconnect event not
2403 * generated if setup packet pending in FIFO
2405 if (dwc
->revision
< DWC3_REVISION_188A
) {
2406 if (dwc
->setup_packet_pending
)
2407 dwc3_gadget_disconnect_interrupt(dwc
);
2410 dwc3_reset_gadget(dwc
);
2412 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2413 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
2414 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2415 dwc
->test_mode
= false;
2417 dwc3_stop_active_transfers(dwc
);
2418 dwc3_clear_stall_all_ep(dwc
);
2420 /* Reset device address to zero */
2421 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2422 reg
&= ~(DWC3_DCFG_DEVADDR_MASK
);
2423 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2426 static void dwc3_update_ram_clk_sel(struct dwc3
*dwc
, u32 speed
)
2429 u32 usb30_clock
= DWC3_GCTL_CLK_BUS
;
2432 * We change the clock only at SS but I dunno why I would want to do
2433 * this. Maybe it becomes part of the power saving plan.
2436 if ((speed
!= DWC3_DSTS_SUPERSPEED
) &&
2437 (speed
!= DWC3_DSTS_SUPERSPEED_PLUS
))
2441 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2442 * each time on Connect Done.
2447 reg
= dwc3_readl(dwc
->regs
, DWC3_GCTL
);
2448 reg
|= DWC3_GCTL_RAMCLKSEL(usb30_clock
);
2449 dwc3_writel(dwc
->regs
, DWC3_GCTL
, reg
);
2452 static void dwc3_gadget_conndone_interrupt(struct dwc3
*dwc
)
2454 struct dwc3_ep
*dep
;
2459 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
2460 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
2463 dwc3_update_ram_clk_sel(dwc
, speed
);
2466 case DWC3_DCFG_SUPERSPEED_PLUS
:
2467 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
2468 dwc
->gadget
.ep0
->maxpacket
= 512;
2469 dwc
->gadget
.speed
= USB_SPEED_SUPER_PLUS
;
2471 case DWC3_DCFG_SUPERSPEED
:
2473 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2474 * would cause a missing USB3 Reset event.
2476 * In such situations, we should force a USB3 Reset
2477 * event by calling our dwc3_gadget_reset_interrupt()
2482 * STAR#9000483510: RTL: SS : USB3 reset event may
2483 * not be generated always when the link enters poll
2485 if (dwc
->revision
< DWC3_REVISION_190A
)
2486 dwc3_gadget_reset_interrupt(dwc
);
2488 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
2489 dwc
->gadget
.ep0
->maxpacket
= 512;
2490 dwc
->gadget
.speed
= USB_SPEED_SUPER
;
2492 case DWC3_DCFG_HIGHSPEED
:
2493 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2494 dwc
->gadget
.ep0
->maxpacket
= 64;
2495 dwc
->gadget
.speed
= USB_SPEED_HIGH
;
2497 case DWC3_DCFG_FULLSPEED2
:
2498 case DWC3_DCFG_FULLSPEED1
:
2499 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2500 dwc
->gadget
.ep0
->maxpacket
= 64;
2501 dwc
->gadget
.speed
= USB_SPEED_FULL
;
2503 case DWC3_DCFG_LOWSPEED
:
2504 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(8);
2505 dwc
->gadget
.ep0
->maxpacket
= 8;
2506 dwc
->gadget
.speed
= USB_SPEED_LOW
;
2510 /* Enable USB2 LPM Capability */
2512 if ((dwc
->revision
> DWC3_REVISION_194A
) &&
2513 (speed
!= DWC3_DCFG_SUPERSPEED
) &&
2514 (speed
!= DWC3_DCFG_SUPERSPEED_PLUS
)) {
2515 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2516 reg
|= DWC3_DCFG_LPM_CAP
;
2517 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2519 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2520 reg
&= ~(DWC3_DCTL_HIRD_THRES_MASK
| DWC3_DCTL_L1_HIBER_EN
);
2522 reg
|= DWC3_DCTL_HIRD_THRES(dwc
->hird_threshold
);
2525 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2526 * DCFG.LPMCap is set, core responses with an ACK and the
2527 * BESL value in the LPM token is less than or equal to LPM
2530 WARN_ONCE(dwc
->revision
< DWC3_REVISION_240A
2531 && dwc
->has_lpm_erratum
,
2532 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2534 if (dwc
->has_lpm_erratum
&& dwc
->revision
>= DWC3_REVISION_240A
)
2535 reg
|= DWC3_DCTL_LPM_ERRATA(dwc
->lpm_nyet_threshold
);
2537 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2539 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2540 reg
&= ~DWC3_DCTL_HIRD_THRES_MASK
;
2541 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2545 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, true,
2548 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2553 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, true,
2556 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2561 * Configure PHY via GUSB3PIPECTLn if required.
2563 * Update GTXFIFOSIZn
2565 * In both cases reset values should be sufficient.
2569 static void dwc3_gadget_wakeup_interrupt(struct dwc3
*dwc
)
2572 * TODO take core out of low power mode when that's
2576 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->resume
) {
2577 spin_unlock(&dwc
->lock
);
2578 dwc
->gadget_driver
->resume(&dwc
->gadget
);
2579 spin_lock(&dwc
->lock
);
2583 static void dwc3_gadget_linksts_change_interrupt(struct dwc3
*dwc
,
2584 unsigned int evtinfo
)
2586 enum dwc3_link_state next
= evtinfo
& DWC3_LINK_STATE_MASK
;
2587 unsigned int pwropt
;
2590 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2591 * Hibernation mode enabled which would show up when device detects
2592 * host-initiated U3 exit.
2594 * In that case, device will generate a Link State Change Interrupt
2595 * from U3 to RESUME which is only necessary if Hibernation is
2598 * There are no functional changes due to such spurious event and we
2599 * just need to ignore it.
2603 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2606 pwropt
= DWC3_GHWPARAMS1_EN_PWROPT(dwc
->hwparams
.hwparams1
);
2607 if ((dwc
->revision
< DWC3_REVISION_250A
) &&
2608 (pwropt
!= DWC3_GHWPARAMS1_EN_PWROPT_HIB
)) {
2609 if ((dwc
->link_state
== DWC3_LINK_STATE_U3
) &&
2610 (next
== DWC3_LINK_STATE_RESUME
)) {
2611 dwc3_trace(trace_dwc3_gadget
,
2612 "ignoring transition U3 -> Resume");
2618 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2619 * on the link partner, the USB session might do multiple entry/exit
2620 * of low power states before a transfer takes place.
2622 * Due to this problem, we might experience lower throughput. The
2623 * suggested workaround is to disable DCTL[12:9] bits if we're
2624 * transitioning from U1/U2 to U0 and enable those bits again
2625 * after a transfer completes and there are no pending transfers
2626 * on any of the enabled endpoints.
2628 * This is the first half of that workaround.
2632 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2633 * core send LGO_Ux entering U0
2635 if (dwc
->revision
< DWC3_REVISION_183A
) {
2636 if (next
== DWC3_LINK_STATE_U0
) {
2640 switch (dwc
->link_state
) {
2641 case DWC3_LINK_STATE_U1
:
2642 case DWC3_LINK_STATE_U2
:
2643 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2644 u1u2
= reg
& (DWC3_DCTL_INITU2ENA
2645 | DWC3_DCTL_ACCEPTU2ENA
2646 | DWC3_DCTL_INITU1ENA
2647 | DWC3_DCTL_ACCEPTU1ENA
);
2650 dwc
->u1u2
= reg
& u1u2
;
2654 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2664 case DWC3_LINK_STATE_U1
:
2665 if (dwc
->speed
== USB_SPEED_SUPER
)
2666 dwc3_suspend_gadget(dwc
);
2668 case DWC3_LINK_STATE_U2
:
2669 case DWC3_LINK_STATE_U3
:
2670 dwc3_suspend_gadget(dwc
);
2672 case DWC3_LINK_STATE_RESUME
:
2673 dwc3_resume_gadget(dwc
);
2680 dwc
->link_state
= next
;
2683 static void dwc3_gadget_hibernation_interrupt(struct dwc3
*dwc
,
2684 unsigned int evtinfo
)
2686 unsigned int is_ss
= evtinfo
& BIT(4);
2689 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2690 * have a known issue which can cause USB CV TD.9.23 to fail
2693 * Because of this issue, core could generate bogus hibernation
2694 * events which SW needs to ignore.
2698 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2699 * Device Fallback from SuperSpeed
2701 if (is_ss
^ (dwc
->speed
== USB_SPEED_SUPER
))
2704 /* enter hibernation here */
2707 static void dwc3_gadget_interrupt(struct dwc3
*dwc
,
2708 const struct dwc3_event_devt
*event
)
2710 switch (event
->type
) {
2711 case DWC3_DEVICE_EVENT_DISCONNECT
:
2712 dwc3_gadget_disconnect_interrupt(dwc
);
2714 case DWC3_DEVICE_EVENT_RESET
:
2715 dwc3_gadget_reset_interrupt(dwc
);
2717 case DWC3_DEVICE_EVENT_CONNECT_DONE
:
2718 dwc3_gadget_conndone_interrupt(dwc
);
2720 case DWC3_DEVICE_EVENT_WAKEUP
:
2721 dwc3_gadget_wakeup_interrupt(dwc
);
2723 case DWC3_DEVICE_EVENT_HIBER_REQ
:
2724 if (dev_WARN_ONCE(dwc
->dev
, !dwc
->has_hibernation
,
2725 "unexpected hibernation event\n"))
2728 dwc3_gadget_hibernation_interrupt(dwc
, event
->event_info
);
2730 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE
:
2731 dwc3_gadget_linksts_change_interrupt(dwc
, event
->event_info
);
2733 case DWC3_DEVICE_EVENT_EOPF
:
2734 dwc3_trace(trace_dwc3_gadget
, "End of Periodic Frame");
2736 case DWC3_DEVICE_EVENT_SOF
:
2737 dwc3_trace(trace_dwc3_gadget
, "Start of Periodic Frame");
2739 case DWC3_DEVICE_EVENT_ERRATIC_ERROR
:
2740 dwc3_trace(trace_dwc3_gadget
, "Erratic Error");
2742 case DWC3_DEVICE_EVENT_CMD_CMPL
:
2743 dwc3_trace(trace_dwc3_gadget
, "Command Complete");
2745 case DWC3_DEVICE_EVENT_OVERFLOW
:
2746 dwc3_trace(trace_dwc3_gadget
, "Overflow");
2749 dev_WARN(dwc
->dev
, "UNKNOWN IRQ %d\n", event
->type
);
2753 static void dwc3_process_event_entry(struct dwc3
*dwc
,
2754 const union dwc3_event
*event
)
2756 trace_dwc3_event(event
->raw
);
2758 /* Endpoint IRQ, handle it and return early */
2759 if (event
->type
.is_devspec
== 0) {
2761 return dwc3_endpoint_interrupt(dwc
, &event
->depevt
);
2764 switch (event
->type
.type
) {
2765 case DWC3_EVENT_TYPE_DEV
:
2766 dwc3_gadget_interrupt(dwc
, &event
->devt
);
2768 /* REVISIT what to do with Carkit and I2C events ? */
2770 dev_err(dwc
->dev
, "UNKNOWN IRQ type %d\n", event
->raw
);
2774 static irqreturn_t
dwc3_process_event_buf(struct dwc3_event_buffer
*evt
)
2776 struct dwc3
*dwc
= evt
->dwc
;
2777 irqreturn_t ret
= IRQ_NONE
;
2783 if (!(evt
->flags
& DWC3_EVENT_PENDING
))
2787 union dwc3_event event
;
2789 event
.raw
= *(u32
*) (evt
->buf
+ evt
->lpos
);
2791 dwc3_process_event_entry(dwc
, &event
);
2794 * FIXME we wrap around correctly to the next entry as
2795 * almost all entries are 4 bytes in size. There is one
2796 * entry which has 12 bytes which is a regular entry
2797 * followed by 8 bytes data. ATM I don't know how
2798 * things are organized if we get next to the a
2799 * boundary so I worry about that once we try to handle
2802 evt
->lpos
= (evt
->lpos
+ 4) % DWC3_EVENT_BUFFERS_SIZE
;
2805 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(0), 4);
2809 evt
->flags
&= ~DWC3_EVENT_PENDING
;
2812 /* Unmask interrupt */
2813 reg
= dwc3_readl(dwc
->regs
, DWC3_GEVNTSIZ(0));
2814 reg
&= ~DWC3_GEVNTSIZ_INTMASK
;
2815 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(0), reg
);
2820 static irqreturn_t
dwc3_thread_interrupt(int irq
, void *_evt
)
2822 struct dwc3_event_buffer
*evt
= _evt
;
2823 struct dwc3
*dwc
= evt
->dwc
;
2824 unsigned long flags
;
2825 irqreturn_t ret
= IRQ_NONE
;
2827 spin_lock_irqsave(&dwc
->lock
, flags
);
2828 ret
= dwc3_process_event_buf(evt
);
2829 spin_unlock_irqrestore(&dwc
->lock
, flags
);
2834 static irqreturn_t
dwc3_check_event_buf(struct dwc3_event_buffer
*evt
)
2836 struct dwc3
*dwc
= evt
->dwc
;
2840 if (pm_runtime_suspended(dwc
->dev
)) {
2841 pm_runtime_get(dwc
->dev
);
2842 disable_irq_nosync(dwc
->irq_gadget
);
2843 dwc
->pending_events
= true;
2847 count
= dwc3_readl(dwc
->regs
, DWC3_GEVNTCOUNT(0));
2848 count
&= DWC3_GEVNTCOUNT_MASK
;
2853 evt
->flags
|= DWC3_EVENT_PENDING
;
2855 /* Mask interrupt */
2856 reg
= dwc3_readl(dwc
->regs
, DWC3_GEVNTSIZ(0));
2857 reg
|= DWC3_GEVNTSIZ_INTMASK
;
2858 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(0), reg
);
2860 return IRQ_WAKE_THREAD
;
2863 static irqreturn_t
dwc3_interrupt(int irq
, void *_evt
)
2865 struct dwc3_event_buffer
*evt
= _evt
;
2867 return dwc3_check_event_buf(evt
);
2871 * dwc3_gadget_init - Initializes gadget related registers
2872 * @dwc: pointer to our controller context structure
2874 * Returns 0 on success otherwise negative errno.
2876 int dwc3_gadget_init(struct dwc3
*dwc
)
2880 dwc
->ctrl_req
= dma_alloc_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
2881 &dwc
->ctrl_req_addr
, GFP_KERNEL
);
2882 if (!dwc
->ctrl_req
) {
2883 dev_err(dwc
->dev
, "failed to allocate ctrl request\n");
2888 dwc
->ep0_trb
= dma_alloc_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
) * 2,
2889 &dwc
->ep0_trb_addr
, GFP_KERNEL
);
2890 if (!dwc
->ep0_trb
) {
2891 dev_err(dwc
->dev
, "failed to allocate ep0 trb\n");
2896 dwc
->setup_buf
= kzalloc(DWC3_EP0_BOUNCE_SIZE
, GFP_KERNEL
);
2897 if (!dwc
->setup_buf
) {
2902 dwc
->ep0_bounce
= dma_alloc_coherent(dwc
->dev
,
2903 DWC3_EP0_BOUNCE_SIZE
, &dwc
->ep0_bounce_addr
,
2905 if (!dwc
->ep0_bounce
) {
2906 dev_err(dwc
->dev
, "failed to allocate ep0 bounce buffer\n");
2911 dwc
->zlp_buf
= kzalloc(DWC3_ZLP_BUF_SIZE
, GFP_KERNEL
);
2912 if (!dwc
->zlp_buf
) {
2917 dwc
->gadget
.ops
= &dwc3_gadget_ops
;
2918 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2919 dwc
->gadget
.sg_supported
= true;
2920 dwc
->gadget
.name
= "dwc3-gadget";
2921 dwc
->gadget
.is_otg
= dwc
->dr_mode
== USB_DR_MODE_OTG
;
2924 * FIXME We might be setting max_speed to <SUPER, however versions
2925 * <2.20a of dwc3 have an issue with metastability (documented
2926 * elsewhere in this driver) which tells us we can't set max speed to
2927 * anything lower than SUPER.
2929 * Because gadget.max_speed is only used by composite.c and function
2930 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2931 * to happen so we avoid sending SuperSpeed Capability descriptor
2932 * together with our BOS descriptor as that could confuse host into
2933 * thinking we can handle super speed.
2935 * Note that, in fact, we won't even support GetBOS requests when speed
2936 * is less than super speed because we don't have means, yet, to tell
2937 * composite.c that we are USB 2.0 + LPM ECN.
2939 if (dwc
->revision
< DWC3_REVISION_220A
)
2940 dwc3_trace(trace_dwc3_gadget
,
2941 "Changing max_speed on rev %08x\n",
2944 dwc
->gadget
.max_speed
= dwc
->maximum_speed
;
2947 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2950 dwc
->gadget
.quirk_ep_out_aligned_size
= true;
2953 * REVISIT: Here we should clear all pending IRQs to be
2954 * sure we're starting from a well known location.
2957 ret
= dwc3_gadget_init_endpoints(dwc
);
2961 ret
= usb_add_gadget_udc(dwc
->dev
, &dwc
->gadget
);
2963 dev_err(dwc
->dev
, "failed to register udc\n");
2970 kfree(dwc
->zlp_buf
);
2973 dwc3_gadget_free_endpoints(dwc
);
2974 dma_free_coherent(dwc
->dev
, DWC3_EP0_BOUNCE_SIZE
,
2975 dwc
->ep0_bounce
, dwc
->ep0_bounce_addr
);
2978 kfree(dwc
->setup_buf
);
2981 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
),
2982 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
2985 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
2986 dwc
->ctrl_req
, dwc
->ctrl_req_addr
);
2992 /* -------------------------------------------------------------------------- */
2994 void dwc3_gadget_exit(struct dwc3
*dwc
)
2996 usb_del_gadget_udc(&dwc
->gadget
);
2998 dwc3_gadget_free_endpoints(dwc
);
3000 dma_free_coherent(dwc
->dev
, DWC3_EP0_BOUNCE_SIZE
,
3001 dwc
->ep0_bounce
, dwc
->ep0_bounce_addr
);
3003 kfree(dwc
->setup_buf
);
3004 kfree(dwc
->zlp_buf
);
3006 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
),
3007 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
3009 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
3010 dwc
->ctrl_req
, dwc
->ctrl_req_addr
);
3013 int dwc3_gadget_suspend(struct dwc3
*dwc
)
3017 if (!dwc
->gadget_driver
)
3020 ret
= dwc3_gadget_run_stop(dwc
, false, false);
3024 dwc3_disconnect_gadget(dwc
);
3025 __dwc3_gadget_stop(dwc
);
3030 int dwc3_gadget_resume(struct dwc3
*dwc
)
3034 if (!dwc
->gadget_driver
)
3037 ret
= __dwc3_gadget_start(dwc
);
3041 ret
= dwc3_gadget_run_stop(dwc
, true, false);
3048 __dwc3_gadget_stop(dwc
);
3054 void dwc3_gadget_process_pending_events(struct dwc3
*dwc
)
3056 if (dwc
->pending_events
) {
3057 dwc3_interrupt(dwc
->irq_gadget
, dwc
->ev_buf
);
3058 dwc
->pending_events
= false;
3059 enable_irq(dwc
->irq_gadget
);