1 // SPDX-License-Identifier: GPL-2.0
3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/spinlock.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/interrupt.h>
19 #include <linux/list.h>
20 #include <linux/dma-mapping.h>
22 #include <linux/usb/ch9.h>
23 #include <linux/usb/gadget.h>
30 #define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \
31 & ~((d)->interval - 1))
34 * dwc3_gadget_set_test_mode - enables usb2 test modes
35 * @dwc: pointer to our context structure
36 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
38 * Caller should take care of locking. This function will return 0 on
39 * success or -EINVAL if wrong Test Selector is passed.
41 int dwc3_gadget_set_test_mode(struct dwc3
*dwc
, int mode
)
45 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
46 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
51 case USB_TEST_SE0_NAK
:
53 case USB_TEST_FORCE_ENABLE
:
60 dwc3_gadget_dctl_write_safe(dwc
, reg
);
66 * dwc3_gadget_get_link_state - gets current state of usb link
67 * @dwc: pointer to our context structure
69 * Caller should take care of locking. This function will
70 * return the link state on success (>= 0) or -ETIMEDOUT.
72 int dwc3_gadget_get_link_state(struct dwc3
*dwc
)
76 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
78 return DWC3_DSTS_USBLNKST(reg
);
82 * dwc3_gadget_set_link_state - sets usb link to a particular state
83 * @dwc: pointer to our context structure
84 * @state: the state to put link into
86 * Caller should take care of locking. This function will
87 * return 0 on success or -ETIMEDOUT.
89 int dwc3_gadget_set_link_state(struct dwc3
*dwc
, enum dwc3_link_state state
)
95 * Wait until device controller is ready. Only applies to 1.94a and
98 if (!DWC3_VER_IS_PRIOR(DWC3
, 194A
)) {
100 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
101 if (reg
& DWC3_DSTS_DCNRD
)
111 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
112 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
114 /* set no action before sending new link state change */
115 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
117 /* set requested state */
118 reg
|= DWC3_DCTL_ULSTCHNGREQ(state
);
119 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
122 * The following code is racy when called from dwc3_gadget_wakeup,
123 * and is not needed, at least on newer versions
125 if (!DWC3_VER_IS_PRIOR(DWC3
, 194A
))
128 /* wait for a change in DSTS */
131 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
133 if (DWC3_DSTS_USBLNKST(reg
) == state
)
143 * dwc3_ep_inc_trb - increment a trb index.
144 * @index: Pointer to the TRB index to increment.
146 * The index should never point to the link TRB. After incrementing,
147 * if it is point to the link TRB, wrap around to the beginning. The
148 * link TRB is always at the last TRB entry.
150 static void dwc3_ep_inc_trb(u8
*index
)
153 if (*index
== (DWC3_TRB_NUM
- 1))
158 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
159 * @dep: The endpoint whose enqueue pointer we're incrementing
161 static void dwc3_ep_inc_enq(struct dwc3_ep
*dep
)
163 dwc3_ep_inc_trb(&dep
->trb_enqueue
);
167 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
168 * @dep: The endpoint whose enqueue pointer we're incrementing
170 static void dwc3_ep_inc_deq(struct dwc3_ep
*dep
)
172 dwc3_ep_inc_trb(&dep
->trb_dequeue
);
175 static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep
*dep
,
176 struct dwc3_request
*req
, int status
)
178 struct dwc3
*dwc
= dep
->dwc
;
180 list_del(&req
->list
);
182 req
->needs_extra_trb
= false;
184 if (req
->request
.status
== -EINPROGRESS
)
185 req
->request
.status
= status
;
188 usb_gadget_unmap_request_by_dev(dwc
->sysdev
,
189 &req
->request
, req
->direction
);
192 trace_dwc3_gadget_giveback(req
);
195 pm_runtime_put(dwc
->dev
);
199 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
200 * @dep: The endpoint to whom the request belongs to
201 * @req: The request we're giving back
202 * @status: completion code for the request
204 * Must be called with controller's lock held and interrupts disabled. This
205 * function will unmap @req and call its ->complete() callback to notify upper
206 * layers that it has completed.
208 void dwc3_gadget_giveback(struct dwc3_ep
*dep
, struct dwc3_request
*req
,
211 struct dwc3
*dwc
= dep
->dwc
;
213 dwc3_gadget_del_and_unmap_request(dep
, req
, status
);
214 req
->status
= DWC3_REQUEST_STATUS_COMPLETED
;
216 spin_unlock(&dwc
->lock
);
217 usb_gadget_giveback_request(&dep
->endpoint
, &req
->request
);
218 spin_lock(&dwc
->lock
);
222 * dwc3_send_gadget_generic_command - issue a generic command for the controller
223 * @dwc: pointer to the controller context
224 * @cmd: the command to be issued
225 * @param: command parameter
227 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
228 * and wait for its completion.
230 int dwc3_send_gadget_generic_command(struct dwc3
*dwc
, unsigned int cmd
,
238 dwc3_writel(dwc
->regs
, DWC3_DGCMDPAR
, param
);
239 dwc3_writel(dwc
->regs
, DWC3_DGCMD
, cmd
| DWC3_DGCMD_CMDACT
);
242 reg
= dwc3_readl(dwc
->regs
, DWC3_DGCMD
);
243 if (!(reg
& DWC3_DGCMD_CMDACT
)) {
244 status
= DWC3_DGCMD_STATUS(reg
);
256 trace_dwc3_gadget_generic_cmd(cmd
, param
, status
);
261 static int __dwc3_gadget_wakeup(struct dwc3
*dwc
);
264 * dwc3_send_gadget_ep_cmd - issue an endpoint command
265 * @dep: the endpoint to which the command is going to be issued
266 * @cmd: the command to be issued
267 * @params: parameters to the command
269 * Caller should handle locking. This function will issue @cmd with given
270 * @params to @dep and wait for its completion.
272 int dwc3_send_gadget_ep_cmd(struct dwc3_ep
*dep
, unsigned int cmd
,
273 struct dwc3_gadget_ep_cmd_params
*params
)
275 const struct usb_endpoint_descriptor
*desc
= dep
->endpoint
.desc
;
276 struct dwc3
*dwc
= dep
->dwc
;
278 u32 saved_config
= 0;
285 * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
286 * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
289 * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
290 * settings. Restore them after the command is completed.
292 * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
294 if (dwc
->gadget
->speed
<= USB_SPEED_HIGH
) {
295 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
296 if (unlikely(reg
& DWC3_GUSB2PHYCFG_SUSPHY
)) {
297 saved_config
|= DWC3_GUSB2PHYCFG_SUSPHY
;
298 reg
&= ~DWC3_GUSB2PHYCFG_SUSPHY
;
301 if (reg
& DWC3_GUSB2PHYCFG_ENBLSLPM
) {
302 saved_config
|= DWC3_GUSB2PHYCFG_ENBLSLPM
;
303 reg
&= ~DWC3_GUSB2PHYCFG_ENBLSLPM
;
307 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
310 if (DWC3_DEPCMD_CMD(cmd
) == DWC3_DEPCMD_STARTTRANSFER
) {
313 link_state
= dwc3_gadget_get_link_state(dwc
);
314 if (link_state
== DWC3_LINK_STATE_U1
||
315 link_state
== DWC3_LINK_STATE_U2
||
316 link_state
== DWC3_LINK_STATE_U3
) {
317 ret
= __dwc3_gadget_wakeup(dwc
);
318 dev_WARN_ONCE(dwc
->dev
, ret
, "wakeup failed --> %d\n",
323 dwc3_writel(dep
->regs
, DWC3_DEPCMDPAR0
, params
->param0
);
324 dwc3_writel(dep
->regs
, DWC3_DEPCMDPAR1
, params
->param1
);
325 dwc3_writel(dep
->regs
, DWC3_DEPCMDPAR2
, params
->param2
);
328 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
329 * not relying on XferNotReady, we can make use of a special "No
330 * Response Update Transfer" command where we should clear both CmdAct
333 * With this, we don't need to wait for command completion and can
334 * straight away issue further commands to the endpoint.
336 * NOTICE: We're making an assumption that control endpoints will never
337 * make use of Update Transfer command. This is a safe assumption
338 * because we can never have more than one request at a time with
339 * Control Endpoints. If anybody changes that assumption, this chunk
340 * needs to be updated accordingly.
342 if (DWC3_DEPCMD_CMD(cmd
) == DWC3_DEPCMD_UPDATETRANSFER
&&
343 !usb_endpoint_xfer_isoc(desc
))
344 cmd
&= ~(DWC3_DEPCMD_CMDIOC
| DWC3_DEPCMD_CMDACT
);
346 cmd
|= DWC3_DEPCMD_CMDACT
;
348 dwc3_writel(dep
->regs
, DWC3_DEPCMD
, cmd
);
350 reg
= dwc3_readl(dep
->regs
, DWC3_DEPCMD
);
351 if (!(reg
& DWC3_DEPCMD_CMDACT
)) {
352 cmd_status
= DWC3_DEPCMD_STATUS(reg
);
354 switch (cmd_status
) {
358 case DEPEVT_TRANSFER_NO_RESOURCE
:
359 dev_WARN(dwc
->dev
, "No resource for %s\n",
363 case DEPEVT_TRANSFER_BUS_EXPIRY
:
365 * SW issues START TRANSFER command to
366 * isochronous ep with future frame interval. If
367 * future interval time has already passed when
368 * core receives the command, it will respond
369 * with an error status of 'Bus Expiry'.
371 * Instead of always returning -EINVAL, let's
372 * give a hint to the gadget driver that this is
373 * the case by returning -EAGAIN.
378 dev_WARN(dwc
->dev
, "UNKNOWN cmd status\n");
387 cmd_status
= -ETIMEDOUT
;
390 trace_dwc3_gadget_ep_cmd(dep
, cmd
, params
, cmd_status
);
392 if (DWC3_DEPCMD_CMD(cmd
) == DWC3_DEPCMD_STARTTRANSFER
) {
394 dep
->flags
|= DWC3_EP_TRANSFER_STARTED
;
396 if (ret
!= -ETIMEDOUT
)
397 dwc3_gadget_ep_get_transfer_index(dep
);
401 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
403 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
409 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep
*dep
)
411 struct dwc3
*dwc
= dep
->dwc
;
412 struct dwc3_gadget_ep_cmd_params params
;
413 u32 cmd
= DWC3_DEPCMD_CLEARSTALL
;
416 * As of core revision 2.60a the recommended programming model
417 * is to set the ClearPendIN bit when issuing a Clear Stall EP
418 * command for IN endpoints. This is to prevent an issue where
419 * some (non-compliant) hosts may not send ACK TPs for pending
420 * IN transfers due to a mishandled error condition. Synopsys
423 if (dep
->direction
&&
424 !DWC3_VER_IS_PRIOR(DWC3
, 260A
) &&
425 (dwc
->gadget
->speed
>= USB_SPEED_SUPER
))
426 cmd
|= DWC3_DEPCMD_CLEARPENDIN
;
428 memset(¶ms
, 0, sizeof(params
));
430 return dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
433 static dma_addr_t
dwc3_trb_dma_offset(struct dwc3_ep
*dep
,
434 struct dwc3_trb
*trb
)
436 u32 offset
= (char *) trb
- (char *) dep
->trb_pool
;
438 return dep
->trb_pool_dma
+ offset
;
441 static int dwc3_alloc_trb_pool(struct dwc3_ep
*dep
)
443 struct dwc3
*dwc
= dep
->dwc
;
448 dep
->trb_pool
= dma_alloc_coherent(dwc
->sysdev
,
449 sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
450 &dep
->trb_pool_dma
, GFP_KERNEL
);
451 if (!dep
->trb_pool
) {
452 dev_err(dep
->dwc
->dev
, "failed to allocate trb pool for %s\n",
460 static void dwc3_free_trb_pool(struct dwc3_ep
*dep
)
462 struct dwc3
*dwc
= dep
->dwc
;
464 dma_free_coherent(dwc
->sysdev
, sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
465 dep
->trb_pool
, dep
->trb_pool_dma
);
467 dep
->trb_pool
= NULL
;
468 dep
->trb_pool_dma
= 0;
471 static int dwc3_gadget_set_xfer_resource(struct dwc3_ep
*dep
)
473 struct dwc3_gadget_ep_cmd_params params
;
475 memset(¶ms
, 0x00, sizeof(params
));
477 params
.param0
= DWC3_DEPXFERCFG_NUM_XFER_RES(1);
479 return dwc3_send_gadget_ep_cmd(dep
, DWC3_DEPCMD_SETTRANSFRESOURCE
,
484 * dwc3_gadget_start_config - configure ep resources
485 * @dep: endpoint that is being enabled
487 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
488 * completion, it will set Transfer Resource for all available endpoints.
490 * The assignment of transfer resources cannot perfectly follow the data book
491 * due to the fact that the controller driver does not have all knowledge of the
492 * configuration in advance. It is given this information piecemeal by the
493 * composite gadget framework after every SET_CONFIGURATION and
494 * SET_INTERFACE. Trying to follow the databook programming model in this
495 * scenario can cause errors. For two reasons:
497 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
498 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
499 * incorrect in the scenario of multiple interfaces.
501 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
502 * endpoint on alt setting (8.1.6).
504 * The following simplified method is used instead:
506 * All hardware endpoints can be assigned a transfer resource and this setting
507 * will stay persistent until either a core reset or hibernation. So whenever we
508 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
509 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
510 * guaranteed that there are as many transfer resources as endpoints.
512 * This function is called for each endpoint when it is being enabled but is
513 * triggered only when called for EP0-out, which always happens first, and which
514 * should only happen in one of the above conditions.
516 static int dwc3_gadget_start_config(struct dwc3_ep
*dep
)
518 struct dwc3_gadget_ep_cmd_params params
;
527 memset(¶ms
, 0x00, sizeof(params
));
528 cmd
= DWC3_DEPCMD_DEPSTARTCFG
;
531 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
535 for (i
= 0; i
< DWC3_ENDPOINTS_NUM
; i
++) {
536 struct dwc3_ep
*dep
= dwc
->eps
[i
];
541 ret
= dwc3_gadget_set_xfer_resource(dep
);
549 static int dwc3_gadget_set_ep_config(struct dwc3_ep
*dep
, unsigned int action
)
551 const struct usb_ss_ep_comp_descriptor
*comp_desc
;
552 const struct usb_endpoint_descriptor
*desc
;
553 struct dwc3_gadget_ep_cmd_params params
;
554 struct dwc3
*dwc
= dep
->dwc
;
556 comp_desc
= dep
->endpoint
.comp_desc
;
557 desc
= dep
->endpoint
.desc
;
559 memset(¶ms
, 0x00, sizeof(params
));
561 params
.param0
= DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc
))
562 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc
));
564 /* Burst size is only needed in SuperSpeed mode */
565 if (dwc
->gadget
->speed
>= USB_SPEED_SUPER
) {
566 u32 burst
= dep
->endpoint
.maxburst
;
568 params
.param0
|= DWC3_DEPCFG_BURST_SIZE(burst
- 1);
571 params
.param0
|= action
;
572 if (action
== DWC3_DEPCFG_ACTION_RESTORE
)
573 params
.param2
|= dep
->saved_state
;
575 if (usb_endpoint_xfer_control(desc
))
576 params
.param1
= DWC3_DEPCFG_XFER_COMPLETE_EN
;
578 if (dep
->number
<= 1 || usb_endpoint_xfer_isoc(desc
))
579 params
.param1
|= DWC3_DEPCFG_XFER_NOT_READY_EN
;
581 if (usb_ss_max_streams(comp_desc
) && usb_endpoint_xfer_bulk(desc
)) {
582 params
.param1
|= DWC3_DEPCFG_STREAM_CAPABLE
583 | DWC3_DEPCFG_XFER_COMPLETE_EN
584 | DWC3_DEPCFG_STREAM_EVENT_EN
;
585 dep
->stream_capable
= true;
588 if (!usb_endpoint_xfer_control(desc
))
589 params
.param1
|= DWC3_DEPCFG_XFER_IN_PROGRESS_EN
;
592 * We are doing 1:1 mapping for endpoints, meaning
593 * Physical Endpoints 2 maps to Logical Endpoint 2 and
594 * so on. We consider the direction bit as part of the physical
595 * endpoint number. So USB endpoint 0x81 is 0x03.
597 params
.param1
|= DWC3_DEPCFG_EP_NUMBER(dep
->number
);
600 * We must use the lower 16 TX FIFOs even though
604 params
.param0
|= DWC3_DEPCFG_FIFO_NUMBER(dep
->number
>> 1);
606 if (desc
->bInterval
) {
610 * Valid range for DEPCFG.bInterval_m1 is from 0 to 13.
612 * NOTE: The programming guide incorrectly stated bInterval_m1
613 * must be set to 0 when operating in fullspeed. Internally the
614 * controller does not have this limitation. See DWC_usb3x
615 * programming guide section 3.2.2.1.
617 bInterval_m1
= min_t(u8
, desc
->bInterval
- 1, 13);
619 if (usb_endpoint_type(desc
) == USB_ENDPOINT_XFER_INT
&&
620 dwc
->gadget
->speed
== USB_SPEED_FULL
)
621 dep
->interval
= desc
->bInterval
;
623 dep
->interval
= 1 << (desc
->bInterval
- 1);
625 params
.param1
|= DWC3_DEPCFG_BINTERVAL_M1(bInterval_m1
);
628 return dwc3_send_gadget_ep_cmd(dep
, DWC3_DEPCMD_SETEPCONFIG
, ¶ms
);
631 static void dwc3_stop_active_transfer(struct dwc3_ep
*dep
, bool force
,
635 * __dwc3_gadget_ep_enable - initializes a hw endpoint
636 * @dep: endpoint to be initialized
637 * @action: one of INIT, MODIFY or RESTORE
639 * Caller should take care of locking. Execute all necessary commands to
640 * initialize a HW endpoint so it can be used by a gadget driver.
642 static int __dwc3_gadget_ep_enable(struct dwc3_ep
*dep
, unsigned int action
)
644 const struct usb_endpoint_descriptor
*desc
= dep
->endpoint
.desc
;
645 struct dwc3
*dwc
= dep
->dwc
;
650 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
651 ret
= dwc3_gadget_start_config(dep
);
656 ret
= dwc3_gadget_set_ep_config(dep
, action
);
660 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
661 struct dwc3_trb
*trb_st_hw
;
662 struct dwc3_trb
*trb_link
;
664 dep
->type
= usb_endpoint_type(desc
);
665 dep
->flags
|= DWC3_EP_ENABLED
;
667 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
668 reg
|= DWC3_DALEPENA_EP(dep
->number
);
669 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
671 if (usb_endpoint_xfer_control(desc
))
674 /* Initialize the TRB ring */
675 dep
->trb_dequeue
= 0;
676 dep
->trb_enqueue
= 0;
677 memset(dep
->trb_pool
, 0,
678 sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
);
680 /* Link TRB. The HWO bit is never reset */
681 trb_st_hw
= &dep
->trb_pool
[0];
683 trb_link
= &dep
->trb_pool
[DWC3_TRB_NUM
- 1];
684 trb_link
->bpl
= lower_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
685 trb_link
->bph
= upper_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
686 trb_link
->ctrl
|= DWC3_TRBCTL_LINK_TRB
;
687 trb_link
->ctrl
|= DWC3_TRB_CTRL_HWO
;
691 * Issue StartTransfer here with no-op TRB so we can always rely on No
692 * Response Update Transfer command.
694 if (usb_endpoint_xfer_bulk(desc
) ||
695 usb_endpoint_xfer_int(desc
)) {
696 struct dwc3_gadget_ep_cmd_params params
;
697 struct dwc3_trb
*trb
;
701 memset(¶ms
, 0, sizeof(params
));
702 trb
= &dep
->trb_pool
[0];
703 trb_dma
= dwc3_trb_dma_offset(dep
, trb
);
705 params
.param0
= upper_32_bits(trb_dma
);
706 params
.param1
= lower_32_bits(trb_dma
);
708 cmd
= DWC3_DEPCMD_STARTTRANSFER
;
710 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
714 if (dep
->stream_capable
) {
716 * For streams, at start, there maybe a race where the
717 * host primes the endpoint before the function driver
718 * queues a request to initiate a stream. In that case,
719 * the controller will not see the prime to generate the
720 * ERDY and start stream. To workaround this, issue a
721 * no-op TRB as normal, but end it immediately. As a
722 * result, when the function driver queues the request,
723 * the next START_TRANSFER command will cause the
724 * controller to generate an ERDY to initiate the
727 dwc3_stop_active_transfer(dep
, true, true);
730 * All stream eps will reinitiate stream on NoStream
731 * rejection until we can determine that the host can
732 * prime after the first transfer.
734 dep
->flags
|= DWC3_EP_FORCE_RESTART_STREAM
;
739 trace_dwc3_gadget_ep_enable(dep
);
744 static void dwc3_remove_requests(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
746 struct dwc3_request
*req
;
748 dwc3_stop_active_transfer(dep
, true, false);
750 /* - giveback all requests to gadget driver */
751 while (!list_empty(&dep
->started_list
)) {
752 req
= next_request(&dep
->started_list
);
754 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
757 while (!list_empty(&dep
->pending_list
)) {
758 req
= next_request(&dep
->pending_list
);
760 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
763 while (!list_empty(&dep
->cancelled_list
)) {
764 req
= next_request(&dep
->cancelled_list
);
766 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
771 * __dwc3_gadget_ep_disable - disables a hw endpoint
772 * @dep: the endpoint to disable
774 * This function undoes what __dwc3_gadget_ep_enable did and also removes
775 * requests which are currently being processed by the hardware and those which
776 * are not yet scheduled.
778 * Caller should take care of locking.
780 static int __dwc3_gadget_ep_disable(struct dwc3_ep
*dep
)
782 struct dwc3
*dwc
= dep
->dwc
;
785 trace_dwc3_gadget_ep_disable(dep
);
787 /* make sure HW endpoint isn't stalled */
788 if (dep
->flags
& DWC3_EP_STALL
)
789 __dwc3_gadget_ep_set_halt(dep
, 0, false);
791 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
792 reg
&= ~DWC3_DALEPENA_EP(dep
->number
);
793 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
795 /* Clear out the ep descriptors for non-ep0 */
796 if (dep
->number
> 1) {
797 dep
->endpoint
.comp_desc
= NULL
;
798 dep
->endpoint
.desc
= NULL
;
801 dwc3_remove_requests(dwc
, dep
);
803 dep
->stream_capable
= false;
810 /* -------------------------------------------------------------------------- */
812 static int dwc3_gadget_ep0_enable(struct usb_ep
*ep
,
813 const struct usb_endpoint_descriptor
*desc
)
818 static int dwc3_gadget_ep0_disable(struct usb_ep
*ep
)
823 /* -------------------------------------------------------------------------- */
825 static int dwc3_gadget_ep_enable(struct usb_ep
*ep
,
826 const struct usb_endpoint_descriptor
*desc
)
833 if (!ep
|| !desc
|| desc
->bDescriptorType
!= USB_DT_ENDPOINT
) {
834 pr_debug("dwc3: invalid parameters\n");
838 if (!desc
->wMaxPacketSize
) {
839 pr_debug("dwc3: missing wMaxPacketSize\n");
843 dep
= to_dwc3_ep(ep
);
846 if (dev_WARN_ONCE(dwc
->dev
, dep
->flags
& DWC3_EP_ENABLED
,
847 "%s is already enabled\n",
851 spin_lock_irqsave(&dwc
->lock
, flags
);
852 ret
= __dwc3_gadget_ep_enable(dep
, DWC3_DEPCFG_ACTION_INIT
);
853 spin_unlock_irqrestore(&dwc
->lock
, flags
);
858 static int dwc3_gadget_ep_disable(struct usb_ep
*ep
)
866 pr_debug("dwc3: invalid parameters\n");
870 dep
= to_dwc3_ep(ep
);
873 if (dev_WARN_ONCE(dwc
->dev
, !(dep
->flags
& DWC3_EP_ENABLED
),
874 "%s is already disabled\n",
878 spin_lock_irqsave(&dwc
->lock
, flags
);
879 ret
= __dwc3_gadget_ep_disable(dep
);
880 spin_unlock_irqrestore(&dwc
->lock
, flags
);
885 static struct usb_request
*dwc3_gadget_ep_alloc_request(struct usb_ep
*ep
,
888 struct dwc3_request
*req
;
889 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
891 req
= kzalloc(sizeof(*req
), gfp_flags
);
895 req
->direction
= dep
->direction
;
896 req
->epnum
= dep
->number
;
898 req
->status
= DWC3_REQUEST_STATUS_UNKNOWN
;
900 trace_dwc3_alloc_request(req
);
902 return &req
->request
;
905 static void dwc3_gadget_ep_free_request(struct usb_ep
*ep
,
906 struct usb_request
*request
)
908 struct dwc3_request
*req
= to_dwc3_request(request
);
910 trace_dwc3_free_request(req
);
915 * dwc3_ep_prev_trb - returns the previous TRB in the ring
916 * @dep: The endpoint with the TRB ring
917 * @index: The index of the current TRB in the ring
919 * Returns the TRB prior to the one pointed to by the index. If the
920 * index is 0, we will wrap backwards, skip the link TRB, and return
921 * the one just before that.
923 static struct dwc3_trb
*dwc3_ep_prev_trb(struct dwc3_ep
*dep
, u8 index
)
928 tmp
= DWC3_TRB_NUM
- 1;
930 return &dep
->trb_pool
[tmp
- 1];
933 static u32
dwc3_calc_trbs_left(struct dwc3_ep
*dep
)
935 struct dwc3_trb
*tmp
;
939 * If enqueue & dequeue are equal than it is either full or empty.
941 * One way to know for sure is if the TRB right before us has HWO bit
942 * set or not. If it has, then we're definitely full and can't fit any
943 * more transfers in our ring.
945 if (dep
->trb_enqueue
== dep
->trb_dequeue
) {
946 tmp
= dwc3_ep_prev_trb(dep
, dep
->trb_enqueue
);
947 if (tmp
->ctrl
& DWC3_TRB_CTRL_HWO
)
950 return DWC3_TRB_NUM
- 1;
953 trbs_left
= dep
->trb_dequeue
- dep
->trb_enqueue
;
954 trbs_left
&= (DWC3_TRB_NUM
- 1);
956 if (dep
->trb_dequeue
< dep
->trb_enqueue
)
962 static void __dwc3_prepare_one_trb(struct dwc3_ep
*dep
, struct dwc3_trb
*trb
,
963 dma_addr_t dma
, unsigned int length
, unsigned int chain
,
964 unsigned int node
, unsigned int stream_id
,
965 unsigned int short_not_ok
, unsigned int no_interrupt
,
966 unsigned int is_last
, bool must_interrupt
)
968 struct dwc3
*dwc
= dep
->dwc
;
969 struct usb_gadget
*gadget
= dwc
->gadget
;
970 enum usb_device_speed speed
= gadget
->speed
;
972 trb
->size
= DWC3_TRB_SIZE_LENGTH(length
);
973 trb
->bpl
= lower_32_bits(dma
);
974 trb
->bph
= upper_32_bits(dma
);
976 switch (usb_endpoint_type(dep
->endpoint
.desc
)) {
977 case USB_ENDPOINT_XFER_CONTROL
:
978 trb
->ctrl
= DWC3_TRBCTL_CONTROL_SETUP
;
981 case USB_ENDPOINT_XFER_ISOC
:
983 trb
->ctrl
= DWC3_TRBCTL_ISOCHRONOUS_FIRST
;
986 * USB Specification 2.0 Section 5.9.2 states that: "If
987 * there is only a single transaction in the microframe,
988 * only a DATA0 data packet PID is used. If there are
989 * two transactions per microframe, DATA1 is used for
990 * the first transaction data packet and DATA0 is used
991 * for the second transaction data packet. If there are
992 * three transactions per microframe, DATA2 is used for
993 * the first transaction data packet, DATA1 is used for
994 * the second, and DATA0 is used for the third."
996 * IOW, we should satisfy the following cases:
998 * 1) length <= maxpacket
1001 * 2) maxpacket < length <= (2 * maxpacket)
1004 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
1005 * - DATA2, DATA1, DATA0
1007 if (speed
== USB_SPEED_HIGH
) {
1008 struct usb_ep
*ep
= &dep
->endpoint
;
1009 unsigned int mult
= 2;
1010 unsigned int maxp
= usb_endpoint_maxp(ep
->desc
);
1012 if (length
<= (2 * maxp
))
1018 trb
->size
|= DWC3_TRB_SIZE_PCM1(mult
);
1021 trb
->ctrl
= DWC3_TRBCTL_ISOCHRONOUS
;
1024 /* always enable Interrupt on Missed ISOC */
1025 trb
->ctrl
|= DWC3_TRB_CTRL_ISP_IMI
;
1028 case USB_ENDPOINT_XFER_BULK
:
1029 case USB_ENDPOINT_XFER_INT
:
1030 trb
->ctrl
= DWC3_TRBCTL_NORMAL
;
1034 * This is only possible with faulty memory because we
1035 * checked it already :)
1037 dev_WARN(dwc
->dev
, "Unknown endpoint type %d\n",
1038 usb_endpoint_type(dep
->endpoint
.desc
));
1042 * Enable Continue on Short Packet
1043 * when endpoint is not a stream capable
1045 if (usb_endpoint_dir_out(dep
->endpoint
.desc
)) {
1046 if (!dep
->stream_capable
)
1047 trb
->ctrl
|= DWC3_TRB_CTRL_CSP
;
1050 trb
->ctrl
|= DWC3_TRB_CTRL_ISP_IMI
;
1053 if ((!no_interrupt
&& !chain
) || must_interrupt
)
1054 trb
->ctrl
|= DWC3_TRB_CTRL_IOC
;
1057 trb
->ctrl
|= DWC3_TRB_CTRL_CHN
;
1058 else if (dep
->stream_capable
&& is_last
)
1059 trb
->ctrl
|= DWC3_TRB_CTRL_LST
;
1061 if (usb_endpoint_xfer_bulk(dep
->endpoint
.desc
) && dep
->stream_capable
)
1062 trb
->ctrl
|= DWC3_TRB_CTRL_SID_SOFN(stream_id
);
1064 trb
->ctrl
|= DWC3_TRB_CTRL_HWO
;
1066 dwc3_ep_inc_enq(dep
);
1068 trace_dwc3_prepare_trb(dep
, trb
);
1072 * dwc3_prepare_one_trb - setup one TRB from one request
1073 * @dep: endpoint for which this request is prepared
1074 * @req: dwc3_request pointer
1075 * @trb_length: buffer size of the TRB
1076 * @chain: should this TRB be chained to the next?
1077 * @node: only for isochronous endpoints. First TRB needs different type.
1078 * @use_bounce_buffer: set to use bounce buffer
1079 * @must_interrupt: set to interrupt on TRB completion
1081 static void dwc3_prepare_one_trb(struct dwc3_ep
*dep
,
1082 struct dwc3_request
*req
, unsigned int trb_length
,
1083 unsigned int chain
, unsigned int node
, bool use_bounce_buffer
,
1084 bool must_interrupt
)
1086 struct dwc3_trb
*trb
;
1088 unsigned int stream_id
= req
->request
.stream_id
;
1089 unsigned int short_not_ok
= req
->request
.short_not_ok
;
1090 unsigned int no_interrupt
= req
->request
.no_interrupt
;
1091 unsigned int is_last
= req
->request
.is_last
;
1093 if (use_bounce_buffer
)
1094 dma
= dep
->dwc
->bounce_addr
;
1095 else if (req
->request
.num_sgs
> 0)
1096 dma
= sg_dma_address(req
->start_sg
);
1098 dma
= req
->request
.dma
;
1100 trb
= &dep
->trb_pool
[dep
->trb_enqueue
];
1103 dwc3_gadget_move_started_request(req
);
1105 req
->trb_dma
= dwc3_trb_dma_offset(dep
, trb
);
1110 __dwc3_prepare_one_trb(dep
, trb
, dma
, trb_length
, chain
, node
,
1111 stream_id
, short_not_ok
, no_interrupt
, is_last
,
1115 static bool dwc3_needs_extra_trb(struct dwc3_ep
*dep
, struct dwc3_request
*req
)
1117 unsigned int maxp
= usb_endpoint_maxp(dep
->endpoint
.desc
);
1118 unsigned int rem
= req
->request
.length
% maxp
;
1120 if ((req
->request
.length
&& req
->request
.zero
&& !rem
&&
1121 !usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) ||
1122 (!req
->direction
&& rem
))
1129 * dwc3_prepare_last_sg - prepare TRBs for the last SG entry
1130 * @dep: The endpoint that the request belongs to
1131 * @req: The request to prepare
1132 * @entry_length: The last SG entry size
1133 * @node: Indicates whether this is not the first entry (for isoc only)
1135 * Return the number of TRBs prepared.
1137 static int dwc3_prepare_last_sg(struct dwc3_ep
*dep
,
1138 struct dwc3_request
*req
, unsigned int entry_length
,
1141 unsigned int maxp
= usb_endpoint_maxp(dep
->endpoint
.desc
);
1142 unsigned int rem
= req
->request
.length
% maxp
;
1143 unsigned int num_trbs
= 1;
1145 if (dwc3_needs_extra_trb(dep
, req
))
1148 if (dwc3_calc_trbs_left(dep
) < num_trbs
)
1151 req
->needs_extra_trb
= num_trbs
> 1;
1153 /* Prepare a normal TRB */
1154 if (req
->direction
|| req
->request
.length
)
1155 dwc3_prepare_one_trb(dep
, req
, entry_length
,
1156 req
->needs_extra_trb
, node
, false, false);
1158 /* Prepare extra TRBs for ZLP and MPS OUT transfer alignment */
1159 if ((!req
->direction
&& !req
->request
.length
) || req
->needs_extra_trb
)
1160 dwc3_prepare_one_trb(dep
, req
,
1161 req
->direction
? 0 : maxp
- rem
,
1162 false, 1, true, false);
1167 static int dwc3_prepare_trbs_sg(struct dwc3_ep
*dep
,
1168 struct dwc3_request
*req
)
1170 struct scatterlist
*sg
= req
->start_sg
;
1171 struct scatterlist
*s
;
1173 unsigned int length
= req
->request
.length
;
1174 unsigned int remaining
= req
->request
.num_mapped_sgs
1175 - req
->num_queued_sgs
;
1176 unsigned int num_trbs
= req
->num_trbs
;
1177 bool needs_extra_trb
= dwc3_needs_extra_trb(dep
, req
);
1180 * If we resume preparing the request, then get the remaining length of
1181 * the request and resume where we left off.
1183 for_each_sg(req
->request
.sg
, s
, req
->num_queued_sgs
, i
)
1184 length
-= sg_dma_len(s
);
1186 for_each_sg(sg
, s
, remaining
, i
) {
1187 unsigned int num_trbs_left
= dwc3_calc_trbs_left(dep
);
1188 unsigned int trb_length
;
1189 bool must_interrupt
= false;
1190 bool last_sg
= false;
1192 trb_length
= min_t(unsigned int, length
, sg_dma_len(s
));
1194 length
-= trb_length
;
1197 * IOMMU driver is coalescing the list of sgs which shares a
1198 * page boundary into one and giving it to USB driver. With
1199 * this the number of sgs mapped is not equal to the number of
1200 * sgs passed. So mark the chain bit to false if it isthe last
1203 if ((i
== remaining
- 1) || !length
)
1210 if (!dwc3_prepare_last_sg(dep
, req
, trb_length
, i
))
1214 * Look ahead to check if we have enough TRBs for the
1215 * next SG entry. If not, set interrupt on this TRB to
1216 * resume preparing the next SG entry when more TRBs are
1219 if (num_trbs_left
== 1 || (needs_extra_trb
&&
1220 num_trbs_left
<= 2 &&
1221 sg_dma_len(sg_next(s
)) >= length
))
1222 must_interrupt
= true;
1224 dwc3_prepare_one_trb(dep
, req
, trb_length
, 1, i
, false,
1229 * There can be a situation where all sgs in sglist are not
1230 * queued because of insufficient trb number. To handle this
1231 * case, update start_sg to next sg to be queued, so that
1232 * we have free trbs we can continue queuing from where we
1233 * previously stopped
1236 req
->start_sg
= sg_next(s
);
1238 req
->num_queued_sgs
++;
1241 * The number of pending SG entries may not correspond to the
1242 * number of mapped SG entries. If all the data are queued, then
1243 * don't include unused SG entries.
1246 req
->num_pending_sgs
-= req
->request
.num_mapped_sgs
- req
->num_queued_sgs
;
1254 return req
->num_trbs
- num_trbs
;
1257 static int dwc3_prepare_trbs_linear(struct dwc3_ep
*dep
,
1258 struct dwc3_request
*req
)
1260 return dwc3_prepare_last_sg(dep
, req
, req
->request
.length
, 0);
1264 * dwc3_prepare_trbs - setup TRBs from requests
1265 * @dep: endpoint for which requests are being prepared
1267 * The function goes through the requests list and sets up TRBs for the
1268 * transfers. The function returns once there are no more TRBs available or
1269 * it runs out of requests.
1271 * Returns the number of TRBs prepared or negative errno.
1273 static int dwc3_prepare_trbs(struct dwc3_ep
*dep
)
1275 struct dwc3_request
*req
, *n
;
1278 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM
);
1281 * We can get in a situation where there's a request in the started list
1282 * but there weren't enough TRBs to fully kick it in the first time
1283 * around, so it has been waiting for more TRBs to be freed up.
1285 * In that case, we should check if we have a request with pending_sgs
1286 * in the started list and prepare TRBs for that request first,
1287 * otherwise we will prepare TRBs completely out of order and that will
1290 list_for_each_entry(req
, &dep
->started_list
, list
) {
1291 if (req
->num_pending_sgs
> 0) {
1292 ret
= dwc3_prepare_trbs_sg(dep
, req
);
1293 if (!ret
|| req
->num_pending_sgs
)
1297 if (!dwc3_calc_trbs_left(dep
))
1301 * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1302 * burst capability may try to read and use TRBs beyond the
1303 * active transfer instead of stopping.
1305 if (dep
->stream_capable
&& req
->request
.is_last
)
1309 list_for_each_entry_safe(req
, n
, &dep
->pending_list
, list
) {
1310 struct dwc3
*dwc
= dep
->dwc
;
1312 ret
= usb_gadget_map_request_by_dev(dwc
->sysdev
, &req
->request
,
1317 req
->sg
= req
->request
.sg
;
1318 req
->start_sg
= req
->sg
;
1319 req
->num_queued_sgs
= 0;
1320 req
->num_pending_sgs
= req
->request
.num_mapped_sgs
;
1322 if (req
->num_pending_sgs
> 0) {
1323 ret
= dwc3_prepare_trbs_sg(dep
, req
);
1324 if (req
->num_pending_sgs
)
1327 ret
= dwc3_prepare_trbs_linear(dep
, req
);
1330 if (!ret
|| !dwc3_calc_trbs_left(dep
))
1334 * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1335 * burst capability may try to read and use TRBs beyond the
1336 * active transfer instead of stopping.
1338 if (dep
->stream_capable
&& req
->request
.is_last
)
1345 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep
*dep
);
1347 static int __dwc3_gadget_kick_transfer(struct dwc3_ep
*dep
)
1349 struct dwc3_gadget_ep_cmd_params params
;
1350 struct dwc3_request
*req
;
1356 * Note that it's normal to have no new TRBs prepared (i.e. ret == 0).
1357 * This happens when we need to stop and restart a transfer such as in
1358 * the case of reinitiating a stream or retrying an isoc transfer.
1360 ret
= dwc3_prepare_trbs(dep
);
1364 starting
= !(dep
->flags
& DWC3_EP_TRANSFER_STARTED
);
1367 * If there's no new TRB prepared and we don't need to restart a
1368 * transfer, there's no need to update the transfer.
1370 if (!ret
&& !starting
)
1373 req
= next_request(&dep
->started_list
);
1375 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
1379 memset(¶ms
, 0, sizeof(params
));
1382 params
.param0
= upper_32_bits(req
->trb_dma
);
1383 params
.param1
= lower_32_bits(req
->trb_dma
);
1384 cmd
= DWC3_DEPCMD_STARTTRANSFER
;
1386 if (dep
->stream_capable
)
1387 cmd
|= DWC3_DEPCMD_PARAM(req
->request
.stream_id
);
1389 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
1390 cmd
|= DWC3_DEPCMD_PARAM(dep
->frame_number
);
1392 cmd
= DWC3_DEPCMD_UPDATETRANSFER
|
1393 DWC3_DEPCMD_PARAM(dep
->resource_index
);
1396 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
1398 struct dwc3_request
*tmp
;
1403 dwc3_stop_active_transfer(dep
, true, true);
1405 list_for_each_entry_safe(req
, tmp
, &dep
->started_list
, list
)
1406 dwc3_gadget_move_cancelled_request(req
);
1408 /* If ep isn't started, then there's no end transfer pending */
1409 if (!(dep
->flags
& DWC3_EP_END_TRANSFER_PENDING
))
1410 dwc3_gadget_ep_cleanup_cancelled_requests(dep
);
1415 if (dep
->stream_capable
&& req
->request
.is_last
)
1416 dep
->flags
|= DWC3_EP_WAIT_TRANSFER_COMPLETE
;
1421 static int __dwc3_gadget_get_frame(struct dwc3
*dwc
)
1425 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1426 return DWC3_DSTS_SOFFN(reg
);
1430 * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
1431 * @dep: isoc endpoint
1433 * This function tests for the correct combination of BIT[15:14] from the 16-bit
1434 * microframe number reported by the XferNotReady event for the future frame
1435 * number to start the isoc transfer.
1437 * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
1438 * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
1439 * XferNotReady event are invalid. The driver uses this number to schedule the
1440 * isochronous transfer and passes it to the START TRANSFER command. Because
1441 * this number is invalid, the command may fail. If BIT[15:14] matches the
1442 * internal 16-bit microframe, the START TRANSFER command will pass and the
1443 * transfer will start at the scheduled time, if it is off by 1, the command
1444 * will still pass, but the transfer will start 2 seconds in the future. For all
1445 * other conditions, the START TRANSFER command will fail with bus-expiry.
1447 * In order to workaround this issue, we can test for the correct combination of
1448 * BIT[15:14] by sending START TRANSFER commands with different values of
1449 * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
1450 * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
1451 * As the result, within the 4 possible combinations for BIT[15:14], there will
1452 * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
1453 * command status will result in a 2-second delay start. The smaller BIT[15:14]
1454 * value is the correct combination.
1456 * Since there are only 4 outcomes and the results are ordered, we can simply
1457 * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
1458 * deduce the smaller successful combination.
1460 * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
1461 * of BIT[15:14]. The correct combination is as follow:
1463 * if test0 fails and test1 passes, BIT[15:14] is 'b01
1464 * if test0 fails and test1 fails, BIT[15:14] is 'b10
1465 * if test0 passes and test1 fails, BIT[15:14] is 'b11
1466 * if test0 passes and test1 passes, BIT[15:14] is 'b00
1468 * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
1471 static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep
*dep
)
1477 while (dep
->combo_num
< 2) {
1478 struct dwc3_gadget_ep_cmd_params params
;
1479 u32 test_frame_number
;
1483 * Check if we can start isoc transfer on the next interval or
1484 * 4 uframes in the future with BIT[15:14] as dep->combo_num
1486 test_frame_number
= dep
->frame_number
& DWC3_FRNUMBER_MASK
;
1487 test_frame_number
|= dep
->combo_num
<< 14;
1488 test_frame_number
+= max_t(u32
, 4, dep
->interval
);
1490 params
.param0
= upper_32_bits(dep
->dwc
->bounce_addr
);
1491 params
.param1
= lower_32_bits(dep
->dwc
->bounce_addr
);
1493 cmd
= DWC3_DEPCMD_STARTTRANSFER
;
1494 cmd
|= DWC3_DEPCMD_PARAM(test_frame_number
);
1495 cmd_status
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
1497 /* Redo if some other failure beside bus-expiry is received */
1498 if (cmd_status
&& cmd_status
!= -EAGAIN
) {
1499 dep
->start_cmd_status
= 0;
1504 /* Store the first test status */
1505 if (dep
->combo_num
== 0)
1506 dep
->start_cmd_status
= cmd_status
;
1511 * End the transfer if the START_TRANSFER command is successful
1512 * to wait for the next XferNotReady to test the command again
1514 if (cmd_status
== 0) {
1515 dwc3_stop_active_transfer(dep
, true, true);
1520 /* test0 and test1 are both completed at this point */
1521 test0
= (dep
->start_cmd_status
== 0);
1522 test1
= (cmd_status
== 0);
1524 if (!test0
&& test1
)
1526 else if (!test0
&& !test1
)
1528 else if (test0
&& !test1
)
1530 else if (test0
&& test1
)
1533 dep
->frame_number
&= DWC3_FRNUMBER_MASK
;
1534 dep
->frame_number
|= dep
->combo_num
<< 14;
1535 dep
->frame_number
+= max_t(u32
, 4, dep
->interval
);
1537 /* Reinitialize test variables */
1538 dep
->start_cmd_status
= 0;
1541 return __dwc3_gadget_kick_transfer(dep
);
1544 static int __dwc3_gadget_start_isoc(struct dwc3_ep
*dep
)
1546 const struct usb_endpoint_descriptor
*desc
= dep
->endpoint
.desc
;
1547 struct dwc3
*dwc
= dep
->dwc
;
1551 if (list_empty(&dep
->pending_list
) &&
1552 list_empty(&dep
->started_list
)) {
1553 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
1557 if (!dwc
->dis_start_transfer_quirk
&&
1558 (DWC3_VER_IS_PRIOR(DWC31
, 170A
) ||
1559 DWC3_VER_TYPE_IS_WITHIN(DWC31
, 170A
, EA01
, EA06
))) {
1560 if (dwc
->gadget
->speed
<= USB_SPEED_HIGH
&& dep
->direction
)
1561 return dwc3_gadget_start_isoc_quirk(dep
);
1564 if (desc
->bInterval
<= 14 &&
1565 dwc
->gadget
->speed
>= USB_SPEED_HIGH
) {
1566 u32 frame
= __dwc3_gadget_get_frame(dwc
);
1567 bool rollover
= frame
<
1568 (dep
->frame_number
& DWC3_FRNUMBER_MASK
);
1571 * frame_number is set from XferNotReady and may be already
1572 * out of date. DSTS only provides the lower 14 bit of the
1573 * current frame number. So add the upper two bits of
1574 * frame_number and handle a possible rollover.
1575 * This will provide the correct frame_number unless more than
1576 * rollover has happened since XferNotReady.
1579 dep
->frame_number
= (dep
->frame_number
& ~DWC3_FRNUMBER_MASK
) |
1582 dep
->frame_number
+= BIT(14);
1585 for (i
= 0; i
< DWC3_ISOC_MAX_RETRIES
; i
++) {
1586 dep
->frame_number
= DWC3_ALIGN_FRAME(dep
, i
+ 1);
1588 ret
= __dwc3_gadget_kick_transfer(dep
);
1594 * After a number of unsuccessful start attempts due to bus-expiry
1595 * status, issue END_TRANSFER command and retry on the next XferNotReady
1598 if (ret
== -EAGAIN
) {
1599 struct dwc3_gadget_ep_cmd_params params
;
1602 cmd
= DWC3_DEPCMD_ENDTRANSFER
|
1603 DWC3_DEPCMD_CMDIOC
|
1604 DWC3_DEPCMD_PARAM(dep
->resource_index
);
1606 dep
->resource_index
= 0;
1607 memset(¶ms
, 0, sizeof(params
));
1609 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
1611 dep
->flags
|= DWC3_EP_END_TRANSFER_PENDING
;
1617 static int __dwc3_gadget_ep_queue(struct dwc3_ep
*dep
, struct dwc3_request
*req
)
1619 struct dwc3
*dwc
= dep
->dwc
;
1621 if (!dep
->endpoint
.desc
|| !dwc
->pullups_connected
|| !dwc
->connected
) {
1622 dev_err(dwc
->dev
, "%s: can't queue to disabled endpoint\n",
1627 if (WARN(req
->dep
!= dep
, "request %pK belongs to '%s'\n",
1628 &req
->request
, req
->dep
->name
))
1631 if (WARN(req
->status
< DWC3_REQUEST_STATUS_COMPLETED
,
1632 "%s: request %pK already in flight\n",
1633 dep
->name
, &req
->request
))
1636 pm_runtime_get(dwc
->dev
);
1638 req
->request
.actual
= 0;
1639 req
->request
.status
= -EINPROGRESS
;
1641 trace_dwc3_ep_queue(req
);
1643 list_add_tail(&req
->list
, &dep
->pending_list
);
1644 req
->status
= DWC3_REQUEST_STATUS_QUEUED
;
1646 if (dep
->flags
& DWC3_EP_WAIT_TRANSFER_COMPLETE
)
1650 * Start the transfer only after the END_TRANSFER is completed
1651 * and endpoint STALL is cleared.
1653 if ((dep
->flags
& DWC3_EP_END_TRANSFER_PENDING
) ||
1654 (dep
->flags
& DWC3_EP_WEDGE
) ||
1655 (dep
->flags
& DWC3_EP_STALL
)) {
1656 dep
->flags
|= DWC3_EP_DELAY_START
;
1661 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1662 * wait for a XferNotReady event so we will know what's the current
1663 * (micro-)frame number.
1665 * Without this trick, we are very, very likely gonna get Bus Expiry
1666 * errors which will force us issue EndTransfer command.
1668 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1669 if (!(dep
->flags
& DWC3_EP_PENDING_REQUEST
) &&
1670 !(dep
->flags
& DWC3_EP_TRANSFER_STARTED
))
1673 if ((dep
->flags
& DWC3_EP_PENDING_REQUEST
)) {
1674 if (!(dep
->flags
& DWC3_EP_TRANSFER_STARTED
))
1675 return __dwc3_gadget_start_isoc(dep
);
1679 return __dwc3_gadget_kick_transfer(dep
);
1682 static int dwc3_gadget_ep_queue(struct usb_ep
*ep
, struct usb_request
*request
,
1685 struct dwc3_request
*req
= to_dwc3_request(request
);
1686 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1687 struct dwc3
*dwc
= dep
->dwc
;
1689 unsigned long flags
;
1693 spin_lock_irqsave(&dwc
->lock
, flags
);
1694 ret
= __dwc3_gadget_ep_queue(dep
, req
);
1695 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1700 static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep
*dep
, struct dwc3_request
*req
)
1704 /* If req->trb is not set, then the request has not started */
1709 * If request was already started, this means we had to
1710 * stop the transfer. With that we also need to ignore
1711 * all TRBs used by the request, however TRBs can only
1712 * be modified after completion of END_TRANSFER
1713 * command. So what we do here is that we wait for
1714 * END_TRANSFER completion and only after that, we jump
1715 * over TRBs by clearing HWO and incrementing dequeue
1718 for (i
= 0; i
< req
->num_trbs
; i
++) {
1719 struct dwc3_trb
*trb
;
1721 trb
= &dep
->trb_pool
[dep
->trb_dequeue
];
1722 trb
->ctrl
&= ~DWC3_TRB_CTRL_HWO
;
1723 dwc3_ep_inc_deq(dep
);
1729 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep
*dep
)
1731 struct dwc3_request
*req
;
1732 struct dwc3_request
*tmp
;
1734 list_for_each_entry_safe(req
, tmp
, &dep
->cancelled_list
, list
) {
1735 dwc3_gadget_ep_skip_trbs(dep
, req
);
1736 dwc3_gadget_giveback(dep
, req
, -ECONNRESET
);
1740 static int dwc3_gadget_ep_dequeue(struct usb_ep
*ep
,
1741 struct usb_request
*request
)
1743 struct dwc3_request
*req
= to_dwc3_request(request
);
1744 struct dwc3_request
*r
= NULL
;
1746 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1747 struct dwc3
*dwc
= dep
->dwc
;
1749 unsigned long flags
;
1752 trace_dwc3_ep_dequeue(req
);
1754 spin_lock_irqsave(&dwc
->lock
, flags
);
1756 list_for_each_entry(r
, &dep
->cancelled_list
, list
) {
1761 list_for_each_entry(r
, &dep
->pending_list
, list
) {
1763 dwc3_gadget_giveback(dep
, req
, -ECONNRESET
);
1768 list_for_each_entry(r
, &dep
->started_list
, list
) {
1770 struct dwc3_request
*t
;
1772 /* wait until it is processed */
1773 dwc3_stop_active_transfer(dep
, true, true);
1776 * Remove any started request if the transfer is
1779 list_for_each_entry_safe(r
, t
, &dep
->started_list
, list
)
1780 dwc3_gadget_move_cancelled_request(r
);
1782 dep
->flags
&= ~DWC3_EP_WAIT_TRANSFER_COMPLETE
;
1788 dev_err(dwc
->dev
, "request %pK was not queued to %s\n",
1792 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1797 int __dwc3_gadget_ep_set_halt(struct dwc3_ep
*dep
, int value
, int protocol
)
1799 struct dwc3_gadget_ep_cmd_params params
;
1800 struct dwc3
*dwc
= dep
->dwc
;
1801 struct dwc3_request
*req
;
1802 struct dwc3_request
*tmp
;
1805 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1806 dev_err(dwc
->dev
, "%s is of Isochronous type\n", dep
->name
);
1810 memset(¶ms
, 0x00, sizeof(params
));
1813 struct dwc3_trb
*trb
;
1815 unsigned int transfer_in_flight
;
1816 unsigned int started
;
1818 if (dep
->number
> 1)
1819 trb
= dwc3_ep_prev_trb(dep
, dep
->trb_enqueue
);
1821 trb
= &dwc
->ep0_trb
[dep
->trb_enqueue
];
1823 transfer_in_flight
= trb
->ctrl
& DWC3_TRB_CTRL_HWO
;
1824 started
= !list_empty(&dep
->started_list
);
1826 if (!protocol
&& ((dep
->direction
&& transfer_in_flight
) ||
1827 (!dep
->direction
&& started
))) {
1831 ret
= dwc3_send_gadget_ep_cmd(dep
, DWC3_DEPCMD_SETSTALL
,
1834 dev_err(dwc
->dev
, "failed to set STALL on %s\n",
1837 dep
->flags
|= DWC3_EP_STALL
;
1840 * Don't issue CLEAR_STALL command to control endpoints. The
1841 * controller automatically clears the STALL when it receives
1844 if (dep
->number
<= 1) {
1845 dep
->flags
&= ~(DWC3_EP_STALL
| DWC3_EP_WEDGE
);
1849 dwc3_stop_active_transfer(dep
, true, true);
1851 list_for_each_entry_safe(req
, tmp
, &dep
->started_list
, list
)
1852 dwc3_gadget_move_cancelled_request(req
);
1854 if (dep
->flags
& DWC3_EP_END_TRANSFER_PENDING
) {
1855 dep
->flags
|= DWC3_EP_PENDING_CLEAR_STALL
;
1859 dwc3_gadget_ep_cleanup_cancelled_requests(dep
);
1861 ret
= dwc3_send_clear_stall_ep_cmd(dep
);
1863 dev_err(dwc
->dev
, "failed to clear STALL on %s\n",
1868 dep
->flags
&= ~(DWC3_EP_STALL
| DWC3_EP_WEDGE
);
1870 if ((dep
->flags
& DWC3_EP_DELAY_START
) &&
1871 !usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
1872 __dwc3_gadget_kick_transfer(dep
);
1874 dep
->flags
&= ~DWC3_EP_DELAY_START
;
1880 static int dwc3_gadget_ep_set_halt(struct usb_ep
*ep
, int value
)
1882 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1883 struct dwc3
*dwc
= dep
->dwc
;
1885 unsigned long flags
;
1889 spin_lock_irqsave(&dwc
->lock
, flags
);
1890 ret
= __dwc3_gadget_ep_set_halt(dep
, value
, false);
1891 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1896 static int dwc3_gadget_ep_set_wedge(struct usb_ep
*ep
)
1898 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1899 struct dwc3
*dwc
= dep
->dwc
;
1900 unsigned long flags
;
1903 spin_lock_irqsave(&dwc
->lock
, flags
);
1904 dep
->flags
|= DWC3_EP_WEDGE
;
1906 if (dep
->number
== 0 || dep
->number
== 1)
1907 ret
= __dwc3_gadget_ep0_set_halt(ep
, 1);
1909 ret
= __dwc3_gadget_ep_set_halt(dep
, 1, false);
1910 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1915 /* -------------------------------------------------------------------------- */
1917 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc
= {
1918 .bLength
= USB_DT_ENDPOINT_SIZE
,
1919 .bDescriptorType
= USB_DT_ENDPOINT
,
1920 .bmAttributes
= USB_ENDPOINT_XFER_CONTROL
,
1923 static const struct usb_ep_ops dwc3_gadget_ep0_ops
= {
1924 .enable
= dwc3_gadget_ep0_enable
,
1925 .disable
= dwc3_gadget_ep0_disable
,
1926 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1927 .free_request
= dwc3_gadget_ep_free_request
,
1928 .queue
= dwc3_gadget_ep0_queue
,
1929 .dequeue
= dwc3_gadget_ep_dequeue
,
1930 .set_halt
= dwc3_gadget_ep0_set_halt
,
1931 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1934 static const struct usb_ep_ops dwc3_gadget_ep_ops
= {
1935 .enable
= dwc3_gadget_ep_enable
,
1936 .disable
= dwc3_gadget_ep_disable
,
1937 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1938 .free_request
= dwc3_gadget_ep_free_request
,
1939 .queue
= dwc3_gadget_ep_queue
,
1940 .dequeue
= dwc3_gadget_ep_dequeue
,
1941 .set_halt
= dwc3_gadget_ep_set_halt
,
1942 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1945 /* -------------------------------------------------------------------------- */
1947 static int dwc3_gadget_get_frame(struct usb_gadget
*g
)
1949 struct dwc3
*dwc
= gadget_to_dwc(g
);
1951 return __dwc3_gadget_get_frame(dwc
);
1954 static int __dwc3_gadget_wakeup(struct dwc3
*dwc
)
1964 * According to the Databook Remote wakeup request should
1965 * be issued only when the device is in early suspend state.
1967 * We can check that via USB Link State bits in DSTS register.
1969 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1971 link_state
= DWC3_DSTS_USBLNKST(reg
);
1973 switch (link_state
) {
1974 case DWC3_LINK_STATE_RESET
:
1975 case DWC3_LINK_STATE_RX_DET
: /* in HS, means Early Suspend */
1976 case DWC3_LINK_STATE_U3
: /* in HS, means SUSPEND */
1977 case DWC3_LINK_STATE_U2
: /* in HS, means Sleep (L1) */
1978 case DWC3_LINK_STATE_U1
:
1979 case DWC3_LINK_STATE_RESUME
:
1985 ret
= dwc3_gadget_set_link_state(dwc
, DWC3_LINK_STATE_RECOV
);
1987 dev_err(dwc
->dev
, "failed to put link in Recovery\n");
1991 /* Recent versions do this automatically */
1992 if (DWC3_VER_IS_PRIOR(DWC3
, 194A
)) {
1993 /* write zeroes to Link Change Request */
1994 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1995 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
1996 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1999 /* poll until Link State changes to ON */
2003 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
2005 /* in HS, means ON */
2006 if (DWC3_DSTS_USBLNKST(reg
) == DWC3_LINK_STATE_U0
)
2010 if (DWC3_DSTS_USBLNKST(reg
) != DWC3_LINK_STATE_U0
) {
2011 dev_err(dwc
->dev
, "failed to send remote wakeup\n");
2018 static int dwc3_gadget_wakeup(struct usb_gadget
*g
)
2020 struct dwc3
*dwc
= gadget_to_dwc(g
);
2021 unsigned long flags
;
2024 spin_lock_irqsave(&dwc
->lock
, flags
);
2025 ret
= __dwc3_gadget_wakeup(dwc
);
2026 spin_unlock_irqrestore(&dwc
->lock
, flags
);
2031 static int dwc3_gadget_set_selfpowered(struct usb_gadget
*g
,
2034 struct dwc3
*dwc
= gadget_to_dwc(g
);
2035 unsigned long flags
;
2037 spin_lock_irqsave(&dwc
->lock
, flags
);
2038 g
->is_selfpowered
= !!is_selfpowered
;
2039 spin_unlock_irqrestore(&dwc
->lock
, flags
);
2044 static void dwc3_stop_active_transfers(struct dwc3
*dwc
)
2048 for (epnum
= 2; epnum
< dwc
->num_eps
; epnum
++) {
2049 struct dwc3_ep
*dep
;
2051 dep
= dwc
->eps
[epnum
];
2055 dwc3_remove_requests(dwc
, dep
);
2059 static int dwc3_gadget_run_stop(struct dwc3
*dwc
, int is_on
, int suspend
)
2064 if (pm_runtime_suspended(dwc
->dev
))
2067 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2069 if (DWC3_VER_IS_WITHIN(DWC3
, ANY
, 187A
)) {
2070 reg
&= ~DWC3_DCTL_TRGTULST_MASK
;
2071 reg
|= DWC3_DCTL_TRGTULST_RX_DET
;
2074 if (!DWC3_VER_IS_PRIOR(DWC3
, 194A
))
2075 reg
&= ~DWC3_DCTL_KEEP_CONNECT
;
2076 reg
|= DWC3_DCTL_RUN_STOP
;
2078 if (dwc
->has_hibernation
)
2079 reg
|= DWC3_DCTL_KEEP_CONNECT
;
2081 dwc
->pullups_connected
= true;
2083 reg
&= ~DWC3_DCTL_RUN_STOP
;
2085 if (dwc
->has_hibernation
&& !suspend
)
2086 reg
&= ~DWC3_DCTL_KEEP_CONNECT
;
2088 dwc
->pullups_connected
= false;
2091 dwc3_gadget_dctl_write_safe(dwc
, reg
);
2094 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
2095 reg
&= DWC3_DSTS_DEVCTRLHLT
;
2096 } while (--timeout
&& !(!is_on
^ !reg
));
2104 static void dwc3_gadget_disable_irq(struct dwc3
*dwc
);
2105 static void __dwc3_gadget_stop(struct dwc3
*dwc
);
2106 static int __dwc3_gadget_start(struct dwc3
*dwc
);
2108 static int dwc3_gadget_pullup(struct usb_gadget
*g
, int is_on
)
2110 struct dwc3
*dwc
= gadget_to_dwc(g
);
2111 unsigned long flags
;
2117 * Per databook, when we want to stop the gadget, if a control transfer
2118 * is still in process, complete it and get the core into setup phase.
2120 if (!is_on
&& dwc
->ep0state
!= EP0_SETUP_PHASE
) {
2121 reinit_completion(&dwc
->ep0_in_setup
);
2123 ret
= wait_for_completion_timeout(&dwc
->ep0_in_setup
,
2124 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT
));
2126 dev_err(dwc
->dev
, "timed out waiting for SETUP phase\n");
2132 * Check the return value for successful resume, or error. For a
2133 * successful resume, the DWC3 runtime PM resume routine will handle
2134 * the run stop sequence, so avoid duplicate operations here.
2136 ret
= pm_runtime_get_sync(dwc
->dev
);
2137 if (!ret
|| ret
< 0) {
2138 pm_runtime_put(dwc
->dev
);
2143 * Synchronize any pending event handling before executing the controller
2147 dwc3_gadget_disable_irq(dwc
);
2148 synchronize_irq(dwc
->irq_gadget
);
2151 spin_lock_irqsave(&dwc
->lock
, flags
);
2156 dwc
->connected
= false;
2158 * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
2159 * Section 4.1.8 Table 4-7, it states that for a device-initiated
2160 * disconnect, the SW needs to ensure that it sends "a DEPENDXFER
2161 * command for any active transfers" before clearing the RunStop
2164 dwc3_stop_active_transfers(dwc
);
2165 __dwc3_gadget_stop(dwc
);
2168 * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
2169 * Section 1.3.4, it mentions that for the DEVCTRLHLT bit, the
2170 * "software needs to acknowledge the events that are generated
2171 * (by writing to GEVNTCOUNTn) while it is waiting for this bit
2172 * to be set to '1'."
2174 count
= dwc3_readl(dwc
->regs
, DWC3_GEVNTCOUNT(0));
2175 count
&= DWC3_GEVNTCOUNT_MASK
;
2177 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(0), count
);
2178 dwc
->ev_buf
->lpos
= (dwc
->ev_buf
->lpos
+ count
) %
2179 dwc
->ev_buf
->length
;
2182 __dwc3_gadget_start(dwc
);
2185 ret
= dwc3_gadget_run_stop(dwc
, is_on
, false);
2186 spin_unlock_irqrestore(&dwc
->lock
, flags
);
2187 pm_runtime_put(dwc
->dev
);
2192 static void dwc3_gadget_enable_irq(struct dwc3
*dwc
)
2196 /* Enable all but Start and End of Frame IRQs */
2197 reg
= (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN
|
2198 DWC3_DEVTEN_EVNTOVERFLOWEN
|
2199 DWC3_DEVTEN_CMDCMPLTEN
|
2200 DWC3_DEVTEN_ERRTICERREN
|
2201 DWC3_DEVTEN_WKUPEVTEN
|
2202 DWC3_DEVTEN_CONNECTDONEEN
|
2203 DWC3_DEVTEN_USBRSTEN
|
2204 DWC3_DEVTEN_DISCONNEVTEN
);
2206 if (DWC3_VER_IS_PRIOR(DWC3
, 250A
))
2207 reg
|= DWC3_DEVTEN_ULSTCNGEN
;
2209 /* On 2.30a and above this bit enables U3/L2-L1 Suspend Events */
2210 if (!DWC3_VER_IS_PRIOR(DWC3
, 230A
))
2211 reg
|= DWC3_DEVTEN_EOPFEN
;
2213 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, reg
);
2216 static void dwc3_gadget_disable_irq(struct dwc3
*dwc
)
2218 /* mask all interrupts */
2219 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, 0x00);
2222 static irqreturn_t
dwc3_interrupt(int irq
, void *_dwc
);
2223 static irqreturn_t
dwc3_thread_interrupt(int irq
, void *_dwc
);
2226 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
2227 * @dwc: pointer to our context structure
2229 * The following looks like complex but it's actually very simple. In order to
2230 * calculate the number of packets we can burst at once on OUT transfers, we're
2231 * gonna use RxFIFO size.
2233 * To calculate RxFIFO size we need two numbers:
2234 * MDWIDTH = size, in bits, of the internal memory bus
2235 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
2237 * Given these two numbers, the formula is simple:
2239 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
2241 * 24 bytes is for 3x SETUP packets
2242 * 16 bytes is a clock domain crossing tolerance
2244 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
2246 static void dwc3_gadget_setup_nump(struct dwc3
*dwc
)
2253 ram2_depth
= DWC3_GHWPARAMS7_RAM2_DEPTH(dwc
->hwparams
.hwparams7
);
2254 mdwidth
= DWC3_GHWPARAMS0_MDWIDTH(dwc
->hwparams
.hwparams0
);
2255 if (DWC3_IP_IS(DWC32
))
2256 mdwidth
+= DWC3_GHWPARAMS6_MDWIDTH(dwc
->hwparams
.hwparams6
);
2258 nump
= ((ram2_depth
* mdwidth
/ 8) - 24 - 16) / 1024;
2259 nump
= min_t(u32
, nump
, 16);
2262 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2263 reg
&= ~DWC3_DCFG_NUMP_MASK
;
2264 reg
|= nump
<< DWC3_DCFG_NUMP_SHIFT
;
2265 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2268 static int __dwc3_gadget_start(struct dwc3
*dwc
)
2270 struct dwc3_ep
*dep
;
2275 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
2276 * the core supports IMOD, disable it.
2278 if (dwc
->imod_interval
) {
2279 dwc3_writel(dwc
->regs
, DWC3_DEV_IMOD(0), dwc
->imod_interval
);
2280 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB
);
2281 } else if (dwc3_has_imod(dwc
)) {
2282 dwc3_writel(dwc
->regs
, DWC3_DEV_IMOD(0), 0);
2286 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
2287 * field instead of letting dwc3 itself calculate that automatically.
2289 * This way, we maximize the chances that we'll be able to get several
2290 * bursts of data without going through any sort of endpoint throttling.
2292 reg
= dwc3_readl(dwc
->regs
, DWC3_GRXTHRCFG
);
2293 if (DWC3_IP_IS(DWC3
))
2294 reg
&= ~DWC3_GRXTHRCFG_PKTCNTSEL
;
2296 reg
&= ~DWC31_GRXTHRCFG_PKTCNTSEL
;
2298 dwc3_writel(dwc
->regs
, DWC3_GRXTHRCFG
, reg
);
2300 dwc3_gadget_setup_nump(dwc
);
2302 /* Start with SuperSpeed Default */
2303 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
2306 ret
= __dwc3_gadget_ep_enable(dep
, DWC3_DEPCFG_ACTION_INIT
);
2308 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2313 ret
= __dwc3_gadget_ep_enable(dep
, DWC3_DEPCFG_ACTION_INIT
);
2315 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2319 /* begin to receive SETUP packets */
2320 dwc
->ep0state
= EP0_SETUP_PHASE
;
2321 dwc
->link_state
= DWC3_LINK_STATE_SS_DIS
;
2322 dwc3_ep0_out_start(dwc
);
2324 dwc3_gadget_enable_irq(dwc
);
2329 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
2335 static int dwc3_gadget_start(struct usb_gadget
*g
,
2336 struct usb_gadget_driver
*driver
)
2338 struct dwc3
*dwc
= gadget_to_dwc(g
);
2339 unsigned long flags
;
2343 irq
= dwc
->irq_gadget
;
2344 ret
= request_threaded_irq(irq
, dwc3_interrupt
, dwc3_thread_interrupt
,
2345 IRQF_SHARED
, "dwc3", dwc
->ev_buf
);
2347 dev_err(dwc
->dev
, "failed to request irq #%d --> %d\n",
2352 spin_lock_irqsave(&dwc
->lock
, flags
);
2353 if (dwc
->gadget_driver
) {
2354 dev_err(dwc
->dev
, "%s is already bound to %s\n",
2356 dwc
->gadget_driver
->driver
.name
);
2361 dwc
->gadget_driver
= driver
;
2362 spin_unlock_irqrestore(&dwc
->lock
, flags
);
2367 spin_unlock_irqrestore(&dwc
->lock
, flags
);
2374 static void __dwc3_gadget_stop(struct dwc3
*dwc
)
2376 dwc3_gadget_disable_irq(dwc
);
2377 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
2378 __dwc3_gadget_ep_disable(dwc
->eps
[1]);
2381 static int dwc3_gadget_stop(struct usb_gadget
*g
)
2383 struct dwc3
*dwc
= gadget_to_dwc(g
);
2384 unsigned long flags
;
2386 spin_lock_irqsave(&dwc
->lock
, flags
);
2387 dwc
->gadget_driver
= NULL
;
2388 spin_unlock_irqrestore(&dwc
->lock
, flags
);
2390 free_irq(dwc
->irq_gadget
, dwc
->ev_buf
);
2395 static void dwc3_gadget_config_params(struct usb_gadget
*g
,
2396 struct usb_dcd_config_params
*params
)
2398 struct dwc3
*dwc
= gadget_to_dwc(g
);
2400 params
->besl_baseline
= USB_DEFAULT_BESL_UNSPECIFIED
;
2401 params
->besl_deep
= USB_DEFAULT_BESL_UNSPECIFIED
;
2403 /* Recommended BESL */
2404 if (!dwc
->dis_enblslpm_quirk
) {
2406 * If the recommended BESL baseline is 0 or if the BESL deep is
2407 * less than 2, Microsoft's Windows 10 host usb stack will issue
2408 * a usb reset immediately after it receives the extended BOS
2409 * descriptor and the enumeration will fail. To maintain
2410 * compatibility with the Windows' usb stack, let's set the
2411 * recommended BESL baseline to 1 and clamp the BESL deep to be
2414 params
->besl_baseline
= 1;
2415 if (dwc
->is_utmi_l1_suspend
)
2417 clamp_t(u8
, dwc
->hird_threshold
, 2, 15);
2420 /* U1 Device exit Latency */
2421 if (dwc
->dis_u1_entry_quirk
)
2422 params
->bU1devExitLat
= 0;
2424 params
->bU1devExitLat
= DWC3_DEFAULT_U1_DEV_EXIT_LAT
;
2426 /* U2 Device exit Latency */
2427 if (dwc
->dis_u2_entry_quirk
)
2428 params
->bU2DevExitLat
= 0;
2430 params
->bU2DevExitLat
=
2431 cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT
);
2434 static void dwc3_gadget_set_speed(struct usb_gadget
*g
,
2435 enum usb_device_speed speed
)
2437 struct dwc3
*dwc
= gadget_to_dwc(g
);
2438 unsigned long flags
;
2441 spin_lock_irqsave(&dwc
->lock
, flags
);
2442 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2443 reg
&= ~(DWC3_DCFG_SPEED_MASK
);
2446 * WORKAROUND: DWC3 revision < 2.20a have an issue
2447 * which would cause metastability state on Run/Stop
2448 * bit if we try to force the IP to USB2-only mode.
2450 * Because of that, we cannot configure the IP to any
2451 * speed other than the SuperSpeed
2455 * STAR#9000525659: Clock Domain Crossing on DCTL in
2458 if (DWC3_VER_IS_PRIOR(DWC3
, 220A
) &&
2459 !dwc
->dis_metastability_quirk
) {
2460 reg
|= DWC3_DCFG_SUPERSPEED
;
2464 reg
|= DWC3_DCFG_LOWSPEED
;
2466 case USB_SPEED_FULL
:
2467 reg
|= DWC3_DCFG_FULLSPEED
;
2469 case USB_SPEED_HIGH
:
2470 reg
|= DWC3_DCFG_HIGHSPEED
;
2472 case USB_SPEED_SUPER
:
2473 reg
|= DWC3_DCFG_SUPERSPEED
;
2475 case USB_SPEED_SUPER_PLUS
:
2476 if (DWC3_IP_IS(DWC3
))
2477 reg
|= DWC3_DCFG_SUPERSPEED
;
2479 reg
|= DWC3_DCFG_SUPERSPEED_PLUS
;
2482 dev_err(dwc
->dev
, "invalid speed (%d)\n", speed
);
2484 if (DWC3_IP_IS(DWC3
))
2485 reg
|= DWC3_DCFG_SUPERSPEED
;
2487 reg
|= DWC3_DCFG_SUPERSPEED_PLUS
;
2490 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2492 spin_unlock_irqrestore(&dwc
->lock
, flags
);
2495 static const struct usb_gadget_ops dwc3_gadget_ops
= {
2496 .get_frame
= dwc3_gadget_get_frame
,
2497 .wakeup
= dwc3_gadget_wakeup
,
2498 .set_selfpowered
= dwc3_gadget_set_selfpowered
,
2499 .pullup
= dwc3_gadget_pullup
,
2500 .udc_start
= dwc3_gadget_start
,
2501 .udc_stop
= dwc3_gadget_stop
,
2502 .udc_set_speed
= dwc3_gadget_set_speed
,
2503 .get_config_params
= dwc3_gadget_config_params
,
2506 /* -------------------------------------------------------------------------- */
2508 static int dwc3_gadget_init_control_endpoint(struct dwc3_ep
*dep
)
2510 struct dwc3
*dwc
= dep
->dwc
;
2512 usb_ep_set_maxpacket_limit(&dep
->endpoint
, 512);
2513 dep
->endpoint
.maxburst
= 1;
2514 dep
->endpoint
.ops
= &dwc3_gadget_ep0_ops
;
2515 if (!dep
->direction
)
2516 dwc
->gadget
->ep0
= &dep
->endpoint
;
2518 dep
->endpoint
.caps
.type_control
= true;
2523 static int dwc3_gadget_init_in_endpoint(struct dwc3_ep
*dep
)
2525 struct dwc3
*dwc
= dep
->dwc
;
2529 mdwidth
= DWC3_MDWIDTH(dwc
->hwparams
.hwparams0
);
2530 if (DWC3_IP_IS(DWC32
))
2531 mdwidth
+= DWC3_GHWPARAMS6_MDWIDTH(dwc
->hwparams
.hwparams6
);
2533 /* MDWIDTH is represented in bits, we need it in bytes */
2536 size
= dwc3_readl(dwc
->regs
, DWC3_GTXFIFOSIZ(dep
->number
>> 1));
2537 if (DWC3_IP_IS(DWC3
))
2538 size
= DWC3_GTXFIFOSIZ_TXFDEP(size
);
2540 size
= DWC31_GTXFIFOSIZ_TXFDEP(size
);
2542 /* FIFO Depth is in MDWDITH bytes. Multiply */
2546 * To meet performance requirement, a minimum TxFIFO size of 3x
2547 * MaxPacketSize is recommended for endpoints that support burst and a
2548 * minimum TxFIFO size of 2x MaxPacketSize for endpoints that don't
2549 * support burst. Use those numbers and we can calculate the max packet
2552 if (dwc
->maximum_speed
>= USB_SPEED_SUPER
)
2557 usb_ep_set_maxpacket_limit(&dep
->endpoint
, size
);
2559 dep
->endpoint
.max_streams
= 16;
2560 dep
->endpoint
.ops
= &dwc3_gadget_ep_ops
;
2561 list_add_tail(&dep
->endpoint
.ep_list
,
2562 &dwc
->gadget
->ep_list
);
2563 dep
->endpoint
.caps
.type_iso
= true;
2564 dep
->endpoint
.caps
.type_bulk
= true;
2565 dep
->endpoint
.caps
.type_int
= true;
2567 return dwc3_alloc_trb_pool(dep
);
2570 static int dwc3_gadget_init_out_endpoint(struct dwc3_ep
*dep
)
2572 struct dwc3
*dwc
= dep
->dwc
;
2576 mdwidth
= DWC3_MDWIDTH(dwc
->hwparams
.hwparams0
);
2577 if (DWC3_IP_IS(DWC32
))
2578 mdwidth
+= DWC3_GHWPARAMS6_MDWIDTH(dwc
->hwparams
.hwparams6
);
2580 /* MDWIDTH is represented in bits, convert to bytes */
2583 /* All OUT endpoints share a single RxFIFO space */
2584 size
= dwc3_readl(dwc
->regs
, DWC3_GRXFIFOSIZ(0));
2585 if (DWC3_IP_IS(DWC3
))
2586 size
= DWC3_GRXFIFOSIZ_RXFDEP(size
);
2588 size
= DWC31_GRXFIFOSIZ_RXFDEP(size
);
2590 /* FIFO depth is in MDWDITH bytes */
2594 * To meet performance requirement, a minimum recommended RxFIFO size
2595 * is defined as follow:
2596 * RxFIFO size >= (3 x MaxPacketSize) +
2597 * (3 x 8 bytes setup packets size) + (16 bytes clock crossing margin)
2599 * Then calculate the max packet limit as below.
2601 size
-= (3 * 8) + 16;
2607 usb_ep_set_maxpacket_limit(&dep
->endpoint
, size
);
2608 dep
->endpoint
.max_streams
= 16;
2609 dep
->endpoint
.ops
= &dwc3_gadget_ep_ops
;
2610 list_add_tail(&dep
->endpoint
.ep_list
,
2611 &dwc
->gadget
->ep_list
);
2612 dep
->endpoint
.caps
.type_iso
= true;
2613 dep
->endpoint
.caps
.type_bulk
= true;
2614 dep
->endpoint
.caps
.type_int
= true;
2616 return dwc3_alloc_trb_pool(dep
);
2619 static int dwc3_gadget_init_endpoint(struct dwc3
*dwc
, u8 epnum
)
2621 struct dwc3_ep
*dep
;
2622 bool direction
= epnum
& 1;
2624 u8 num
= epnum
>> 1;
2626 dep
= kzalloc(sizeof(*dep
), GFP_KERNEL
);
2631 dep
->number
= epnum
;
2632 dep
->direction
= direction
;
2633 dep
->regs
= dwc
->regs
+ DWC3_DEP_BASE(epnum
);
2634 dwc
->eps
[epnum
] = dep
;
2636 dep
->start_cmd_status
= 0;
2638 snprintf(dep
->name
, sizeof(dep
->name
), "ep%u%s", num
,
2639 direction
? "in" : "out");
2641 dep
->endpoint
.name
= dep
->name
;
2643 if (!(dep
->number
> 1)) {
2644 dep
->endpoint
.desc
= &dwc3_gadget_ep0_desc
;
2645 dep
->endpoint
.comp_desc
= NULL
;
2649 ret
= dwc3_gadget_init_control_endpoint(dep
);
2651 ret
= dwc3_gadget_init_in_endpoint(dep
);
2653 ret
= dwc3_gadget_init_out_endpoint(dep
);
2658 dep
->endpoint
.caps
.dir_in
= direction
;
2659 dep
->endpoint
.caps
.dir_out
= !direction
;
2661 INIT_LIST_HEAD(&dep
->pending_list
);
2662 INIT_LIST_HEAD(&dep
->started_list
);
2663 INIT_LIST_HEAD(&dep
->cancelled_list
);
2668 static int dwc3_gadget_init_endpoints(struct dwc3
*dwc
, u8 total
)
2672 INIT_LIST_HEAD(&dwc
->gadget
->ep_list
);
2674 for (epnum
= 0; epnum
< total
; epnum
++) {
2677 ret
= dwc3_gadget_init_endpoint(dwc
, epnum
);
2685 static void dwc3_gadget_free_endpoints(struct dwc3
*dwc
)
2687 struct dwc3_ep
*dep
;
2690 for (epnum
= 0; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
2691 dep
= dwc
->eps
[epnum
];
2695 * Physical endpoints 0 and 1 are special; they form the
2696 * bi-directional USB endpoint 0.
2698 * For those two physical endpoints, we don't allocate a TRB
2699 * pool nor do we add them the endpoints list. Due to that, we
2700 * shouldn't do these two operations otherwise we would end up
2701 * with all sorts of bugs when removing dwc3.ko.
2703 if (epnum
!= 0 && epnum
!= 1) {
2704 dwc3_free_trb_pool(dep
);
2705 list_del(&dep
->endpoint
.ep_list
);
2712 /* -------------------------------------------------------------------------- */
2714 static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep
*dep
,
2715 struct dwc3_request
*req
, struct dwc3_trb
*trb
,
2716 const struct dwc3_event_depevt
*event
, int status
, int chain
)
2720 dwc3_ep_inc_deq(dep
);
2722 trace_dwc3_complete_trb(dep
, trb
);
2726 * If we're in the middle of series of chained TRBs and we
2727 * receive a short transfer along the way, DWC3 will skip
2728 * through all TRBs including the last TRB in the chain (the
2729 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2730 * bit and SW has to do it manually.
2732 * We're going to do that here to avoid problems of HW trying
2733 * to use bogus TRBs for transfers.
2735 if (chain
&& (trb
->ctrl
& DWC3_TRB_CTRL_HWO
))
2736 trb
->ctrl
&= ~DWC3_TRB_CTRL_HWO
;
2739 * For isochronous transfers, the first TRB in a service interval must
2740 * have the Isoc-First type. Track and report its interval frame number.
2742 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) &&
2743 (trb
->ctrl
& DWC3_TRBCTL_ISOCHRONOUS_FIRST
)) {
2744 unsigned int frame_number
;
2746 frame_number
= DWC3_TRB_CTRL_GET_SID_SOFN(trb
->ctrl
);
2747 frame_number
&= ~(dep
->interval
- 1);
2748 req
->request
.frame_number
= frame_number
;
2752 * We use bounce buffer for requests that needs extra TRB or OUT ZLP. If
2753 * this TRB points to the bounce buffer address, it's a MPS alignment
2754 * TRB. Don't add it to req->remaining calculation.
2756 if (trb
->bpl
== lower_32_bits(dep
->dwc
->bounce_addr
) &&
2757 trb
->bph
== upper_32_bits(dep
->dwc
->bounce_addr
)) {
2758 trb
->ctrl
&= ~DWC3_TRB_CTRL_HWO
;
2762 count
= trb
->size
& DWC3_TRB_SIZE_MASK
;
2763 req
->remaining
+= count
;
2765 if ((trb
->ctrl
& DWC3_TRB_CTRL_HWO
) && status
!= -ESHUTDOWN
)
2768 if (event
->status
& DEPEVT_STATUS_SHORT
&& !chain
)
2771 if ((trb
->ctrl
& DWC3_TRB_CTRL_IOC
) ||
2772 (trb
->ctrl
& DWC3_TRB_CTRL_LST
))
2778 static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep
*dep
,
2779 struct dwc3_request
*req
, const struct dwc3_event_depevt
*event
,
2782 struct dwc3_trb
*trb
= &dep
->trb_pool
[dep
->trb_dequeue
];
2783 struct scatterlist
*sg
= req
->sg
;
2784 struct scatterlist
*s
;
2785 unsigned int pending
= req
->num_pending_sgs
;
2789 for_each_sg(sg
, s
, pending
, i
) {
2790 trb
= &dep
->trb_pool
[dep
->trb_dequeue
];
2792 req
->sg
= sg_next(s
);
2793 req
->num_pending_sgs
--;
2795 ret
= dwc3_gadget_ep_reclaim_completed_trb(dep
, req
,
2796 trb
, event
, status
, true);
2804 static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep
*dep
,
2805 struct dwc3_request
*req
, const struct dwc3_event_depevt
*event
,
2808 struct dwc3_trb
*trb
= &dep
->trb_pool
[dep
->trb_dequeue
];
2810 return dwc3_gadget_ep_reclaim_completed_trb(dep
, req
, trb
,
2811 event
, status
, false);
2814 static bool dwc3_gadget_ep_request_completed(struct dwc3_request
*req
)
2816 return req
->num_pending_sgs
== 0;
2819 static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep
*dep
,
2820 const struct dwc3_event_depevt
*event
,
2821 struct dwc3_request
*req
, int status
)
2825 if (req
->num_pending_sgs
)
2826 ret
= dwc3_gadget_ep_reclaim_trb_sg(dep
, req
, event
,
2829 ret
= dwc3_gadget_ep_reclaim_trb_linear(dep
, req
, event
,
2832 req
->request
.actual
= req
->request
.length
- req
->remaining
;
2834 if (!dwc3_gadget_ep_request_completed(req
))
2837 if (req
->needs_extra_trb
) {
2838 ret
= dwc3_gadget_ep_reclaim_trb_linear(dep
, req
, event
,
2840 req
->needs_extra_trb
= false;
2843 dwc3_gadget_giveback(dep
, req
, status
);
2849 static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep
*dep
,
2850 const struct dwc3_event_depevt
*event
, int status
)
2852 struct dwc3_request
*req
;
2853 struct dwc3_request
*tmp
;
2855 list_for_each_entry_safe(req
, tmp
, &dep
->started_list
, list
) {
2858 ret
= dwc3_gadget_ep_cleanup_completed_request(dep
, event
,
2865 static bool dwc3_gadget_ep_should_continue(struct dwc3_ep
*dep
)
2867 struct dwc3_request
*req
;
2869 if (!list_empty(&dep
->pending_list
))
2873 * We only need to check the first entry of the started list. We can
2874 * assume the completed requests are removed from the started list.
2876 req
= next_request(&dep
->started_list
);
2880 return !dwc3_gadget_ep_request_completed(req
);
2883 static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep
*dep
,
2884 const struct dwc3_event_depevt
*event
)
2886 dep
->frame_number
= event
->parameters
;
2889 static bool dwc3_gadget_endpoint_trbs_complete(struct dwc3_ep
*dep
,
2890 const struct dwc3_event_depevt
*event
, int status
)
2892 struct dwc3
*dwc
= dep
->dwc
;
2893 bool no_started_trb
= true;
2895 dwc3_gadget_ep_cleanup_completed_requests(dep
, event
, status
);
2897 if (dep
->flags
& DWC3_EP_END_TRANSFER_PENDING
)
2900 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) &&
2901 list_empty(&dep
->started_list
) &&
2902 (list_empty(&dep
->pending_list
) || status
== -EXDEV
))
2903 dwc3_stop_active_transfer(dep
, true, true);
2904 else if (dwc3_gadget_ep_should_continue(dep
))
2905 if (__dwc3_gadget_kick_transfer(dep
) == 0)
2906 no_started_trb
= false;
2910 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2911 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2913 if (DWC3_VER_IS_PRIOR(DWC3
, 183A
)) {
2917 for (i
= 0; i
< DWC3_ENDPOINTS_NUM
; i
++) {
2920 if (!(dep
->flags
& DWC3_EP_ENABLED
))
2923 if (!list_empty(&dep
->started_list
))
2924 return no_started_trb
;
2927 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2929 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2934 return no_started_trb
;
2937 static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep
*dep
,
2938 const struct dwc3_event_depevt
*event
)
2942 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
2943 dwc3_gadget_endpoint_frame_from_event(dep
, event
);
2945 if (event
->status
& DEPEVT_STATUS_BUSERR
)
2946 status
= -ECONNRESET
;
2948 if (event
->status
& DEPEVT_STATUS_MISSED_ISOC
)
2951 dwc3_gadget_endpoint_trbs_complete(dep
, event
, status
);
2954 static void dwc3_gadget_endpoint_transfer_complete(struct dwc3_ep
*dep
,
2955 const struct dwc3_event_depevt
*event
)
2959 dep
->flags
&= ~DWC3_EP_TRANSFER_STARTED
;
2961 if (event
->status
& DEPEVT_STATUS_BUSERR
)
2962 status
= -ECONNRESET
;
2964 if (dwc3_gadget_endpoint_trbs_complete(dep
, event
, status
))
2965 dep
->flags
&= ~DWC3_EP_WAIT_TRANSFER_COMPLETE
;
2968 static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep
*dep
,
2969 const struct dwc3_event_depevt
*event
)
2971 dwc3_gadget_endpoint_frame_from_event(dep
, event
);
2974 * The XferNotReady event is generated only once before the endpoint
2975 * starts. It will be generated again when END_TRANSFER command is
2976 * issued. For some controller versions, the XferNotReady event may be
2977 * generated while the END_TRANSFER command is still in process. Ignore
2978 * it and wait for the next XferNotReady event after the command is
2981 if (dep
->flags
& DWC3_EP_END_TRANSFER_PENDING
)
2984 (void) __dwc3_gadget_start_isoc(dep
);
2987 static void dwc3_gadget_endpoint_command_complete(struct dwc3_ep
*dep
,
2988 const struct dwc3_event_depevt
*event
)
2990 u8 cmd
= DEPEVT_PARAMETER_CMD(event
->parameters
);
2992 if (cmd
!= DWC3_DEPCMD_ENDTRANSFER
)
2995 dep
->flags
&= ~DWC3_EP_END_TRANSFER_PENDING
;
2996 dep
->flags
&= ~DWC3_EP_TRANSFER_STARTED
;
2997 dwc3_gadget_ep_cleanup_cancelled_requests(dep
);
2999 if (dep
->flags
& DWC3_EP_PENDING_CLEAR_STALL
) {
3000 struct dwc3
*dwc
= dep
->dwc
;
3002 dep
->flags
&= ~DWC3_EP_PENDING_CLEAR_STALL
;
3003 if (dwc3_send_clear_stall_ep_cmd(dep
)) {
3004 struct usb_ep
*ep0
= &dwc
->eps
[0]->endpoint
;
3006 dev_err(dwc
->dev
, "failed to clear STALL on %s\n", dep
->name
);
3007 if (dwc
->delayed_status
)
3008 __dwc3_gadget_ep0_set_halt(ep0
, 1);
3012 dep
->flags
&= ~(DWC3_EP_STALL
| DWC3_EP_WEDGE
);
3013 if (dwc
->delayed_status
)
3014 dwc3_ep0_send_delayed_status(dwc
);
3017 if ((dep
->flags
& DWC3_EP_DELAY_START
) &&
3018 !usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
3019 __dwc3_gadget_kick_transfer(dep
);
3021 dep
->flags
&= ~DWC3_EP_DELAY_START
;
3024 static void dwc3_gadget_endpoint_stream_event(struct dwc3_ep
*dep
,
3025 const struct dwc3_event_depevt
*event
)
3027 struct dwc3
*dwc
= dep
->dwc
;
3029 if (event
->status
== DEPEVT_STREAMEVT_FOUND
) {
3030 dep
->flags
|= DWC3_EP_FIRST_STREAM_PRIMED
;
3034 /* Note: NoStream rejection event param value is 0 and not 0xFFFF */
3035 switch (event
->parameters
) {
3036 case DEPEVT_STREAM_PRIME
:
3038 * If the host can properly transition the endpoint state from
3039 * idle to prime after a NoStream rejection, there's no need to
3040 * force restarting the endpoint to reinitiate the stream. To
3041 * simplify the check, assume the host follows the USB spec if
3042 * it primed the endpoint more than once.
3044 if (dep
->flags
& DWC3_EP_FORCE_RESTART_STREAM
) {
3045 if (dep
->flags
& DWC3_EP_FIRST_STREAM_PRIMED
)
3046 dep
->flags
&= ~DWC3_EP_FORCE_RESTART_STREAM
;
3048 dep
->flags
|= DWC3_EP_FIRST_STREAM_PRIMED
;
3052 case DEPEVT_STREAM_NOSTREAM
:
3053 if ((dep
->flags
& DWC3_EP_IGNORE_NEXT_NOSTREAM
) ||
3054 !(dep
->flags
& DWC3_EP_FORCE_RESTART_STREAM
) ||
3055 !(dep
->flags
& DWC3_EP_WAIT_TRANSFER_COMPLETE
))
3059 * If the host rejects a stream due to no active stream, by the
3060 * USB and xHCI spec, the endpoint will be put back to idle
3061 * state. When the host is ready (buffer added/updated), it will
3062 * prime the endpoint to inform the usb device controller. This
3063 * triggers the device controller to issue ERDY to restart the
3064 * stream. However, some hosts don't follow this and keep the
3065 * endpoint in the idle state. No prime will come despite host
3066 * streams are updated, and the device controller will not be
3067 * triggered to generate ERDY to move the next stream data. To
3068 * workaround this and maintain compatibility with various
3069 * hosts, force to reinitate the stream until the host is ready
3070 * instead of waiting for the host to prime the endpoint.
3072 if (DWC3_VER_IS_WITHIN(DWC32
, 100A
, ANY
)) {
3073 unsigned int cmd
= DWC3_DGCMD_SET_ENDPOINT_PRIME
;
3075 dwc3_send_gadget_generic_command(dwc
, cmd
, dep
->number
);
3077 dep
->flags
|= DWC3_EP_DELAY_START
;
3078 dwc3_stop_active_transfer(dep
, true, true);
3085 dep
->flags
&= ~DWC3_EP_IGNORE_NEXT_NOSTREAM
;
3088 static void dwc3_endpoint_interrupt(struct dwc3
*dwc
,
3089 const struct dwc3_event_depevt
*event
)
3091 struct dwc3_ep
*dep
;
3092 u8 epnum
= event
->endpoint_number
;
3094 dep
= dwc
->eps
[epnum
];
3096 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
3097 if (!(dep
->flags
& DWC3_EP_TRANSFER_STARTED
))
3100 /* Handle only EPCMDCMPLT when EP disabled */
3101 if (event
->endpoint_event
!= DWC3_DEPEVT_EPCMDCMPLT
)
3105 if (epnum
== 0 || epnum
== 1) {
3106 dwc3_ep0_interrupt(dwc
, event
);
3110 switch (event
->endpoint_event
) {
3111 case DWC3_DEPEVT_XFERINPROGRESS
:
3112 dwc3_gadget_endpoint_transfer_in_progress(dep
, event
);
3114 case DWC3_DEPEVT_XFERNOTREADY
:
3115 dwc3_gadget_endpoint_transfer_not_ready(dep
, event
);
3117 case DWC3_DEPEVT_EPCMDCMPLT
:
3118 dwc3_gadget_endpoint_command_complete(dep
, event
);
3120 case DWC3_DEPEVT_XFERCOMPLETE
:
3121 dwc3_gadget_endpoint_transfer_complete(dep
, event
);
3123 case DWC3_DEPEVT_STREAMEVT
:
3124 dwc3_gadget_endpoint_stream_event(dep
, event
);
3126 case DWC3_DEPEVT_RXTXFIFOEVT
:
3131 static void dwc3_disconnect_gadget(struct dwc3
*dwc
)
3133 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->disconnect
) {
3134 spin_unlock(&dwc
->lock
);
3135 dwc
->gadget_driver
->disconnect(dwc
->gadget
);
3136 spin_lock(&dwc
->lock
);
3140 static void dwc3_suspend_gadget(struct dwc3
*dwc
)
3142 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->suspend
) {
3143 spin_unlock(&dwc
->lock
);
3144 dwc
->gadget_driver
->suspend(dwc
->gadget
);
3145 spin_lock(&dwc
->lock
);
3149 static void dwc3_resume_gadget(struct dwc3
*dwc
)
3151 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->resume
) {
3152 spin_unlock(&dwc
->lock
);
3153 dwc
->gadget_driver
->resume(dwc
->gadget
);
3154 spin_lock(&dwc
->lock
);
3158 static void dwc3_reset_gadget(struct dwc3
*dwc
)
3160 if (!dwc
->gadget_driver
)
3163 if (dwc
->gadget
->speed
!= USB_SPEED_UNKNOWN
) {
3164 spin_unlock(&dwc
->lock
);
3165 usb_gadget_udc_reset(dwc
->gadget
, dwc
->gadget_driver
);
3166 spin_lock(&dwc
->lock
);
3170 static void dwc3_stop_active_transfer(struct dwc3_ep
*dep
, bool force
,
3173 struct dwc3_gadget_ep_cmd_params params
;
3177 if (!(dep
->flags
& DWC3_EP_TRANSFER_STARTED
) ||
3178 (dep
->flags
& DWC3_EP_END_TRANSFER_PENDING
))
3182 * NOTICE: We are violating what the Databook says about the
3183 * EndTransfer command. Ideally we would _always_ wait for the
3184 * EndTransfer Command Completion IRQ, but that's causing too
3185 * much trouble synchronizing between us and gadget driver.
3187 * We have discussed this with the IP Provider and it was
3188 * suggested to giveback all requests here.
3190 * Note also that a similar handling was tested by Synopsys
3191 * (thanks a lot Paul) and nothing bad has come out of it.
3192 * In short, what we're doing is issuing EndTransfer with
3193 * CMDIOC bit set and delay kicking transfer until the
3194 * EndTransfer command had completed.
3196 * As of IP version 3.10a of the DWC_usb3 IP, the controller
3197 * supports a mode to work around the above limitation. The
3198 * software can poll the CMDACT bit in the DEPCMD register
3199 * after issuing a EndTransfer command. This mode is enabled
3200 * by writing GUCTL2[14]. This polling is already done in the
3201 * dwc3_send_gadget_ep_cmd() function so if the mode is
3202 * enabled, the EndTransfer command will have completed upon
3203 * returning from this function.
3205 * This mode is NOT available on the DWC_usb31 IP.
3208 cmd
= DWC3_DEPCMD_ENDTRANSFER
;
3209 cmd
|= force
? DWC3_DEPCMD_HIPRI_FORCERM
: 0;
3210 cmd
|= interrupt
? DWC3_DEPCMD_CMDIOC
: 0;
3211 cmd
|= DWC3_DEPCMD_PARAM(dep
->resource_index
);
3212 memset(¶ms
, 0, sizeof(params
));
3213 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
3215 dep
->resource_index
= 0;
3218 * The END_TRANSFER command will cause the controller to generate a
3219 * NoStream Event, and it's not due to the host DP NoStream rejection.
3220 * Ignore the next NoStream event.
3222 if (dep
->stream_capable
)
3223 dep
->flags
|= DWC3_EP_IGNORE_NEXT_NOSTREAM
;
3226 dep
->flags
&= ~DWC3_EP_TRANSFER_STARTED
;
3228 dep
->flags
|= DWC3_EP_END_TRANSFER_PENDING
;
3231 static void dwc3_clear_stall_all_ep(struct dwc3
*dwc
)
3235 for (epnum
= 1; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
3236 struct dwc3_ep
*dep
;
3239 dep
= dwc
->eps
[epnum
];
3243 if (!(dep
->flags
& DWC3_EP_STALL
))
3246 dep
->flags
&= ~DWC3_EP_STALL
;
3248 ret
= dwc3_send_clear_stall_ep_cmd(dep
);
3253 static void dwc3_gadget_disconnect_interrupt(struct dwc3
*dwc
)
3257 dwc3_gadget_set_link_state(dwc
, DWC3_LINK_STATE_RX_DET
);
3259 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
3260 reg
&= ~DWC3_DCTL_INITU1ENA
;
3261 reg
&= ~DWC3_DCTL_INITU2ENA
;
3262 dwc3_gadget_dctl_write_safe(dwc
, reg
);
3264 dwc3_disconnect_gadget(dwc
);
3266 dwc
->gadget
->speed
= USB_SPEED_UNKNOWN
;
3267 dwc
->setup_packet_pending
= false;
3268 usb_gadget_set_state(dwc
->gadget
, USB_STATE_NOTATTACHED
);
3270 dwc
->connected
= false;
3273 static void dwc3_gadget_reset_interrupt(struct dwc3
*dwc
)
3278 * Ideally, dwc3_reset_gadget() would trigger the function
3279 * drivers to stop any active transfers through ep disable.
3280 * However, for functions which defer ep disable, such as mass
3281 * storage, we will need to rely on the call to stop active
3282 * transfers here, and avoid allowing of request queuing.
3284 dwc
->connected
= false;
3287 * WORKAROUND: DWC3 revisions <1.88a have an issue which
3288 * would cause a missing Disconnect Event if there's a
3289 * pending Setup Packet in the FIFO.
3291 * There's no suggested workaround on the official Bug
3292 * report, which states that "unless the driver/application
3293 * is doing any special handling of a disconnect event,
3294 * there is no functional issue".
3296 * Unfortunately, it turns out that we _do_ some special
3297 * handling of a disconnect event, namely complete all
3298 * pending transfers, notify gadget driver of the
3299 * disconnection, and so on.
3301 * Our suggested workaround is to follow the Disconnect
3302 * Event steps here, instead, based on a setup_packet_pending
3303 * flag. Such flag gets set whenever we have a SETUP_PENDING
3304 * status for EP0 TRBs and gets cleared on XferComplete for the
3309 * STAR#9000466709: RTL: Device : Disconnect event not
3310 * generated if setup packet pending in FIFO
3312 if (DWC3_VER_IS_PRIOR(DWC3
, 188A
)) {
3313 if (dwc
->setup_packet_pending
)
3314 dwc3_gadget_disconnect_interrupt(dwc
);
3317 dwc3_reset_gadget(dwc
);
3319 * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
3320 * Section 4.1.2 Table 4-2, it states that during a USB reset, the SW
3321 * needs to ensure that it sends "a DEPENDXFER command for any active
3324 dwc3_stop_active_transfers(dwc
);
3325 dwc
->connected
= true;
3327 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
3328 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
3329 dwc3_gadget_dctl_write_safe(dwc
, reg
);
3330 dwc
->test_mode
= false;
3331 dwc3_clear_stall_all_ep(dwc
);
3333 /* Reset device address to zero */
3334 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
3335 reg
&= ~(DWC3_DCFG_DEVADDR_MASK
);
3336 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
3339 static void dwc3_gadget_conndone_interrupt(struct dwc3
*dwc
)
3341 struct dwc3_ep
*dep
;
3346 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
3347 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
3351 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
3352 * each time on Connect Done.
3354 * Currently we always use the reset value. If any platform
3355 * wants to set this to a different value, we need to add a
3356 * setting and update GCTL.RAMCLKSEL here.
3360 case DWC3_DSTS_SUPERSPEED_PLUS
:
3361 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
3362 dwc
->gadget
->ep0
->maxpacket
= 512;
3363 dwc
->gadget
->speed
= USB_SPEED_SUPER_PLUS
;
3365 case DWC3_DSTS_SUPERSPEED
:
3367 * WORKAROUND: DWC3 revisions <1.90a have an issue which
3368 * would cause a missing USB3 Reset event.
3370 * In such situations, we should force a USB3 Reset
3371 * event by calling our dwc3_gadget_reset_interrupt()
3376 * STAR#9000483510: RTL: SS : USB3 reset event may
3377 * not be generated always when the link enters poll
3379 if (DWC3_VER_IS_PRIOR(DWC3
, 190A
))
3380 dwc3_gadget_reset_interrupt(dwc
);
3382 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
3383 dwc
->gadget
->ep0
->maxpacket
= 512;
3384 dwc
->gadget
->speed
= USB_SPEED_SUPER
;
3386 case DWC3_DSTS_HIGHSPEED
:
3387 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
3388 dwc
->gadget
->ep0
->maxpacket
= 64;
3389 dwc
->gadget
->speed
= USB_SPEED_HIGH
;
3391 case DWC3_DSTS_FULLSPEED
:
3392 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
3393 dwc
->gadget
->ep0
->maxpacket
= 64;
3394 dwc
->gadget
->speed
= USB_SPEED_FULL
;
3396 case DWC3_DSTS_LOWSPEED
:
3397 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(8);
3398 dwc
->gadget
->ep0
->maxpacket
= 8;
3399 dwc
->gadget
->speed
= USB_SPEED_LOW
;
3403 dwc
->eps
[1]->endpoint
.maxpacket
= dwc
->gadget
->ep0
->maxpacket
;
3405 /* Enable USB2 LPM Capability */
3407 if (!DWC3_VER_IS_WITHIN(DWC3
, ANY
, 194A
) &&
3408 !dwc
->usb2_gadget_lpm_disable
&&
3409 (speed
!= DWC3_DSTS_SUPERSPEED
) &&
3410 (speed
!= DWC3_DSTS_SUPERSPEED_PLUS
)) {
3411 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
3412 reg
|= DWC3_DCFG_LPM_CAP
;
3413 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
3415 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
3416 reg
&= ~(DWC3_DCTL_HIRD_THRES_MASK
| DWC3_DCTL_L1_HIBER_EN
);
3418 reg
|= DWC3_DCTL_HIRD_THRES(dwc
->hird_threshold
|
3419 (dwc
->is_utmi_l1_suspend
<< 4));
3422 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
3423 * DCFG.LPMCap is set, core responses with an ACK and the
3424 * BESL value in the LPM token is less than or equal to LPM
3427 WARN_ONCE(DWC3_VER_IS_PRIOR(DWC3
, 240A
) && dwc
->has_lpm_erratum
,
3428 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
3430 if (dwc
->has_lpm_erratum
&& !DWC3_VER_IS_PRIOR(DWC3
, 240A
))
3431 reg
|= DWC3_DCTL_NYET_THRES(dwc
->lpm_nyet_threshold
);
3433 dwc3_gadget_dctl_write_safe(dwc
, reg
);
3435 if (dwc
->usb2_gadget_lpm_disable
) {
3436 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
3437 reg
&= ~DWC3_DCFG_LPM_CAP
;
3438 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
3441 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
3442 reg
&= ~DWC3_DCTL_HIRD_THRES_MASK
;
3443 dwc3_gadget_dctl_write_safe(dwc
, reg
);
3447 ret
= __dwc3_gadget_ep_enable(dep
, DWC3_DEPCFG_ACTION_MODIFY
);
3449 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
3454 ret
= __dwc3_gadget_ep_enable(dep
, DWC3_DEPCFG_ACTION_MODIFY
);
3456 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
3461 * Configure PHY via GUSB3PIPECTLn if required.
3463 * Update GTXFIFOSIZn
3465 * In both cases reset values should be sufficient.
3469 static void dwc3_gadget_wakeup_interrupt(struct dwc3
*dwc
)
3472 * TODO take core out of low power mode when that's
3476 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->resume
) {
3477 spin_unlock(&dwc
->lock
);
3478 dwc
->gadget_driver
->resume(dwc
->gadget
);
3479 spin_lock(&dwc
->lock
);
3483 static void dwc3_gadget_linksts_change_interrupt(struct dwc3
*dwc
,
3484 unsigned int evtinfo
)
3486 enum dwc3_link_state next
= evtinfo
& DWC3_LINK_STATE_MASK
;
3487 unsigned int pwropt
;
3490 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
3491 * Hibernation mode enabled which would show up when device detects
3492 * host-initiated U3 exit.
3494 * In that case, device will generate a Link State Change Interrupt
3495 * from U3 to RESUME which is only necessary if Hibernation is
3498 * There are no functional changes due to such spurious event and we
3499 * just need to ignore it.
3503 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
3506 pwropt
= DWC3_GHWPARAMS1_EN_PWROPT(dwc
->hwparams
.hwparams1
);
3507 if (DWC3_VER_IS_PRIOR(DWC3
, 250A
) &&
3508 (pwropt
!= DWC3_GHWPARAMS1_EN_PWROPT_HIB
)) {
3509 if ((dwc
->link_state
== DWC3_LINK_STATE_U3
) &&
3510 (next
== DWC3_LINK_STATE_RESUME
)) {
3516 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
3517 * on the link partner, the USB session might do multiple entry/exit
3518 * of low power states before a transfer takes place.
3520 * Due to this problem, we might experience lower throughput. The
3521 * suggested workaround is to disable DCTL[12:9] bits if we're
3522 * transitioning from U1/U2 to U0 and enable those bits again
3523 * after a transfer completes and there are no pending transfers
3524 * on any of the enabled endpoints.
3526 * This is the first half of that workaround.
3530 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
3531 * core send LGO_Ux entering U0
3533 if (DWC3_VER_IS_PRIOR(DWC3
, 183A
)) {
3534 if (next
== DWC3_LINK_STATE_U0
) {
3538 switch (dwc
->link_state
) {
3539 case DWC3_LINK_STATE_U1
:
3540 case DWC3_LINK_STATE_U2
:
3541 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
3542 u1u2
= reg
& (DWC3_DCTL_INITU2ENA
3543 | DWC3_DCTL_ACCEPTU2ENA
3544 | DWC3_DCTL_INITU1ENA
3545 | DWC3_DCTL_ACCEPTU1ENA
);
3548 dwc
->u1u2
= reg
& u1u2
;
3552 dwc3_gadget_dctl_write_safe(dwc
, reg
);
3562 case DWC3_LINK_STATE_U1
:
3563 if (dwc
->speed
== USB_SPEED_SUPER
)
3564 dwc3_suspend_gadget(dwc
);
3566 case DWC3_LINK_STATE_U2
:
3567 case DWC3_LINK_STATE_U3
:
3568 dwc3_suspend_gadget(dwc
);
3570 case DWC3_LINK_STATE_RESUME
:
3571 dwc3_resume_gadget(dwc
);
3578 dwc
->link_state
= next
;
3581 static void dwc3_gadget_suspend_interrupt(struct dwc3
*dwc
,
3582 unsigned int evtinfo
)
3584 enum dwc3_link_state next
= evtinfo
& DWC3_LINK_STATE_MASK
;
3586 if (dwc
->link_state
!= next
&& next
== DWC3_LINK_STATE_U3
)
3587 dwc3_suspend_gadget(dwc
);
3589 dwc
->link_state
= next
;
3592 static void dwc3_gadget_hibernation_interrupt(struct dwc3
*dwc
,
3593 unsigned int evtinfo
)
3595 unsigned int is_ss
= evtinfo
& BIT(4);
3598 * WORKAROUND: DWC3 revison 2.20a with hibernation support
3599 * have a known issue which can cause USB CV TD.9.23 to fail
3602 * Because of this issue, core could generate bogus hibernation
3603 * events which SW needs to ignore.
3607 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
3608 * Device Fallback from SuperSpeed
3610 if (is_ss
^ (dwc
->speed
== USB_SPEED_SUPER
))
3613 /* enter hibernation here */
3616 static void dwc3_gadget_interrupt(struct dwc3
*dwc
,
3617 const struct dwc3_event_devt
*event
)
3619 switch (event
->type
) {
3620 case DWC3_DEVICE_EVENT_DISCONNECT
:
3621 dwc3_gadget_disconnect_interrupt(dwc
);
3623 case DWC3_DEVICE_EVENT_RESET
:
3624 dwc3_gadget_reset_interrupt(dwc
);
3626 case DWC3_DEVICE_EVENT_CONNECT_DONE
:
3627 dwc3_gadget_conndone_interrupt(dwc
);
3629 case DWC3_DEVICE_EVENT_WAKEUP
:
3630 dwc3_gadget_wakeup_interrupt(dwc
);
3632 case DWC3_DEVICE_EVENT_HIBER_REQ
:
3633 if (dev_WARN_ONCE(dwc
->dev
, !dwc
->has_hibernation
,
3634 "unexpected hibernation event\n"))
3637 dwc3_gadget_hibernation_interrupt(dwc
, event
->event_info
);
3639 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE
:
3640 dwc3_gadget_linksts_change_interrupt(dwc
, event
->event_info
);
3642 case DWC3_DEVICE_EVENT_EOPF
:
3643 /* It changed to be suspend event for version 2.30a and above */
3644 if (!DWC3_VER_IS_PRIOR(DWC3
, 230A
)) {
3646 * Ignore suspend event until the gadget enters into
3647 * USB_STATE_CONFIGURED state.
3649 if (dwc
->gadget
->state
>= USB_STATE_CONFIGURED
)
3650 dwc3_gadget_suspend_interrupt(dwc
,
3654 case DWC3_DEVICE_EVENT_SOF
:
3655 case DWC3_DEVICE_EVENT_ERRATIC_ERROR
:
3656 case DWC3_DEVICE_EVENT_CMD_CMPL
:
3657 case DWC3_DEVICE_EVENT_OVERFLOW
:
3660 dev_WARN(dwc
->dev
, "UNKNOWN IRQ %d\n", event
->type
);
3664 static void dwc3_process_event_entry(struct dwc3
*dwc
,
3665 const union dwc3_event
*event
)
3667 trace_dwc3_event(event
->raw
, dwc
);
3669 if (!event
->type
.is_devspec
)
3670 dwc3_endpoint_interrupt(dwc
, &event
->depevt
);
3671 else if (event
->type
.type
== DWC3_EVENT_TYPE_DEV
)
3672 dwc3_gadget_interrupt(dwc
, &event
->devt
);
3674 dev_err(dwc
->dev
, "UNKNOWN IRQ type %d\n", event
->raw
);
3677 static irqreturn_t
dwc3_process_event_buf(struct dwc3_event_buffer
*evt
)
3679 struct dwc3
*dwc
= evt
->dwc
;
3680 irqreturn_t ret
= IRQ_NONE
;
3686 if (!(evt
->flags
& DWC3_EVENT_PENDING
))
3690 union dwc3_event event
;
3692 event
.raw
= *(u32
*) (evt
->cache
+ evt
->lpos
);
3694 dwc3_process_event_entry(dwc
, &event
);
3697 * FIXME we wrap around correctly to the next entry as
3698 * almost all entries are 4 bytes in size. There is one
3699 * entry which has 12 bytes which is a regular entry
3700 * followed by 8 bytes data. ATM I don't know how
3701 * things are organized if we get next to the a
3702 * boundary so I worry about that once we try to handle
3705 evt
->lpos
= (evt
->lpos
+ 4) % evt
->length
;
3710 evt
->flags
&= ~DWC3_EVENT_PENDING
;
3713 /* Unmask interrupt */
3714 reg
= dwc3_readl(dwc
->regs
, DWC3_GEVNTSIZ(0));
3715 reg
&= ~DWC3_GEVNTSIZ_INTMASK
;
3716 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(0), reg
);
3718 if (dwc
->imod_interval
) {
3719 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB
);
3720 dwc3_writel(dwc
->regs
, DWC3_DEV_IMOD(0), dwc
->imod_interval
);
3726 static irqreturn_t
dwc3_thread_interrupt(int irq
, void *_evt
)
3728 struct dwc3_event_buffer
*evt
= _evt
;
3729 struct dwc3
*dwc
= evt
->dwc
;
3730 unsigned long flags
;
3731 irqreturn_t ret
= IRQ_NONE
;
3733 spin_lock_irqsave(&dwc
->lock
, flags
);
3734 ret
= dwc3_process_event_buf(evt
);
3735 spin_unlock_irqrestore(&dwc
->lock
, flags
);
3740 static irqreturn_t
dwc3_check_event_buf(struct dwc3_event_buffer
*evt
)
3742 struct dwc3
*dwc
= evt
->dwc
;
3747 if (pm_runtime_suspended(dwc
->dev
)) {
3748 pm_runtime_get(dwc
->dev
);
3749 disable_irq_nosync(dwc
->irq_gadget
);
3750 dwc
->pending_events
= true;
3755 * With PCIe legacy interrupt, test shows that top-half irq handler can
3756 * be called again after HW interrupt deassertion. Check if bottom-half
3757 * irq event handler completes before caching new event to prevent
3760 if (evt
->flags
& DWC3_EVENT_PENDING
)
3763 count
= dwc3_readl(dwc
->regs
, DWC3_GEVNTCOUNT(0));
3764 count
&= DWC3_GEVNTCOUNT_MASK
;
3769 evt
->flags
|= DWC3_EVENT_PENDING
;
3771 /* Mask interrupt */
3772 reg
= dwc3_readl(dwc
->regs
, DWC3_GEVNTSIZ(0));
3773 reg
|= DWC3_GEVNTSIZ_INTMASK
;
3774 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(0), reg
);
3776 amount
= min(count
, evt
->length
- evt
->lpos
);
3777 memcpy(evt
->cache
+ evt
->lpos
, evt
->buf
+ evt
->lpos
, amount
);
3780 memcpy(evt
->cache
, evt
->buf
, count
- amount
);
3782 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(0), count
);
3784 return IRQ_WAKE_THREAD
;
3787 static irqreturn_t
dwc3_interrupt(int irq
, void *_evt
)
3789 struct dwc3_event_buffer
*evt
= _evt
;
3791 return dwc3_check_event_buf(evt
);
3794 static int dwc3_gadget_get_irq(struct dwc3
*dwc
)
3796 struct platform_device
*dwc3_pdev
= to_platform_device(dwc
->dev
);
3799 irq
= platform_get_irq_byname_optional(dwc3_pdev
, "peripheral");
3803 if (irq
== -EPROBE_DEFER
)
3806 irq
= platform_get_irq_byname_optional(dwc3_pdev
, "dwc_usb3");
3810 if (irq
== -EPROBE_DEFER
)
3813 irq
= platform_get_irq(dwc3_pdev
, 0);
3824 static void dwc_gadget_release(struct device
*dev
)
3826 struct usb_gadget
*gadget
= container_of(dev
, struct usb_gadget
, dev
);
3832 * dwc3_gadget_init - initializes gadget related registers
3833 * @dwc: pointer to our controller context structure
3835 * Returns 0 on success otherwise negative errno.
3837 int dwc3_gadget_init(struct dwc3
*dwc
)
3843 irq
= dwc3_gadget_get_irq(dwc
);
3849 dwc
->irq_gadget
= irq
;
3851 dwc
->ep0_trb
= dma_alloc_coherent(dwc
->sysdev
,
3852 sizeof(*dwc
->ep0_trb
) * 2,
3853 &dwc
->ep0_trb_addr
, GFP_KERNEL
);
3854 if (!dwc
->ep0_trb
) {
3855 dev_err(dwc
->dev
, "failed to allocate ep0 trb\n");
3860 dwc
->setup_buf
= kzalloc(DWC3_EP0_SETUP_SIZE
, GFP_KERNEL
);
3861 if (!dwc
->setup_buf
) {
3866 dwc
->bounce
= dma_alloc_coherent(dwc
->sysdev
, DWC3_BOUNCE_SIZE
,
3867 &dwc
->bounce_addr
, GFP_KERNEL
);
3873 init_completion(&dwc
->ep0_in_setup
);
3874 dwc
->gadget
= kzalloc(sizeof(struct usb_gadget
), GFP_KERNEL
);
3881 usb_initialize_gadget(dwc
->dev
, dwc
->gadget
, dwc_gadget_release
);
3882 dev
= &dwc
->gadget
->dev
;
3883 dev
->platform_data
= dwc
;
3884 dwc
->gadget
->ops
= &dwc3_gadget_ops
;
3885 dwc
->gadget
->speed
= USB_SPEED_UNKNOWN
;
3886 dwc
->gadget
->sg_supported
= true;
3887 dwc
->gadget
->name
= "dwc3-gadget";
3888 dwc
->gadget
->lpm_capable
= !dwc
->usb2_gadget_lpm_disable
;
3891 * FIXME We might be setting max_speed to <SUPER, however versions
3892 * <2.20a of dwc3 have an issue with metastability (documented
3893 * elsewhere in this driver) which tells us we can't set max speed to
3894 * anything lower than SUPER.
3896 * Because gadget.max_speed is only used by composite.c and function
3897 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3898 * to happen so we avoid sending SuperSpeed Capability descriptor
3899 * together with our BOS descriptor as that could confuse host into
3900 * thinking we can handle super speed.
3902 * Note that, in fact, we won't even support GetBOS requests when speed
3903 * is less than super speed because we don't have means, yet, to tell
3904 * composite.c that we are USB 2.0 + LPM ECN.
3906 if (DWC3_VER_IS_PRIOR(DWC3
, 220A
) &&
3907 !dwc
->dis_metastability_quirk
)
3908 dev_info(dwc
->dev
, "changing max_speed on rev %08x\n",
3911 dwc
->gadget
->max_speed
= dwc
->maximum_speed
;
3914 * REVISIT: Here we should clear all pending IRQs to be
3915 * sure we're starting from a well known location.
3918 ret
= dwc3_gadget_init_endpoints(dwc
, dwc
->num_eps
);
3922 ret
= usb_add_gadget(dwc
->gadget
);
3924 dev_err(dwc
->dev
, "failed to add gadget\n");
3928 dwc3_gadget_set_speed(dwc
->gadget
, dwc
->maximum_speed
);
3933 dwc3_gadget_free_endpoints(dwc
);
3935 usb_put_gadget(dwc
->gadget
);
3937 dma_free_coherent(dwc
->sysdev
, DWC3_BOUNCE_SIZE
, dwc
->bounce
,
3941 kfree(dwc
->setup_buf
);
3944 dma_free_coherent(dwc
->sysdev
, sizeof(*dwc
->ep0_trb
) * 2,
3945 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
3951 /* -------------------------------------------------------------------------- */
3953 void dwc3_gadget_exit(struct dwc3
*dwc
)
3955 usb_del_gadget(dwc
->gadget
);
3956 dwc3_gadget_free_endpoints(dwc
);
3957 usb_put_gadget(dwc
->gadget
);
3958 dma_free_coherent(dwc
->sysdev
, DWC3_BOUNCE_SIZE
, dwc
->bounce
,
3960 kfree(dwc
->setup_buf
);
3961 dma_free_coherent(dwc
->sysdev
, sizeof(*dwc
->ep0_trb
) * 2,
3962 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
3965 int dwc3_gadget_suspend(struct dwc3
*dwc
)
3967 if (!dwc
->gadget_driver
)
3970 dwc3_gadget_run_stop(dwc
, false, false);
3971 dwc3_disconnect_gadget(dwc
);
3972 __dwc3_gadget_stop(dwc
);
3977 int dwc3_gadget_resume(struct dwc3
*dwc
)
3981 if (!dwc
->gadget_driver
)
3984 ret
= __dwc3_gadget_start(dwc
);
3988 ret
= dwc3_gadget_run_stop(dwc
, true, false);
3995 __dwc3_gadget_stop(dwc
);
4001 void dwc3_gadget_process_pending_events(struct dwc3
*dwc
)
4003 if (dwc
->pending_events
) {
4004 dwc3_interrupt(dwc
->irq_gadget
, dwc
->ev_buf
);
4005 dwc
->pending_events
= false;
4006 enable_irq(dwc
->irq_gadget
);