1 // SPDX-License-Identifier: GPL-2.0
3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/spinlock.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/interrupt.h>
19 #include <linux/list.h>
20 #include <linux/dma-mapping.h>
22 #include <linux/usb/ch9.h>
23 #include <linux/usb/gadget.h>
31 * dwc3_gadget_set_test_mode - enables usb2 test modes
32 * @dwc: pointer to our context structure
33 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
35 * Caller should take care of locking. This function will return 0 on
36 * success or -EINVAL if wrong Test Selector is passed.
38 int dwc3_gadget_set_test_mode(struct dwc3
*dwc
, int mode
)
42 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
43 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
57 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
63 * dwc3_gadget_get_link_state - gets current state of usb link
64 * @dwc: pointer to our context structure
66 * Caller should take care of locking. This function will
67 * return the link state on success (>= 0) or -ETIMEDOUT.
69 int dwc3_gadget_get_link_state(struct dwc3
*dwc
)
73 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
75 return DWC3_DSTS_USBLNKST(reg
);
79 * dwc3_gadget_set_link_state - sets usb link to a particular state
80 * @dwc: pointer to our context structure
81 * @state: the state to put link into
83 * Caller should take care of locking. This function will
84 * return 0 on success or -ETIMEDOUT.
86 int dwc3_gadget_set_link_state(struct dwc3
*dwc
, enum dwc3_link_state state
)
92 * Wait until device controller is ready. Only applies to 1.94a and
95 if (dwc
->revision
>= DWC3_REVISION_194A
) {
97 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
98 if (reg
& DWC3_DSTS_DCNRD
)
108 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
109 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
111 /* set requested state */
112 reg
|= DWC3_DCTL_ULSTCHNGREQ(state
);
113 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
116 * The following code is racy when called from dwc3_gadget_wakeup,
117 * and is not needed, at least on newer versions
119 if (dwc
->revision
>= DWC3_REVISION_194A
)
122 /* wait for a change in DSTS */
125 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
127 if (DWC3_DSTS_USBLNKST(reg
) == state
)
137 * dwc3_ep_inc_trb - increment a trb index.
138 * @index: Pointer to the TRB index to increment.
140 * The index should never point to the link TRB. After incrementing,
141 * if it is point to the link TRB, wrap around to the beginning. The
142 * link TRB is always at the last TRB entry.
144 static void dwc3_ep_inc_trb(u8
*index
)
147 if (*index
== (DWC3_TRB_NUM
- 1))
152 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
153 * @dep: The endpoint whose enqueue pointer we're incrementing
155 static void dwc3_ep_inc_enq(struct dwc3_ep
*dep
)
157 dwc3_ep_inc_trb(&dep
->trb_enqueue
);
161 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
162 * @dep: The endpoint whose enqueue pointer we're incrementing
164 static void dwc3_ep_inc_deq(struct dwc3_ep
*dep
)
166 dwc3_ep_inc_trb(&dep
->trb_dequeue
);
169 void dwc3_gadget_del_and_unmap_request(struct dwc3_ep
*dep
,
170 struct dwc3_request
*req
, int status
)
172 struct dwc3
*dwc
= dep
->dwc
;
174 req
->started
= false;
175 list_del(&req
->list
);
177 req
->unaligned
= false;
180 if (req
->request
.status
== -EINPROGRESS
)
181 req
->request
.status
= status
;
184 usb_gadget_unmap_request_by_dev(dwc
->sysdev
,
185 &req
->request
, req
->direction
);
188 trace_dwc3_gadget_giveback(req
);
191 pm_runtime_put(dwc
->dev
);
195 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
196 * @dep: The endpoint to whom the request belongs to
197 * @req: The request we're giving back
198 * @status: completion code for the request
200 * Must be called with controller's lock held and interrupts disabled. This
201 * function will unmap @req and call its ->complete() callback to notify upper
202 * layers that it has completed.
204 void dwc3_gadget_giveback(struct dwc3_ep
*dep
, struct dwc3_request
*req
,
207 struct dwc3
*dwc
= dep
->dwc
;
209 dwc3_gadget_del_and_unmap_request(dep
, req
, status
);
211 spin_unlock(&dwc
->lock
);
212 usb_gadget_giveback_request(&dep
->endpoint
, &req
->request
);
213 spin_lock(&dwc
->lock
);
217 * dwc3_send_gadget_generic_command - issue a generic command for the controller
218 * @dwc: pointer to the controller context
219 * @cmd: the command to be issued
220 * @param: command parameter
222 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
223 * and wait for its completion.
225 int dwc3_send_gadget_generic_command(struct dwc3
*dwc
, unsigned cmd
, u32 param
)
232 dwc3_writel(dwc
->regs
, DWC3_DGCMDPAR
, param
);
233 dwc3_writel(dwc
->regs
, DWC3_DGCMD
, cmd
| DWC3_DGCMD_CMDACT
);
236 reg
= dwc3_readl(dwc
->regs
, DWC3_DGCMD
);
237 if (!(reg
& DWC3_DGCMD_CMDACT
)) {
238 status
= DWC3_DGCMD_STATUS(reg
);
250 trace_dwc3_gadget_generic_cmd(cmd
, param
, status
);
255 static int __dwc3_gadget_wakeup(struct dwc3
*dwc
);
258 * dwc3_send_gadget_ep_cmd - issue an endpoint command
259 * @dep: the endpoint to which the command is going to be issued
260 * @cmd: the command to be issued
261 * @params: parameters to the command
263 * Caller should handle locking. This function will issue @cmd with given
264 * @params to @dep and wait for its completion.
266 int dwc3_send_gadget_ep_cmd(struct dwc3_ep
*dep
, unsigned cmd
,
267 struct dwc3_gadget_ep_cmd_params
*params
)
269 const struct usb_endpoint_descriptor
*desc
= dep
->endpoint
.desc
;
270 struct dwc3
*dwc
= dep
->dwc
;
279 * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
280 * we're issuing an endpoint command, we must check if
281 * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
283 * We will also set SUSPHY bit to what it was before returning as stated
284 * by the same section on Synopsys databook.
286 if (dwc
->gadget
.speed
<= USB_SPEED_HIGH
) {
287 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
288 if (unlikely(reg
& DWC3_GUSB2PHYCFG_SUSPHY
)) {
290 reg
&= ~DWC3_GUSB2PHYCFG_SUSPHY
;
291 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
295 if (DWC3_DEPCMD_CMD(cmd
) == DWC3_DEPCMD_STARTTRANSFER
) {
298 needs_wakeup
= (dwc
->link_state
== DWC3_LINK_STATE_U1
||
299 dwc
->link_state
== DWC3_LINK_STATE_U2
||
300 dwc
->link_state
== DWC3_LINK_STATE_U3
);
302 if (unlikely(needs_wakeup
)) {
303 ret
= __dwc3_gadget_wakeup(dwc
);
304 dev_WARN_ONCE(dwc
->dev
, ret
, "wakeup failed --> %d\n",
309 dwc3_writel(dep
->regs
, DWC3_DEPCMDPAR0
, params
->param0
);
310 dwc3_writel(dep
->regs
, DWC3_DEPCMDPAR1
, params
->param1
);
311 dwc3_writel(dep
->regs
, DWC3_DEPCMDPAR2
, params
->param2
);
314 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
315 * not relying on XferNotReady, we can make use of a special "No
316 * Response Update Transfer" command where we should clear both CmdAct
319 * With this, we don't need to wait for command completion and can
320 * straight away issue further commands to the endpoint.
322 * NOTICE: We're making an assumption that control endpoints will never
323 * make use of Update Transfer command. This is a safe assumption
324 * because we can never have more than one request at a time with
325 * Control Endpoints. If anybody changes that assumption, this chunk
326 * needs to be updated accordingly.
328 if (DWC3_DEPCMD_CMD(cmd
) == DWC3_DEPCMD_UPDATETRANSFER
&&
329 !usb_endpoint_xfer_isoc(desc
))
330 cmd
&= ~(DWC3_DEPCMD_CMDIOC
| DWC3_DEPCMD_CMDACT
);
332 cmd
|= DWC3_DEPCMD_CMDACT
;
334 dwc3_writel(dep
->regs
, DWC3_DEPCMD
, cmd
);
336 reg
= dwc3_readl(dep
->regs
, DWC3_DEPCMD
);
337 if (!(reg
& DWC3_DEPCMD_CMDACT
)) {
338 cmd_status
= DWC3_DEPCMD_STATUS(reg
);
340 switch (cmd_status
) {
344 case DEPEVT_TRANSFER_NO_RESOURCE
:
347 case DEPEVT_TRANSFER_BUS_EXPIRY
:
349 * SW issues START TRANSFER command to
350 * isochronous ep with future frame interval. If
351 * future interval time has already passed when
352 * core receives the command, it will respond
353 * with an error status of 'Bus Expiry'.
355 * Instead of always returning -EINVAL, let's
356 * give a hint to the gadget driver that this is
357 * the case by returning -EAGAIN.
362 dev_WARN(dwc
->dev
, "UNKNOWN cmd status\n");
371 cmd_status
= -ETIMEDOUT
;
374 trace_dwc3_gadget_ep_cmd(dep
, cmd
, params
, cmd_status
);
377 switch (DWC3_DEPCMD_CMD(cmd
)) {
378 case DWC3_DEPCMD_STARTTRANSFER
:
379 dep
->flags
|= DWC3_EP_TRANSFER_STARTED
;
381 case DWC3_DEPCMD_ENDTRANSFER
:
382 dep
->flags
&= ~DWC3_EP_TRANSFER_STARTED
;
390 if (unlikely(susphy
)) {
391 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
392 reg
|= DWC3_GUSB2PHYCFG_SUSPHY
;
393 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
399 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep
*dep
)
401 struct dwc3
*dwc
= dep
->dwc
;
402 struct dwc3_gadget_ep_cmd_params params
;
403 u32 cmd
= DWC3_DEPCMD_CLEARSTALL
;
406 * As of core revision 2.60a the recommended programming model
407 * is to set the ClearPendIN bit when issuing a Clear Stall EP
408 * command for IN endpoints. This is to prevent an issue where
409 * some (non-compliant) hosts may not send ACK TPs for pending
410 * IN transfers due to a mishandled error condition. Synopsys
413 if (dep
->direction
&& (dwc
->revision
>= DWC3_REVISION_260A
) &&
414 (dwc
->gadget
.speed
>= USB_SPEED_SUPER
))
415 cmd
|= DWC3_DEPCMD_CLEARPENDIN
;
417 memset(¶ms
, 0, sizeof(params
));
419 return dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
422 static dma_addr_t
dwc3_trb_dma_offset(struct dwc3_ep
*dep
,
423 struct dwc3_trb
*trb
)
425 u32 offset
= (char *) trb
- (char *) dep
->trb_pool
;
427 return dep
->trb_pool_dma
+ offset
;
430 static int dwc3_alloc_trb_pool(struct dwc3_ep
*dep
)
432 struct dwc3
*dwc
= dep
->dwc
;
437 dep
->trb_pool
= dma_alloc_coherent(dwc
->sysdev
,
438 sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
439 &dep
->trb_pool_dma
, GFP_KERNEL
);
440 if (!dep
->trb_pool
) {
441 dev_err(dep
->dwc
->dev
, "failed to allocate trb pool for %s\n",
449 static void dwc3_free_trb_pool(struct dwc3_ep
*dep
)
451 struct dwc3
*dwc
= dep
->dwc
;
453 dma_free_coherent(dwc
->sysdev
, sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
454 dep
->trb_pool
, dep
->trb_pool_dma
);
456 dep
->trb_pool
= NULL
;
457 dep
->trb_pool_dma
= 0;
460 static int dwc3_gadget_set_xfer_resource(struct dwc3
*dwc
, struct dwc3_ep
*dep
);
463 * dwc3_gadget_start_config - configure ep resources
464 * @dwc: pointer to our controller context structure
465 * @dep: endpoint that is being enabled
467 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
468 * completion, it will set Transfer Resource for all available endpoints.
470 * The assignment of transfer resources cannot perfectly follow the data book
471 * due to the fact that the controller driver does not have all knowledge of the
472 * configuration in advance. It is given this information piecemeal by the
473 * composite gadget framework after every SET_CONFIGURATION and
474 * SET_INTERFACE. Trying to follow the databook programming model in this
475 * scenario can cause errors. For two reasons:
477 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
478 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
479 * incorrect in the scenario of multiple interfaces.
481 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
482 * endpoint on alt setting (8.1.6).
484 * The following simplified method is used instead:
486 * All hardware endpoints can be assigned a transfer resource and this setting
487 * will stay persistent until either a core reset or hibernation. So whenever we
488 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
489 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
490 * guaranteed that there are as many transfer resources as endpoints.
492 * This function is called for each endpoint when it is being enabled but is
493 * triggered only when called for EP0-out, which always happens first, and which
494 * should only happen in one of the above conditions.
496 static int dwc3_gadget_start_config(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
498 struct dwc3_gadget_ep_cmd_params params
;
506 memset(¶ms
, 0x00, sizeof(params
));
507 cmd
= DWC3_DEPCMD_DEPSTARTCFG
;
509 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
513 for (i
= 0; i
< DWC3_ENDPOINTS_NUM
; i
++) {
514 struct dwc3_ep
*dep
= dwc
->eps
[i
];
519 ret
= dwc3_gadget_set_xfer_resource(dwc
, dep
);
527 static int dwc3_gadget_set_ep_config(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
528 bool modify
, bool restore
)
530 const struct usb_ss_ep_comp_descriptor
*comp_desc
;
531 const struct usb_endpoint_descriptor
*desc
;
532 struct dwc3_gadget_ep_cmd_params params
;
534 if (dev_WARN_ONCE(dwc
->dev
, modify
&& restore
,
535 "Can't modify and restore\n"))
538 comp_desc
= dep
->endpoint
.comp_desc
;
539 desc
= dep
->endpoint
.desc
;
541 memset(¶ms
, 0x00, sizeof(params
));
543 params
.param0
= DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc
))
544 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc
));
546 /* Burst size is only needed in SuperSpeed mode */
547 if (dwc
->gadget
.speed
>= USB_SPEED_SUPER
) {
548 u32 burst
= dep
->endpoint
.maxburst
;
549 params
.param0
|= DWC3_DEPCFG_BURST_SIZE(burst
- 1);
553 params
.param0
|= DWC3_DEPCFG_ACTION_MODIFY
;
554 } else if (restore
) {
555 params
.param0
|= DWC3_DEPCFG_ACTION_RESTORE
;
556 params
.param2
|= dep
->saved_state
;
558 params
.param0
|= DWC3_DEPCFG_ACTION_INIT
;
561 if (usb_endpoint_xfer_control(desc
))
562 params
.param1
= DWC3_DEPCFG_XFER_COMPLETE_EN
;
564 if (dep
->number
<= 1 || usb_endpoint_xfer_isoc(desc
))
565 params
.param1
|= DWC3_DEPCFG_XFER_NOT_READY_EN
;
567 if (usb_ss_max_streams(comp_desc
) && usb_endpoint_xfer_bulk(desc
)) {
568 params
.param1
|= DWC3_DEPCFG_STREAM_CAPABLE
569 | DWC3_DEPCFG_STREAM_EVENT_EN
;
570 dep
->stream_capable
= true;
573 if (!usb_endpoint_xfer_control(desc
))
574 params
.param1
|= DWC3_DEPCFG_XFER_IN_PROGRESS_EN
;
577 * We are doing 1:1 mapping for endpoints, meaning
578 * Physical Endpoints 2 maps to Logical Endpoint 2 and
579 * so on. We consider the direction bit as part of the physical
580 * endpoint number. So USB endpoint 0x81 is 0x03.
582 params
.param1
|= DWC3_DEPCFG_EP_NUMBER(dep
->number
);
585 * We must use the lower 16 TX FIFOs even though
589 params
.param0
|= DWC3_DEPCFG_FIFO_NUMBER(dep
->number
>> 1);
591 if (desc
->bInterval
) {
592 params
.param1
|= DWC3_DEPCFG_BINTERVAL_M1(desc
->bInterval
- 1);
593 dep
->interval
= 1 << (desc
->bInterval
- 1);
596 return dwc3_send_gadget_ep_cmd(dep
, DWC3_DEPCMD_SETEPCONFIG
, ¶ms
);
599 static int dwc3_gadget_set_xfer_resource(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
601 struct dwc3_gadget_ep_cmd_params params
;
603 memset(¶ms
, 0x00, sizeof(params
));
605 params
.param0
= DWC3_DEPXFERCFG_NUM_XFER_RES(1);
607 return dwc3_send_gadget_ep_cmd(dep
, DWC3_DEPCMD_SETTRANSFRESOURCE
,
612 * __dwc3_gadget_ep_enable - initializes a hw endpoint
613 * @dep: endpoint to be initialized
614 * @modify: if true, modify existing endpoint configuration
615 * @restore: if true, restore endpoint configuration from scratch buffer
617 * Caller should take care of locking. Execute all necessary commands to
618 * initialize a HW endpoint so it can be used by a gadget driver.
620 static int __dwc3_gadget_ep_enable(struct dwc3_ep
*dep
,
621 bool modify
, bool restore
)
623 const struct usb_endpoint_descriptor
*desc
= dep
->endpoint
.desc
;
624 struct dwc3
*dwc
= dep
->dwc
;
629 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
630 ret
= dwc3_gadget_start_config(dwc
, dep
);
635 ret
= dwc3_gadget_set_ep_config(dwc
, dep
, modify
, restore
);
639 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
640 struct dwc3_trb
*trb_st_hw
;
641 struct dwc3_trb
*trb_link
;
643 dep
->type
= usb_endpoint_type(desc
);
644 dep
->flags
|= DWC3_EP_ENABLED
;
645 dep
->flags
&= ~DWC3_EP_END_TRANSFER_PENDING
;
647 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
648 reg
|= DWC3_DALEPENA_EP(dep
->number
);
649 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
651 init_waitqueue_head(&dep
->wait_end_transfer
);
653 if (usb_endpoint_xfer_control(desc
))
656 /* Initialize the TRB ring */
657 dep
->trb_dequeue
= 0;
658 dep
->trb_enqueue
= 0;
659 memset(dep
->trb_pool
, 0,
660 sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
);
662 /* Link TRB. The HWO bit is never reset */
663 trb_st_hw
= &dep
->trb_pool
[0];
665 trb_link
= &dep
->trb_pool
[DWC3_TRB_NUM
- 1];
666 trb_link
->bpl
= lower_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
667 trb_link
->bph
= upper_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
668 trb_link
->ctrl
|= DWC3_TRBCTL_LINK_TRB
;
669 trb_link
->ctrl
|= DWC3_TRB_CTRL_HWO
;
673 * Issue StartTransfer here with no-op TRB so we can always rely on No
674 * Response Update Transfer command.
676 if (usb_endpoint_xfer_bulk(desc
)) {
677 struct dwc3_gadget_ep_cmd_params params
;
678 struct dwc3_trb
*trb
;
682 memset(¶ms
, 0, sizeof(params
));
683 trb
= &dep
->trb_pool
[0];
684 trb_dma
= dwc3_trb_dma_offset(dep
, trb
);
686 params
.param0
= upper_32_bits(trb_dma
);
687 params
.param1
= lower_32_bits(trb_dma
);
689 cmd
= DWC3_DEPCMD_STARTTRANSFER
;
691 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
695 dep
->flags
|= DWC3_EP_BUSY
;
697 dep
->resource_index
= dwc3_gadget_ep_get_transfer_index(dep
);
698 WARN_ON_ONCE(!dep
->resource_index
);
703 trace_dwc3_gadget_ep_enable(dep
);
708 static void dwc3_stop_active_transfer(struct dwc3
*dwc
, u32 epnum
, bool force
);
709 static void dwc3_remove_requests(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
711 struct dwc3_request
*req
;
713 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
715 /* - giveback all requests to gadget driver */
716 while (!list_empty(&dep
->started_list
)) {
717 req
= next_request(&dep
->started_list
);
719 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
722 while (!list_empty(&dep
->pending_list
)) {
723 req
= next_request(&dep
->pending_list
);
725 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
730 * __dwc3_gadget_ep_disable - disables a hw endpoint
731 * @dep: the endpoint to disable
733 * This function undoes what __dwc3_gadget_ep_enable did and also removes
734 * requests which are currently being processed by the hardware and those which
735 * are not yet scheduled.
737 * Caller should take care of locking.
739 static int __dwc3_gadget_ep_disable(struct dwc3_ep
*dep
)
741 struct dwc3
*dwc
= dep
->dwc
;
744 trace_dwc3_gadget_ep_disable(dep
);
746 dwc3_remove_requests(dwc
, dep
);
748 /* make sure HW endpoint isn't stalled */
749 if (dep
->flags
& DWC3_EP_STALL
)
750 __dwc3_gadget_ep_set_halt(dep
, 0, false);
752 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
753 reg
&= ~DWC3_DALEPENA_EP(dep
->number
);
754 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
756 dep
->stream_capable
= false;
758 dep
->flags
&= DWC3_EP_END_TRANSFER_PENDING
;
760 /* Clear out the ep descriptors for non-ep0 */
761 if (dep
->number
> 1) {
762 dep
->endpoint
.comp_desc
= NULL
;
763 dep
->endpoint
.desc
= NULL
;
769 /* -------------------------------------------------------------------------- */
771 static int dwc3_gadget_ep0_enable(struct usb_ep
*ep
,
772 const struct usb_endpoint_descriptor
*desc
)
777 static int dwc3_gadget_ep0_disable(struct usb_ep
*ep
)
782 /* -------------------------------------------------------------------------- */
784 static int dwc3_gadget_ep_enable(struct usb_ep
*ep
,
785 const struct usb_endpoint_descriptor
*desc
)
792 if (!ep
|| !desc
|| desc
->bDescriptorType
!= USB_DT_ENDPOINT
) {
793 pr_debug("dwc3: invalid parameters\n");
797 if (!desc
->wMaxPacketSize
) {
798 pr_debug("dwc3: missing wMaxPacketSize\n");
802 dep
= to_dwc3_ep(ep
);
805 if (dev_WARN_ONCE(dwc
->dev
, dep
->flags
& DWC3_EP_ENABLED
,
806 "%s is already enabled\n",
810 spin_lock_irqsave(&dwc
->lock
, flags
);
811 ret
= __dwc3_gadget_ep_enable(dep
, false, false);
812 spin_unlock_irqrestore(&dwc
->lock
, flags
);
817 static int dwc3_gadget_ep_disable(struct usb_ep
*ep
)
825 pr_debug("dwc3: invalid parameters\n");
829 dep
= to_dwc3_ep(ep
);
832 if (dev_WARN_ONCE(dwc
->dev
, !(dep
->flags
& DWC3_EP_ENABLED
),
833 "%s is already disabled\n",
837 spin_lock_irqsave(&dwc
->lock
, flags
);
838 ret
= __dwc3_gadget_ep_disable(dep
);
839 spin_unlock_irqrestore(&dwc
->lock
, flags
);
844 static struct usb_request
*dwc3_gadget_ep_alloc_request(struct usb_ep
*ep
,
847 struct dwc3_request
*req
;
848 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
850 req
= kzalloc(sizeof(*req
), gfp_flags
);
854 req
->epnum
= dep
->number
;
857 dep
->allocated_requests
++;
859 trace_dwc3_alloc_request(req
);
861 return &req
->request
;
864 static void dwc3_gadget_ep_free_request(struct usb_ep
*ep
,
865 struct usb_request
*request
)
867 struct dwc3_request
*req
= to_dwc3_request(request
);
868 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
870 dep
->allocated_requests
--;
871 trace_dwc3_free_request(req
);
875 static u32
dwc3_calc_trbs_left(struct dwc3_ep
*dep
);
877 static void __dwc3_prepare_one_trb(struct dwc3_ep
*dep
, struct dwc3_trb
*trb
,
878 dma_addr_t dma
, unsigned length
, unsigned chain
, unsigned node
,
879 unsigned stream_id
, unsigned short_not_ok
, unsigned no_interrupt
)
881 struct dwc3
*dwc
= dep
->dwc
;
882 struct usb_gadget
*gadget
= &dwc
->gadget
;
883 enum usb_device_speed speed
= gadget
->speed
;
885 trb
->size
= DWC3_TRB_SIZE_LENGTH(length
);
886 trb
->bpl
= lower_32_bits(dma
);
887 trb
->bph
= upper_32_bits(dma
);
889 switch (usb_endpoint_type(dep
->endpoint
.desc
)) {
890 case USB_ENDPOINT_XFER_CONTROL
:
891 trb
->ctrl
= DWC3_TRBCTL_CONTROL_SETUP
;
894 case USB_ENDPOINT_XFER_ISOC
:
896 trb
->ctrl
= DWC3_TRBCTL_ISOCHRONOUS_FIRST
;
899 * USB Specification 2.0 Section 5.9.2 states that: "If
900 * there is only a single transaction in the microframe,
901 * only a DATA0 data packet PID is used. If there are
902 * two transactions per microframe, DATA1 is used for
903 * the first transaction data packet and DATA0 is used
904 * for the second transaction data packet. If there are
905 * three transactions per microframe, DATA2 is used for
906 * the first transaction data packet, DATA1 is used for
907 * the second, and DATA0 is used for the third."
909 * IOW, we should satisfy the following cases:
911 * 1) length <= maxpacket
914 * 2) maxpacket < length <= (2 * maxpacket)
917 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
918 * - DATA2, DATA1, DATA0
920 if (speed
== USB_SPEED_HIGH
) {
921 struct usb_ep
*ep
= &dep
->endpoint
;
922 unsigned int mult
= 2;
923 unsigned int maxp
= usb_endpoint_maxp(ep
->desc
);
925 if (length
<= (2 * maxp
))
931 trb
->size
|= DWC3_TRB_SIZE_PCM1(mult
);
934 trb
->ctrl
= DWC3_TRBCTL_ISOCHRONOUS
;
937 /* always enable Interrupt on Missed ISOC */
938 trb
->ctrl
|= DWC3_TRB_CTRL_ISP_IMI
;
941 case USB_ENDPOINT_XFER_BULK
:
942 case USB_ENDPOINT_XFER_INT
:
943 trb
->ctrl
= DWC3_TRBCTL_NORMAL
;
947 * This is only possible with faulty memory because we
948 * checked it already :)
950 dev_WARN(dwc
->dev
, "Unknown endpoint type %d\n",
951 usb_endpoint_type(dep
->endpoint
.desc
));
955 * Enable Continue on Short Packet
956 * when endpoint is not a stream capable
958 if (usb_endpoint_dir_out(dep
->endpoint
.desc
)) {
959 if (!dep
->stream_capable
)
960 trb
->ctrl
|= DWC3_TRB_CTRL_CSP
;
963 trb
->ctrl
|= DWC3_TRB_CTRL_ISP_IMI
;
966 if ((!no_interrupt
&& !chain
) ||
967 (dwc3_calc_trbs_left(dep
) == 1))
968 trb
->ctrl
|= DWC3_TRB_CTRL_IOC
;
971 trb
->ctrl
|= DWC3_TRB_CTRL_CHN
;
973 if (usb_endpoint_xfer_bulk(dep
->endpoint
.desc
) && dep
->stream_capable
)
974 trb
->ctrl
|= DWC3_TRB_CTRL_SID_SOFN(stream_id
);
976 trb
->ctrl
|= DWC3_TRB_CTRL_HWO
;
978 dwc3_ep_inc_enq(dep
);
980 trace_dwc3_prepare_trb(dep
, trb
);
984 * dwc3_prepare_one_trb - setup one TRB from one request
985 * @dep: endpoint for which this request is prepared
986 * @req: dwc3_request pointer
987 * @chain: should this TRB be chained to the next?
988 * @node: only for isochronous endpoints. First TRB needs different type.
990 static void dwc3_prepare_one_trb(struct dwc3_ep
*dep
,
991 struct dwc3_request
*req
, unsigned chain
, unsigned node
)
993 struct dwc3_trb
*trb
;
994 unsigned length
= req
->request
.length
;
995 unsigned stream_id
= req
->request
.stream_id
;
996 unsigned short_not_ok
= req
->request
.short_not_ok
;
997 unsigned no_interrupt
= req
->request
.no_interrupt
;
998 dma_addr_t dma
= req
->request
.dma
;
1000 trb
= &dep
->trb_pool
[dep
->trb_enqueue
];
1003 dwc3_gadget_move_started_request(req
);
1005 req
->trb_dma
= dwc3_trb_dma_offset(dep
, trb
);
1006 dep
->queued_requests
++;
1009 __dwc3_prepare_one_trb(dep
, trb
, dma
, length
, chain
, node
,
1010 stream_id
, short_not_ok
, no_interrupt
);
1014 * dwc3_ep_prev_trb - returns the previous TRB in the ring
1015 * @dep: The endpoint with the TRB ring
1016 * @index: The index of the current TRB in the ring
1018 * Returns the TRB prior to the one pointed to by the index. If the
1019 * index is 0, we will wrap backwards, skip the link TRB, and return
1020 * the one just before that.
1022 static struct dwc3_trb
*dwc3_ep_prev_trb(struct dwc3_ep
*dep
, u8 index
)
1027 tmp
= DWC3_TRB_NUM
- 1;
1029 return &dep
->trb_pool
[tmp
- 1];
1032 static u32
dwc3_calc_trbs_left(struct dwc3_ep
*dep
)
1034 struct dwc3_trb
*tmp
;
1038 * If enqueue & dequeue are equal than it is either full or empty.
1040 * One way to know for sure is if the TRB right before us has HWO bit
1041 * set or not. If it has, then we're definitely full and can't fit any
1042 * more transfers in our ring.
1044 if (dep
->trb_enqueue
== dep
->trb_dequeue
) {
1045 tmp
= dwc3_ep_prev_trb(dep
, dep
->trb_enqueue
);
1046 if (tmp
->ctrl
& DWC3_TRB_CTRL_HWO
)
1049 return DWC3_TRB_NUM
- 1;
1052 trbs_left
= dep
->trb_dequeue
- dep
->trb_enqueue
;
1053 trbs_left
&= (DWC3_TRB_NUM
- 1);
1055 if (dep
->trb_dequeue
< dep
->trb_enqueue
)
1061 static void dwc3_prepare_one_trb_sg(struct dwc3_ep
*dep
,
1062 struct dwc3_request
*req
)
1064 struct scatterlist
*sg
= req
->sg
;
1065 struct scatterlist
*s
;
1068 for_each_sg(sg
, s
, req
->num_pending_sgs
, i
) {
1069 unsigned int length
= req
->request
.length
;
1070 unsigned int maxp
= usb_endpoint_maxp(dep
->endpoint
.desc
);
1071 unsigned int rem
= length
% maxp
;
1072 unsigned chain
= true;
1077 if (rem
&& usb_endpoint_dir_out(dep
->endpoint
.desc
) && !chain
) {
1078 struct dwc3
*dwc
= dep
->dwc
;
1079 struct dwc3_trb
*trb
;
1081 req
->unaligned
= true;
1083 /* prepare normal TRB */
1084 dwc3_prepare_one_trb(dep
, req
, true, i
);
1086 /* Now prepare one extra TRB to align transfer size */
1087 trb
= &dep
->trb_pool
[dep
->trb_enqueue
];
1088 __dwc3_prepare_one_trb(dep
, trb
, dwc
->bounce_addr
,
1089 maxp
- rem
, false, 1,
1090 req
->request
.stream_id
,
1091 req
->request
.short_not_ok
,
1092 req
->request
.no_interrupt
);
1094 dwc3_prepare_one_trb(dep
, req
, chain
, i
);
1097 if (!dwc3_calc_trbs_left(dep
))
1102 static void dwc3_prepare_one_trb_linear(struct dwc3_ep
*dep
,
1103 struct dwc3_request
*req
)
1105 unsigned int length
= req
->request
.length
;
1106 unsigned int maxp
= usb_endpoint_maxp(dep
->endpoint
.desc
);
1107 unsigned int rem
= length
% maxp
;
1109 if ((!length
|| rem
) && usb_endpoint_dir_out(dep
->endpoint
.desc
)) {
1110 struct dwc3
*dwc
= dep
->dwc
;
1111 struct dwc3_trb
*trb
;
1113 req
->unaligned
= true;
1115 /* prepare normal TRB */
1116 dwc3_prepare_one_trb(dep
, req
, true, 0);
1118 /* Now prepare one extra TRB to align transfer size */
1119 trb
= &dep
->trb_pool
[dep
->trb_enqueue
];
1120 __dwc3_prepare_one_trb(dep
, trb
, dwc
->bounce_addr
, maxp
- rem
,
1121 false, 1, req
->request
.stream_id
,
1122 req
->request
.short_not_ok
,
1123 req
->request
.no_interrupt
);
1124 } else if (req
->request
.zero
&& req
->request
.length
&&
1125 (IS_ALIGNED(req
->request
.length
,dep
->endpoint
.maxpacket
))) {
1126 struct dwc3
*dwc
= dep
->dwc
;
1127 struct dwc3_trb
*trb
;
1131 /* prepare normal TRB */
1132 dwc3_prepare_one_trb(dep
, req
, true, 0);
1134 /* Now prepare one extra TRB to handle ZLP */
1135 trb
= &dep
->trb_pool
[dep
->trb_enqueue
];
1136 __dwc3_prepare_one_trb(dep
, trb
, dwc
->bounce_addr
, 0,
1137 false, 1, req
->request
.stream_id
,
1138 req
->request
.short_not_ok
,
1139 req
->request
.no_interrupt
);
1141 dwc3_prepare_one_trb(dep
, req
, false, 0);
1146 * dwc3_prepare_trbs - setup TRBs from requests
1147 * @dep: endpoint for which requests are being prepared
1149 * The function goes through the requests list and sets up TRBs for the
1150 * transfers. The function returns once there are no more TRBs available or
1151 * it runs out of requests.
1153 static void dwc3_prepare_trbs(struct dwc3_ep
*dep
)
1155 struct dwc3_request
*req
, *n
;
1157 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM
);
1160 * We can get in a situation where there's a request in the started list
1161 * but there weren't enough TRBs to fully kick it in the first time
1162 * around, so it has been waiting for more TRBs to be freed up.
1164 * In that case, we should check if we have a request with pending_sgs
1165 * in the started list and prepare TRBs for that request first,
1166 * otherwise we will prepare TRBs completely out of order and that will
1169 list_for_each_entry(req
, &dep
->started_list
, list
) {
1170 if (req
->num_pending_sgs
> 0)
1171 dwc3_prepare_one_trb_sg(dep
, req
);
1173 if (!dwc3_calc_trbs_left(dep
))
1177 list_for_each_entry_safe(req
, n
, &dep
->pending_list
, list
) {
1178 struct dwc3
*dwc
= dep
->dwc
;
1181 ret
= usb_gadget_map_request_by_dev(dwc
->sysdev
, &req
->request
,
1186 req
->sg
= req
->request
.sg
;
1187 req
->num_pending_sgs
= req
->request
.num_mapped_sgs
;
1189 if (req
->num_pending_sgs
> 0)
1190 dwc3_prepare_one_trb_sg(dep
, req
);
1192 dwc3_prepare_one_trb_linear(dep
, req
);
1194 if (!dwc3_calc_trbs_left(dep
))
1199 static int __dwc3_gadget_kick_transfer(struct dwc3_ep
*dep
)
1201 struct dwc3_gadget_ep_cmd_params params
;
1202 struct dwc3_request
*req
;
1207 if (!dwc3_calc_trbs_left(dep
))
1210 starting
= !(dep
->flags
& DWC3_EP_BUSY
);
1212 dwc3_prepare_trbs(dep
);
1213 req
= next_request(&dep
->started_list
);
1215 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
1219 memset(¶ms
, 0, sizeof(params
));
1222 params
.param0
= upper_32_bits(req
->trb_dma
);
1223 params
.param1
= lower_32_bits(req
->trb_dma
);
1224 cmd
= DWC3_DEPCMD_STARTTRANSFER
;
1226 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
1227 cmd
|= DWC3_DEPCMD_PARAM(dep
->frame_number
);
1229 cmd
= DWC3_DEPCMD_UPDATETRANSFER
|
1230 DWC3_DEPCMD_PARAM(dep
->resource_index
);
1233 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
1236 * FIXME we need to iterate over the list of requests
1237 * here and stop, unmap, free and del each of the linked
1238 * requests instead of what we do now.
1241 memset(req
->trb
, 0, sizeof(struct dwc3_trb
));
1242 dep
->queued_requests
--;
1243 dwc3_gadget_del_and_unmap_request(dep
, req
, ret
);
1247 dep
->flags
|= DWC3_EP_BUSY
;
1250 dep
->resource_index
= dwc3_gadget_ep_get_transfer_index(dep
);
1251 WARN_ON_ONCE(!dep
->resource_index
);
1257 static int __dwc3_gadget_get_frame(struct dwc3
*dwc
)
1261 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1262 return DWC3_DSTS_SOFFN(reg
);
1265 static void __dwc3_gadget_start_isoc(struct dwc3
*dwc
,
1266 struct dwc3_ep
*dep
, u32 cur_uf
)
1268 if (list_empty(&dep
->pending_list
)) {
1269 dev_info(dwc
->dev
, "%s: ran out of requests\n",
1271 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
1276 * Schedule the first trb for one interval in the future or at
1277 * least 4 microframes.
1279 dep
->frame_number
= cur_uf
+ max_t(u32
, 4, dep
->interval
);
1280 __dwc3_gadget_kick_transfer(dep
);
1283 static void dwc3_gadget_start_isoc(struct dwc3
*dwc
,
1284 struct dwc3_ep
*dep
, const struct dwc3_event_depevt
*event
)
1288 mask
= ~(dep
->interval
- 1);
1289 cur_uf
= event
->parameters
& mask
;
1291 __dwc3_gadget_start_isoc(dwc
, dep
, cur_uf
);
1294 static int __dwc3_gadget_ep_queue(struct dwc3_ep
*dep
, struct dwc3_request
*req
)
1296 struct dwc3
*dwc
= dep
->dwc
;
1298 if (!dep
->endpoint
.desc
) {
1299 dev_err(dwc
->dev
, "%s: can't queue to disabled endpoint\n",
1304 if (WARN(req
->dep
!= dep
, "request %pK belongs to '%s'\n",
1305 &req
->request
, req
->dep
->name
))
1308 pm_runtime_get(dwc
->dev
);
1310 req
->request
.actual
= 0;
1311 req
->request
.status
= -EINPROGRESS
;
1312 req
->direction
= dep
->direction
;
1313 req
->epnum
= dep
->number
;
1315 trace_dwc3_ep_queue(req
);
1317 list_add_tail(&req
->list
, &dep
->pending_list
);
1320 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1321 * wait for a XferNotReady event so we will know what's the current
1322 * (micro-)frame number.
1324 * Without this trick, we are very, very likely gonna get Bus Expiry
1325 * errors which will force us issue EndTransfer command.
1327 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1328 if ((dep
->flags
& DWC3_EP_PENDING_REQUEST
)) {
1329 if (dep
->flags
& DWC3_EP_TRANSFER_STARTED
) {
1330 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
1331 dep
->flags
= DWC3_EP_ENABLED
;
1335 cur_uf
= __dwc3_gadget_get_frame(dwc
);
1336 __dwc3_gadget_start_isoc(dwc
, dep
, cur_uf
);
1337 dep
->flags
&= ~DWC3_EP_PENDING_REQUEST
;
1342 if ((dep
->flags
& DWC3_EP_BUSY
) &&
1343 !(dep
->flags
& DWC3_EP_MISSED_ISOC
))
1350 return __dwc3_gadget_kick_transfer(dep
);
1353 static int dwc3_gadget_ep_queue(struct usb_ep
*ep
, struct usb_request
*request
,
1356 struct dwc3_request
*req
= to_dwc3_request(request
);
1357 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1358 struct dwc3
*dwc
= dep
->dwc
;
1360 unsigned long flags
;
1364 spin_lock_irqsave(&dwc
->lock
, flags
);
1365 ret
= __dwc3_gadget_ep_queue(dep
, req
);
1366 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1371 static int dwc3_gadget_ep_dequeue(struct usb_ep
*ep
,
1372 struct usb_request
*request
)
1374 struct dwc3_request
*req
= to_dwc3_request(request
);
1375 struct dwc3_request
*r
= NULL
;
1377 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1378 struct dwc3
*dwc
= dep
->dwc
;
1380 unsigned long flags
;
1383 trace_dwc3_ep_dequeue(req
);
1385 spin_lock_irqsave(&dwc
->lock
, flags
);
1387 list_for_each_entry(r
, &dep
->pending_list
, list
) {
1393 list_for_each_entry(r
, &dep
->started_list
, list
) {
1398 /* wait until it is processed */
1399 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
1402 * If request was already started, this means we had to
1403 * stop the transfer. With that we also need to ignore
1404 * all TRBs used by the request, however TRBs can only
1405 * be modified after completion of END_TRANSFER
1406 * command. So what we do here is that we wait for
1407 * END_TRANSFER completion and only after that, we jump
1408 * over TRBs by clearing HWO and incrementing dequeue
1411 * Note that we have 2 possible types of transfers here:
1413 * i) Linear buffer request
1414 * ii) SG-list based request
1416 * SG-list based requests will have r->num_pending_sgs
1417 * set to a valid number (> 0). Linear requests,
1418 * normally use a single TRB.
1420 * For each of these two cases, if r->unaligned flag is
1421 * set, one extra TRB has been used to align transfer
1422 * size to wMaxPacketSize.
1424 * All of these cases need to be taken into
1425 * consideration so we don't mess up our TRB ring
1428 wait_event_lock_irq(dep
->wait_end_transfer
,
1429 !(dep
->flags
& DWC3_EP_END_TRANSFER_PENDING
),
1435 if (r
->num_pending_sgs
) {
1436 struct dwc3_trb
*trb
;
1439 for (i
= 0; i
< r
->num_pending_sgs
; i
++) {
1441 trb
->ctrl
&= ~DWC3_TRB_CTRL_HWO
;
1442 dwc3_ep_inc_deq(dep
);
1445 if (r
->unaligned
|| r
->zero
) {
1446 trb
= r
->trb
+ r
->num_pending_sgs
+ 1;
1447 trb
->ctrl
&= ~DWC3_TRB_CTRL_HWO
;
1448 dwc3_ep_inc_deq(dep
);
1451 struct dwc3_trb
*trb
= r
->trb
;
1453 trb
->ctrl
&= ~DWC3_TRB_CTRL_HWO
;
1454 dwc3_ep_inc_deq(dep
);
1456 if (r
->unaligned
|| r
->zero
) {
1458 trb
->ctrl
&= ~DWC3_TRB_CTRL_HWO
;
1459 dwc3_ep_inc_deq(dep
);
1464 dev_err(dwc
->dev
, "request %pK was not queued to %s\n",
1471 /* giveback the request */
1472 dep
->queued_requests
--;
1473 dwc3_gadget_giveback(dep
, req
, -ECONNRESET
);
1476 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1481 int __dwc3_gadget_ep_set_halt(struct dwc3_ep
*dep
, int value
, int protocol
)
1483 struct dwc3_gadget_ep_cmd_params params
;
1484 struct dwc3
*dwc
= dep
->dwc
;
1487 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1488 dev_err(dwc
->dev
, "%s is of Isochronous type\n", dep
->name
);
1492 memset(¶ms
, 0x00, sizeof(params
));
1495 struct dwc3_trb
*trb
;
1497 unsigned transfer_in_flight
;
1500 if (dep
->number
> 1)
1501 trb
= dwc3_ep_prev_trb(dep
, dep
->trb_enqueue
);
1503 trb
= &dwc
->ep0_trb
[dep
->trb_enqueue
];
1505 transfer_in_flight
= trb
->ctrl
& DWC3_TRB_CTRL_HWO
;
1506 started
= !list_empty(&dep
->started_list
);
1508 if (!protocol
&& ((dep
->direction
&& transfer_in_flight
) ||
1509 (!dep
->direction
&& started
))) {
1513 ret
= dwc3_send_gadget_ep_cmd(dep
, DWC3_DEPCMD_SETSTALL
,
1516 dev_err(dwc
->dev
, "failed to set STALL on %s\n",
1519 dep
->flags
|= DWC3_EP_STALL
;
1522 ret
= dwc3_send_clear_stall_ep_cmd(dep
);
1524 dev_err(dwc
->dev
, "failed to clear STALL on %s\n",
1527 dep
->flags
&= ~(DWC3_EP_STALL
| DWC3_EP_WEDGE
);
1533 static int dwc3_gadget_ep_set_halt(struct usb_ep
*ep
, int value
)
1535 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1536 struct dwc3
*dwc
= dep
->dwc
;
1538 unsigned long flags
;
1542 spin_lock_irqsave(&dwc
->lock
, flags
);
1543 ret
= __dwc3_gadget_ep_set_halt(dep
, value
, false);
1544 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1549 static int dwc3_gadget_ep_set_wedge(struct usb_ep
*ep
)
1551 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1552 struct dwc3
*dwc
= dep
->dwc
;
1553 unsigned long flags
;
1556 spin_lock_irqsave(&dwc
->lock
, flags
);
1557 dep
->flags
|= DWC3_EP_WEDGE
;
1559 if (dep
->number
== 0 || dep
->number
== 1)
1560 ret
= __dwc3_gadget_ep0_set_halt(ep
, 1);
1562 ret
= __dwc3_gadget_ep_set_halt(dep
, 1, false);
1563 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1568 /* -------------------------------------------------------------------------- */
1570 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc
= {
1571 .bLength
= USB_DT_ENDPOINT_SIZE
,
1572 .bDescriptorType
= USB_DT_ENDPOINT
,
1573 .bmAttributes
= USB_ENDPOINT_XFER_CONTROL
,
1576 static const struct usb_ep_ops dwc3_gadget_ep0_ops
= {
1577 .enable
= dwc3_gadget_ep0_enable
,
1578 .disable
= dwc3_gadget_ep0_disable
,
1579 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1580 .free_request
= dwc3_gadget_ep_free_request
,
1581 .queue
= dwc3_gadget_ep0_queue
,
1582 .dequeue
= dwc3_gadget_ep_dequeue
,
1583 .set_halt
= dwc3_gadget_ep0_set_halt
,
1584 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1587 static const struct usb_ep_ops dwc3_gadget_ep_ops
= {
1588 .enable
= dwc3_gadget_ep_enable
,
1589 .disable
= dwc3_gadget_ep_disable
,
1590 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1591 .free_request
= dwc3_gadget_ep_free_request
,
1592 .queue
= dwc3_gadget_ep_queue
,
1593 .dequeue
= dwc3_gadget_ep_dequeue
,
1594 .set_halt
= dwc3_gadget_ep_set_halt
,
1595 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1598 /* -------------------------------------------------------------------------- */
1600 static int dwc3_gadget_get_frame(struct usb_gadget
*g
)
1602 struct dwc3
*dwc
= gadget_to_dwc(g
);
1604 return __dwc3_gadget_get_frame(dwc
);
1607 static int __dwc3_gadget_wakeup(struct dwc3
*dwc
)
1618 * According to the Databook Remote wakeup request should
1619 * be issued only when the device is in early suspend state.
1621 * We can check that via USB Link State bits in DSTS register.
1623 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1625 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
1626 if ((speed
== DWC3_DSTS_SUPERSPEED
) ||
1627 (speed
== DWC3_DSTS_SUPERSPEED_PLUS
))
1630 link_state
= DWC3_DSTS_USBLNKST(reg
);
1632 switch (link_state
) {
1633 case DWC3_LINK_STATE_RX_DET
: /* in HS, means Early Suspend */
1634 case DWC3_LINK_STATE_U3
: /* in HS, means SUSPEND */
1640 ret
= dwc3_gadget_set_link_state(dwc
, DWC3_LINK_STATE_RECOV
);
1642 dev_err(dwc
->dev
, "failed to put link in Recovery\n");
1646 /* Recent versions do this automatically */
1647 if (dwc
->revision
< DWC3_REVISION_194A
) {
1648 /* write zeroes to Link Change Request */
1649 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1650 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
1651 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1654 /* poll until Link State changes to ON */
1658 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1660 /* in HS, means ON */
1661 if (DWC3_DSTS_USBLNKST(reg
) == DWC3_LINK_STATE_U0
)
1665 if (DWC3_DSTS_USBLNKST(reg
) != DWC3_LINK_STATE_U0
) {
1666 dev_err(dwc
->dev
, "failed to send remote wakeup\n");
1673 static int dwc3_gadget_wakeup(struct usb_gadget
*g
)
1675 struct dwc3
*dwc
= gadget_to_dwc(g
);
1676 unsigned long flags
;
1679 spin_lock_irqsave(&dwc
->lock
, flags
);
1680 ret
= __dwc3_gadget_wakeup(dwc
);
1681 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1686 static int dwc3_gadget_set_selfpowered(struct usb_gadget
*g
,
1689 struct dwc3
*dwc
= gadget_to_dwc(g
);
1690 unsigned long flags
;
1692 spin_lock_irqsave(&dwc
->lock
, flags
);
1693 g
->is_selfpowered
= !!is_selfpowered
;
1694 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1699 static int dwc3_gadget_run_stop(struct dwc3
*dwc
, int is_on
, int suspend
)
1704 if (pm_runtime_suspended(dwc
->dev
))
1707 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1709 if (dwc
->revision
<= DWC3_REVISION_187A
) {
1710 reg
&= ~DWC3_DCTL_TRGTULST_MASK
;
1711 reg
|= DWC3_DCTL_TRGTULST_RX_DET
;
1714 if (dwc
->revision
>= DWC3_REVISION_194A
)
1715 reg
&= ~DWC3_DCTL_KEEP_CONNECT
;
1716 reg
|= DWC3_DCTL_RUN_STOP
;
1718 if (dwc
->has_hibernation
)
1719 reg
|= DWC3_DCTL_KEEP_CONNECT
;
1721 dwc
->pullups_connected
= true;
1723 reg
&= ~DWC3_DCTL_RUN_STOP
;
1725 if (dwc
->has_hibernation
&& !suspend
)
1726 reg
&= ~DWC3_DCTL_KEEP_CONNECT
;
1728 dwc
->pullups_connected
= false;
1731 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1734 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1735 reg
&= DWC3_DSTS_DEVCTRLHLT
;
1736 } while (--timeout
&& !(!is_on
^ !reg
));
1744 static int dwc3_gadget_pullup(struct usb_gadget
*g
, int is_on
)
1746 struct dwc3
*dwc
= gadget_to_dwc(g
);
1747 unsigned long flags
;
1753 * Per databook, when we want to stop the gadget, if a control transfer
1754 * is still in process, complete it and get the core into setup phase.
1756 if (!is_on
&& dwc
->ep0state
!= EP0_SETUP_PHASE
) {
1757 reinit_completion(&dwc
->ep0_in_setup
);
1759 ret
= wait_for_completion_timeout(&dwc
->ep0_in_setup
,
1760 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT
));
1762 dev_err(dwc
->dev
, "timed out waiting for SETUP phase\n");
1767 spin_lock_irqsave(&dwc
->lock
, flags
);
1768 ret
= dwc3_gadget_run_stop(dwc
, is_on
, false);
1769 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1774 static void dwc3_gadget_enable_irq(struct dwc3
*dwc
)
1778 /* Enable all but Start and End of Frame IRQs */
1779 reg
= (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN
|
1780 DWC3_DEVTEN_EVNTOVERFLOWEN
|
1781 DWC3_DEVTEN_CMDCMPLTEN
|
1782 DWC3_DEVTEN_ERRTICERREN
|
1783 DWC3_DEVTEN_WKUPEVTEN
|
1784 DWC3_DEVTEN_CONNECTDONEEN
|
1785 DWC3_DEVTEN_USBRSTEN
|
1786 DWC3_DEVTEN_DISCONNEVTEN
);
1788 if (dwc
->revision
< DWC3_REVISION_250A
)
1789 reg
|= DWC3_DEVTEN_ULSTCNGEN
;
1791 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, reg
);
1794 static void dwc3_gadget_disable_irq(struct dwc3
*dwc
)
1796 /* mask all interrupts */
1797 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, 0x00);
1800 static irqreturn_t
dwc3_interrupt(int irq
, void *_dwc
);
1801 static irqreturn_t
dwc3_thread_interrupt(int irq
, void *_dwc
);
1804 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
1805 * @dwc: pointer to our context structure
1807 * The following looks like complex but it's actually very simple. In order to
1808 * calculate the number of packets we can burst at once on OUT transfers, we're
1809 * gonna use RxFIFO size.
1811 * To calculate RxFIFO size we need two numbers:
1812 * MDWIDTH = size, in bits, of the internal memory bus
1813 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1815 * Given these two numbers, the formula is simple:
1817 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1819 * 24 bytes is for 3x SETUP packets
1820 * 16 bytes is a clock domain crossing tolerance
1822 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1824 static void dwc3_gadget_setup_nump(struct dwc3
*dwc
)
1831 ram2_depth
= DWC3_GHWPARAMS7_RAM2_DEPTH(dwc
->hwparams
.hwparams7
);
1832 mdwidth
= DWC3_GHWPARAMS0_MDWIDTH(dwc
->hwparams
.hwparams0
);
1834 nump
= ((ram2_depth
* mdwidth
/ 8) - 24 - 16) / 1024;
1835 nump
= min_t(u32
, nump
, 16);
1838 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
1839 reg
&= ~DWC3_DCFG_NUMP_MASK
;
1840 reg
|= nump
<< DWC3_DCFG_NUMP_SHIFT
;
1841 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
1844 static int __dwc3_gadget_start(struct dwc3
*dwc
)
1846 struct dwc3_ep
*dep
;
1851 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1852 * the core supports IMOD, disable it.
1854 if (dwc
->imod_interval
) {
1855 dwc3_writel(dwc
->regs
, DWC3_DEV_IMOD(0), dwc
->imod_interval
);
1856 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB
);
1857 } else if (dwc3_has_imod(dwc
)) {
1858 dwc3_writel(dwc
->regs
, DWC3_DEV_IMOD(0), 0);
1862 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1863 * field instead of letting dwc3 itself calculate that automatically.
1865 * This way, we maximize the chances that we'll be able to get several
1866 * bursts of data without going through any sort of endpoint throttling.
1868 reg
= dwc3_readl(dwc
->regs
, DWC3_GRXTHRCFG
);
1869 reg
&= ~DWC3_GRXTHRCFG_PKTCNTSEL
;
1870 dwc3_writel(dwc
->regs
, DWC3_GRXTHRCFG
, reg
);
1872 dwc3_gadget_setup_nump(dwc
);
1874 /* Start with SuperSpeed Default */
1875 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
1878 ret
= __dwc3_gadget_ep_enable(dep
, false, false);
1880 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1885 ret
= __dwc3_gadget_ep_enable(dep
, false, false);
1887 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1891 /* begin to receive SETUP packets */
1892 dwc
->ep0state
= EP0_SETUP_PHASE
;
1893 dwc
->link_state
= DWC3_LINK_STATE_SS_DIS
;
1894 dwc3_ep0_out_start(dwc
);
1896 dwc3_gadget_enable_irq(dwc
);
1901 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
1907 static int dwc3_gadget_start(struct usb_gadget
*g
,
1908 struct usb_gadget_driver
*driver
)
1910 struct dwc3
*dwc
= gadget_to_dwc(g
);
1911 unsigned long flags
;
1915 irq
= dwc
->irq_gadget
;
1916 ret
= request_threaded_irq(irq
, dwc3_interrupt
, dwc3_thread_interrupt
,
1917 IRQF_SHARED
, "dwc3", dwc
->ev_buf
);
1919 dev_err(dwc
->dev
, "failed to request irq #%d --> %d\n",
1924 spin_lock_irqsave(&dwc
->lock
, flags
);
1925 if (dwc
->gadget_driver
) {
1926 dev_err(dwc
->dev
, "%s is already bound to %s\n",
1928 dwc
->gadget_driver
->driver
.name
);
1933 dwc
->gadget_driver
= driver
;
1935 if (pm_runtime_active(dwc
->dev
))
1936 __dwc3_gadget_start(dwc
);
1938 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1943 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1950 static void __dwc3_gadget_stop(struct dwc3
*dwc
)
1952 dwc3_gadget_disable_irq(dwc
);
1953 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
1954 __dwc3_gadget_ep_disable(dwc
->eps
[1]);
1957 static int dwc3_gadget_stop(struct usb_gadget
*g
)
1959 struct dwc3
*dwc
= gadget_to_dwc(g
);
1960 unsigned long flags
;
1963 spin_lock_irqsave(&dwc
->lock
, flags
);
1965 if (pm_runtime_suspended(dwc
->dev
))
1968 __dwc3_gadget_stop(dwc
);
1970 for (epnum
= 2; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
1971 struct dwc3_ep
*dep
= dwc
->eps
[epnum
];
1976 if (!(dep
->flags
& DWC3_EP_END_TRANSFER_PENDING
))
1979 wait_event_lock_irq(dep
->wait_end_transfer
,
1980 !(dep
->flags
& DWC3_EP_END_TRANSFER_PENDING
),
1985 dwc
->gadget_driver
= NULL
;
1986 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1988 free_irq(dwc
->irq_gadget
, dwc
->ev_buf
);
1993 static void dwc3_gadget_set_speed(struct usb_gadget
*g
,
1994 enum usb_device_speed speed
)
1996 struct dwc3
*dwc
= gadget_to_dwc(g
);
1997 unsigned long flags
;
2000 spin_lock_irqsave(&dwc
->lock
, flags
);
2001 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2002 reg
&= ~(DWC3_DCFG_SPEED_MASK
);
2005 * WORKAROUND: DWC3 revision < 2.20a have an issue
2006 * which would cause metastability state on Run/Stop
2007 * bit if we try to force the IP to USB2-only mode.
2009 * Because of that, we cannot configure the IP to any
2010 * speed other than the SuperSpeed
2014 * STAR#9000525659: Clock Domain Crossing on DCTL in
2017 if (dwc
->revision
< DWC3_REVISION_220A
) {
2018 reg
|= DWC3_DCFG_SUPERSPEED
;
2022 reg
|= DWC3_DCFG_LOWSPEED
;
2024 case USB_SPEED_FULL
:
2025 reg
|= DWC3_DCFG_FULLSPEED
;
2027 case USB_SPEED_HIGH
:
2028 reg
|= DWC3_DCFG_HIGHSPEED
;
2030 case USB_SPEED_SUPER
:
2031 reg
|= DWC3_DCFG_SUPERSPEED
;
2033 case USB_SPEED_SUPER_PLUS
:
2034 reg
|= DWC3_DCFG_SUPERSPEED_PLUS
;
2037 dev_err(dwc
->dev
, "invalid speed (%d)\n", speed
);
2039 if (dwc
->revision
& DWC3_REVISION_IS_DWC31
)
2040 reg
|= DWC3_DCFG_SUPERSPEED_PLUS
;
2042 reg
|= DWC3_DCFG_SUPERSPEED
;
2045 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2047 spin_unlock_irqrestore(&dwc
->lock
, flags
);
2050 static const struct usb_gadget_ops dwc3_gadget_ops
= {
2051 .get_frame
= dwc3_gadget_get_frame
,
2052 .wakeup
= dwc3_gadget_wakeup
,
2053 .set_selfpowered
= dwc3_gadget_set_selfpowered
,
2054 .pullup
= dwc3_gadget_pullup
,
2055 .udc_start
= dwc3_gadget_start
,
2056 .udc_stop
= dwc3_gadget_stop
,
2057 .udc_set_speed
= dwc3_gadget_set_speed
,
2060 /* -------------------------------------------------------------------------- */
2062 static int dwc3_gadget_init_endpoints(struct dwc3
*dwc
, u8 total
)
2064 struct dwc3_ep
*dep
;
2067 INIT_LIST_HEAD(&dwc
->gadget
.ep_list
);
2069 for (epnum
= 0; epnum
< total
; epnum
++) {
2070 bool direction
= epnum
& 1;
2071 u8 num
= epnum
>> 1;
2073 dep
= kzalloc(sizeof(*dep
), GFP_KERNEL
);
2078 dep
->number
= epnum
;
2079 dep
->direction
= direction
;
2080 dep
->regs
= dwc
->regs
+ DWC3_DEP_BASE(epnum
);
2081 dwc
->eps
[epnum
] = dep
;
2083 snprintf(dep
->name
, sizeof(dep
->name
), "ep%u%s", num
,
2084 direction
? "in" : "out");
2086 dep
->endpoint
.name
= dep
->name
;
2088 if (!(dep
->number
> 1)) {
2089 dep
->endpoint
.desc
= &dwc3_gadget_ep0_desc
;
2090 dep
->endpoint
.comp_desc
= NULL
;
2093 spin_lock_init(&dep
->lock
);
2096 usb_ep_set_maxpacket_limit(&dep
->endpoint
, 512);
2097 dep
->endpoint
.maxburst
= 1;
2098 dep
->endpoint
.ops
= &dwc3_gadget_ep0_ops
;
2100 dwc
->gadget
.ep0
= &dep
->endpoint
;
2101 } else if (direction
) {
2107 mdwidth
= DWC3_MDWIDTH(dwc
->hwparams
.hwparams0
);
2108 /* MDWIDTH is represented in bits, we need it in bytes */
2111 size
= dwc3_readl(dwc
->regs
, DWC3_GTXFIFOSIZ(num
));
2112 size
= DWC3_GTXFIFOSIZ_TXFDEF(size
);
2114 /* FIFO Depth is in MDWDITH bytes. Multiply */
2117 kbytes
= size
/ 1024;
2122 * FIFO sizes account an extra MDWIDTH * (kbytes + 1) bytes for
2123 * internal overhead. We don't really know how these are used,
2124 * but documentation say it exists.
2126 size
-= mdwidth
* (kbytes
+ 1);
2129 usb_ep_set_maxpacket_limit(&dep
->endpoint
, size
);
2131 dep
->endpoint
.max_streams
= 15;
2132 dep
->endpoint
.ops
= &dwc3_gadget_ep_ops
;
2133 list_add_tail(&dep
->endpoint
.ep_list
,
2134 &dwc
->gadget
.ep_list
);
2136 ret
= dwc3_alloc_trb_pool(dep
);
2142 usb_ep_set_maxpacket_limit(&dep
->endpoint
, 1024);
2143 dep
->endpoint
.max_streams
= 15;
2144 dep
->endpoint
.ops
= &dwc3_gadget_ep_ops
;
2145 list_add_tail(&dep
->endpoint
.ep_list
,
2146 &dwc
->gadget
.ep_list
);
2148 ret
= dwc3_alloc_trb_pool(dep
);
2154 dep
->endpoint
.caps
.type_control
= true;
2156 dep
->endpoint
.caps
.type_iso
= true;
2157 dep
->endpoint
.caps
.type_bulk
= true;
2158 dep
->endpoint
.caps
.type_int
= true;
2161 dep
->endpoint
.caps
.dir_in
= direction
;
2162 dep
->endpoint
.caps
.dir_out
= !direction
;
2164 INIT_LIST_HEAD(&dep
->pending_list
);
2165 INIT_LIST_HEAD(&dep
->started_list
);
2171 static void dwc3_gadget_free_endpoints(struct dwc3
*dwc
)
2173 struct dwc3_ep
*dep
;
2176 for (epnum
= 0; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
2177 dep
= dwc
->eps
[epnum
];
2181 * Physical endpoints 0 and 1 are special; they form the
2182 * bi-directional USB endpoint 0.
2184 * For those two physical endpoints, we don't allocate a TRB
2185 * pool nor do we add them the endpoints list. Due to that, we
2186 * shouldn't do these two operations otherwise we would end up
2187 * with all sorts of bugs when removing dwc3.ko.
2189 if (epnum
!= 0 && epnum
!= 1) {
2190 dwc3_free_trb_pool(dep
);
2191 list_del(&dep
->endpoint
.ep_list
);
2198 /* -------------------------------------------------------------------------- */
2200 static int __dwc3_cleanup_done_trbs(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
2201 struct dwc3_request
*req
, struct dwc3_trb
*trb
,
2202 const struct dwc3_event_depevt
*event
, int status
,
2206 unsigned int s_pkt
= 0;
2207 unsigned int trb_status
;
2209 dwc3_ep_inc_deq(dep
);
2211 if (req
->trb
== trb
)
2212 dep
->queued_requests
--;
2214 trace_dwc3_complete_trb(dep
, trb
);
2217 * If we're in the middle of series of chained TRBs and we
2218 * receive a short transfer along the way, DWC3 will skip
2219 * through all TRBs including the last TRB in the chain (the
2220 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2221 * bit and SW has to do it manually.
2223 * We're going to do that here to avoid problems of HW trying
2224 * to use bogus TRBs for transfers.
2226 if (chain
&& (trb
->ctrl
& DWC3_TRB_CTRL_HWO
))
2227 trb
->ctrl
&= ~DWC3_TRB_CTRL_HWO
;
2230 * If we're dealing with unaligned size OUT transfer, we will be left
2231 * with one TRB pending in the ring. We need to manually clear HWO bit
2234 if ((req
->zero
|| req
->unaligned
) && !(trb
->ctrl
& DWC3_TRB_CTRL_CHN
)) {
2235 trb
->ctrl
&= ~DWC3_TRB_CTRL_HWO
;
2239 count
= trb
->size
& DWC3_TRB_SIZE_MASK
;
2240 req
->remaining
+= count
;
2242 if ((trb
->ctrl
& DWC3_TRB_CTRL_HWO
) && status
!= -ESHUTDOWN
)
2245 if (dep
->direction
) {
2247 trb_status
= DWC3_TRB_SIZE_TRBSTS(trb
->size
);
2248 if (trb_status
== DWC3_TRBSTS_MISSED_ISOC
) {
2250 * If missed isoc occurred and there is
2251 * no request queued then issue END
2252 * TRANSFER, so that core generates
2253 * next xfernotready and we will issue
2254 * a fresh START TRANSFER.
2255 * If there are still queued request
2256 * then wait, do not issue either END
2257 * or UPDATE TRANSFER, just attach next
2258 * request in pending_list during
2259 * giveback.If any future queued request
2260 * is successfully transferred then we
2261 * will issue UPDATE TRANSFER for all
2262 * request in the pending_list.
2264 dep
->flags
|= DWC3_EP_MISSED_ISOC
;
2266 dev_err(dwc
->dev
, "incomplete IN transfer %s\n",
2268 status
= -ECONNRESET
;
2271 dep
->flags
&= ~DWC3_EP_MISSED_ISOC
;
2274 if (count
&& (event
->status
& DEPEVT_STATUS_SHORT
))
2278 if (s_pkt
&& !chain
)
2281 if ((event
->status
& DEPEVT_STATUS_IOC
) &&
2282 (trb
->ctrl
& DWC3_TRB_CTRL_IOC
))
2288 static int dwc3_cleanup_done_reqs(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
2289 const struct dwc3_event_depevt
*event
, int status
)
2291 struct dwc3_request
*req
, *n
;
2292 struct dwc3_trb
*trb
;
2296 list_for_each_entry_safe(req
, n
, &dep
->started_list
, list
) {
2300 length
= req
->request
.length
;
2301 chain
= req
->num_pending_sgs
> 0;
2303 struct scatterlist
*sg
= req
->sg
;
2304 struct scatterlist
*s
;
2305 unsigned int pending
= req
->num_pending_sgs
;
2308 for_each_sg(sg
, s
, pending
, i
) {
2309 trb
= &dep
->trb_pool
[dep
->trb_dequeue
];
2311 if (trb
->ctrl
& DWC3_TRB_CTRL_HWO
)
2314 req
->sg
= sg_next(s
);
2315 req
->num_pending_sgs
--;
2317 ret
= __dwc3_cleanup_done_trbs(dwc
, dep
, req
, trb
,
2318 event
, status
, chain
);
2323 trb
= &dep
->trb_pool
[dep
->trb_dequeue
];
2324 ret
= __dwc3_cleanup_done_trbs(dwc
, dep
, req
, trb
,
2325 event
, status
, chain
);
2328 if (req
->unaligned
|| req
->zero
) {
2329 trb
= &dep
->trb_pool
[dep
->trb_dequeue
];
2330 ret
= __dwc3_cleanup_done_trbs(dwc
, dep
, req
, trb
,
2331 event
, status
, false);
2332 req
->unaligned
= false;
2336 req
->request
.actual
= length
- req
->remaining
;
2338 if ((req
->request
.actual
< length
) && req
->num_pending_sgs
)
2339 return __dwc3_gadget_kick_transfer(dep
);
2341 dwc3_gadget_giveback(dep
, req
, status
);
2344 if ((event
->status
& DEPEVT_STATUS_IOC
) &&
2345 (trb
->ctrl
& DWC3_TRB_CTRL_IOC
))
2352 * Our endpoint might get disabled by another thread during
2353 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2354 * early on so DWC3_EP_BUSY flag gets cleared
2356 if (!dep
->endpoint
.desc
)
2359 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) &&
2360 list_empty(&dep
->started_list
)) {
2361 if (list_empty(&dep
->pending_list
)) {
2363 * If there is no entry in request list then do
2364 * not issue END TRANSFER now. Just set PENDING
2365 * flag, so that END TRANSFER is issued when an
2366 * entry is added into request list.
2368 dep
->flags
= DWC3_EP_PENDING_REQUEST
;
2370 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
2371 dep
->flags
= DWC3_EP_ENABLED
;
2376 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) && ioc
)
2382 static void dwc3_endpoint_transfer_complete(struct dwc3
*dwc
,
2383 struct dwc3_ep
*dep
, const struct dwc3_event_depevt
*event
)
2385 unsigned status
= 0;
2387 u32 is_xfer_complete
;
2389 is_xfer_complete
= (event
->endpoint_event
== DWC3_DEPEVT_XFERCOMPLETE
);
2391 if (event
->status
& DEPEVT_STATUS_BUSERR
)
2392 status
= -ECONNRESET
;
2394 clean_busy
= dwc3_cleanup_done_reqs(dwc
, dep
, event
, status
);
2395 if (clean_busy
&& (!dep
->endpoint
.desc
|| is_xfer_complete
||
2396 usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)))
2397 dep
->flags
&= ~DWC3_EP_BUSY
;
2400 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2401 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2403 if (dwc
->revision
< DWC3_REVISION_183A
) {
2407 for (i
= 0; i
< DWC3_ENDPOINTS_NUM
; i
++) {
2410 if (!(dep
->flags
& DWC3_EP_ENABLED
))
2413 if (!list_empty(&dep
->started_list
))
2417 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2419 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2425 * Our endpoint might get disabled by another thread during
2426 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2427 * early on so DWC3_EP_BUSY flag gets cleared
2429 if (!dep
->endpoint
.desc
)
2432 if (!usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
2433 __dwc3_gadget_kick_transfer(dep
);
2436 static void dwc3_endpoint_interrupt(struct dwc3
*dwc
,
2437 const struct dwc3_event_depevt
*event
)
2439 struct dwc3_ep
*dep
;
2440 u8 epnum
= event
->endpoint_number
;
2443 dep
= dwc
->eps
[epnum
];
2445 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
2446 if (!(dep
->flags
& DWC3_EP_END_TRANSFER_PENDING
))
2449 /* Handle only EPCMDCMPLT when EP disabled */
2450 if (event
->endpoint_event
!= DWC3_DEPEVT_EPCMDCMPLT
)
2454 if (epnum
== 0 || epnum
== 1) {
2455 dwc3_ep0_interrupt(dwc
, event
);
2459 switch (event
->endpoint_event
) {
2460 case DWC3_DEPEVT_XFERCOMPLETE
:
2461 dep
->resource_index
= 0;
2463 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
2464 dev_err(dwc
->dev
, "XferComplete for Isochronous endpoint\n");
2468 dwc3_endpoint_transfer_complete(dwc
, dep
, event
);
2470 case DWC3_DEPEVT_XFERINPROGRESS
:
2471 dwc3_endpoint_transfer_complete(dwc
, dep
, event
);
2473 case DWC3_DEPEVT_XFERNOTREADY
:
2474 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
2475 dwc3_gadget_start_isoc(dwc
, dep
, event
);
2477 __dwc3_gadget_kick_transfer(dep
);
2480 case DWC3_DEPEVT_STREAMEVT
:
2481 if (!usb_endpoint_xfer_bulk(dep
->endpoint
.desc
)) {
2482 dev_err(dwc
->dev
, "Stream event for non-Bulk %s\n",
2487 case DWC3_DEPEVT_EPCMDCMPLT
:
2488 cmd
= DEPEVT_PARAMETER_CMD(event
->parameters
);
2490 if (cmd
== DWC3_DEPCMD_ENDTRANSFER
) {
2491 dep
->flags
&= ~DWC3_EP_END_TRANSFER_PENDING
;
2492 wake_up(&dep
->wait_end_transfer
);
2495 case DWC3_DEPEVT_RXTXFIFOEVT
:
2500 static void dwc3_disconnect_gadget(struct dwc3
*dwc
)
2502 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->disconnect
) {
2503 spin_unlock(&dwc
->lock
);
2504 dwc
->gadget_driver
->disconnect(&dwc
->gadget
);
2505 spin_lock(&dwc
->lock
);
2509 static void dwc3_suspend_gadget(struct dwc3
*dwc
)
2511 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->suspend
) {
2512 spin_unlock(&dwc
->lock
);
2513 dwc
->gadget_driver
->suspend(&dwc
->gadget
);
2514 spin_lock(&dwc
->lock
);
2518 static void dwc3_resume_gadget(struct dwc3
*dwc
)
2520 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->resume
) {
2521 spin_unlock(&dwc
->lock
);
2522 dwc
->gadget_driver
->resume(&dwc
->gadget
);
2523 spin_lock(&dwc
->lock
);
2527 static void dwc3_reset_gadget(struct dwc3
*dwc
)
2529 if (!dwc
->gadget_driver
)
2532 if (dwc
->gadget
.speed
!= USB_SPEED_UNKNOWN
) {
2533 spin_unlock(&dwc
->lock
);
2534 usb_gadget_udc_reset(&dwc
->gadget
, dwc
->gadget_driver
);
2535 spin_lock(&dwc
->lock
);
2539 static void dwc3_stop_active_transfer(struct dwc3
*dwc
, u32 epnum
, bool force
)
2541 struct dwc3_ep
*dep
;
2542 struct dwc3_gadget_ep_cmd_params params
;
2546 dep
= dwc
->eps
[epnum
];
2548 if ((dep
->flags
& DWC3_EP_END_TRANSFER_PENDING
) ||
2549 !dep
->resource_index
)
2553 * NOTICE: We are violating what the Databook says about the
2554 * EndTransfer command. Ideally we would _always_ wait for the
2555 * EndTransfer Command Completion IRQ, but that's causing too
2556 * much trouble synchronizing between us and gadget driver.
2558 * We have discussed this with the IP Provider and it was
2559 * suggested to giveback all requests here, but give HW some
2560 * extra time to synchronize with the interconnect. We're using
2561 * an arbitrary 100us delay for that.
2563 * Note also that a similar handling was tested by Synopsys
2564 * (thanks a lot Paul) and nothing bad has come out of it.
2565 * In short, what we're doing is:
2567 * - Issue EndTransfer WITH CMDIOC bit set
2570 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2571 * supports a mode to work around the above limitation. The
2572 * software can poll the CMDACT bit in the DEPCMD register
2573 * after issuing a EndTransfer command. This mode is enabled
2574 * by writing GUCTL2[14]. This polling is already done in the
2575 * dwc3_send_gadget_ep_cmd() function so if the mode is
2576 * enabled, the EndTransfer command will have completed upon
2577 * returning from this function and we don't need to delay for
2580 * This mode is NOT available on the DWC_usb31 IP.
2583 cmd
= DWC3_DEPCMD_ENDTRANSFER
;
2584 cmd
|= force
? DWC3_DEPCMD_HIPRI_FORCERM
: 0;
2585 cmd
|= DWC3_DEPCMD_CMDIOC
;
2586 cmd
|= DWC3_DEPCMD_PARAM(dep
->resource_index
);
2587 memset(¶ms
, 0, sizeof(params
));
2588 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
2590 dep
->resource_index
= 0;
2591 dep
->flags
&= ~DWC3_EP_BUSY
;
2593 if (dwc3_is_usb31(dwc
) || dwc
->revision
< DWC3_REVISION_310A
) {
2594 dep
->flags
|= DWC3_EP_END_TRANSFER_PENDING
;
2599 static void dwc3_clear_stall_all_ep(struct dwc3
*dwc
)
2603 for (epnum
= 1; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
2604 struct dwc3_ep
*dep
;
2607 dep
= dwc
->eps
[epnum
];
2611 if (!(dep
->flags
& DWC3_EP_STALL
))
2614 dep
->flags
&= ~DWC3_EP_STALL
;
2616 ret
= dwc3_send_clear_stall_ep_cmd(dep
);
2621 static void dwc3_gadget_disconnect_interrupt(struct dwc3
*dwc
)
2625 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2626 reg
&= ~DWC3_DCTL_INITU1ENA
;
2627 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2629 reg
&= ~DWC3_DCTL_INITU2ENA
;
2630 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2632 dwc3_disconnect_gadget(dwc
);
2634 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2635 dwc
->setup_packet_pending
= false;
2636 usb_gadget_set_state(&dwc
->gadget
, USB_STATE_NOTATTACHED
);
2638 dwc
->connected
= false;
2641 static void dwc3_gadget_reset_interrupt(struct dwc3
*dwc
)
2645 dwc
->connected
= true;
2648 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2649 * would cause a missing Disconnect Event if there's a
2650 * pending Setup Packet in the FIFO.
2652 * There's no suggested workaround on the official Bug
2653 * report, which states that "unless the driver/application
2654 * is doing any special handling of a disconnect event,
2655 * there is no functional issue".
2657 * Unfortunately, it turns out that we _do_ some special
2658 * handling of a disconnect event, namely complete all
2659 * pending transfers, notify gadget driver of the
2660 * disconnection, and so on.
2662 * Our suggested workaround is to follow the Disconnect
2663 * Event steps here, instead, based on a setup_packet_pending
2664 * flag. Such flag gets set whenever we have a SETUP_PENDING
2665 * status for EP0 TRBs and gets cleared on XferComplete for the
2670 * STAR#9000466709: RTL: Device : Disconnect event not
2671 * generated if setup packet pending in FIFO
2673 if (dwc
->revision
< DWC3_REVISION_188A
) {
2674 if (dwc
->setup_packet_pending
)
2675 dwc3_gadget_disconnect_interrupt(dwc
);
2678 dwc3_reset_gadget(dwc
);
2680 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2681 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
2682 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2683 dwc
->test_mode
= false;
2684 dwc3_clear_stall_all_ep(dwc
);
2686 /* Reset device address to zero */
2687 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2688 reg
&= ~(DWC3_DCFG_DEVADDR_MASK
);
2689 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2692 static void dwc3_gadget_conndone_interrupt(struct dwc3
*dwc
)
2694 struct dwc3_ep
*dep
;
2699 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
2700 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
2704 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2705 * each time on Connect Done.
2707 * Currently we always use the reset value. If any platform
2708 * wants to set this to a different value, we need to add a
2709 * setting and update GCTL.RAMCLKSEL here.
2713 case DWC3_DSTS_SUPERSPEED_PLUS
:
2714 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
2715 dwc
->gadget
.ep0
->maxpacket
= 512;
2716 dwc
->gadget
.speed
= USB_SPEED_SUPER_PLUS
;
2718 case DWC3_DSTS_SUPERSPEED
:
2720 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2721 * would cause a missing USB3 Reset event.
2723 * In such situations, we should force a USB3 Reset
2724 * event by calling our dwc3_gadget_reset_interrupt()
2729 * STAR#9000483510: RTL: SS : USB3 reset event may
2730 * not be generated always when the link enters poll
2732 if (dwc
->revision
< DWC3_REVISION_190A
)
2733 dwc3_gadget_reset_interrupt(dwc
);
2735 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
2736 dwc
->gadget
.ep0
->maxpacket
= 512;
2737 dwc
->gadget
.speed
= USB_SPEED_SUPER
;
2739 case DWC3_DSTS_HIGHSPEED
:
2740 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2741 dwc
->gadget
.ep0
->maxpacket
= 64;
2742 dwc
->gadget
.speed
= USB_SPEED_HIGH
;
2744 case DWC3_DSTS_FULLSPEED
:
2745 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2746 dwc
->gadget
.ep0
->maxpacket
= 64;
2747 dwc
->gadget
.speed
= USB_SPEED_FULL
;
2749 case DWC3_DSTS_LOWSPEED
:
2750 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(8);
2751 dwc
->gadget
.ep0
->maxpacket
= 8;
2752 dwc
->gadget
.speed
= USB_SPEED_LOW
;
2756 dwc
->eps
[1]->endpoint
.maxpacket
= dwc
->gadget
.ep0
->maxpacket
;
2758 /* Enable USB2 LPM Capability */
2760 if ((dwc
->revision
> DWC3_REVISION_194A
) &&
2761 (speed
!= DWC3_DSTS_SUPERSPEED
) &&
2762 (speed
!= DWC3_DSTS_SUPERSPEED_PLUS
)) {
2763 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2764 reg
|= DWC3_DCFG_LPM_CAP
;
2765 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2767 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2768 reg
&= ~(DWC3_DCTL_HIRD_THRES_MASK
| DWC3_DCTL_L1_HIBER_EN
);
2770 reg
|= DWC3_DCTL_HIRD_THRES(dwc
->hird_threshold
);
2773 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2774 * DCFG.LPMCap is set, core responses with an ACK and the
2775 * BESL value in the LPM token is less than or equal to LPM
2778 WARN_ONCE(dwc
->revision
< DWC3_REVISION_240A
2779 && dwc
->has_lpm_erratum
,
2780 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
2782 if (dwc
->has_lpm_erratum
&& dwc
->revision
>= DWC3_REVISION_240A
)
2783 reg
|= DWC3_DCTL_LPM_ERRATA(dwc
->lpm_nyet_threshold
);
2785 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2787 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2788 reg
&= ~DWC3_DCTL_HIRD_THRES_MASK
;
2789 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2793 ret
= __dwc3_gadget_ep_enable(dep
, true, false);
2795 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2800 ret
= __dwc3_gadget_ep_enable(dep
, true, false);
2802 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2807 * Configure PHY via GUSB3PIPECTLn if required.
2809 * Update GTXFIFOSIZn
2811 * In both cases reset values should be sufficient.
2815 static void dwc3_gadget_wakeup_interrupt(struct dwc3
*dwc
)
2818 * TODO take core out of low power mode when that's
2822 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->resume
) {
2823 spin_unlock(&dwc
->lock
);
2824 dwc
->gadget_driver
->resume(&dwc
->gadget
);
2825 spin_lock(&dwc
->lock
);
2829 static void dwc3_gadget_linksts_change_interrupt(struct dwc3
*dwc
,
2830 unsigned int evtinfo
)
2832 enum dwc3_link_state next
= evtinfo
& DWC3_LINK_STATE_MASK
;
2833 unsigned int pwropt
;
2836 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2837 * Hibernation mode enabled which would show up when device detects
2838 * host-initiated U3 exit.
2840 * In that case, device will generate a Link State Change Interrupt
2841 * from U3 to RESUME which is only necessary if Hibernation is
2844 * There are no functional changes due to such spurious event and we
2845 * just need to ignore it.
2849 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2852 pwropt
= DWC3_GHWPARAMS1_EN_PWROPT(dwc
->hwparams
.hwparams1
);
2853 if ((dwc
->revision
< DWC3_REVISION_250A
) &&
2854 (pwropt
!= DWC3_GHWPARAMS1_EN_PWROPT_HIB
)) {
2855 if ((dwc
->link_state
== DWC3_LINK_STATE_U3
) &&
2856 (next
== DWC3_LINK_STATE_RESUME
)) {
2862 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2863 * on the link partner, the USB session might do multiple entry/exit
2864 * of low power states before a transfer takes place.
2866 * Due to this problem, we might experience lower throughput. The
2867 * suggested workaround is to disable DCTL[12:9] bits if we're
2868 * transitioning from U1/U2 to U0 and enable those bits again
2869 * after a transfer completes and there are no pending transfers
2870 * on any of the enabled endpoints.
2872 * This is the first half of that workaround.
2876 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2877 * core send LGO_Ux entering U0
2879 if (dwc
->revision
< DWC3_REVISION_183A
) {
2880 if (next
== DWC3_LINK_STATE_U0
) {
2884 switch (dwc
->link_state
) {
2885 case DWC3_LINK_STATE_U1
:
2886 case DWC3_LINK_STATE_U2
:
2887 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2888 u1u2
= reg
& (DWC3_DCTL_INITU2ENA
2889 | DWC3_DCTL_ACCEPTU2ENA
2890 | DWC3_DCTL_INITU1ENA
2891 | DWC3_DCTL_ACCEPTU1ENA
);
2894 dwc
->u1u2
= reg
& u1u2
;
2898 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2908 case DWC3_LINK_STATE_U1
:
2909 if (dwc
->speed
== USB_SPEED_SUPER
)
2910 dwc3_suspend_gadget(dwc
);
2912 case DWC3_LINK_STATE_U2
:
2913 case DWC3_LINK_STATE_U3
:
2914 dwc3_suspend_gadget(dwc
);
2916 case DWC3_LINK_STATE_RESUME
:
2917 dwc3_resume_gadget(dwc
);
2924 dwc
->link_state
= next
;
2927 static void dwc3_gadget_suspend_interrupt(struct dwc3
*dwc
,
2928 unsigned int evtinfo
)
2930 enum dwc3_link_state next
= evtinfo
& DWC3_LINK_STATE_MASK
;
2932 if (dwc
->link_state
!= next
&& next
== DWC3_LINK_STATE_U3
)
2933 dwc3_suspend_gadget(dwc
);
2935 dwc
->link_state
= next
;
2938 static void dwc3_gadget_hibernation_interrupt(struct dwc3
*dwc
,
2939 unsigned int evtinfo
)
2941 unsigned int is_ss
= evtinfo
& BIT(4);
2944 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2945 * have a known issue which can cause USB CV TD.9.23 to fail
2948 * Because of this issue, core could generate bogus hibernation
2949 * events which SW needs to ignore.
2953 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2954 * Device Fallback from SuperSpeed
2956 if (is_ss
^ (dwc
->speed
== USB_SPEED_SUPER
))
2959 /* enter hibernation here */
2962 static void dwc3_gadget_interrupt(struct dwc3
*dwc
,
2963 const struct dwc3_event_devt
*event
)
2965 switch (event
->type
) {
2966 case DWC3_DEVICE_EVENT_DISCONNECT
:
2967 dwc3_gadget_disconnect_interrupt(dwc
);
2969 case DWC3_DEVICE_EVENT_RESET
:
2970 dwc3_gadget_reset_interrupt(dwc
);
2972 case DWC3_DEVICE_EVENT_CONNECT_DONE
:
2973 dwc3_gadget_conndone_interrupt(dwc
);
2975 case DWC3_DEVICE_EVENT_WAKEUP
:
2976 dwc3_gadget_wakeup_interrupt(dwc
);
2978 case DWC3_DEVICE_EVENT_HIBER_REQ
:
2979 if (dev_WARN_ONCE(dwc
->dev
, !dwc
->has_hibernation
,
2980 "unexpected hibernation event\n"))
2983 dwc3_gadget_hibernation_interrupt(dwc
, event
->event_info
);
2985 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE
:
2986 dwc3_gadget_linksts_change_interrupt(dwc
, event
->event_info
);
2988 case DWC3_DEVICE_EVENT_EOPF
:
2989 /* It changed to be suspend event for version 2.30a and above */
2990 if (dwc
->revision
>= DWC3_REVISION_230A
) {
2992 * Ignore suspend event until the gadget enters into
2993 * USB_STATE_CONFIGURED state.
2995 if (dwc
->gadget
.state
>= USB_STATE_CONFIGURED
)
2996 dwc3_gadget_suspend_interrupt(dwc
,
3000 case DWC3_DEVICE_EVENT_SOF
:
3001 case DWC3_DEVICE_EVENT_ERRATIC_ERROR
:
3002 case DWC3_DEVICE_EVENT_CMD_CMPL
:
3003 case DWC3_DEVICE_EVENT_OVERFLOW
:
3006 dev_WARN(dwc
->dev
, "UNKNOWN IRQ %d\n", event
->type
);
3010 static void dwc3_process_event_entry(struct dwc3
*dwc
,
3011 const union dwc3_event
*event
)
3013 trace_dwc3_event(event
->raw
, dwc
);
3015 if (!event
->type
.is_devspec
)
3016 dwc3_endpoint_interrupt(dwc
, &event
->depevt
);
3017 else if (event
->type
.type
== DWC3_EVENT_TYPE_DEV
)
3018 dwc3_gadget_interrupt(dwc
, &event
->devt
);
3020 dev_err(dwc
->dev
, "UNKNOWN IRQ type %d\n", event
->raw
);
3023 static irqreturn_t
dwc3_process_event_buf(struct dwc3_event_buffer
*evt
)
3025 struct dwc3
*dwc
= evt
->dwc
;
3026 irqreturn_t ret
= IRQ_NONE
;
3032 if (!(evt
->flags
& DWC3_EVENT_PENDING
))
3036 union dwc3_event event
;
3038 event
.raw
= *(u32
*) (evt
->cache
+ evt
->lpos
);
3040 dwc3_process_event_entry(dwc
, &event
);
3043 * FIXME we wrap around correctly to the next entry as
3044 * almost all entries are 4 bytes in size. There is one
3045 * entry which has 12 bytes which is a regular entry
3046 * followed by 8 bytes data. ATM I don't know how
3047 * things are organized if we get next to the a
3048 * boundary so I worry about that once we try to handle
3051 evt
->lpos
= (evt
->lpos
+ 4) % evt
->length
;
3056 evt
->flags
&= ~DWC3_EVENT_PENDING
;
3059 /* Unmask interrupt */
3060 reg
= dwc3_readl(dwc
->regs
, DWC3_GEVNTSIZ(0));
3061 reg
&= ~DWC3_GEVNTSIZ_INTMASK
;
3062 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(0), reg
);
3064 if (dwc
->imod_interval
) {
3065 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB
);
3066 dwc3_writel(dwc
->regs
, DWC3_DEV_IMOD(0), dwc
->imod_interval
);
3072 static irqreturn_t
dwc3_thread_interrupt(int irq
, void *_evt
)
3074 struct dwc3_event_buffer
*evt
= _evt
;
3075 struct dwc3
*dwc
= evt
->dwc
;
3076 unsigned long flags
;
3077 irqreturn_t ret
= IRQ_NONE
;
3079 spin_lock_irqsave(&dwc
->lock
, flags
);
3080 ret
= dwc3_process_event_buf(evt
);
3081 spin_unlock_irqrestore(&dwc
->lock
, flags
);
3086 static irqreturn_t
dwc3_check_event_buf(struct dwc3_event_buffer
*evt
)
3088 struct dwc3
*dwc
= evt
->dwc
;
3093 if (pm_runtime_suspended(dwc
->dev
)) {
3094 pm_runtime_get(dwc
->dev
);
3095 disable_irq_nosync(dwc
->irq_gadget
);
3096 dwc
->pending_events
= true;
3101 * With PCIe legacy interrupt, test shows that top-half irq handler can
3102 * be called again after HW interrupt deassertion. Check if bottom-half
3103 * irq event handler completes before caching new event to prevent
3106 if (evt
->flags
& DWC3_EVENT_PENDING
)
3109 count
= dwc3_readl(dwc
->regs
, DWC3_GEVNTCOUNT(0));
3110 count
&= DWC3_GEVNTCOUNT_MASK
;
3115 evt
->flags
|= DWC3_EVENT_PENDING
;
3117 /* Mask interrupt */
3118 reg
= dwc3_readl(dwc
->regs
, DWC3_GEVNTSIZ(0));
3119 reg
|= DWC3_GEVNTSIZ_INTMASK
;
3120 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(0), reg
);
3122 amount
= min(count
, evt
->length
- evt
->lpos
);
3123 memcpy(evt
->cache
+ evt
->lpos
, evt
->buf
+ evt
->lpos
, amount
);
3126 memcpy(evt
->cache
, evt
->buf
, count
- amount
);
3128 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(0), count
);
3130 return IRQ_WAKE_THREAD
;
3133 static irqreturn_t
dwc3_interrupt(int irq
, void *_evt
)
3135 struct dwc3_event_buffer
*evt
= _evt
;
3137 return dwc3_check_event_buf(evt
);
3140 static int dwc3_gadget_get_irq(struct dwc3
*dwc
)
3142 struct platform_device
*dwc3_pdev
= to_platform_device(dwc
->dev
);
3145 irq
= platform_get_irq_byname(dwc3_pdev
, "peripheral");
3149 if (irq
== -EPROBE_DEFER
)
3152 irq
= platform_get_irq_byname(dwc3_pdev
, "dwc_usb3");
3156 if (irq
== -EPROBE_DEFER
)
3159 irq
= platform_get_irq(dwc3_pdev
, 0);
3163 if (irq
!= -EPROBE_DEFER
)
3164 dev_err(dwc
->dev
, "missing peripheral IRQ\n");
3174 * dwc3_gadget_init - initializes gadget related registers
3175 * @dwc: pointer to our controller context structure
3177 * Returns 0 on success otherwise negative errno.
3179 int dwc3_gadget_init(struct dwc3
*dwc
)
3184 irq
= dwc3_gadget_get_irq(dwc
);
3190 dwc
->irq_gadget
= irq
;
3192 dwc
->ep0_trb
= dma_alloc_coherent(dwc
->sysdev
,
3193 sizeof(*dwc
->ep0_trb
) * 2,
3194 &dwc
->ep0_trb_addr
, GFP_KERNEL
);
3195 if (!dwc
->ep0_trb
) {
3196 dev_err(dwc
->dev
, "failed to allocate ep0 trb\n");
3201 dwc
->setup_buf
= kzalloc(DWC3_EP0_SETUP_SIZE
, GFP_KERNEL
);
3202 if (!dwc
->setup_buf
) {
3207 dwc
->bounce
= dma_alloc_coherent(dwc
->sysdev
, DWC3_BOUNCE_SIZE
,
3208 &dwc
->bounce_addr
, GFP_KERNEL
);
3214 init_completion(&dwc
->ep0_in_setup
);
3216 dwc
->gadget
.ops
= &dwc3_gadget_ops
;
3217 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
3218 dwc
->gadget
.sg_supported
= true;
3219 dwc
->gadget
.name
= "dwc3-gadget";
3220 dwc
->gadget
.is_otg
= dwc
->dr_mode
== USB_DR_MODE_OTG
;
3223 * FIXME We might be setting max_speed to <SUPER, however versions
3224 * <2.20a of dwc3 have an issue with metastability (documented
3225 * elsewhere in this driver) which tells us we can't set max speed to
3226 * anything lower than SUPER.
3228 * Because gadget.max_speed is only used by composite.c and function
3229 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3230 * to happen so we avoid sending SuperSpeed Capability descriptor
3231 * together with our BOS descriptor as that could confuse host into
3232 * thinking we can handle super speed.
3234 * Note that, in fact, we won't even support GetBOS requests when speed
3235 * is less than super speed because we don't have means, yet, to tell
3236 * composite.c that we are USB 2.0 + LPM ECN.
3238 if (dwc
->revision
< DWC3_REVISION_220A
)
3239 dev_info(dwc
->dev
, "changing max_speed on rev %08x\n",
3242 dwc
->gadget
.max_speed
= dwc
->maximum_speed
;
3245 * REVISIT: Here we should clear all pending IRQs to be
3246 * sure we're starting from a well known location.
3249 ret
= dwc3_gadget_init_endpoints(dwc
, dwc
->num_eps
);
3253 ret
= usb_add_gadget_udc(dwc
->dev
, &dwc
->gadget
);
3255 dev_err(dwc
->dev
, "failed to register udc\n");
3262 dwc3_gadget_free_endpoints(dwc
);
3265 dma_free_coherent(dwc
->sysdev
, DWC3_BOUNCE_SIZE
, dwc
->bounce
,
3269 kfree(dwc
->setup_buf
);
3272 dma_free_coherent(dwc
->sysdev
, sizeof(*dwc
->ep0_trb
) * 2,
3273 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
3279 /* -------------------------------------------------------------------------- */
3281 void dwc3_gadget_exit(struct dwc3
*dwc
)
3283 usb_del_gadget_udc(&dwc
->gadget
);
3284 dwc3_gadget_free_endpoints(dwc
);
3285 dma_free_coherent(dwc
->sysdev
, DWC3_BOUNCE_SIZE
, dwc
->bounce
,
3287 kfree(dwc
->setup_buf
);
3288 dma_free_coherent(dwc
->sysdev
, sizeof(*dwc
->ep0_trb
) * 2,
3289 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
3292 int dwc3_gadget_suspend(struct dwc3
*dwc
)
3294 if (!dwc
->gadget_driver
)
3297 dwc3_gadget_run_stop(dwc
, false, false);
3298 dwc3_disconnect_gadget(dwc
);
3299 __dwc3_gadget_stop(dwc
);
3301 synchronize_irq(dwc
->irq_gadget
);
3306 int dwc3_gadget_resume(struct dwc3
*dwc
)
3310 if (!dwc
->gadget_driver
)
3313 ret
= __dwc3_gadget_start(dwc
);
3317 ret
= dwc3_gadget_run_stop(dwc
, true, false);
3324 __dwc3_gadget_stop(dwc
);
3330 void dwc3_gadget_process_pending_events(struct dwc3
*dwc
)
3332 if (dwc
->pending_events
) {
3333 dwc3_interrupt(dwc
->irq_gadget
, dwc
->ev_buf
);
3334 dwc
->pending_events
= false;
3335 enable_irq(dwc
->irq_gadget
);