1 // SPDX-License-Identifier: GPL-2.0
3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/spinlock.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/interrupt.h>
19 #include <linux/list.h>
20 #include <linux/dma-mapping.h>
22 #include <linux/usb/ch9.h>
23 #include <linux/usb/gadget.h>
30 #define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \
31 & ~((d)->interval - 1))
34 * dwc3_gadget_set_test_mode - enables usb2 test modes
35 * @dwc: pointer to our context structure
36 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
38 * Caller should take care of locking. This function will return 0 on
39 * success or -EINVAL if wrong Test Selector is passed.
41 int dwc3_gadget_set_test_mode(struct dwc3
*dwc
, int mode
)
45 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
46 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
60 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
66 * dwc3_gadget_get_link_state - gets current state of usb link
67 * @dwc: pointer to our context structure
69 * Caller should take care of locking. This function will
70 * return the link state on success (>= 0) or -ETIMEDOUT.
72 int dwc3_gadget_get_link_state(struct dwc3
*dwc
)
76 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
78 return DWC3_DSTS_USBLNKST(reg
);
82 * dwc3_gadget_set_link_state - sets usb link to a particular state
83 * @dwc: pointer to our context structure
84 * @state: the state to put link into
86 * Caller should take care of locking. This function will
87 * return 0 on success or -ETIMEDOUT.
89 int dwc3_gadget_set_link_state(struct dwc3
*dwc
, enum dwc3_link_state state
)
95 * Wait until device controller is ready. Only applies to 1.94a and
98 if (dwc
->revision
>= DWC3_REVISION_194A
) {
100 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
101 if (reg
& DWC3_DSTS_DCNRD
)
111 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
112 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
114 /* set requested state */
115 reg
|= DWC3_DCTL_ULSTCHNGREQ(state
);
116 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
119 * The following code is racy when called from dwc3_gadget_wakeup,
120 * and is not needed, at least on newer versions
122 if (dwc
->revision
>= DWC3_REVISION_194A
)
125 /* wait for a change in DSTS */
128 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
130 if (DWC3_DSTS_USBLNKST(reg
) == state
)
140 * dwc3_ep_inc_trb - increment a trb index.
141 * @index: Pointer to the TRB index to increment.
143 * The index should never point to the link TRB. After incrementing,
144 * if it is point to the link TRB, wrap around to the beginning. The
145 * link TRB is always at the last TRB entry.
147 static void dwc3_ep_inc_trb(u8
*index
)
150 if (*index
== (DWC3_TRB_NUM
- 1))
155 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
156 * @dep: The endpoint whose enqueue pointer we're incrementing
158 static void dwc3_ep_inc_enq(struct dwc3_ep
*dep
)
160 dwc3_ep_inc_trb(&dep
->trb_enqueue
);
164 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
165 * @dep: The endpoint whose enqueue pointer we're incrementing
167 static void dwc3_ep_inc_deq(struct dwc3_ep
*dep
)
169 dwc3_ep_inc_trb(&dep
->trb_dequeue
);
172 static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep
*dep
,
173 struct dwc3_request
*req
, int status
)
175 struct dwc3
*dwc
= dep
->dwc
;
177 list_del(&req
->list
);
179 req
->needs_extra_trb
= false;
181 if (req
->request
.status
== -EINPROGRESS
)
182 req
->request
.status
= status
;
185 usb_gadget_unmap_request_by_dev(dwc
->sysdev
,
186 &req
->request
, req
->direction
);
189 trace_dwc3_gadget_giveback(req
);
192 pm_runtime_put(dwc
->dev
);
196 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
197 * @dep: The endpoint to whom the request belongs to
198 * @req: The request we're giving back
199 * @status: completion code for the request
201 * Must be called with controller's lock held and interrupts disabled. This
202 * function will unmap @req and call its ->complete() callback to notify upper
203 * layers that it has completed.
205 void dwc3_gadget_giveback(struct dwc3_ep
*dep
, struct dwc3_request
*req
,
208 struct dwc3
*dwc
= dep
->dwc
;
210 dwc3_gadget_del_and_unmap_request(dep
, req
, status
);
211 req
->status
= DWC3_REQUEST_STATUS_COMPLETED
;
213 spin_unlock(&dwc
->lock
);
214 usb_gadget_giveback_request(&dep
->endpoint
, &req
->request
);
215 spin_lock(&dwc
->lock
);
219 * dwc3_send_gadget_generic_command - issue a generic command for the controller
220 * @dwc: pointer to the controller context
221 * @cmd: the command to be issued
222 * @param: command parameter
224 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
225 * and wait for its completion.
227 int dwc3_send_gadget_generic_command(struct dwc3
*dwc
, unsigned cmd
, u32 param
)
234 dwc3_writel(dwc
->regs
, DWC3_DGCMDPAR
, param
);
235 dwc3_writel(dwc
->regs
, DWC3_DGCMD
, cmd
| DWC3_DGCMD_CMDACT
);
238 reg
= dwc3_readl(dwc
->regs
, DWC3_DGCMD
);
239 if (!(reg
& DWC3_DGCMD_CMDACT
)) {
240 status
= DWC3_DGCMD_STATUS(reg
);
252 trace_dwc3_gadget_generic_cmd(cmd
, param
, status
);
257 static int __dwc3_gadget_wakeup(struct dwc3
*dwc
);
260 * dwc3_send_gadget_ep_cmd - issue an endpoint command
261 * @dep: the endpoint to which the command is going to be issued
262 * @cmd: the command to be issued
263 * @params: parameters to the command
265 * Caller should handle locking. This function will issue @cmd with given
266 * @params to @dep and wait for its completion.
268 int dwc3_send_gadget_ep_cmd(struct dwc3_ep
*dep
, unsigned cmd
,
269 struct dwc3_gadget_ep_cmd_params
*params
)
271 const struct usb_endpoint_descriptor
*desc
= dep
->endpoint
.desc
;
272 struct dwc3
*dwc
= dep
->dwc
;
274 u32 saved_config
= 0;
281 * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
282 * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
285 * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
286 * settings. Restore them after the command is completed.
288 * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
290 if (dwc
->gadget
.speed
<= USB_SPEED_HIGH
) {
291 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
292 if (unlikely(reg
& DWC3_GUSB2PHYCFG_SUSPHY
)) {
293 saved_config
|= DWC3_GUSB2PHYCFG_SUSPHY
;
294 reg
&= ~DWC3_GUSB2PHYCFG_SUSPHY
;
297 if (reg
& DWC3_GUSB2PHYCFG_ENBLSLPM
) {
298 saved_config
|= DWC3_GUSB2PHYCFG_ENBLSLPM
;
299 reg
&= ~DWC3_GUSB2PHYCFG_ENBLSLPM
;
303 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
306 if (DWC3_DEPCMD_CMD(cmd
) == DWC3_DEPCMD_STARTTRANSFER
) {
309 needs_wakeup
= (dwc
->link_state
== DWC3_LINK_STATE_U1
||
310 dwc
->link_state
== DWC3_LINK_STATE_U2
||
311 dwc
->link_state
== DWC3_LINK_STATE_U3
);
313 if (unlikely(needs_wakeup
)) {
314 ret
= __dwc3_gadget_wakeup(dwc
);
315 dev_WARN_ONCE(dwc
->dev
, ret
, "wakeup failed --> %d\n",
320 dwc3_writel(dep
->regs
, DWC3_DEPCMDPAR0
, params
->param0
);
321 dwc3_writel(dep
->regs
, DWC3_DEPCMDPAR1
, params
->param1
);
322 dwc3_writel(dep
->regs
, DWC3_DEPCMDPAR2
, params
->param2
);
325 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
326 * not relying on XferNotReady, we can make use of a special "No
327 * Response Update Transfer" command where we should clear both CmdAct
330 * With this, we don't need to wait for command completion and can
331 * straight away issue further commands to the endpoint.
333 * NOTICE: We're making an assumption that control endpoints will never
334 * make use of Update Transfer command. This is a safe assumption
335 * because we can never have more than one request at a time with
336 * Control Endpoints. If anybody changes that assumption, this chunk
337 * needs to be updated accordingly.
339 if (DWC3_DEPCMD_CMD(cmd
) == DWC3_DEPCMD_UPDATETRANSFER
&&
340 !usb_endpoint_xfer_isoc(desc
))
341 cmd
&= ~(DWC3_DEPCMD_CMDIOC
| DWC3_DEPCMD_CMDACT
);
343 cmd
|= DWC3_DEPCMD_CMDACT
;
345 dwc3_writel(dep
->regs
, DWC3_DEPCMD
, cmd
);
347 reg
= dwc3_readl(dep
->regs
, DWC3_DEPCMD
);
348 if (!(reg
& DWC3_DEPCMD_CMDACT
)) {
349 cmd_status
= DWC3_DEPCMD_STATUS(reg
);
351 switch (cmd_status
) {
355 case DEPEVT_TRANSFER_NO_RESOURCE
:
358 case DEPEVT_TRANSFER_BUS_EXPIRY
:
360 * SW issues START TRANSFER command to
361 * isochronous ep with future frame interval. If
362 * future interval time has already passed when
363 * core receives the command, it will respond
364 * with an error status of 'Bus Expiry'.
366 * Instead of always returning -EINVAL, let's
367 * give a hint to the gadget driver that this is
368 * the case by returning -EAGAIN.
373 dev_WARN(dwc
->dev
, "UNKNOWN cmd status\n");
382 cmd_status
= -ETIMEDOUT
;
385 trace_dwc3_gadget_ep_cmd(dep
, cmd
, params
, cmd_status
);
387 if (ret
== 0 && DWC3_DEPCMD_CMD(cmd
) == DWC3_DEPCMD_STARTTRANSFER
) {
388 dep
->flags
|= DWC3_EP_TRANSFER_STARTED
;
389 dwc3_gadget_ep_get_transfer_index(dep
);
393 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
395 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
401 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep
*dep
)
403 struct dwc3
*dwc
= dep
->dwc
;
404 struct dwc3_gadget_ep_cmd_params params
;
405 u32 cmd
= DWC3_DEPCMD_CLEARSTALL
;
408 * As of core revision 2.60a the recommended programming model
409 * is to set the ClearPendIN bit when issuing a Clear Stall EP
410 * command for IN endpoints. This is to prevent an issue where
411 * some (non-compliant) hosts may not send ACK TPs for pending
412 * IN transfers due to a mishandled error condition. Synopsys
415 if (dep
->direction
&& (dwc
->revision
>= DWC3_REVISION_260A
) &&
416 (dwc
->gadget
.speed
>= USB_SPEED_SUPER
))
417 cmd
|= DWC3_DEPCMD_CLEARPENDIN
;
419 memset(¶ms
, 0, sizeof(params
));
421 return dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
424 static dma_addr_t
dwc3_trb_dma_offset(struct dwc3_ep
*dep
,
425 struct dwc3_trb
*trb
)
427 u32 offset
= (char *) trb
- (char *) dep
->trb_pool
;
429 return dep
->trb_pool_dma
+ offset
;
432 static int dwc3_alloc_trb_pool(struct dwc3_ep
*dep
)
434 struct dwc3
*dwc
= dep
->dwc
;
439 dep
->trb_pool
= dma_alloc_coherent(dwc
->sysdev
,
440 sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
441 &dep
->trb_pool_dma
, GFP_KERNEL
);
442 if (!dep
->trb_pool
) {
443 dev_err(dep
->dwc
->dev
, "failed to allocate trb pool for %s\n",
451 static void dwc3_free_trb_pool(struct dwc3_ep
*dep
)
453 struct dwc3
*dwc
= dep
->dwc
;
455 dma_free_coherent(dwc
->sysdev
, sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
456 dep
->trb_pool
, dep
->trb_pool_dma
);
458 dep
->trb_pool
= NULL
;
459 dep
->trb_pool_dma
= 0;
462 static int dwc3_gadget_set_xfer_resource(struct dwc3_ep
*dep
)
464 struct dwc3_gadget_ep_cmd_params params
;
466 memset(¶ms
, 0x00, sizeof(params
));
468 params
.param0
= DWC3_DEPXFERCFG_NUM_XFER_RES(1);
470 return dwc3_send_gadget_ep_cmd(dep
, DWC3_DEPCMD_SETTRANSFRESOURCE
,
475 * dwc3_gadget_start_config - configure ep resources
476 * @dep: endpoint that is being enabled
478 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
479 * completion, it will set Transfer Resource for all available endpoints.
481 * The assignment of transfer resources cannot perfectly follow the data book
482 * due to the fact that the controller driver does not have all knowledge of the
483 * configuration in advance. It is given this information piecemeal by the
484 * composite gadget framework after every SET_CONFIGURATION and
485 * SET_INTERFACE. Trying to follow the databook programming model in this
486 * scenario can cause errors. For two reasons:
488 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
489 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
490 * incorrect in the scenario of multiple interfaces.
492 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
493 * endpoint on alt setting (8.1.6).
495 * The following simplified method is used instead:
497 * All hardware endpoints can be assigned a transfer resource and this setting
498 * will stay persistent until either a core reset or hibernation. So whenever we
499 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
500 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
501 * guaranteed that there are as many transfer resources as endpoints.
503 * This function is called for each endpoint when it is being enabled but is
504 * triggered only when called for EP0-out, which always happens first, and which
505 * should only happen in one of the above conditions.
507 static int dwc3_gadget_start_config(struct dwc3_ep
*dep
)
509 struct dwc3_gadget_ep_cmd_params params
;
518 memset(¶ms
, 0x00, sizeof(params
));
519 cmd
= DWC3_DEPCMD_DEPSTARTCFG
;
522 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
526 for (i
= 0; i
< DWC3_ENDPOINTS_NUM
; i
++) {
527 struct dwc3_ep
*dep
= dwc
->eps
[i
];
532 ret
= dwc3_gadget_set_xfer_resource(dep
);
540 static int dwc3_gadget_set_ep_config(struct dwc3_ep
*dep
, unsigned int action
)
542 const struct usb_ss_ep_comp_descriptor
*comp_desc
;
543 const struct usb_endpoint_descriptor
*desc
;
544 struct dwc3_gadget_ep_cmd_params params
;
545 struct dwc3
*dwc
= dep
->dwc
;
547 comp_desc
= dep
->endpoint
.comp_desc
;
548 desc
= dep
->endpoint
.desc
;
550 memset(¶ms
, 0x00, sizeof(params
));
552 params
.param0
= DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc
))
553 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc
));
555 /* Burst size is only needed in SuperSpeed mode */
556 if (dwc
->gadget
.speed
>= USB_SPEED_SUPER
) {
557 u32 burst
= dep
->endpoint
.maxburst
;
558 params
.param0
|= DWC3_DEPCFG_BURST_SIZE(burst
- 1);
561 params
.param0
|= action
;
562 if (action
== DWC3_DEPCFG_ACTION_RESTORE
)
563 params
.param2
|= dep
->saved_state
;
565 if (usb_endpoint_xfer_control(desc
))
566 params
.param1
= DWC3_DEPCFG_XFER_COMPLETE_EN
;
568 if (dep
->number
<= 1 || usb_endpoint_xfer_isoc(desc
))
569 params
.param1
|= DWC3_DEPCFG_XFER_NOT_READY_EN
;
571 if (usb_ss_max_streams(comp_desc
) && usb_endpoint_xfer_bulk(desc
)) {
572 params
.param1
|= DWC3_DEPCFG_STREAM_CAPABLE
573 | DWC3_DEPCFG_STREAM_EVENT_EN
;
574 dep
->stream_capable
= true;
577 if (!usb_endpoint_xfer_control(desc
))
578 params
.param1
|= DWC3_DEPCFG_XFER_IN_PROGRESS_EN
;
581 * We are doing 1:1 mapping for endpoints, meaning
582 * Physical Endpoints 2 maps to Logical Endpoint 2 and
583 * so on. We consider the direction bit as part of the physical
584 * endpoint number. So USB endpoint 0x81 is 0x03.
586 params
.param1
|= DWC3_DEPCFG_EP_NUMBER(dep
->number
);
589 * We must use the lower 16 TX FIFOs even though
593 params
.param0
|= DWC3_DEPCFG_FIFO_NUMBER(dep
->number
>> 1);
595 if (desc
->bInterval
) {
596 params
.param1
|= DWC3_DEPCFG_BINTERVAL_M1(desc
->bInterval
- 1);
597 dep
->interval
= 1 << (desc
->bInterval
- 1);
600 return dwc3_send_gadget_ep_cmd(dep
, DWC3_DEPCMD_SETEPCONFIG
, ¶ms
);
604 * __dwc3_gadget_ep_enable - initializes a hw endpoint
605 * @dep: endpoint to be initialized
606 * @action: one of INIT, MODIFY or RESTORE
608 * Caller should take care of locking. Execute all necessary commands to
609 * initialize a HW endpoint so it can be used by a gadget driver.
611 static int __dwc3_gadget_ep_enable(struct dwc3_ep
*dep
, unsigned int action
)
613 const struct usb_endpoint_descriptor
*desc
= dep
->endpoint
.desc
;
614 struct dwc3
*dwc
= dep
->dwc
;
619 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
620 ret
= dwc3_gadget_start_config(dep
);
625 ret
= dwc3_gadget_set_ep_config(dep
, action
);
629 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
630 struct dwc3_trb
*trb_st_hw
;
631 struct dwc3_trb
*trb_link
;
633 dep
->type
= usb_endpoint_type(desc
);
634 dep
->flags
|= DWC3_EP_ENABLED
;
635 dep
->flags
&= ~DWC3_EP_END_TRANSFER_PENDING
;
637 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
638 reg
|= DWC3_DALEPENA_EP(dep
->number
);
639 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
641 if (usb_endpoint_xfer_control(desc
))
644 /* Initialize the TRB ring */
645 dep
->trb_dequeue
= 0;
646 dep
->trb_enqueue
= 0;
647 memset(dep
->trb_pool
, 0,
648 sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
);
650 /* Link TRB. The HWO bit is never reset */
651 trb_st_hw
= &dep
->trb_pool
[0];
653 trb_link
= &dep
->trb_pool
[DWC3_TRB_NUM
- 1];
654 trb_link
->bpl
= lower_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
655 trb_link
->bph
= upper_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
656 trb_link
->ctrl
|= DWC3_TRBCTL_LINK_TRB
;
657 trb_link
->ctrl
|= DWC3_TRB_CTRL_HWO
;
661 * Issue StartTransfer here with no-op TRB so we can always rely on No
662 * Response Update Transfer command.
664 if ((usb_endpoint_xfer_bulk(desc
) && !dep
->stream_capable
) ||
665 usb_endpoint_xfer_int(desc
)) {
666 struct dwc3_gadget_ep_cmd_params params
;
667 struct dwc3_trb
*trb
;
671 memset(¶ms
, 0, sizeof(params
));
672 trb
= &dep
->trb_pool
[0];
673 trb_dma
= dwc3_trb_dma_offset(dep
, trb
);
675 params
.param0
= upper_32_bits(trb_dma
);
676 params
.param1
= lower_32_bits(trb_dma
);
678 cmd
= DWC3_DEPCMD_STARTTRANSFER
;
680 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
686 trace_dwc3_gadget_ep_enable(dep
);
691 static void dwc3_stop_active_transfer(struct dwc3_ep
*dep
, bool force
);
692 static void dwc3_remove_requests(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
694 struct dwc3_request
*req
;
696 dwc3_stop_active_transfer(dep
, true);
698 /* - giveback all requests to gadget driver */
699 while (!list_empty(&dep
->started_list
)) {
700 req
= next_request(&dep
->started_list
);
702 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
705 while (!list_empty(&dep
->pending_list
)) {
706 req
= next_request(&dep
->pending_list
);
708 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
713 * __dwc3_gadget_ep_disable - disables a hw endpoint
714 * @dep: the endpoint to disable
716 * This function undoes what __dwc3_gadget_ep_enable did and also removes
717 * requests which are currently being processed by the hardware and those which
718 * are not yet scheduled.
720 * Caller should take care of locking.
722 static int __dwc3_gadget_ep_disable(struct dwc3_ep
*dep
)
724 struct dwc3
*dwc
= dep
->dwc
;
727 trace_dwc3_gadget_ep_disable(dep
);
729 dwc3_remove_requests(dwc
, dep
);
731 /* make sure HW endpoint isn't stalled */
732 if (dep
->flags
& DWC3_EP_STALL
)
733 __dwc3_gadget_ep_set_halt(dep
, 0, false);
735 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
736 reg
&= ~DWC3_DALEPENA_EP(dep
->number
);
737 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
739 dep
->stream_capable
= false;
741 dep
->flags
&= DWC3_EP_END_TRANSFER_PENDING
;
743 /* Clear out the ep descriptors for non-ep0 */
744 if (dep
->number
> 1) {
745 dep
->endpoint
.comp_desc
= NULL
;
746 dep
->endpoint
.desc
= NULL
;
752 /* -------------------------------------------------------------------------- */
754 static int dwc3_gadget_ep0_enable(struct usb_ep
*ep
,
755 const struct usb_endpoint_descriptor
*desc
)
760 static int dwc3_gadget_ep0_disable(struct usb_ep
*ep
)
765 /* -------------------------------------------------------------------------- */
767 static int dwc3_gadget_ep_enable(struct usb_ep
*ep
,
768 const struct usb_endpoint_descriptor
*desc
)
775 if (!ep
|| !desc
|| desc
->bDescriptorType
!= USB_DT_ENDPOINT
) {
776 pr_debug("dwc3: invalid parameters\n");
780 if (!desc
->wMaxPacketSize
) {
781 pr_debug("dwc3: missing wMaxPacketSize\n");
785 dep
= to_dwc3_ep(ep
);
788 if (dev_WARN_ONCE(dwc
->dev
, dep
->flags
& DWC3_EP_ENABLED
,
789 "%s is already enabled\n",
793 spin_lock_irqsave(&dwc
->lock
, flags
);
794 ret
= __dwc3_gadget_ep_enable(dep
, DWC3_DEPCFG_ACTION_INIT
);
795 spin_unlock_irqrestore(&dwc
->lock
, flags
);
800 static int dwc3_gadget_ep_disable(struct usb_ep
*ep
)
808 pr_debug("dwc3: invalid parameters\n");
812 dep
= to_dwc3_ep(ep
);
815 if (dev_WARN_ONCE(dwc
->dev
, !(dep
->flags
& DWC3_EP_ENABLED
),
816 "%s is already disabled\n",
820 spin_lock_irqsave(&dwc
->lock
, flags
);
821 ret
= __dwc3_gadget_ep_disable(dep
);
822 spin_unlock_irqrestore(&dwc
->lock
, flags
);
827 static struct usb_request
*dwc3_gadget_ep_alloc_request(struct usb_ep
*ep
,
830 struct dwc3_request
*req
;
831 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
833 req
= kzalloc(sizeof(*req
), gfp_flags
);
837 req
->direction
= dep
->direction
;
838 req
->epnum
= dep
->number
;
840 req
->status
= DWC3_REQUEST_STATUS_UNKNOWN
;
842 trace_dwc3_alloc_request(req
);
844 return &req
->request
;
847 static void dwc3_gadget_ep_free_request(struct usb_ep
*ep
,
848 struct usb_request
*request
)
850 struct dwc3_request
*req
= to_dwc3_request(request
);
852 trace_dwc3_free_request(req
);
857 * dwc3_ep_prev_trb - returns the previous TRB in the ring
858 * @dep: The endpoint with the TRB ring
859 * @index: The index of the current TRB in the ring
861 * Returns the TRB prior to the one pointed to by the index. If the
862 * index is 0, we will wrap backwards, skip the link TRB, and return
863 * the one just before that.
865 static struct dwc3_trb
*dwc3_ep_prev_trb(struct dwc3_ep
*dep
, u8 index
)
870 tmp
= DWC3_TRB_NUM
- 1;
872 return &dep
->trb_pool
[tmp
- 1];
875 static u32
dwc3_calc_trbs_left(struct dwc3_ep
*dep
)
877 struct dwc3_trb
*tmp
;
881 * If enqueue & dequeue are equal than it is either full or empty.
883 * One way to know for sure is if the TRB right before us has HWO bit
884 * set or not. If it has, then we're definitely full and can't fit any
885 * more transfers in our ring.
887 if (dep
->trb_enqueue
== dep
->trb_dequeue
) {
888 tmp
= dwc3_ep_prev_trb(dep
, dep
->trb_enqueue
);
889 if (tmp
->ctrl
& DWC3_TRB_CTRL_HWO
)
892 return DWC3_TRB_NUM
- 1;
895 trbs_left
= dep
->trb_dequeue
- dep
->trb_enqueue
;
896 trbs_left
&= (DWC3_TRB_NUM
- 1);
898 if (dep
->trb_dequeue
< dep
->trb_enqueue
)
904 static void __dwc3_prepare_one_trb(struct dwc3_ep
*dep
, struct dwc3_trb
*trb
,
905 dma_addr_t dma
, unsigned length
, unsigned chain
, unsigned node
,
906 unsigned stream_id
, unsigned short_not_ok
, unsigned no_interrupt
)
908 struct dwc3
*dwc
= dep
->dwc
;
909 struct usb_gadget
*gadget
= &dwc
->gadget
;
910 enum usb_device_speed speed
= gadget
->speed
;
912 trb
->size
= DWC3_TRB_SIZE_LENGTH(length
);
913 trb
->bpl
= lower_32_bits(dma
);
914 trb
->bph
= upper_32_bits(dma
);
916 switch (usb_endpoint_type(dep
->endpoint
.desc
)) {
917 case USB_ENDPOINT_XFER_CONTROL
:
918 trb
->ctrl
= DWC3_TRBCTL_CONTROL_SETUP
;
921 case USB_ENDPOINT_XFER_ISOC
:
923 trb
->ctrl
= DWC3_TRBCTL_ISOCHRONOUS_FIRST
;
926 * USB Specification 2.0 Section 5.9.2 states that: "If
927 * there is only a single transaction in the microframe,
928 * only a DATA0 data packet PID is used. If there are
929 * two transactions per microframe, DATA1 is used for
930 * the first transaction data packet and DATA0 is used
931 * for the second transaction data packet. If there are
932 * three transactions per microframe, DATA2 is used for
933 * the first transaction data packet, DATA1 is used for
934 * the second, and DATA0 is used for the third."
936 * IOW, we should satisfy the following cases:
938 * 1) length <= maxpacket
941 * 2) maxpacket < length <= (2 * maxpacket)
944 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
945 * - DATA2, DATA1, DATA0
947 if (speed
== USB_SPEED_HIGH
) {
948 struct usb_ep
*ep
= &dep
->endpoint
;
949 unsigned int mult
= 2;
950 unsigned int maxp
= usb_endpoint_maxp(ep
->desc
);
952 if (length
<= (2 * maxp
))
958 trb
->size
|= DWC3_TRB_SIZE_PCM1(mult
);
961 trb
->ctrl
= DWC3_TRBCTL_ISOCHRONOUS
;
964 /* always enable Interrupt on Missed ISOC */
965 trb
->ctrl
|= DWC3_TRB_CTRL_ISP_IMI
;
968 case USB_ENDPOINT_XFER_BULK
:
969 case USB_ENDPOINT_XFER_INT
:
970 trb
->ctrl
= DWC3_TRBCTL_NORMAL
;
974 * This is only possible with faulty memory because we
975 * checked it already :)
977 dev_WARN(dwc
->dev
, "Unknown endpoint type %d\n",
978 usb_endpoint_type(dep
->endpoint
.desc
));
982 * Enable Continue on Short Packet
983 * when endpoint is not a stream capable
985 if (usb_endpoint_dir_out(dep
->endpoint
.desc
)) {
986 if (!dep
->stream_capable
)
987 trb
->ctrl
|= DWC3_TRB_CTRL_CSP
;
990 trb
->ctrl
|= DWC3_TRB_CTRL_ISP_IMI
;
993 if ((!no_interrupt
&& !chain
) ||
994 (dwc3_calc_trbs_left(dep
) == 1))
995 trb
->ctrl
|= DWC3_TRB_CTRL_IOC
;
998 trb
->ctrl
|= DWC3_TRB_CTRL_CHN
;
1000 if (usb_endpoint_xfer_bulk(dep
->endpoint
.desc
) && dep
->stream_capable
)
1001 trb
->ctrl
|= DWC3_TRB_CTRL_SID_SOFN(stream_id
);
1003 trb
->ctrl
|= DWC3_TRB_CTRL_HWO
;
1005 dwc3_ep_inc_enq(dep
);
1007 trace_dwc3_prepare_trb(dep
, trb
);
1011 * dwc3_prepare_one_trb - setup one TRB from one request
1012 * @dep: endpoint for which this request is prepared
1013 * @req: dwc3_request pointer
1014 * @chain: should this TRB be chained to the next?
1015 * @node: only for isochronous endpoints. First TRB needs different type.
1017 static void dwc3_prepare_one_trb(struct dwc3_ep
*dep
,
1018 struct dwc3_request
*req
, unsigned chain
, unsigned node
)
1020 struct dwc3_trb
*trb
;
1021 unsigned int length
;
1023 unsigned stream_id
= req
->request
.stream_id
;
1024 unsigned short_not_ok
= req
->request
.short_not_ok
;
1025 unsigned no_interrupt
= req
->request
.no_interrupt
;
1027 if (req
->request
.num_sgs
> 0) {
1028 length
= sg_dma_len(req
->start_sg
);
1029 dma
= sg_dma_address(req
->start_sg
);
1031 length
= req
->request
.length
;
1032 dma
= req
->request
.dma
;
1035 trb
= &dep
->trb_pool
[dep
->trb_enqueue
];
1038 dwc3_gadget_move_started_request(req
);
1040 req
->trb_dma
= dwc3_trb_dma_offset(dep
, trb
);
1045 __dwc3_prepare_one_trb(dep
, trb
, dma
, length
, chain
, node
,
1046 stream_id
, short_not_ok
, no_interrupt
);
1049 static void dwc3_prepare_one_trb_sg(struct dwc3_ep
*dep
,
1050 struct dwc3_request
*req
)
1052 struct scatterlist
*sg
= req
->start_sg
;
1053 struct scatterlist
*s
;
1056 unsigned int remaining
= req
->request
.num_mapped_sgs
1057 - req
->num_queued_sgs
;
1059 for_each_sg(sg
, s
, remaining
, i
) {
1060 unsigned int length
= req
->request
.length
;
1061 unsigned int maxp
= usb_endpoint_maxp(dep
->endpoint
.desc
);
1062 unsigned int rem
= length
% maxp
;
1063 unsigned chain
= true;
1068 if (rem
&& usb_endpoint_dir_out(dep
->endpoint
.desc
) && !chain
) {
1069 struct dwc3
*dwc
= dep
->dwc
;
1070 struct dwc3_trb
*trb
;
1072 req
->needs_extra_trb
= true;
1074 /* prepare normal TRB */
1075 dwc3_prepare_one_trb(dep
, req
, true, i
);
1077 /* Now prepare one extra TRB to align transfer size */
1078 trb
= &dep
->trb_pool
[dep
->trb_enqueue
];
1080 __dwc3_prepare_one_trb(dep
, trb
, dwc
->bounce_addr
,
1081 maxp
- rem
, false, 1,
1082 req
->request
.stream_id
,
1083 req
->request
.short_not_ok
,
1084 req
->request
.no_interrupt
);
1086 dwc3_prepare_one_trb(dep
, req
, chain
, i
);
1090 * There can be a situation where all sgs in sglist are not
1091 * queued because of insufficient trb number. To handle this
1092 * case, update start_sg to next sg to be queued, so that
1093 * we have free trbs we can continue queuing from where we
1094 * previously stopped
1097 req
->start_sg
= sg_next(s
);
1099 req
->num_queued_sgs
++;
1101 if (!dwc3_calc_trbs_left(dep
))
1106 static void dwc3_prepare_one_trb_linear(struct dwc3_ep
*dep
,
1107 struct dwc3_request
*req
)
1109 unsigned int length
= req
->request
.length
;
1110 unsigned int maxp
= usb_endpoint_maxp(dep
->endpoint
.desc
);
1111 unsigned int rem
= length
% maxp
;
1113 if (rem
&& usb_endpoint_dir_out(dep
->endpoint
.desc
)) {
1114 struct dwc3
*dwc
= dep
->dwc
;
1115 struct dwc3_trb
*trb
;
1117 req
->needs_extra_trb
= true;
1119 /* prepare normal TRB */
1120 dwc3_prepare_one_trb(dep
, req
, true, 0);
1122 /* Now prepare one extra TRB to align transfer size */
1123 trb
= &dep
->trb_pool
[dep
->trb_enqueue
];
1125 __dwc3_prepare_one_trb(dep
, trb
, dwc
->bounce_addr
, maxp
- rem
,
1126 false, 1, req
->request
.stream_id
,
1127 req
->request
.short_not_ok
,
1128 req
->request
.no_interrupt
);
1129 } else if (req
->request
.zero
&& req
->request
.length
&&
1130 (IS_ALIGNED(req
->request
.length
, maxp
))) {
1131 struct dwc3
*dwc
= dep
->dwc
;
1132 struct dwc3_trb
*trb
;
1134 req
->needs_extra_trb
= true;
1136 /* prepare normal TRB */
1137 dwc3_prepare_one_trb(dep
, req
, true, 0);
1139 /* Now prepare one extra TRB to handle ZLP */
1140 trb
= &dep
->trb_pool
[dep
->trb_enqueue
];
1142 __dwc3_prepare_one_trb(dep
, trb
, dwc
->bounce_addr
, 0,
1143 false, 1, req
->request
.stream_id
,
1144 req
->request
.short_not_ok
,
1145 req
->request
.no_interrupt
);
1147 dwc3_prepare_one_trb(dep
, req
, false, 0);
1152 * dwc3_prepare_trbs - setup TRBs from requests
1153 * @dep: endpoint for which requests are being prepared
1155 * The function goes through the requests list and sets up TRBs for the
1156 * transfers. The function returns once there are no more TRBs available or
1157 * it runs out of requests.
1159 static void dwc3_prepare_trbs(struct dwc3_ep
*dep
)
1161 struct dwc3_request
*req
, *n
;
1163 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM
);
1166 * We can get in a situation where there's a request in the started list
1167 * but there weren't enough TRBs to fully kick it in the first time
1168 * around, so it has been waiting for more TRBs to be freed up.
1170 * In that case, we should check if we have a request with pending_sgs
1171 * in the started list and prepare TRBs for that request first,
1172 * otherwise we will prepare TRBs completely out of order and that will
1175 list_for_each_entry(req
, &dep
->started_list
, list
) {
1176 if (req
->num_pending_sgs
> 0)
1177 dwc3_prepare_one_trb_sg(dep
, req
);
1179 if (!dwc3_calc_trbs_left(dep
))
1183 list_for_each_entry_safe(req
, n
, &dep
->pending_list
, list
) {
1184 struct dwc3
*dwc
= dep
->dwc
;
1187 ret
= usb_gadget_map_request_by_dev(dwc
->sysdev
, &req
->request
,
1192 req
->sg
= req
->request
.sg
;
1193 req
->start_sg
= req
->sg
;
1194 req
->num_queued_sgs
= 0;
1195 req
->num_pending_sgs
= req
->request
.num_mapped_sgs
;
1197 if (req
->num_pending_sgs
> 0)
1198 dwc3_prepare_one_trb_sg(dep
, req
);
1200 dwc3_prepare_one_trb_linear(dep
, req
);
1202 if (!dwc3_calc_trbs_left(dep
))
1207 static int __dwc3_gadget_kick_transfer(struct dwc3_ep
*dep
)
1209 struct dwc3_gadget_ep_cmd_params params
;
1210 struct dwc3_request
*req
;
1215 if (!dwc3_calc_trbs_left(dep
))
1218 starting
= !(dep
->flags
& DWC3_EP_TRANSFER_STARTED
);
1220 dwc3_prepare_trbs(dep
);
1221 req
= next_request(&dep
->started_list
);
1223 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
1227 memset(¶ms
, 0, sizeof(params
));
1230 params
.param0
= upper_32_bits(req
->trb_dma
);
1231 params
.param1
= lower_32_bits(req
->trb_dma
);
1232 cmd
= DWC3_DEPCMD_STARTTRANSFER
;
1234 if (dep
->stream_capable
)
1235 cmd
|= DWC3_DEPCMD_PARAM(req
->request
.stream_id
);
1237 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
1238 cmd
|= DWC3_DEPCMD_PARAM(dep
->frame_number
);
1240 cmd
= DWC3_DEPCMD_UPDATETRANSFER
|
1241 DWC3_DEPCMD_PARAM(dep
->resource_index
);
1244 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
1247 * FIXME we need to iterate over the list of requests
1248 * here and stop, unmap, free and del each of the linked
1249 * requests instead of what we do now.
1252 memset(req
->trb
, 0, sizeof(struct dwc3_trb
));
1253 dwc3_gadget_del_and_unmap_request(dep
, req
, ret
);
1260 static int __dwc3_gadget_get_frame(struct dwc3
*dwc
)
1264 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1265 return DWC3_DSTS_SOFFN(reg
);
1269 * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
1270 * @dep: isoc endpoint
1272 * This function tests for the correct combination of BIT[15:14] from the 16-bit
1273 * microframe number reported by the XferNotReady event for the future frame
1274 * number to start the isoc transfer.
1276 * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
1277 * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
1278 * XferNotReady event are invalid. The driver uses this number to schedule the
1279 * isochronous transfer and passes it to the START TRANSFER command. Because
1280 * this number is invalid, the command may fail. If BIT[15:14] matches the
1281 * internal 16-bit microframe, the START TRANSFER command will pass and the
1282 * transfer will start at the scheduled time, if it is off by 1, the command
1283 * will still pass, but the transfer will start 2 seconds in the future. For all
1284 * other conditions, the START TRANSFER command will fail with bus-expiry.
1286 * In order to workaround this issue, we can test for the correct combination of
1287 * BIT[15:14] by sending START TRANSFER commands with different values of
1288 * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
1289 * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
1290 * As the result, within the 4 possible combinations for BIT[15:14], there will
1291 * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
1292 * command status will result in a 2-second delay start. The smaller BIT[15:14]
1293 * value is the correct combination.
1295 * Since there are only 4 outcomes and the results are ordered, we can simply
1296 * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
1297 * deduce the smaller successful combination.
1299 * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
1300 * of BIT[15:14]. The correct combination is as follow:
1302 * if test0 fails and test1 passes, BIT[15:14] is 'b01
1303 * if test0 fails and test1 fails, BIT[15:14] is 'b10
1304 * if test0 passes and test1 fails, BIT[15:14] is 'b11
1305 * if test0 passes and test1 passes, BIT[15:14] is 'b00
1307 * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
1310 static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep
*dep
)
1316 while (dep
->combo_num
< 2) {
1317 struct dwc3_gadget_ep_cmd_params params
;
1318 u32 test_frame_number
;
1322 * Check if we can start isoc transfer on the next interval or
1323 * 4 uframes in the future with BIT[15:14] as dep->combo_num
1325 test_frame_number
= dep
->frame_number
& 0x3fff;
1326 test_frame_number
|= dep
->combo_num
<< 14;
1327 test_frame_number
+= max_t(u32
, 4, dep
->interval
);
1329 params
.param0
= upper_32_bits(dep
->dwc
->bounce_addr
);
1330 params
.param1
= lower_32_bits(dep
->dwc
->bounce_addr
);
1332 cmd
= DWC3_DEPCMD_STARTTRANSFER
;
1333 cmd
|= DWC3_DEPCMD_PARAM(test_frame_number
);
1334 cmd_status
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
1336 /* Redo if some other failure beside bus-expiry is received */
1337 if (cmd_status
&& cmd_status
!= -EAGAIN
) {
1338 dep
->start_cmd_status
= 0;
1343 /* Store the first test status */
1344 if (dep
->combo_num
== 0)
1345 dep
->start_cmd_status
= cmd_status
;
1350 * End the transfer if the START_TRANSFER command is successful
1351 * to wait for the next XferNotReady to test the command again
1353 if (cmd_status
== 0) {
1354 dwc3_stop_active_transfer(dep
, true);
1359 /* test0 and test1 are both completed at this point */
1360 test0
= (dep
->start_cmd_status
== 0);
1361 test1
= (cmd_status
== 0);
1363 if (!test0
&& test1
)
1365 else if (!test0
&& !test1
)
1367 else if (test0
&& !test1
)
1369 else if (test0
&& test1
)
1372 dep
->frame_number
&= 0x3fff;
1373 dep
->frame_number
|= dep
->combo_num
<< 14;
1374 dep
->frame_number
+= max_t(u32
, 4, dep
->interval
);
1376 /* Reinitialize test variables */
1377 dep
->start_cmd_status
= 0;
1380 return __dwc3_gadget_kick_transfer(dep
);
1383 static int __dwc3_gadget_start_isoc(struct dwc3_ep
*dep
)
1385 struct dwc3
*dwc
= dep
->dwc
;
1389 if (list_empty(&dep
->pending_list
)) {
1390 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
1394 if (!dwc
->dis_start_transfer_quirk
&& dwc3_is_usb31(dwc
) &&
1395 (dwc
->revision
<= DWC3_USB31_REVISION_160A
||
1396 (dwc
->revision
== DWC3_USB31_REVISION_170A
&&
1397 dwc
->version_type
>= DWC31_VERSIONTYPE_EA01
&&
1398 dwc
->version_type
<= DWC31_VERSIONTYPE_EA06
))) {
1400 if (dwc
->gadget
.speed
<= USB_SPEED_HIGH
&& dep
->direction
)
1401 return dwc3_gadget_start_isoc_quirk(dep
);
1404 for (i
= 0; i
< DWC3_ISOC_MAX_RETRIES
; i
++) {
1405 dep
->frame_number
= DWC3_ALIGN_FRAME(dep
, i
+ 1);
1407 ret
= __dwc3_gadget_kick_transfer(dep
);
1415 static int __dwc3_gadget_ep_queue(struct dwc3_ep
*dep
, struct dwc3_request
*req
)
1417 struct dwc3
*dwc
= dep
->dwc
;
1419 if (!dep
->endpoint
.desc
) {
1420 dev_err(dwc
->dev
, "%s: can't queue to disabled endpoint\n",
1425 if (WARN(req
->dep
!= dep
, "request %pK belongs to '%s'\n",
1426 &req
->request
, req
->dep
->name
))
1429 if (WARN(req
->status
< DWC3_REQUEST_STATUS_COMPLETED
,
1430 "%s: request %pK already in flight\n",
1431 dep
->name
, &req
->request
))
1434 pm_runtime_get(dwc
->dev
);
1436 req
->request
.actual
= 0;
1437 req
->request
.status
= -EINPROGRESS
;
1439 trace_dwc3_ep_queue(req
);
1441 list_add_tail(&req
->list
, &dep
->pending_list
);
1442 req
->status
= DWC3_REQUEST_STATUS_QUEUED
;
1445 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1446 * wait for a XferNotReady event so we will know what's the current
1447 * (micro-)frame number.
1449 * Without this trick, we are very, very likely gonna get Bus Expiry
1450 * errors which will force us issue EndTransfer command.
1452 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1453 if (!(dep
->flags
& DWC3_EP_PENDING_REQUEST
) &&
1454 !(dep
->flags
& DWC3_EP_TRANSFER_STARTED
))
1457 if ((dep
->flags
& DWC3_EP_PENDING_REQUEST
)) {
1458 if (!(dep
->flags
& DWC3_EP_TRANSFER_STARTED
)) {
1459 return __dwc3_gadget_start_isoc(dep
);
1464 return __dwc3_gadget_kick_transfer(dep
);
1467 static int dwc3_gadget_ep_queue(struct usb_ep
*ep
, struct usb_request
*request
,
1470 struct dwc3_request
*req
= to_dwc3_request(request
);
1471 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1472 struct dwc3
*dwc
= dep
->dwc
;
1474 unsigned long flags
;
1478 spin_lock_irqsave(&dwc
->lock
, flags
);
1479 ret
= __dwc3_gadget_ep_queue(dep
, req
);
1480 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1485 static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep
*dep
, struct dwc3_request
*req
)
1490 * If request was already started, this means we had to
1491 * stop the transfer. With that we also need to ignore
1492 * all TRBs used by the request, however TRBs can only
1493 * be modified after completion of END_TRANSFER
1494 * command. So what we do here is that we wait for
1495 * END_TRANSFER completion and only after that, we jump
1496 * over TRBs by clearing HWO and incrementing dequeue
1499 for (i
= 0; i
< req
->num_trbs
; i
++) {
1500 struct dwc3_trb
*trb
;
1503 trb
->ctrl
&= ~DWC3_TRB_CTRL_HWO
;
1504 dwc3_ep_inc_deq(dep
);
1508 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep
*dep
)
1510 struct dwc3_request
*req
;
1511 struct dwc3_request
*tmp
;
1513 list_for_each_entry_safe(req
, tmp
, &dep
->cancelled_list
, list
) {
1514 dwc3_gadget_ep_skip_trbs(dep
, req
);
1515 dwc3_gadget_giveback(dep
, req
, -ECONNRESET
);
1519 static int dwc3_gadget_ep_dequeue(struct usb_ep
*ep
,
1520 struct usb_request
*request
)
1522 struct dwc3_request
*req
= to_dwc3_request(request
);
1523 struct dwc3_request
*r
= NULL
;
1525 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1526 struct dwc3
*dwc
= dep
->dwc
;
1528 unsigned long flags
;
1531 trace_dwc3_ep_dequeue(req
);
1533 spin_lock_irqsave(&dwc
->lock
, flags
);
1535 list_for_each_entry(r
, &dep
->pending_list
, list
) {
1541 list_for_each_entry(r
, &dep
->started_list
, list
) {
1546 /* wait until it is processed */
1547 dwc3_stop_active_transfer(dep
, true);
1552 dwc3_gadget_move_cancelled_request(req
);
1553 if (dep
->flags
& DWC3_EP_TRANSFER_STARTED
)
1558 dev_err(dwc
->dev
, "request %pK was not queued to %s\n",
1565 dwc3_gadget_giveback(dep
, req
, -ECONNRESET
);
1568 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1573 int __dwc3_gadget_ep_set_halt(struct dwc3_ep
*dep
, int value
, int protocol
)
1575 struct dwc3_gadget_ep_cmd_params params
;
1576 struct dwc3
*dwc
= dep
->dwc
;
1579 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1580 dev_err(dwc
->dev
, "%s is of Isochronous type\n", dep
->name
);
1584 memset(¶ms
, 0x00, sizeof(params
));
1587 struct dwc3_trb
*trb
;
1589 unsigned transfer_in_flight
;
1592 if (dep
->number
> 1)
1593 trb
= dwc3_ep_prev_trb(dep
, dep
->trb_enqueue
);
1595 trb
= &dwc
->ep0_trb
[dep
->trb_enqueue
];
1597 transfer_in_flight
= trb
->ctrl
& DWC3_TRB_CTRL_HWO
;
1598 started
= !list_empty(&dep
->started_list
);
1600 if (!protocol
&& ((dep
->direction
&& transfer_in_flight
) ||
1601 (!dep
->direction
&& started
))) {
1605 ret
= dwc3_send_gadget_ep_cmd(dep
, DWC3_DEPCMD_SETSTALL
,
1608 dev_err(dwc
->dev
, "failed to set STALL on %s\n",
1611 dep
->flags
|= DWC3_EP_STALL
;
1614 ret
= dwc3_send_clear_stall_ep_cmd(dep
);
1616 dev_err(dwc
->dev
, "failed to clear STALL on %s\n",
1619 dep
->flags
&= ~(DWC3_EP_STALL
| DWC3_EP_WEDGE
);
1625 static int dwc3_gadget_ep_set_halt(struct usb_ep
*ep
, int value
)
1627 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1628 struct dwc3
*dwc
= dep
->dwc
;
1630 unsigned long flags
;
1634 spin_lock_irqsave(&dwc
->lock
, flags
);
1635 ret
= __dwc3_gadget_ep_set_halt(dep
, value
, false);
1636 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1641 static int dwc3_gadget_ep_set_wedge(struct usb_ep
*ep
)
1643 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1644 struct dwc3
*dwc
= dep
->dwc
;
1645 unsigned long flags
;
1648 spin_lock_irqsave(&dwc
->lock
, flags
);
1649 dep
->flags
|= DWC3_EP_WEDGE
;
1651 if (dep
->number
== 0 || dep
->number
== 1)
1652 ret
= __dwc3_gadget_ep0_set_halt(ep
, 1);
1654 ret
= __dwc3_gadget_ep_set_halt(dep
, 1, false);
1655 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1660 /* -------------------------------------------------------------------------- */
1662 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc
= {
1663 .bLength
= USB_DT_ENDPOINT_SIZE
,
1664 .bDescriptorType
= USB_DT_ENDPOINT
,
1665 .bmAttributes
= USB_ENDPOINT_XFER_CONTROL
,
1668 static const struct usb_ep_ops dwc3_gadget_ep0_ops
= {
1669 .enable
= dwc3_gadget_ep0_enable
,
1670 .disable
= dwc3_gadget_ep0_disable
,
1671 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1672 .free_request
= dwc3_gadget_ep_free_request
,
1673 .queue
= dwc3_gadget_ep0_queue
,
1674 .dequeue
= dwc3_gadget_ep_dequeue
,
1675 .set_halt
= dwc3_gadget_ep0_set_halt
,
1676 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1679 static const struct usb_ep_ops dwc3_gadget_ep_ops
= {
1680 .enable
= dwc3_gadget_ep_enable
,
1681 .disable
= dwc3_gadget_ep_disable
,
1682 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1683 .free_request
= dwc3_gadget_ep_free_request
,
1684 .queue
= dwc3_gadget_ep_queue
,
1685 .dequeue
= dwc3_gadget_ep_dequeue
,
1686 .set_halt
= dwc3_gadget_ep_set_halt
,
1687 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1690 /* -------------------------------------------------------------------------- */
1692 static int dwc3_gadget_get_frame(struct usb_gadget
*g
)
1694 struct dwc3
*dwc
= gadget_to_dwc(g
);
1696 return __dwc3_gadget_get_frame(dwc
);
1699 static int __dwc3_gadget_wakeup(struct dwc3
*dwc
)
1710 * According to the Databook Remote wakeup request should
1711 * be issued only when the device is in early suspend state.
1713 * We can check that via USB Link State bits in DSTS register.
1715 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1717 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
1718 if ((speed
== DWC3_DSTS_SUPERSPEED
) ||
1719 (speed
== DWC3_DSTS_SUPERSPEED_PLUS
))
1722 link_state
= DWC3_DSTS_USBLNKST(reg
);
1724 switch (link_state
) {
1725 case DWC3_LINK_STATE_RX_DET
: /* in HS, means Early Suspend */
1726 case DWC3_LINK_STATE_U3
: /* in HS, means SUSPEND */
1732 ret
= dwc3_gadget_set_link_state(dwc
, DWC3_LINK_STATE_RECOV
);
1734 dev_err(dwc
->dev
, "failed to put link in Recovery\n");
1738 /* Recent versions do this automatically */
1739 if (dwc
->revision
< DWC3_REVISION_194A
) {
1740 /* write zeroes to Link Change Request */
1741 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1742 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
1743 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1746 /* poll until Link State changes to ON */
1750 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1752 /* in HS, means ON */
1753 if (DWC3_DSTS_USBLNKST(reg
) == DWC3_LINK_STATE_U0
)
1757 if (DWC3_DSTS_USBLNKST(reg
) != DWC3_LINK_STATE_U0
) {
1758 dev_err(dwc
->dev
, "failed to send remote wakeup\n");
1765 static int dwc3_gadget_wakeup(struct usb_gadget
*g
)
1767 struct dwc3
*dwc
= gadget_to_dwc(g
);
1768 unsigned long flags
;
1771 spin_lock_irqsave(&dwc
->lock
, flags
);
1772 ret
= __dwc3_gadget_wakeup(dwc
);
1773 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1778 static int dwc3_gadget_set_selfpowered(struct usb_gadget
*g
,
1781 struct dwc3
*dwc
= gadget_to_dwc(g
);
1782 unsigned long flags
;
1784 spin_lock_irqsave(&dwc
->lock
, flags
);
1785 g
->is_selfpowered
= !!is_selfpowered
;
1786 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1791 static int dwc3_gadget_run_stop(struct dwc3
*dwc
, int is_on
, int suspend
)
1796 if (pm_runtime_suspended(dwc
->dev
))
1799 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1801 if (dwc
->revision
<= DWC3_REVISION_187A
) {
1802 reg
&= ~DWC3_DCTL_TRGTULST_MASK
;
1803 reg
|= DWC3_DCTL_TRGTULST_RX_DET
;
1806 if (dwc
->revision
>= DWC3_REVISION_194A
)
1807 reg
&= ~DWC3_DCTL_KEEP_CONNECT
;
1808 reg
|= DWC3_DCTL_RUN_STOP
;
1810 if (dwc
->has_hibernation
)
1811 reg
|= DWC3_DCTL_KEEP_CONNECT
;
1813 dwc
->pullups_connected
= true;
1815 reg
&= ~DWC3_DCTL_RUN_STOP
;
1817 if (dwc
->has_hibernation
&& !suspend
)
1818 reg
&= ~DWC3_DCTL_KEEP_CONNECT
;
1820 dwc
->pullups_connected
= false;
1823 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1826 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1827 reg
&= DWC3_DSTS_DEVCTRLHLT
;
1828 } while (--timeout
&& !(!is_on
^ !reg
));
1836 static int dwc3_gadget_pullup(struct usb_gadget
*g
, int is_on
)
1838 struct dwc3
*dwc
= gadget_to_dwc(g
);
1839 unsigned long flags
;
1845 * Per databook, when we want to stop the gadget, if a control transfer
1846 * is still in process, complete it and get the core into setup phase.
1848 if (!is_on
&& dwc
->ep0state
!= EP0_SETUP_PHASE
) {
1849 reinit_completion(&dwc
->ep0_in_setup
);
1851 ret
= wait_for_completion_timeout(&dwc
->ep0_in_setup
,
1852 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT
));
1854 dev_err(dwc
->dev
, "timed out waiting for SETUP phase\n");
1859 spin_lock_irqsave(&dwc
->lock
, flags
);
1860 ret
= dwc3_gadget_run_stop(dwc
, is_on
, false);
1861 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1866 static void dwc3_gadget_enable_irq(struct dwc3
*dwc
)
1870 /* Enable all but Start and End of Frame IRQs */
1871 reg
= (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN
|
1872 DWC3_DEVTEN_EVNTOVERFLOWEN
|
1873 DWC3_DEVTEN_CMDCMPLTEN
|
1874 DWC3_DEVTEN_ERRTICERREN
|
1875 DWC3_DEVTEN_WKUPEVTEN
|
1876 DWC3_DEVTEN_CONNECTDONEEN
|
1877 DWC3_DEVTEN_USBRSTEN
|
1878 DWC3_DEVTEN_DISCONNEVTEN
);
1880 if (dwc
->revision
< DWC3_REVISION_250A
)
1881 reg
|= DWC3_DEVTEN_ULSTCNGEN
;
1883 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, reg
);
1886 static void dwc3_gadget_disable_irq(struct dwc3
*dwc
)
1888 /* mask all interrupts */
1889 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, 0x00);
1892 static irqreturn_t
dwc3_interrupt(int irq
, void *_dwc
);
1893 static irqreturn_t
dwc3_thread_interrupt(int irq
, void *_dwc
);
1896 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
1897 * @dwc: pointer to our context structure
1899 * The following looks like complex but it's actually very simple. In order to
1900 * calculate the number of packets we can burst at once on OUT transfers, we're
1901 * gonna use RxFIFO size.
1903 * To calculate RxFIFO size we need two numbers:
1904 * MDWIDTH = size, in bits, of the internal memory bus
1905 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1907 * Given these two numbers, the formula is simple:
1909 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1911 * 24 bytes is for 3x SETUP packets
1912 * 16 bytes is a clock domain crossing tolerance
1914 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1916 static void dwc3_gadget_setup_nump(struct dwc3
*dwc
)
1923 ram2_depth
= DWC3_GHWPARAMS7_RAM2_DEPTH(dwc
->hwparams
.hwparams7
);
1924 mdwidth
= DWC3_GHWPARAMS0_MDWIDTH(dwc
->hwparams
.hwparams0
);
1926 nump
= ((ram2_depth
* mdwidth
/ 8) - 24 - 16) / 1024;
1927 nump
= min_t(u32
, nump
, 16);
1930 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
1931 reg
&= ~DWC3_DCFG_NUMP_MASK
;
1932 reg
|= nump
<< DWC3_DCFG_NUMP_SHIFT
;
1933 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
1936 static int __dwc3_gadget_start(struct dwc3
*dwc
)
1938 struct dwc3_ep
*dep
;
1943 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1944 * the core supports IMOD, disable it.
1946 if (dwc
->imod_interval
) {
1947 dwc3_writel(dwc
->regs
, DWC3_DEV_IMOD(0), dwc
->imod_interval
);
1948 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB
);
1949 } else if (dwc3_has_imod(dwc
)) {
1950 dwc3_writel(dwc
->regs
, DWC3_DEV_IMOD(0), 0);
1954 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1955 * field instead of letting dwc3 itself calculate that automatically.
1957 * This way, we maximize the chances that we'll be able to get several
1958 * bursts of data without going through any sort of endpoint throttling.
1960 reg
= dwc3_readl(dwc
->regs
, DWC3_GRXTHRCFG
);
1961 if (dwc3_is_usb31(dwc
))
1962 reg
&= ~DWC31_GRXTHRCFG_PKTCNTSEL
;
1964 reg
&= ~DWC3_GRXTHRCFG_PKTCNTSEL
;
1966 dwc3_writel(dwc
->regs
, DWC3_GRXTHRCFG
, reg
);
1968 dwc3_gadget_setup_nump(dwc
);
1970 /* Start with SuperSpeed Default */
1971 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
1974 ret
= __dwc3_gadget_ep_enable(dep
, DWC3_DEPCFG_ACTION_INIT
);
1976 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1981 ret
= __dwc3_gadget_ep_enable(dep
, DWC3_DEPCFG_ACTION_INIT
);
1983 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1987 /* begin to receive SETUP packets */
1988 dwc
->ep0state
= EP0_SETUP_PHASE
;
1989 dwc
->link_state
= DWC3_LINK_STATE_SS_DIS
;
1990 dwc3_ep0_out_start(dwc
);
1992 dwc3_gadget_enable_irq(dwc
);
1997 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
2003 static int dwc3_gadget_start(struct usb_gadget
*g
,
2004 struct usb_gadget_driver
*driver
)
2006 struct dwc3
*dwc
= gadget_to_dwc(g
);
2007 unsigned long flags
;
2011 irq
= dwc
->irq_gadget
;
2012 ret
= request_threaded_irq(irq
, dwc3_interrupt
, dwc3_thread_interrupt
,
2013 IRQF_SHARED
, "dwc3", dwc
->ev_buf
);
2015 dev_err(dwc
->dev
, "failed to request irq #%d --> %d\n",
2020 spin_lock_irqsave(&dwc
->lock
, flags
);
2021 if (dwc
->gadget_driver
) {
2022 dev_err(dwc
->dev
, "%s is already bound to %s\n",
2024 dwc
->gadget_driver
->driver
.name
);
2029 dwc
->gadget_driver
= driver
;
2031 if (pm_runtime_active(dwc
->dev
))
2032 __dwc3_gadget_start(dwc
);
2034 spin_unlock_irqrestore(&dwc
->lock
, flags
);
2039 spin_unlock_irqrestore(&dwc
->lock
, flags
);
2046 static void __dwc3_gadget_stop(struct dwc3
*dwc
)
2048 dwc3_gadget_disable_irq(dwc
);
2049 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
2050 __dwc3_gadget_ep_disable(dwc
->eps
[1]);
2053 static int dwc3_gadget_stop(struct usb_gadget
*g
)
2055 struct dwc3
*dwc
= gadget_to_dwc(g
);
2056 unsigned long flags
;
2058 spin_lock_irqsave(&dwc
->lock
, flags
);
2060 if (pm_runtime_suspended(dwc
->dev
))
2063 __dwc3_gadget_stop(dwc
);
2066 dwc
->gadget_driver
= NULL
;
2067 spin_unlock_irqrestore(&dwc
->lock
, flags
);
2069 free_irq(dwc
->irq_gadget
, dwc
->ev_buf
);
2074 static void dwc3_gadget_set_speed(struct usb_gadget
*g
,
2075 enum usb_device_speed speed
)
2077 struct dwc3
*dwc
= gadget_to_dwc(g
);
2078 unsigned long flags
;
2081 spin_lock_irqsave(&dwc
->lock
, flags
);
2082 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2083 reg
&= ~(DWC3_DCFG_SPEED_MASK
);
2086 * WORKAROUND: DWC3 revision < 2.20a have an issue
2087 * which would cause metastability state on Run/Stop
2088 * bit if we try to force the IP to USB2-only mode.
2090 * Because of that, we cannot configure the IP to any
2091 * speed other than the SuperSpeed
2095 * STAR#9000525659: Clock Domain Crossing on DCTL in
2098 if (dwc
->revision
< DWC3_REVISION_220A
&&
2099 !dwc
->dis_metastability_quirk
) {
2100 reg
|= DWC3_DCFG_SUPERSPEED
;
2104 reg
|= DWC3_DCFG_LOWSPEED
;
2106 case USB_SPEED_FULL
:
2107 reg
|= DWC3_DCFG_FULLSPEED
;
2109 case USB_SPEED_HIGH
:
2110 reg
|= DWC3_DCFG_HIGHSPEED
;
2112 case USB_SPEED_SUPER
:
2113 reg
|= DWC3_DCFG_SUPERSPEED
;
2115 case USB_SPEED_SUPER_PLUS
:
2116 if (dwc3_is_usb31(dwc
))
2117 reg
|= DWC3_DCFG_SUPERSPEED_PLUS
;
2119 reg
|= DWC3_DCFG_SUPERSPEED
;
2122 dev_err(dwc
->dev
, "invalid speed (%d)\n", speed
);
2124 if (dwc
->revision
& DWC3_REVISION_IS_DWC31
)
2125 reg
|= DWC3_DCFG_SUPERSPEED_PLUS
;
2127 reg
|= DWC3_DCFG_SUPERSPEED
;
2130 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2132 spin_unlock_irqrestore(&dwc
->lock
, flags
);
2135 static const struct usb_gadget_ops dwc3_gadget_ops
= {
2136 .get_frame
= dwc3_gadget_get_frame
,
2137 .wakeup
= dwc3_gadget_wakeup
,
2138 .set_selfpowered
= dwc3_gadget_set_selfpowered
,
2139 .pullup
= dwc3_gadget_pullup
,
2140 .udc_start
= dwc3_gadget_start
,
2141 .udc_stop
= dwc3_gadget_stop
,
2142 .udc_set_speed
= dwc3_gadget_set_speed
,
2145 /* -------------------------------------------------------------------------- */
2147 static int dwc3_gadget_init_control_endpoint(struct dwc3_ep
*dep
)
2149 struct dwc3
*dwc
= dep
->dwc
;
2151 usb_ep_set_maxpacket_limit(&dep
->endpoint
, 512);
2152 dep
->endpoint
.maxburst
= 1;
2153 dep
->endpoint
.ops
= &dwc3_gadget_ep0_ops
;
2154 if (!dep
->direction
)
2155 dwc
->gadget
.ep0
= &dep
->endpoint
;
2157 dep
->endpoint
.caps
.type_control
= true;
2162 static int dwc3_gadget_init_in_endpoint(struct dwc3_ep
*dep
)
2164 struct dwc3
*dwc
= dep
->dwc
;
2169 mdwidth
= DWC3_MDWIDTH(dwc
->hwparams
.hwparams0
);
2170 /* MDWIDTH is represented in bits, we need it in bytes */
2173 size
= dwc3_readl(dwc
->regs
, DWC3_GTXFIFOSIZ(dep
->number
>> 1));
2174 if (dwc3_is_usb31(dwc
))
2175 size
= DWC31_GTXFIFOSIZ_TXFDEF(size
);
2177 size
= DWC3_GTXFIFOSIZ_TXFDEF(size
);
2179 /* FIFO Depth is in MDWDITH bytes. Multiply */
2182 kbytes
= size
/ 1024;
2187 * FIFO sizes account an extra MDWIDTH * (kbytes + 1) bytes for
2188 * internal overhead. We don't really know how these are used,
2189 * but documentation say it exists.
2191 size
-= mdwidth
* (kbytes
+ 1);
2194 usb_ep_set_maxpacket_limit(&dep
->endpoint
, size
);
2196 dep
->endpoint
.max_streams
= 15;
2197 dep
->endpoint
.ops
= &dwc3_gadget_ep_ops
;
2198 list_add_tail(&dep
->endpoint
.ep_list
,
2199 &dwc
->gadget
.ep_list
);
2200 dep
->endpoint
.caps
.type_iso
= true;
2201 dep
->endpoint
.caps
.type_bulk
= true;
2202 dep
->endpoint
.caps
.type_int
= true;
2204 return dwc3_alloc_trb_pool(dep
);
2207 static int dwc3_gadget_init_out_endpoint(struct dwc3_ep
*dep
)
2209 struct dwc3
*dwc
= dep
->dwc
;
2211 usb_ep_set_maxpacket_limit(&dep
->endpoint
, 1024);
2212 dep
->endpoint
.max_streams
= 15;
2213 dep
->endpoint
.ops
= &dwc3_gadget_ep_ops
;
2214 list_add_tail(&dep
->endpoint
.ep_list
,
2215 &dwc
->gadget
.ep_list
);
2216 dep
->endpoint
.caps
.type_iso
= true;
2217 dep
->endpoint
.caps
.type_bulk
= true;
2218 dep
->endpoint
.caps
.type_int
= true;
2220 return dwc3_alloc_trb_pool(dep
);
2223 static int dwc3_gadget_init_endpoint(struct dwc3
*dwc
, u8 epnum
)
2225 struct dwc3_ep
*dep
;
2226 bool direction
= epnum
& 1;
2228 u8 num
= epnum
>> 1;
2230 dep
= kzalloc(sizeof(*dep
), GFP_KERNEL
);
2235 dep
->number
= epnum
;
2236 dep
->direction
= direction
;
2237 dep
->regs
= dwc
->regs
+ DWC3_DEP_BASE(epnum
);
2238 dwc
->eps
[epnum
] = dep
;
2240 dep
->start_cmd_status
= 0;
2242 snprintf(dep
->name
, sizeof(dep
->name
), "ep%u%s", num
,
2243 direction
? "in" : "out");
2245 dep
->endpoint
.name
= dep
->name
;
2247 if (!(dep
->number
> 1)) {
2248 dep
->endpoint
.desc
= &dwc3_gadget_ep0_desc
;
2249 dep
->endpoint
.comp_desc
= NULL
;
2252 spin_lock_init(&dep
->lock
);
2255 ret
= dwc3_gadget_init_control_endpoint(dep
);
2257 ret
= dwc3_gadget_init_in_endpoint(dep
);
2259 ret
= dwc3_gadget_init_out_endpoint(dep
);
2264 dep
->endpoint
.caps
.dir_in
= direction
;
2265 dep
->endpoint
.caps
.dir_out
= !direction
;
2267 INIT_LIST_HEAD(&dep
->pending_list
);
2268 INIT_LIST_HEAD(&dep
->started_list
);
2269 INIT_LIST_HEAD(&dep
->cancelled_list
);
2274 static int dwc3_gadget_init_endpoints(struct dwc3
*dwc
, u8 total
)
2278 INIT_LIST_HEAD(&dwc
->gadget
.ep_list
);
2280 for (epnum
= 0; epnum
< total
; epnum
++) {
2283 ret
= dwc3_gadget_init_endpoint(dwc
, epnum
);
2291 static void dwc3_gadget_free_endpoints(struct dwc3
*dwc
)
2293 struct dwc3_ep
*dep
;
2296 for (epnum
= 0; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
2297 dep
= dwc
->eps
[epnum
];
2301 * Physical endpoints 0 and 1 are special; they form the
2302 * bi-directional USB endpoint 0.
2304 * For those two physical endpoints, we don't allocate a TRB
2305 * pool nor do we add them the endpoints list. Due to that, we
2306 * shouldn't do these two operations otherwise we would end up
2307 * with all sorts of bugs when removing dwc3.ko.
2309 if (epnum
!= 0 && epnum
!= 1) {
2310 dwc3_free_trb_pool(dep
);
2311 list_del(&dep
->endpoint
.ep_list
);
2318 /* -------------------------------------------------------------------------- */
2320 static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep
*dep
,
2321 struct dwc3_request
*req
, struct dwc3_trb
*trb
,
2322 const struct dwc3_event_depevt
*event
, int status
, int chain
)
2326 dwc3_ep_inc_deq(dep
);
2328 trace_dwc3_complete_trb(dep
, trb
);
2332 * If we're in the middle of series of chained TRBs and we
2333 * receive a short transfer along the way, DWC3 will skip
2334 * through all TRBs including the last TRB in the chain (the
2335 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2336 * bit and SW has to do it manually.
2338 * We're going to do that here to avoid problems of HW trying
2339 * to use bogus TRBs for transfers.
2341 if (chain
&& (trb
->ctrl
& DWC3_TRB_CTRL_HWO
))
2342 trb
->ctrl
&= ~DWC3_TRB_CTRL_HWO
;
2345 * For isochronous transfers, the first TRB in a service interval must
2346 * have the Isoc-First type. Track and report its interval frame number.
2348 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) &&
2349 (trb
->ctrl
& DWC3_TRBCTL_ISOCHRONOUS_FIRST
)) {
2350 unsigned int frame_number
;
2352 frame_number
= DWC3_TRB_CTRL_GET_SID_SOFN(trb
->ctrl
);
2353 frame_number
&= ~(dep
->interval
- 1);
2354 req
->request
.frame_number
= frame_number
;
2358 * If we're dealing with unaligned size OUT transfer, we will be left
2359 * with one TRB pending in the ring. We need to manually clear HWO bit
2363 if (req
->needs_extra_trb
&& !(trb
->ctrl
& DWC3_TRB_CTRL_CHN
)) {
2364 trb
->ctrl
&= ~DWC3_TRB_CTRL_HWO
;
2368 count
= trb
->size
& DWC3_TRB_SIZE_MASK
;
2369 req
->remaining
+= count
;
2371 if ((trb
->ctrl
& DWC3_TRB_CTRL_HWO
) && status
!= -ESHUTDOWN
)
2374 if (event
->status
& DEPEVT_STATUS_SHORT
&& !chain
)
2377 if (event
->status
& DEPEVT_STATUS_IOC
)
2383 static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep
*dep
,
2384 struct dwc3_request
*req
, const struct dwc3_event_depevt
*event
,
2387 struct dwc3_trb
*trb
= &dep
->trb_pool
[dep
->trb_dequeue
];
2388 struct scatterlist
*sg
= req
->sg
;
2389 struct scatterlist
*s
;
2390 unsigned int pending
= req
->num_pending_sgs
;
2394 for_each_sg(sg
, s
, pending
, i
) {
2395 trb
= &dep
->trb_pool
[dep
->trb_dequeue
];
2397 if (trb
->ctrl
& DWC3_TRB_CTRL_HWO
)
2400 req
->sg
= sg_next(s
);
2401 req
->num_pending_sgs
--;
2403 ret
= dwc3_gadget_ep_reclaim_completed_trb(dep
, req
,
2404 trb
, event
, status
, true);
2412 static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep
*dep
,
2413 struct dwc3_request
*req
, const struct dwc3_event_depevt
*event
,
2416 struct dwc3_trb
*trb
= &dep
->trb_pool
[dep
->trb_dequeue
];
2418 return dwc3_gadget_ep_reclaim_completed_trb(dep
, req
, trb
,
2419 event
, status
, false);
2422 static bool dwc3_gadget_ep_request_completed(struct dwc3_request
*req
)
2424 return req
->request
.actual
== req
->request
.length
;
2427 static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep
*dep
,
2428 const struct dwc3_event_depevt
*event
,
2429 struct dwc3_request
*req
, int status
)
2433 if (req
->num_pending_sgs
)
2434 ret
= dwc3_gadget_ep_reclaim_trb_sg(dep
, req
, event
,
2437 ret
= dwc3_gadget_ep_reclaim_trb_linear(dep
, req
, event
,
2440 if (req
->needs_extra_trb
) {
2441 ret
= dwc3_gadget_ep_reclaim_trb_linear(dep
, req
, event
,
2443 req
->needs_extra_trb
= false;
2446 req
->request
.actual
= req
->request
.length
- req
->remaining
;
2448 if (!dwc3_gadget_ep_request_completed(req
) &&
2449 req
->num_pending_sgs
) {
2450 __dwc3_gadget_kick_transfer(dep
);
2454 dwc3_gadget_giveback(dep
, req
, status
);
2460 static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep
*dep
,
2461 const struct dwc3_event_depevt
*event
, int status
)
2463 struct dwc3_request
*req
;
2464 struct dwc3_request
*tmp
;
2466 list_for_each_entry_safe(req
, tmp
, &dep
->started_list
, list
) {
2469 ret
= dwc3_gadget_ep_cleanup_completed_request(dep
, event
,
2476 static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep
*dep
,
2477 const struct dwc3_event_depevt
*event
)
2479 dep
->frame_number
= event
->parameters
;
2482 static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep
*dep
,
2483 const struct dwc3_event_depevt
*event
)
2485 struct dwc3
*dwc
= dep
->dwc
;
2486 unsigned status
= 0;
2489 dwc3_gadget_endpoint_frame_from_event(dep
, event
);
2491 if (event
->status
& DEPEVT_STATUS_BUSERR
)
2492 status
= -ECONNRESET
;
2494 if (event
->status
& DEPEVT_STATUS_MISSED_ISOC
) {
2497 if (list_empty(&dep
->started_list
))
2501 dwc3_gadget_ep_cleanup_completed_requests(dep
, event
, status
);
2504 dwc3_stop_active_transfer(dep
, true);
2505 dep
->flags
= DWC3_EP_ENABLED
;
2509 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2510 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2512 if (dwc
->revision
< DWC3_REVISION_183A
) {
2516 for (i
= 0; i
< DWC3_ENDPOINTS_NUM
; i
++) {
2519 if (!(dep
->flags
& DWC3_EP_ENABLED
))
2522 if (!list_empty(&dep
->started_list
))
2526 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2528 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2534 static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep
*dep
,
2535 const struct dwc3_event_depevt
*event
)
2537 dwc3_gadget_endpoint_frame_from_event(dep
, event
);
2538 (void) __dwc3_gadget_start_isoc(dep
);
2541 static void dwc3_endpoint_interrupt(struct dwc3
*dwc
,
2542 const struct dwc3_event_depevt
*event
)
2544 struct dwc3_ep
*dep
;
2545 u8 epnum
= event
->endpoint_number
;
2548 dep
= dwc
->eps
[epnum
];
2550 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
2551 if (!(dep
->flags
& DWC3_EP_END_TRANSFER_PENDING
))
2554 /* Handle only EPCMDCMPLT when EP disabled */
2555 if (event
->endpoint_event
!= DWC3_DEPEVT_EPCMDCMPLT
)
2559 if (epnum
== 0 || epnum
== 1) {
2560 dwc3_ep0_interrupt(dwc
, event
);
2564 switch (event
->endpoint_event
) {
2565 case DWC3_DEPEVT_XFERINPROGRESS
:
2566 dwc3_gadget_endpoint_transfer_in_progress(dep
, event
);
2568 case DWC3_DEPEVT_XFERNOTREADY
:
2569 dwc3_gadget_endpoint_transfer_not_ready(dep
, event
);
2571 case DWC3_DEPEVT_EPCMDCMPLT
:
2572 cmd
= DEPEVT_PARAMETER_CMD(event
->parameters
);
2574 if (cmd
== DWC3_DEPCMD_ENDTRANSFER
) {
2575 dep
->flags
&= ~(DWC3_EP_END_TRANSFER_PENDING
|
2576 DWC3_EP_TRANSFER_STARTED
);
2577 dwc3_gadget_ep_cleanup_cancelled_requests(dep
);
2580 case DWC3_DEPEVT_STREAMEVT
:
2581 case DWC3_DEPEVT_XFERCOMPLETE
:
2582 case DWC3_DEPEVT_RXTXFIFOEVT
:
2587 static void dwc3_disconnect_gadget(struct dwc3
*dwc
)
2589 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->disconnect
) {
2590 spin_unlock(&dwc
->lock
);
2591 dwc
->gadget_driver
->disconnect(&dwc
->gadget
);
2592 spin_lock(&dwc
->lock
);
2596 static void dwc3_suspend_gadget(struct dwc3
*dwc
)
2598 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->suspend
) {
2599 spin_unlock(&dwc
->lock
);
2600 dwc
->gadget_driver
->suspend(&dwc
->gadget
);
2601 spin_lock(&dwc
->lock
);
2605 static void dwc3_resume_gadget(struct dwc3
*dwc
)
2607 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->resume
) {
2608 spin_unlock(&dwc
->lock
);
2609 dwc
->gadget_driver
->resume(&dwc
->gadget
);
2610 spin_lock(&dwc
->lock
);
2614 static void dwc3_reset_gadget(struct dwc3
*dwc
)
2616 if (!dwc
->gadget_driver
)
2619 if (dwc
->gadget
.speed
!= USB_SPEED_UNKNOWN
) {
2620 spin_unlock(&dwc
->lock
);
2621 usb_gadget_udc_reset(&dwc
->gadget
, dwc
->gadget_driver
);
2622 spin_lock(&dwc
->lock
);
2626 static void dwc3_stop_active_transfer(struct dwc3_ep
*dep
, bool force
)
2628 struct dwc3
*dwc
= dep
->dwc
;
2629 struct dwc3_gadget_ep_cmd_params params
;
2633 if ((dep
->flags
& DWC3_EP_END_TRANSFER_PENDING
)
2634 || !(dep
->flags
& DWC3_EP_TRANSFER_STARTED
))
2638 * NOTICE: We are violating what the Databook says about the
2639 * EndTransfer command. Ideally we would _always_ wait for the
2640 * EndTransfer Command Completion IRQ, but that's causing too
2641 * much trouble synchronizing between us and gadget driver.
2643 * We have discussed this with the IP Provider and it was
2644 * suggested to giveback all requests here, but give HW some
2645 * extra time to synchronize with the interconnect. We're using
2646 * an arbitrary 100us delay for that.
2648 * Note also that a similar handling was tested by Synopsys
2649 * (thanks a lot Paul) and nothing bad has come out of it.
2650 * In short, what we're doing is:
2652 * - Issue EndTransfer WITH CMDIOC bit set
2655 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2656 * supports a mode to work around the above limitation. The
2657 * software can poll the CMDACT bit in the DEPCMD register
2658 * after issuing a EndTransfer command. This mode is enabled
2659 * by writing GUCTL2[14]. This polling is already done in the
2660 * dwc3_send_gadget_ep_cmd() function so if the mode is
2661 * enabled, the EndTransfer command will have completed upon
2662 * returning from this function and we don't need to delay for
2665 * This mode is NOT available on the DWC_usb31 IP.
2668 cmd
= DWC3_DEPCMD_ENDTRANSFER
;
2669 cmd
|= force
? DWC3_DEPCMD_HIPRI_FORCERM
: 0;
2670 cmd
|= DWC3_DEPCMD_CMDIOC
;
2671 cmd
|= DWC3_DEPCMD_PARAM(dep
->resource_index
);
2672 memset(¶ms
, 0, sizeof(params
));
2673 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
2675 dep
->resource_index
= 0;
2677 if (dwc3_is_usb31(dwc
) || dwc
->revision
< DWC3_REVISION_310A
) {
2678 dep
->flags
|= DWC3_EP_END_TRANSFER_PENDING
;
2683 static void dwc3_clear_stall_all_ep(struct dwc3
*dwc
)
2687 for (epnum
= 1; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
2688 struct dwc3_ep
*dep
;
2691 dep
= dwc
->eps
[epnum
];
2695 if (!(dep
->flags
& DWC3_EP_STALL
))
2698 dep
->flags
&= ~DWC3_EP_STALL
;
2700 ret
= dwc3_send_clear_stall_ep_cmd(dep
);
2705 static void dwc3_gadget_disconnect_interrupt(struct dwc3
*dwc
)
2709 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2710 reg
&= ~DWC3_DCTL_INITU1ENA
;
2711 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2713 reg
&= ~DWC3_DCTL_INITU2ENA
;
2714 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2716 dwc3_disconnect_gadget(dwc
);
2718 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2719 dwc
->setup_packet_pending
= false;
2720 usb_gadget_set_state(&dwc
->gadget
, USB_STATE_NOTATTACHED
);
2722 dwc
->connected
= false;
2725 static void dwc3_gadget_reset_interrupt(struct dwc3
*dwc
)
2729 dwc
->connected
= true;
2732 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2733 * would cause a missing Disconnect Event if there's a
2734 * pending Setup Packet in the FIFO.
2736 * There's no suggested workaround on the official Bug
2737 * report, which states that "unless the driver/application
2738 * is doing any special handling of a disconnect event,
2739 * there is no functional issue".
2741 * Unfortunately, it turns out that we _do_ some special
2742 * handling of a disconnect event, namely complete all
2743 * pending transfers, notify gadget driver of the
2744 * disconnection, and so on.
2746 * Our suggested workaround is to follow the Disconnect
2747 * Event steps here, instead, based on a setup_packet_pending
2748 * flag. Such flag gets set whenever we have a SETUP_PENDING
2749 * status for EP0 TRBs and gets cleared on XferComplete for the
2754 * STAR#9000466709: RTL: Device : Disconnect event not
2755 * generated if setup packet pending in FIFO
2757 if (dwc
->revision
< DWC3_REVISION_188A
) {
2758 if (dwc
->setup_packet_pending
)
2759 dwc3_gadget_disconnect_interrupt(dwc
);
2762 dwc3_reset_gadget(dwc
);
2764 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2765 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
2766 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2767 dwc
->test_mode
= false;
2768 dwc3_clear_stall_all_ep(dwc
);
2770 /* Reset device address to zero */
2771 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2772 reg
&= ~(DWC3_DCFG_DEVADDR_MASK
);
2773 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2776 static void dwc3_gadget_conndone_interrupt(struct dwc3
*dwc
)
2778 struct dwc3_ep
*dep
;
2783 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
2784 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
2788 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2789 * each time on Connect Done.
2791 * Currently we always use the reset value. If any platform
2792 * wants to set this to a different value, we need to add a
2793 * setting and update GCTL.RAMCLKSEL here.
2797 case DWC3_DSTS_SUPERSPEED_PLUS
:
2798 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
2799 dwc
->gadget
.ep0
->maxpacket
= 512;
2800 dwc
->gadget
.speed
= USB_SPEED_SUPER_PLUS
;
2802 case DWC3_DSTS_SUPERSPEED
:
2804 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2805 * would cause a missing USB3 Reset event.
2807 * In such situations, we should force a USB3 Reset
2808 * event by calling our dwc3_gadget_reset_interrupt()
2813 * STAR#9000483510: RTL: SS : USB3 reset event may
2814 * not be generated always when the link enters poll
2816 if (dwc
->revision
< DWC3_REVISION_190A
)
2817 dwc3_gadget_reset_interrupt(dwc
);
2819 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
2820 dwc
->gadget
.ep0
->maxpacket
= 512;
2821 dwc
->gadget
.speed
= USB_SPEED_SUPER
;
2823 case DWC3_DSTS_HIGHSPEED
:
2824 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2825 dwc
->gadget
.ep0
->maxpacket
= 64;
2826 dwc
->gadget
.speed
= USB_SPEED_HIGH
;
2828 case DWC3_DSTS_FULLSPEED
:
2829 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2830 dwc
->gadget
.ep0
->maxpacket
= 64;
2831 dwc
->gadget
.speed
= USB_SPEED_FULL
;
2833 case DWC3_DSTS_LOWSPEED
:
2834 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(8);
2835 dwc
->gadget
.ep0
->maxpacket
= 8;
2836 dwc
->gadget
.speed
= USB_SPEED_LOW
;
2840 dwc
->eps
[1]->endpoint
.maxpacket
= dwc
->gadget
.ep0
->maxpacket
;
2842 /* Enable USB2 LPM Capability */
2844 if ((dwc
->revision
> DWC3_REVISION_194A
) &&
2845 (speed
!= DWC3_DSTS_SUPERSPEED
) &&
2846 (speed
!= DWC3_DSTS_SUPERSPEED_PLUS
)) {
2847 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2848 reg
|= DWC3_DCFG_LPM_CAP
;
2849 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2851 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2852 reg
&= ~(DWC3_DCTL_HIRD_THRES_MASK
| DWC3_DCTL_L1_HIBER_EN
);
2854 reg
|= DWC3_DCTL_HIRD_THRES(dwc
->hird_threshold
);
2857 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2858 * DCFG.LPMCap is set, core responses with an ACK and the
2859 * BESL value in the LPM token is less than or equal to LPM
2862 WARN_ONCE(dwc
->revision
< DWC3_REVISION_240A
2863 && dwc
->has_lpm_erratum
,
2864 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
2866 if (dwc
->has_lpm_erratum
&& dwc
->revision
>= DWC3_REVISION_240A
)
2867 reg
|= DWC3_DCTL_LPM_ERRATA(dwc
->lpm_nyet_threshold
);
2869 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2871 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2872 reg
&= ~DWC3_DCTL_HIRD_THRES_MASK
;
2873 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2877 ret
= __dwc3_gadget_ep_enable(dep
, DWC3_DEPCFG_ACTION_MODIFY
);
2879 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2884 ret
= __dwc3_gadget_ep_enable(dep
, DWC3_DEPCFG_ACTION_MODIFY
);
2886 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2891 * Configure PHY via GUSB3PIPECTLn if required.
2893 * Update GTXFIFOSIZn
2895 * In both cases reset values should be sufficient.
2899 static void dwc3_gadget_wakeup_interrupt(struct dwc3
*dwc
)
2902 * TODO take core out of low power mode when that's
2906 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->resume
) {
2907 spin_unlock(&dwc
->lock
);
2908 dwc
->gadget_driver
->resume(&dwc
->gadget
);
2909 spin_lock(&dwc
->lock
);
2913 static void dwc3_gadget_linksts_change_interrupt(struct dwc3
*dwc
,
2914 unsigned int evtinfo
)
2916 enum dwc3_link_state next
= evtinfo
& DWC3_LINK_STATE_MASK
;
2917 unsigned int pwropt
;
2920 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2921 * Hibernation mode enabled which would show up when device detects
2922 * host-initiated U3 exit.
2924 * In that case, device will generate a Link State Change Interrupt
2925 * from U3 to RESUME which is only necessary if Hibernation is
2928 * There are no functional changes due to such spurious event and we
2929 * just need to ignore it.
2933 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2936 pwropt
= DWC3_GHWPARAMS1_EN_PWROPT(dwc
->hwparams
.hwparams1
);
2937 if ((dwc
->revision
< DWC3_REVISION_250A
) &&
2938 (pwropt
!= DWC3_GHWPARAMS1_EN_PWROPT_HIB
)) {
2939 if ((dwc
->link_state
== DWC3_LINK_STATE_U3
) &&
2940 (next
== DWC3_LINK_STATE_RESUME
)) {
2946 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2947 * on the link partner, the USB session might do multiple entry/exit
2948 * of low power states before a transfer takes place.
2950 * Due to this problem, we might experience lower throughput. The
2951 * suggested workaround is to disable DCTL[12:9] bits if we're
2952 * transitioning from U1/U2 to U0 and enable those bits again
2953 * after a transfer completes and there are no pending transfers
2954 * on any of the enabled endpoints.
2956 * This is the first half of that workaround.
2960 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2961 * core send LGO_Ux entering U0
2963 if (dwc
->revision
< DWC3_REVISION_183A
) {
2964 if (next
== DWC3_LINK_STATE_U0
) {
2968 switch (dwc
->link_state
) {
2969 case DWC3_LINK_STATE_U1
:
2970 case DWC3_LINK_STATE_U2
:
2971 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2972 u1u2
= reg
& (DWC3_DCTL_INITU2ENA
2973 | DWC3_DCTL_ACCEPTU2ENA
2974 | DWC3_DCTL_INITU1ENA
2975 | DWC3_DCTL_ACCEPTU1ENA
);
2978 dwc
->u1u2
= reg
& u1u2
;
2982 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2992 case DWC3_LINK_STATE_U1
:
2993 if (dwc
->speed
== USB_SPEED_SUPER
)
2994 dwc3_suspend_gadget(dwc
);
2996 case DWC3_LINK_STATE_U2
:
2997 case DWC3_LINK_STATE_U3
:
2998 dwc3_suspend_gadget(dwc
);
3000 case DWC3_LINK_STATE_RESUME
:
3001 dwc3_resume_gadget(dwc
);
3008 dwc
->link_state
= next
;
3011 static void dwc3_gadget_suspend_interrupt(struct dwc3
*dwc
,
3012 unsigned int evtinfo
)
3014 enum dwc3_link_state next
= evtinfo
& DWC3_LINK_STATE_MASK
;
3016 if (dwc
->link_state
!= next
&& next
== DWC3_LINK_STATE_U3
)
3017 dwc3_suspend_gadget(dwc
);
3019 dwc
->link_state
= next
;
3022 static void dwc3_gadget_hibernation_interrupt(struct dwc3
*dwc
,
3023 unsigned int evtinfo
)
3025 unsigned int is_ss
= evtinfo
& BIT(4);
3028 * WORKAROUND: DWC3 revison 2.20a with hibernation support
3029 * have a known issue which can cause USB CV TD.9.23 to fail
3032 * Because of this issue, core could generate bogus hibernation
3033 * events which SW needs to ignore.
3037 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
3038 * Device Fallback from SuperSpeed
3040 if (is_ss
^ (dwc
->speed
== USB_SPEED_SUPER
))
3043 /* enter hibernation here */
3046 static void dwc3_gadget_interrupt(struct dwc3
*dwc
,
3047 const struct dwc3_event_devt
*event
)
3049 switch (event
->type
) {
3050 case DWC3_DEVICE_EVENT_DISCONNECT
:
3051 dwc3_gadget_disconnect_interrupt(dwc
);
3053 case DWC3_DEVICE_EVENT_RESET
:
3054 dwc3_gadget_reset_interrupt(dwc
);
3056 case DWC3_DEVICE_EVENT_CONNECT_DONE
:
3057 dwc3_gadget_conndone_interrupt(dwc
);
3059 case DWC3_DEVICE_EVENT_WAKEUP
:
3060 dwc3_gadget_wakeup_interrupt(dwc
);
3062 case DWC3_DEVICE_EVENT_HIBER_REQ
:
3063 if (dev_WARN_ONCE(dwc
->dev
, !dwc
->has_hibernation
,
3064 "unexpected hibernation event\n"))
3067 dwc3_gadget_hibernation_interrupt(dwc
, event
->event_info
);
3069 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE
:
3070 dwc3_gadget_linksts_change_interrupt(dwc
, event
->event_info
);
3072 case DWC3_DEVICE_EVENT_EOPF
:
3073 /* It changed to be suspend event for version 2.30a and above */
3074 if (dwc
->revision
>= DWC3_REVISION_230A
) {
3076 * Ignore suspend event until the gadget enters into
3077 * USB_STATE_CONFIGURED state.
3079 if (dwc
->gadget
.state
>= USB_STATE_CONFIGURED
)
3080 dwc3_gadget_suspend_interrupt(dwc
,
3084 case DWC3_DEVICE_EVENT_SOF
:
3085 case DWC3_DEVICE_EVENT_ERRATIC_ERROR
:
3086 case DWC3_DEVICE_EVENT_CMD_CMPL
:
3087 case DWC3_DEVICE_EVENT_OVERFLOW
:
3090 dev_WARN(dwc
->dev
, "UNKNOWN IRQ %d\n", event
->type
);
3094 static void dwc3_process_event_entry(struct dwc3
*dwc
,
3095 const union dwc3_event
*event
)
3097 trace_dwc3_event(event
->raw
, dwc
);
3099 if (!event
->type
.is_devspec
)
3100 dwc3_endpoint_interrupt(dwc
, &event
->depevt
);
3101 else if (event
->type
.type
== DWC3_EVENT_TYPE_DEV
)
3102 dwc3_gadget_interrupt(dwc
, &event
->devt
);
3104 dev_err(dwc
->dev
, "UNKNOWN IRQ type %d\n", event
->raw
);
3107 static irqreturn_t
dwc3_process_event_buf(struct dwc3_event_buffer
*evt
)
3109 struct dwc3
*dwc
= evt
->dwc
;
3110 irqreturn_t ret
= IRQ_NONE
;
3116 if (!(evt
->flags
& DWC3_EVENT_PENDING
))
3120 union dwc3_event event
;
3122 event
.raw
= *(u32
*) (evt
->cache
+ evt
->lpos
);
3124 dwc3_process_event_entry(dwc
, &event
);
3127 * FIXME we wrap around correctly to the next entry as
3128 * almost all entries are 4 bytes in size. There is one
3129 * entry which has 12 bytes which is a regular entry
3130 * followed by 8 bytes data. ATM I don't know how
3131 * things are organized if we get next to the a
3132 * boundary so I worry about that once we try to handle
3135 evt
->lpos
= (evt
->lpos
+ 4) % evt
->length
;
3140 evt
->flags
&= ~DWC3_EVENT_PENDING
;
3143 /* Unmask interrupt */
3144 reg
= dwc3_readl(dwc
->regs
, DWC3_GEVNTSIZ(0));
3145 reg
&= ~DWC3_GEVNTSIZ_INTMASK
;
3146 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(0), reg
);
3148 if (dwc
->imod_interval
) {
3149 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB
);
3150 dwc3_writel(dwc
->regs
, DWC3_DEV_IMOD(0), dwc
->imod_interval
);
3156 static irqreturn_t
dwc3_thread_interrupt(int irq
, void *_evt
)
3158 struct dwc3_event_buffer
*evt
= _evt
;
3159 struct dwc3
*dwc
= evt
->dwc
;
3160 unsigned long flags
;
3161 irqreturn_t ret
= IRQ_NONE
;
3163 spin_lock_irqsave(&dwc
->lock
, flags
);
3164 ret
= dwc3_process_event_buf(evt
);
3165 spin_unlock_irqrestore(&dwc
->lock
, flags
);
3170 static irqreturn_t
dwc3_check_event_buf(struct dwc3_event_buffer
*evt
)
3172 struct dwc3
*dwc
= evt
->dwc
;
3177 if (pm_runtime_suspended(dwc
->dev
)) {
3178 pm_runtime_get(dwc
->dev
);
3179 disable_irq_nosync(dwc
->irq_gadget
);
3180 dwc
->pending_events
= true;
3185 * With PCIe legacy interrupt, test shows that top-half irq handler can
3186 * be called again after HW interrupt deassertion. Check if bottom-half
3187 * irq event handler completes before caching new event to prevent
3190 if (evt
->flags
& DWC3_EVENT_PENDING
)
3193 count
= dwc3_readl(dwc
->regs
, DWC3_GEVNTCOUNT(0));
3194 count
&= DWC3_GEVNTCOUNT_MASK
;
3199 evt
->flags
|= DWC3_EVENT_PENDING
;
3201 /* Mask interrupt */
3202 reg
= dwc3_readl(dwc
->regs
, DWC3_GEVNTSIZ(0));
3203 reg
|= DWC3_GEVNTSIZ_INTMASK
;
3204 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(0), reg
);
3206 amount
= min(count
, evt
->length
- evt
->lpos
);
3207 memcpy(evt
->cache
+ evt
->lpos
, evt
->buf
+ evt
->lpos
, amount
);
3210 memcpy(evt
->cache
, evt
->buf
, count
- amount
);
3212 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(0), count
);
3214 return IRQ_WAKE_THREAD
;
3217 static irqreturn_t
dwc3_interrupt(int irq
, void *_evt
)
3219 struct dwc3_event_buffer
*evt
= _evt
;
3221 return dwc3_check_event_buf(evt
);
3224 static int dwc3_gadget_get_irq(struct dwc3
*dwc
)
3226 struct platform_device
*dwc3_pdev
= to_platform_device(dwc
->dev
);
3229 irq
= platform_get_irq_byname(dwc3_pdev
, "peripheral");
3233 if (irq
== -EPROBE_DEFER
)
3236 irq
= platform_get_irq_byname(dwc3_pdev
, "dwc_usb3");
3240 if (irq
== -EPROBE_DEFER
)
3243 irq
= platform_get_irq(dwc3_pdev
, 0);
3247 if (irq
!= -EPROBE_DEFER
)
3248 dev_err(dwc
->dev
, "missing peripheral IRQ\n");
3258 * dwc3_gadget_init - initializes gadget related registers
3259 * @dwc: pointer to our controller context structure
3261 * Returns 0 on success otherwise negative errno.
3263 int dwc3_gadget_init(struct dwc3
*dwc
)
3268 irq
= dwc3_gadget_get_irq(dwc
);
3274 dwc
->irq_gadget
= irq
;
3276 dwc
->ep0_trb
= dma_alloc_coherent(dwc
->sysdev
,
3277 sizeof(*dwc
->ep0_trb
) * 2,
3278 &dwc
->ep0_trb_addr
, GFP_KERNEL
);
3279 if (!dwc
->ep0_trb
) {
3280 dev_err(dwc
->dev
, "failed to allocate ep0 trb\n");
3285 dwc
->setup_buf
= kzalloc(DWC3_EP0_SETUP_SIZE
, GFP_KERNEL
);
3286 if (!dwc
->setup_buf
) {
3291 dwc
->bounce
= dma_alloc_coherent(dwc
->sysdev
, DWC3_BOUNCE_SIZE
,
3292 &dwc
->bounce_addr
, GFP_KERNEL
);
3298 init_completion(&dwc
->ep0_in_setup
);
3300 dwc
->gadget
.ops
= &dwc3_gadget_ops
;
3301 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
3302 dwc
->gadget
.sg_supported
= true;
3303 dwc
->gadget
.name
= "dwc3-gadget";
3304 dwc
->gadget
.is_otg
= dwc
->dr_mode
== USB_DR_MODE_OTG
;
3307 * FIXME We might be setting max_speed to <SUPER, however versions
3308 * <2.20a of dwc3 have an issue with metastability (documented
3309 * elsewhere in this driver) which tells us we can't set max speed to
3310 * anything lower than SUPER.
3312 * Because gadget.max_speed is only used by composite.c and function
3313 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3314 * to happen so we avoid sending SuperSpeed Capability descriptor
3315 * together with our BOS descriptor as that could confuse host into
3316 * thinking we can handle super speed.
3318 * Note that, in fact, we won't even support GetBOS requests when speed
3319 * is less than super speed because we don't have means, yet, to tell
3320 * composite.c that we are USB 2.0 + LPM ECN.
3322 if (dwc
->revision
< DWC3_REVISION_220A
&&
3323 !dwc
->dis_metastability_quirk
)
3324 dev_info(dwc
->dev
, "changing max_speed on rev %08x\n",
3327 dwc
->gadget
.max_speed
= dwc
->maximum_speed
;
3330 * REVISIT: Here we should clear all pending IRQs to be
3331 * sure we're starting from a well known location.
3334 ret
= dwc3_gadget_init_endpoints(dwc
, dwc
->num_eps
);
3338 ret
= usb_add_gadget_udc(dwc
->dev
, &dwc
->gadget
);
3340 dev_err(dwc
->dev
, "failed to register udc\n");
3344 dwc3_gadget_set_speed(&dwc
->gadget
, dwc
->maximum_speed
);
3349 dwc3_gadget_free_endpoints(dwc
);
3352 dma_free_coherent(dwc
->sysdev
, DWC3_BOUNCE_SIZE
, dwc
->bounce
,
3356 kfree(dwc
->setup_buf
);
3359 dma_free_coherent(dwc
->sysdev
, sizeof(*dwc
->ep0_trb
) * 2,
3360 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
3366 /* -------------------------------------------------------------------------- */
3368 void dwc3_gadget_exit(struct dwc3
*dwc
)
3370 usb_del_gadget_udc(&dwc
->gadget
);
3371 dwc3_gadget_free_endpoints(dwc
);
3372 dma_free_coherent(dwc
->sysdev
, DWC3_BOUNCE_SIZE
, dwc
->bounce
,
3374 kfree(dwc
->setup_buf
);
3375 dma_free_coherent(dwc
->sysdev
, sizeof(*dwc
->ep0_trb
) * 2,
3376 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
3379 int dwc3_gadget_suspend(struct dwc3
*dwc
)
3381 if (!dwc
->gadget_driver
)
3384 dwc3_gadget_run_stop(dwc
, false, false);
3385 dwc3_disconnect_gadget(dwc
);
3386 __dwc3_gadget_stop(dwc
);
3388 synchronize_irq(dwc
->irq_gadget
);
3393 int dwc3_gadget_resume(struct dwc3
*dwc
)
3397 if (!dwc
->gadget_driver
)
3400 ret
= __dwc3_gadget_start(dwc
);
3404 ret
= dwc3_gadget_run_stop(dwc
, true, false);
3411 __dwc3_gadget_stop(dwc
);
3417 void dwc3_gadget_process_pending_events(struct dwc3
*dwc
)
3419 if (dwc
->pending_events
) {
3420 dwc3_interrupt(dwc
->irq_gadget
, dwc
->ev_buf
);
3421 dwc
->pending_events
= false;
3422 enable_irq(dwc
->irq_gadget
);