2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #include <linux/kernel.h>
40 #include <linux/delay.h>
41 #include <linux/slab.h>
42 #include <linux/spinlock.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/interrupt.h>
47 #include <linux/list.h>
48 #include <linux/dma-mapping.h>
50 #include <linux/usb/ch9.h>
51 #include <linux/usb/gadget.h>
58 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
59 * @dwc: pointer to our context structure
60 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
62 * Caller should take care of locking. This function will
63 * return 0 on success or -EINVAL if wrong Test Selector
66 int dwc3_gadget_set_test_mode(struct dwc3
*dwc
, int mode
)
70 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
71 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
85 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
91 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
92 * @dwc: pointer to our context structure
93 * @state: the state to put link into
95 * Caller should take care of locking. This function will
96 * return 0 on success or -ETIMEDOUT.
98 int dwc3_gadget_set_link_state(struct dwc3
*dwc
, enum dwc3_link_state state
)
104 * Wait until device controller is ready. Only applies to 1.94a and
107 if (dwc
->revision
>= DWC3_REVISION_194A
) {
109 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
110 if (reg
& DWC3_DSTS_DCNRD
)
120 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
121 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
123 /* set requested state */
124 reg
|= DWC3_DCTL_ULSTCHNGREQ(state
);
125 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
128 * The following code is racy when called from dwc3_gadget_wakeup,
129 * and is not needed, at least on newer versions
131 if (dwc
->revision
>= DWC3_REVISION_194A
)
134 /* wait for a change in DSTS */
137 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
139 if (DWC3_DSTS_USBLNKST(reg
) == state
)
145 dev_vdbg(dwc
->dev
, "link state change request timed out\n");
151 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
152 * @dwc: pointer to our context structure
154 * This function will a best effort FIFO allocation in order
155 * to improve FIFO usage and throughput, while still allowing
156 * us to enable as many endpoints as possible.
158 * Keep in mind that this operation will be highly dependent
159 * on the configured size for RAM1 - which contains TxFifo -,
160 * the amount of endpoints enabled on coreConsultant tool, and
161 * the width of the Master Bus.
163 * In the ideal world, we would always be able to satisfy the
164 * following equation:
166 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
167 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
169 * Unfortunately, due to many variables that's not always the case.
171 int dwc3_gadget_resize_tx_fifos(struct dwc3
*dwc
)
173 int last_fifo_depth
= 0;
179 if (!dwc
->needs_fifo_resize
)
182 ram1_depth
= DWC3_RAM1_DEPTH(dwc
->hwparams
.hwparams7
);
183 mdwidth
= DWC3_MDWIDTH(dwc
->hwparams
.hwparams0
);
185 /* MDWIDTH is represented in bits, we need it in bytes */
189 * FIXME For now we will only allocate 1 wMaxPacketSize space
190 * for each enabled endpoint, later patches will come to
191 * improve this algorithm so that we better use the internal
194 for (num
= 0; num
< DWC3_ENDPOINTS_NUM
; num
++) {
195 struct dwc3_ep
*dep
= dwc
->eps
[num
];
196 int fifo_number
= dep
->number
>> 1;
200 if (!(dep
->number
& 1))
203 if (!(dep
->flags
& DWC3_EP_ENABLED
))
206 if (usb_endpoint_xfer_bulk(dep
->endpoint
.desc
)
207 || usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
211 * REVISIT: the following assumes we will always have enough
212 * space available on the FIFO RAM for all possible use cases.
213 * Make sure that's true somehow and change FIFO allocation
216 * If we have Bulk or Isochronous endpoints, we want
217 * them to be able to be very, very fast. So we're giving
218 * those endpoints a fifo_size which is enough for 3 full
221 tmp
= mult
* (dep
->endpoint
.maxpacket
+ mdwidth
);
224 fifo_size
= DIV_ROUND_UP(tmp
, mdwidth
);
226 fifo_size
|= (last_fifo_depth
<< 16);
228 dev_vdbg(dwc
->dev
, "%s: Fifo Addr %04x Size %d\n",
229 dep
->name
, last_fifo_depth
, fifo_size
& 0xffff);
231 dwc3_writel(dwc
->regs
, DWC3_GTXFIFOSIZ(fifo_number
),
234 last_fifo_depth
+= (fifo_size
& 0xffff);
240 void dwc3_gadget_giveback(struct dwc3_ep
*dep
, struct dwc3_request
*req
,
243 struct dwc3
*dwc
= dep
->dwc
;
246 if (req
->request
.num_mapped_sgs
)
247 dep
->busy_slot
+= req
->request
.num_mapped_sgs
;
252 * Skip LINK TRB. We can't use req->trb and check for
253 * DWC3_TRBCTL_LINK_TRB because it points the TRB we just
254 * completed (not the LINK TRB).
256 if (((dep
->busy_slot
& DWC3_TRB_MASK
) == DWC3_TRB_NUM
- 1) &&
257 usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
260 list_del(&req
->list
);
263 if (req
->request
.status
== -EINPROGRESS
)
264 req
->request
.status
= status
;
266 usb_gadget_unmap_request(&dwc
->gadget
, &req
->request
,
269 dev_dbg(dwc
->dev
, "request %p from %s completed %d/%d ===> %d\n",
270 req
, dep
->name
, req
->request
.actual
,
271 req
->request
.length
, status
);
273 spin_unlock(&dwc
->lock
);
274 req
->request
.complete(&dep
->endpoint
, &req
->request
);
275 spin_lock(&dwc
->lock
);
278 static const char *dwc3_gadget_ep_cmd_string(u8 cmd
)
281 case DWC3_DEPCMD_DEPSTARTCFG
:
282 return "Start New Configuration";
283 case DWC3_DEPCMD_ENDTRANSFER
:
284 return "End Transfer";
285 case DWC3_DEPCMD_UPDATETRANSFER
:
286 return "Update Transfer";
287 case DWC3_DEPCMD_STARTTRANSFER
:
288 return "Start Transfer";
289 case DWC3_DEPCMD_CLEARSTALL
:
290 return "Clear Stall";
291 case DWC3_DEPCMD_SETSTALL
:
293 case DWC3_DEPCMD_GETEPSTATE
:
294 return "Get Endpoint State";
295 case DWC3_DEPCMD_SETTRANSFRESOURCE
:
296 return "Set Endpoint Transfer Resource";
297 case DWC3_DEPCMD_SETEPCONFIG
:
298 return "Set Endpoint Configuration";
300 return "UNKNOWN command";
304 int dwc3_send_gadget_generic_command(struct dwc3
*dwc
, int cmd
, u32 param
)
309 dwc3_writel(dwc
->regs
, DWC3_DGCMDPAR
, param
);
310 dwc3_writel(dwc
->regs
, DWC3_DGCMD
, cmd
| DWC3_DGCMD_CMDACT
);
313 reg
= dwc3_readl(dwc
->regs
, DWC3_DGCMD
);
314 if (!(reg
& DWC3_DGCMD_CMDACT
)) {
315 dev_vdbg(dwc
->dev
, "Command Complete --> %d\n",
316 DWC3_DGCMD_STATUS(reg
));
321 * We can't sleep here, because it's also called from
331 int dwc3_send_gadget_ep_cmd(struct dwc3
*dwc
, unsigned ep
,
332 unsigned cmd
, struct dwc3_gadget_ep_cmd_params
*params
)
334 struct dwc3_ep
*dep
= dwc
->eps
[ep
];
338 dev_vdbg(dwc
->dev
, "%s: cmd '%s' params %08x %08x %08x\n",
340 dwc3_gadget_ep_cmd_string(cmd
), params
->param0
,
341 params
->param1
, params
->param2
);
343 dwc3_writel(dwc
->regs
, DWC3_DEPCMDPAR0(ep
), params
->param0
);
344 dwc3_writel(dwc
->regs
, DWC3_DEPCMDPAR1(ep
), params
->param1
);
345 dwc3_writel(dwc
->regs
, DWC3_DEPCMDPAR2(ep
), params
->param2
);
347 dwc3_writel(dwc
->regs
, DWC3_DEPCMD(ep
), cmd
| DWC3_DEPCMD_CMDACT
);
349 reg
= dwc3_readl(dwc
->regs
, DWC3_DEPCMD(ep
));
350 if (!(reg
& DWC3_DEPCMD_CMDACT
)) {
351 dev_vdbg(dwc
->dev
, "Command Complete --> %d\n",
352 DWC3_DEPCMD_STATUS(reg
));
357 * We can't sleep here, because it is also called from
368 static dma_addr_t
dwc3_trb_dma_offset(struct dwc3_ep
*dep
,
369 struct dwc3_trb
*trb
)
371 u32 offset
= (char *) trb
- (char *) dep
->trb_pool
;
373 return dep
->trb_pool_dma
+ offset
;
376 static int dwc3_alloc_trb_pool(struct dwc3_ep
*dep
)
378 struct dwc3
*dwc
= dep
->dwc
;
383 if (dep
->number
== 0 || dep
->number
== 1)
386 dep
->trb_pool
= dma_alloc_coherent(dwc
->dev
,
387 sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
388 &dep
->trb_pool_dma
, GFP_KERNEL
);
389 if (!dep
->trb_pool
) {
390 dev_err(dep
->dwc
->dev
, "failed to allocate trb pool for %s\n",
398 static void dwc3_free_trb_pool(struct dwc3_ep
*dep
)
400 struct dwc3
*dwc
= dep
->dwc
;
402 dma_free_coherent(dwc
->dev
, sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
403 dep
->trb_pool
, dep
->trb_pool_dma
);
405 dep
->trb_pool
= NULL
;
406 dep
->trb_pool_dma
= 0;
409 static int dwc3_gadget_start_config(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
411 struct dwc3_gadget_ep_cmd_params params
;
414 memset(¶ms
, 0x00, sizeof(params
));
416 if (dep
->number
!= 1) {
417 cmd
= DWC3_DEPCMD_DEPSTARTCFG
;
418 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
419 if (dep
->number
> 1) {
420 if (dwc
->start_config_issued
)
422 dwc
->start_config_issued
= true;
423 cmd
|= DWC3_DEPCMD_PARAM(2);
426 return dwc3_send_gadget_ep_cmd(dwc
, 0, cmd
, ¶ms
);
432 static int dwc3_gadget_set_ep_config(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
433 const struct usb_endpoint_descriptor
*desc
,
434 const struct usb_ss_ep_comp_descriptor
*comp_desc
,
437 struct dwc3_gadget_ep_cmd_params params
;
439 memset(¶ms
, 0x00, sizeof(params
));
441 params
.param0
= DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc
))
442 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc
));
444 /* Burst size is only needed in SuperSpeed mode */
445 if (dwc
->gadget
.speed
== USB_SPEED_SUPER
) {
446 u32 burst
= dep
->endpoint
.maxburst
- 1;
448 params
.param0
|= DWC3_DEPCFG_BURST_SIZE(burst
);
452 params
.param0
|= DWC3_DEPCFG_IGN_SEQ_NUM
;
454 params
.param1
= DWC3_DEPCFG_XFER_COMPLETE_EN
455 | DWC3_DEPCFG_XFER_NOT_READY_EN
;
457 if (usb_ss_max_streams(comp_desc
) && usb_endpoint_xfer_bulk(desc
)) {
458 params
.param1
|= DWC3_DEPCFG_STREAM_CAPABLE
459 | DWC3_DEPCFG_STREAM_EVENT_EN
;
460 dep
->stream_capable
= true;
463 if (usb_endpoint_xfer_isoc(desc
))
464 params
.param1
|= DWC3_DEPCFG_XFER_IN_PROGRESS_EN
;
467 * We are doing 1:1 mapping for endpoints, meaning
468 * Physical Endpoints 2 maps to Logical Endpoint 2 and
469 * so on. We consider the direction bit as part of the physical
470 * endpoint number. So USB endpoint 0x81 is 0x03.
472 params
.param1
|= DWC3_DEPCFG_EP_NUMBER(dep
->number
);
475 * We must use the lower 16 TX FIFOs even though
479 params
.param0
|= DWC3_DEPCFG_FIFO_NUMBER(dep
->number
>> 1);
481 if (desc
->bInterval
) {
482 params
.param1
|= DWC3_DEPCFG_BINTERVAL_M1(desc
->bInterval
- 1);
483 dep
->interval
= 1 << (desc
->bInterval
- 1);
486 return dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
487 DWC3_DEPCMD_SETEPCONFIG
, ¶ms
);
490 static int dwc3_gadget_set_xfer_resource(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
492 struct dwc3_gadget_ep_cmd_params params
;
494 memset(¶ms
, 0x00, sizeof(params
));
496 params
.param0
= DWC3_DEPXFERCFG_NUM_XFER_RES(1);
498 return dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
499 DWC3_DEPCMD_SETTRANSFRESOURCE
, ¶ms
);
503 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
504 * @dep: endpoint to be initialized
505 * @desc: USB Endpoint Descriptor
507 * Caller should take care of locking
509 static int __dwc3_gadget_ep_enable(struct dwc3_ep
*dep
,
510 const struct usb_endpoint_descriptor
*desc
,
511 const struct usb_ss_ep_comp_descriptor
*comp_desc
,
514 struct dwc3
*dwc
= dep
->dwc
;
518 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
519 ret
= dwc3_gadget_start_config(dwc
, dep
);
524 ret
= dwc3_gadget_set_ep_config(dwc
, dep
, desc
, comp_desc
, ignore
);
528 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
529 struct dwc3_trb
*trb_st_hw
;
530 struct dwc3_trb
*trb_link
;
532 ret
= dwc3_gadget_set_xfer_resource(dwc
, dep
);
536 dep
->endpoint
.desc
= desc
;
537 dep
->comp_desc
= comp_desc
;
538 dep
->type
= usb_endpoint_type(desc
);
539 dep
->flags
|= DWC3_EP_ENABLED
;
541 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
542 reg
|= DWC3_DALEPENA_EP(dep
->number
);
543 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
545 if (!usb_endpoint_xfer_isoc(desc
))
548 memset(&trb_link
, 0, sizeof(trb_link
));
550 /* Link TRB for ISOC. The HWO bit is never reset */
551 trb_st_hw
= &dep
->trb_pool
[0];
553 trb_link
= &dep
->trb_pool
[DWC3_TRB_NUM
- 1];
555 trb_link
->bpl
= lower_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
556 trb_link
->bph
= upper_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
557 trb_link
->ctrl
|= DWC3_TRBCTL_LINK_TRB
;
558 trb_link
->ctrl
|= DWC3_TRB_CTRL_HWO
;
564 static void dwc3_stop_active_transfer(struct dwc3
*dwc
, u32 epnum
);
565 static void dwc3_remove_requests(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
567 struct dwc3_request
*req
;
569 if (!list_empty(&dep
->req_queued
)) {
570 dwc3_stop_active_transfer(dwc
, dep
->number
);
572 /* - giveback all requests to gadget driver */
573 while (!list_empty(&dep
->req_queued
)) {
574 req
= next_request(&dep
->req_queued
);
576 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
580 while (!list_empty(&dep
->request_list
)) {
581 req
= next_request(&dep
->request_list
);
583 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
588 * __dwc3_gadget_ep_disable - Disables a HW endpoint
589 * @dep: the endpoint to disable
591 * This function also removes requests which are currently processed ny the
592 * hardware and those which are not yet scheduled.
593 * Caller should take care of locking.
595 static int __dwc3_gadget_ep_disable(struct dwc3_ep
*dep
)
597 struct dwc3
*dwc
= dep
->dwc
;
600 dwc3_remove_requests(dwc
, dep
);
602 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
603 reg
&= ~DWC3_DALEPENA_EP(dep
->number
);
604 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
606 dep
->stream_capable
= false;
607 dep
->endpoint
.desc
= NULL
;
608 dep
->comp_desc
= NULL
;
615 /* -------------------------------------------------------------------------- */
617 static int dwc3_gadget_ep0_enable(struct usb_ep
*ep
,
618 const struct usb_endpoint_descriptor
*desc
)
623 static int dwc3_gadget_ep0_disable(struct usb_ep
*ep
)
628 /* -------------------------------------------------------------------------- */
630 static int dwc3_gadget_ep_enable(struct usb_ep
*ep
,
631 const struct usb_endpoint_descriptor
*desc
)
638 if (!ep
|| !desc
|| desc
->bDescriptorType
!= USB_DT_ENDPOINT
) {
639 pr_debug("dwc3: invalid parameters\n");
643 if (!desc
->wMaxPacketSize
) {
644 pr_debug("dwc3: missing wMaxPacketSize\n");
648 dep
= to_dwc3_ep(ep
);
651 if (dep
->flags
& DWC3_EP_ENABLED
) {
652 dev_WARN_ONCE(dwc
->dev
, true, "%s is already enabled\n",
657 switch (usb_endpoint_type(desc
)) {
658 case USB_ENDPOINT_XFER_CONTROL
:
659 strlcat(dep
->name
, "-control", sizeof(dep
->name
));
661 case USB_ENDPOINT_XFER_ISOC
:
662 strlcat(dep
->name
, "-isoc", sizeof(dep
->name
));
664 case USB_ENDPOINT_XFER_BULK
:
665 strlcat(dep
->name
, "-bulk", sizeof(dep
->name
));
667 case USB_ENDPOINT_XFER_INT
:
668 strlcat(dep
->name
, "-int", sizeof(dep
->name
));
671 dev_err(dwc
->dev
, "invalid endpoint transfer type\n");
674 dev_vdbg(dwc
->dev
, "Enabling %s\n", dep
->name
);
676 spin_lock_irqsave(&dwc
->lock
, flags
);
677 ret
= __dwc3_gadget_ep_enable(dep
, desc
, ep
->comp_desc
, false);
678 spin_unlock_irqrestore(&dwc
->lock
, flags
);
683 static int dwc3_gadget_ep_disable(struct usb_ep
*ep
)
691 pr_debug("dwc3: invalid parameters\n");
695 dep
= to_dwc3_ep(ep
);
698 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
699 dev_WARN_ONCE(dwc
->dev
, true, "%s is already disabled\n",
704 snprintf(dep
->name
, sizeof(dep
->name
), "ep%d%s",
706 (dep
->number
& 1) ? "in" : "out");
708 spin_lock_irqsave(&dwc
->lock
, flags
);
709 ret
= __dwc3_gadget_ep_disable(dep
);
710 spin_unlock_irqrestore(&dwc
->lock
, flags
);
715 static struct usb_request
*dwc3_gadget_ep_alloc_request(struct usb_ep
*ep
,
718 struct dwc3_request
*req
;
719 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
720 struct dwc3
*dwc
= dep
->dwc
;
722 req
= kzalloc(sizeof(*req
), gfp_flags
);
724 dev_err(dwc
->dev
, "not enough memory\n");
728 req
->epnum
= dep
->number
;
731 return &req
->request
;
734 static void dwc3_gadget_ep_free_request(struct usb_ep
*ep
,
735 struct usb_request
*request
)
737 struct dwc3_request
*req
= to_dwc3_request(request
);
743 * dwc3_prepare_one_trb - setup one TRB from one request
744 * @dep: endpoint for which this request is prepared
745 * @req: dwc3_request pointer
747 static void dwc3_prepare_one_trb(struct dwc3_ep
*dep
,
748 struct dwc3_request
*req
, dma_addr_t dma
,
749 unsigned length
, unsigned last
, unsigned chain
)
751 struct dwc3
*dwc
= dep
->dwc
;
752 struct dwc3_trb
*trb
;
754 unsigned int cur_slot
;
756 dev_vdbg(dwc
->dev
, "%s: req %p dma %08llx length %d%s%s\n",
757 dep
->name
, req
, (unsigned long long) dma
,
758 length
, last
? " last" : "",
759 chain
? " chain" : "");
761 trb
= &dep
->trb_pool
[dep
->free_slot
& DWC3_TRB_MASK
];
762 cur_slot
= dep
->free_slot
;
765 /* Skip the LINK-TRB on ISOC */
766 if (((cur_slot
& DWC3_TRB_MASK
) == DWC3_TRB_NUM
- 1) &&
767 usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
771 dwc3_gadget_move_request_queued(req
);
773 req
->trb_dma
= dwc3_trb_dma_offset(dep
, trb
);
776 trb
->size
= DWC3_TRB_SIZE_LENGTH(length
);
777 trb
->bpl
= lower_32_bits(dma
);
778 trb
->bph
= upper_32_bits(dma
);
780 switch (usb_endpoint_type(dep
->endpoint
.desc
)) {
781 case USB_ENDPOINT_XFER_CONTROL
:
782 trb
->ctrl
= DWC3_TRBCTL_CONTROL_SETUP
;
785 case USB_ENDPOINT_XFER_ISOC
:
786 trb
->ctrl
= DWC3_TRBCTL_ISOCHRONOUS_FIRST
;
788 if (!req
->request
.no_interrupt
)
789 trb
->ctrl
|= DWC3_TRB_CTRL_IOC
;
792 case USB_ENDPOINT_XFER_BULK
:
793 case USB_ENDPOINT_XFER_INT
:
794 trb
->ctrl
= DWC3_TRBCTL_NORMAL
;
798 * This is only possible with faulty memory because we
799 * checked it already :)
804 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
805 trb
->ctrl
|= DWC3_TRB_CTRL_ISP_IMI
;
806 trb
->ctrl
|= DWC3_TRB_CTRL_CSP
;
809 trb
->ctrl
|= DWC3_TRB_CTRL_CHN
;
812 trb
->ctrl
|= DWC3_TRB_CTRL_LST
;
815 if (usb_endpoint_xfer_bulk(dep
->endpoint
.desc
) && dep
->stream_capable
)
816 trb
->ctrl
|= DWC3_TRB_CTRL_SID_SOFN(req
->request
.stream_id
);
818 trb
->ctrl
|= DWC3_TRB_CTRL_HWO
;
822 * dwc3_prepare_trbs - setup TRBs from requests
823 * @dep: endpoint for which requests are being prepared
824 * @starting: true if the endpoint is idle and no requests are queued.
826 * The function goes through the requests list and sets up TRBs for the
827 * transfers. The function returns once there are no more TRBs available or
828 * it runs out of requests.
830 static void dwc3_prepare_trbs(struct dwc3_ep
*dep
, bool starting
)
832 struct dwc3_request
*req
, *n
;
835 unsigned int last_one
= 0;
837 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM
);
839 /* the first request must not be queued */
840 trbs_left
= (dep
->busy_slot
- dep
->free_slot
) & DWC3_TRB_MASK
;
842 /* Can't wrap around on a non-isoc EP since there's no link TRB */
843 if (!usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
844 max
= DWC3_TRB_NUM
- (dep
->free_slot
& DWC3_TRB_MASK
);
850 * If busy & slot are equal than it is either full or empty. If we are
851 * starting to process requests then we are empty. Otherwise we are
852 * full and don't do anything
857 trbs_left
= DWC3_TRB_NUM
;
859 * In case we start from scratch, we queue the ISOC requests
860 * starting from slot 1. This is done because we use ring
861 * buffer and have no LST bit to stop us. Instead, we place
862 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
863 * after the first request so we start at slot 1 and have
864 * 7 requests proceed before we hit the first IOC.
865 * Other transfer types don't use the ring buffer and are
866 * processed from the first TRB until the last one. Since we
867 * don't wrap around we have to start at the beginning.
869 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
878 /* The last TRB is a link TRB, not used for xfer */
879 if ((trbs_left
<= 1) && usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
882 list_for_each_entry_safe(req
, n
, &dep
->request_list
, list
) {
886 if (req
->request
.num_mapped_sgs
> 0) {
887 struct usb_request
*request
= &req
->request
;
888 struct scatterlist
*sg
= request
->sg
;
889 struct scatterlist
*s
;
892 for_each_sg(sg
, s
, request
->num_mapped_sgs
, i
) {
893 unsigned chain
= true;
895 length
= sg_dma_len(s
);
896 dma
= sg_dma_address(s
);
898 if (i
== (request
->num_mapped_sgs
- 1) ||
911 dwc3_prepare_one_trb(dep
, req
, dma
, length
,
918 dma
= req
->request
.dma
;
919 length
= req
->request
.length
;
925 /* Is this the last request? */
926 if (list_is_last(&req
->list
, &dep
->request_list
))
929 dwc3_prepare_one_trb(dep
, req
, dma
, length
,
938 static int __dwc3_gadget_kick_transfer(struct dwc3_ep
*dep
, u16 cmd_param
,
941 struct dwc3_gadget_ep_cmd_params params
;
942 struct dwc3_request
*req
;
943 struct dwc3
*dwc
= dep
->dwc
;
947 if (start_new
&& (dep
->flags
& DWC3_EP_BUSY
)) {
948 dev_vdbg(dwc
->dev
, "%s: endpoint busy\n", dep
->name
);
951 dep
->flags
&= ~DWC3_EP_PENDING_REQUEST
;
954 * If we are getting here after a short-out-packet we don't enqueue any
955 * new requests as we try to set the IOC bit only on the last request.
958 if (list_empty(&dep
->req_queued
))
959 dwc3_prepare_trbs(dep
, start_new
);
961 /* req points to the first request which will be sent */
962 req
= next_request(&dep
->req_queued
);
964 dwc3_prepare_trbs(dep
, start_new
);
967 * req points to the first request where HWO changed from 0 to 1
969 req
= next_request(&dep
->req_queued
);
972 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
976 memset(¶ms
, 0, sizeof(params
));
977 params
.param0
= upper_32_bits(req
->trb_dma
);
978 params
.param1
= lower_32_bits(req
->trb_dma
);
981 cmd
= DWC3_DEPCMD_STARTTRANSFER
;
983 cmd
= DWC3_DEPCMD_UPDATETRANSFER
;
985 cmd
|= DWC3_DEPCMD_PARAM(cmd_param
);
986 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
, cmd
, ¶ms
);
988 dev_dbg(dwc
->dev
, "failed to send STARTTRANSFER command\n");
991 * FIXME we need to iterate over the list of requests
992 * here and stop, unmap, free and del each of the linked
993 * requests instead of what we do now.
995 usb_gadget_unmap_request(&dwc
->gadget
, &req
->request
,
997 list_del(&req
->list
);
1001 dep
->flags
|= DWC3_EP_BUSY
;
1004 dep
->resource_index
= dwc3_gadget_ep_get_transfer_index(dwc
,
1006 WARN_ON_ONCE(!dep
->resource_index
);
1012 static void __dwc3_gadget_start_isoc(struct dwc3
*dwc
,
1013 struct dwc3_ep
*dep
, u32 cur_uf
)
1017 if (list_empty(&dep
->request_list
)) {
1018 dev_vdbg(dwc
->dev
, "ISOC ep %s run out for requests.\n",
1023 /* 4 micro frames in the future */
1024 uf
= cur_uf
+ dep
->interval
* 4;
1026 __dwc3_gadget_kick_transfer(dep
, uf
, 1);
1029 static void dwc3_gadget_start_isoc(struct dwc3
*dwc
,
1030 struct dwc3_ep
*dep
, const struct dwc3_event_depevt
*event
)
1034 mask
= ~(dep
->interval
- 1);
1035 cur_uf
= event
->parameters
& mask
;
1037 __dwc3_gadget_start_isoc(dwc
, dep
, cur_uf
);
1040 static int __dwc3_gadget_ep_queue(struct dwc3_ep
*dep
, struct dwc3_request
*req
)
1042 struct dwc3
*dwc
= dep
->dwc
;
1045 req
->request
.actual
= 0;
1046 req
->request
.status
= -EINPROGRESS
;
1047 req
->direction
= dep
->direction
;
1048 req
->epnum
= dep
->number
;
1051 * We only add to our list of requests now and
1052 * start consuming the list once we get XferNotReady
1055 * That way, we avoid doing anything that we don't need
1056 * to do now and defer it until the point we receive a
1057 * particular token from the Host side.
1059 * This will also avoid Host cancelling URBs due to too
1062 ret
= usb_gadget_map_request(&dwc
->gadget
, &req
->request
,
1067 list_add_tail(&req
->list
, &dep
->request_list
);
1070 * There are a few special cases:
1072 * 1. XferNotReady with empty list of requests. We need to kick the
1073 * transfer here in that situation, otherwise we will be NAKing
1074 * forever. If we get XferNotReady before gadget driver has a
1075 * chance to queue a request, we will ACK the IRQ but won't be
1076 * able to receive the data until the next request is queued.
1077 * The following code is handling exactly that.
1080 if (dep
->flags
& DWC3_EP_PENDING_REQUEST
) {
1081 ret
= __dwc3_gadget_kick_transfer(dep
, 0, true);
1082 if (ret
&& ret
!= -EBUSY
)
1083 dev_dbg(dwc
->dev
, "%s: failed to kick transfers\n",
1088 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1089 * kick the transfer here after queuing a request, otherwise the
1090 * core may not see the modified TRB(s).
1092 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) &&
1093 (dep
->flags
& DWC3_EP_BUSY
) &&
1094 !(dep
->flags
& DWC3_EP_MISSED_ISOC
)) {
1095 WARN_ON_ONCE(!dep
->resource_index
);
1096 ret
= __dwc3_gadget_kick_transfer(dep
, dep
->resource_index
,
1098 if (ret
&& ret
!= -EBUSY
)
1099 dev_dbg(dwc
->dev
, "%s: failed to kick transfers\n",
1104 * 3. Missed ISOC Handling. We need to start isoc transfer on the saved
1107 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) &&
1108 (dep
->flags
& DWC3_EP_MISSED_ISOC
)) {
1109 __dwc3_gadget_start_isoc(dwc
, dep
, dep
->current_uf
);
1110 dep
->flags
&= ~DWC3_EP_MISSED_ISOC
;
1116 static int dwc3_gadget_ep_queue(struct usb_ep
*ep
, struct usb_request
*request
,
1119 struct dwc3_request
*req
= to_dwc3_request(request
);
1120 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1121 struct dwc3
*dwc
= dep
->dwc
;
1123 unsigned long flags
;
1127 if (!dep
->endpoint
.desc
) {
1128 dev_dbg(dwc
->dev
, "trying to queue request %p to disabled %s\n",
1133 dev_vdbg(dwc
->dev
, "queing request %p to %s length %d\n",
1134 request
, ep
->name
, request
->length
);
1136 spin_lock_irqsave(&dwc
->lock
, flags
);
1137 ret
= __dwc3_gadget_ep_queue(dep
, req
);
1138 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1143 static int dwc3_gadget_ep_dequeue(struct usb_ep
*ep
,
1144 struct usb_request
*request
)
1146 struct dwc3_request
*req
= to_dwc3_request(request
);
1147 struct dwc3_request
*r
= NULL
;
1149 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1150 struct dwc3
*dwc
= dep
->dwc
;
1152 unsigned long flags
;
1155 spin_lock_irqsave(&dwc
->lock
, flags
);
1157 list_for_each_entry(r
, &dep
->request_list
, list
) {
1163 list_for_each_entry(r
, &dep
->req_queued
, list
) {
1168 /* wait until it is processed */
1169 dwc3_stop_active_transfer(dwc
, dep
->number
);
1172 dev_err(dwc
->dev
, "request %p was not queued to %s\n",
1179 /* giveback the request */
1180 dwc3_gadget_giveback(dep
, req
, -ECONNRESET
);
1183 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1188 int __dwc3_gadget_ep_set_halt(struct dwc3_ep
*dep
, int value
)
1190 struct dwc3_gadget_ep_cmd_params params
;
1191 struct dwc3
*dwc
= dep
->dwc
;
1194 memset(¶ms
, 0x00, sizeof(params
));
1197 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
1198 DWC3_DEPCMD_SETSTALL
, ¶ms
);
1200 dev_err(dwc
->dev
, "failed to %s STALL on %s\n",
1201 value
? "set" : "clear",
1204 dep
->flags
|= DWC3_EP_STALL
;
1206 if (dep
->flags
& DWC3_EP_WEDGE
)
1209 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
1210 DWC3_DEPCMD_CLEARSTALL
, ¶ms
);
1212 dev_err(dwc
->dev
, "failed to %s STALL on %s\n",
1213 value
? "set" : "clear",
1216 dep
->flags
&= ~DWC3_EP_STALL
;
1222 static int dwc3_gadget_ep_set_halt(struct usb_ep
*ep
, int value
)
1224 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1225 struct dwc3
*dwc
= dep
->dwc
;
1227 unsigned long flags
;
1231 spin_lock_irqsave(&dwc
->lock
, flags
);
1233 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1234 dev_err(dwc
->dev
, "%s is of Isochronous type\n", dep
->name
);
1239 ret
= __dwc3_gadget_ep_set_halt(dep
, value
);
1241 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1246 static int dwc3_gadget_ep_set_wedge(struct usb_ep
*ep
)
1248 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1249 struct dwc3
*dwc
= dep
->dwc
;
1250 unsigned long flags
;
1252 spin_lock_irqsave(&dwc
->lock
, flags
);
1253 dep
->flags
|= DWC3_EP_WEDGE
;
1254 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1256 if (dep
->number
== 0 || dep
->number
== 1)
1257 return dwc3_gadget_ep0_set_halt(ep
, 1);
1259 return dwc3_gadget_ep_set_halt(ep
, 1);
1262 /* -------------------------------------------------------------------------- */
1264 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc
= {
1265 .bLength
= USB_DT_ENDPOINT_SIZE
,
1266 .bDescriptorType
= USB_DT_ENDPOINT
,
1267 .bmAttributes
= USB_ENDPOINT_XFER_CONTROL
,
1270 static const struct usb_ep_ops dwc3_gadget_ep0_ops
= {
1271 .enable
= dwc3_gadget_ep0_enable
,
1272 .disable
= dwc3_gadget_ep0_disable
,
1273 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1274 .free_request
= dwc3_gadget_ep_free_request
,
1275 .queue
= dwc3_gadget_ep0_queue
,
1276 .dequeue
= dwc3_gadget_ep_dequeue
,
1277 .set_halt
= dwc3_gadget_ep0_set_halt
,
1278 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1281 static const struct usb_ep_ops dwc3_gadget_ep_ops
= {
1282 .enable
= dwc3_gadget_ep_enable
,
1283 .disable
= dwc3_gadget_ep_disable
,
1284 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1285 .free_request
= dwc3_gadget_ep_free_request
,
1286 .queue
= dwc3_gadget_ep_queue
,
1287 .dequeue
= dwc3_gadget_ep_dequeue
,
1288 .set_halt
= dwc3_gadget_ep_set_halt
,
1289 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1292 /* -------------------------------------------------------------------------- */
1294 static int dwc3_gadget_get_frame(struct usb_gadget
*g
)
1296 struct dwc3
*dwc
= gadget_to_dwc(g
);
1299 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1300 return DWC3_DSTS_SOFFN(reg
);
1303 static int dwc3_gadget_wakeup(struct usb_gadget
*g
)
1305 struct dwc3
*dwc
= gadget_to_dwc(g
);
1307 unsigned long timeout
;
1308 unsigned long flags
;
1317 spin_lock_irqsave(&dwc
->lock
, flags
);
1320 * According to the Databook Remote wakeup request should
1321 * be issued only when the device is in early suspend state.
1323 * We can check that via USB Link State bits in DSTS register.
1325 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1327 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
1328 if (speed
== DWC3_DSTS_SUPERSPEED
) {
1329 dev_dbg(dwc
->dev
, "no wakeup on SuperSpeed\n");
1334 link_state
= DWC3_DSTS_USBLNKST(reg
);
1336 switch (link_state
) {
1337 case DWC3_LINK_STATE_RX_DET
: /* in HS, means Early Suspend */
1338 case DWC3_LINK_STATE_U3
: /* in HS, means SUSPEND */
1341 dev_dbg(dwc
->dev
, "can't wakeup from link state %d\n",
1347 ret
= dwc3_gadget_set_link_state(dwc
, DWC3_LINK_STATE_RECOV
);
1349 dev_err(dwc
->dev
, "failed to put link in Recovery\n");
1353 /* Recent versions do this automatically */
1354 if (dwc
->revision
< DWC3_REVISION_194A
) {
1355 /* write zeroes to Link Change Request */
1356 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1357 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
1358 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1361 /* poll until Link State changes to ON */
1362 timeout
= jiffies
+ msecs_to_jiffies(100);
1364 while (!time_after(jiffies
, timeout
)) {
1365 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1367 /* in HS, means ON */
1368 if (DWC3_DSTS_USBLNKST(reg
) == DWC3_LINK_STATE_U0
)
1372 if (DWC3_DSTS_USBLNKST(reg
) != DWC3_LINK_STATE_U0
) {
1373 dev_err(dwc
->dev
, "failed to send remote wakeup\n");
1378 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1383 static int dwc3_gadget_set_selfpowered(struct usb_gadget
*g
,
1386 struct dwc3
*dwc
= gadget_to_dwc(g
);
1387 unsigned long flags
;
1389 spin_lock_irqsave(&dwc
->lock
, flags
);
1390 dwc
->is_selfpowered
= !!is_selfpowered
;
1391 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1396 static int dwc3_gadget_run_stop(struct dwc3
*dwc
, int is_on
)
1401 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1403 if (dwc
->revision
<= DWC3_REVISION_187A
) {
1404 reg
&= ~DWC3_DCTL_TRGTULST_MASK
;
1405 reg
|= DWC3_DCTL_TRGTULST_RX_DET
;
1408 if (dwc
->revision
>= DWC3_REVISION_194A
)
1409 reg
&= ~DWC3_DCTL_KEEP_CONNECT
;
1410 reg
|= DWC3_DCTL_RUN_STOP
;
1412 reg
&= ~DWC3_DCTL_RUN_STOP
;
1415 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1418 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1420 if (!(reg
& DWC3_DSTS_DEVCTRLHLT
))
1423 if (reg
& DWC3_DSTS_DEVCTRLHLT
)
1432 dev_vdbg(dwc
->dev
, "gadget %s data soft-%s\n",
1434 ? dwc
->gadget_driver
->function
: "no-function",
1435 is_on
? "connect" : "disconnect");
1440 static int dwc3_gadget_pullup(struct usb_gadget
*g
, int is_on
)
1442 struct dwc3
*dwc
= gadget_to_dwc(g
);
1443 unsigned long flags
;
1448 spin_lock_irqsave(&dwc
->lock
, flags
);
1449 ret
= dwc3_gadget_run_stop(dwc
, is_on
);
1450 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1455 static int dwc3_gadget_start(struct usb_gadget
*g
,
1456 struct usb_gadget_driver
*driver
)
1458 struct dwc3
*dwc
= gadget_to_dwc(g
);
1459 struct dwc3_ep
*dep
;
1460 unsigned long flags
;
1464 spin_lock_irqsave(&dwc
->lock
, flags
);
1466 if (dwc
->gadget_driver
) {
1467 dev_err(dwc
->dev
, "%s is already bound to %s\n",
1469 dwc
->gadget_driver
->driver
.name
);
1474 dwc
->gadget_driver
= driver
;
1475 dwc
->gadget
.dev
.driver
= &driver
->driver
;
1477 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
1478 reg
&= ~(DWC3_DCFG_SPEED_MASK
);
1481 * WORKAROUND: DWC3 revision < 2.20a have an issue
1482 * which would cause metastability state on Run/Stop
1483 * bit if we try to force the IP to USB2-only mode.
1485 * Because of that, we cannot configure the IP to any
1486 * speed other than the SuperSpeed
1490 * STAR#9000525659: Clock Domain Crossing on DCTL in
1493 if (dwc
->revision
< DWC3_REVISION_220A
)
1494 reg
|= DWC3_DCFG_SUPERSPEED
;
1496 reg
|= dwc
->maximum_speed
;
1497 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
1499 dwc
->start_config_issued
= false;
1501 /* Start with SuperSpeed Default */
1502 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
1505 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, false);
1507 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1512 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, false);
1514 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1518 /* begin to receive SETUP packets */
1519 dwc
->ep0state
= EP0_SETUP_PHASE
;
1520 dwc3_ep0_out_start(dwc
);
1522 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1527 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
1530 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1535 static int dwc3_gadget_stop(struct usb_gadget
*g
,
1536 struct usb_gadget_driver
*driver
)
1538 struct dwc3
*dwc
= gadget_to_dwc(g
);
1539 unsigned long flags
;
1541 spin_lock_irqsave(&dwc
->lock
, flags
);
1543 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
1544 __dwc3_gadget_ep_disable(dwc
->eps
[1]);
1546 dwc
->gadget_driver
= NULL
;
1547 dwc
->gadget
.dev
.driver
= NULL
;
1549 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1554 static const struct usb_gadget_ops dwc3_gadget_ops
= {
1555 .get_frame
= dwc3_gadget_get_frame
,
1556 .wakeup
= dwc3_gadget_wakeup
,
1557 .set_selfpowered
= dwc3_gadget_set_selfpowered
,
1558 .pullup
= dwc3_gadget_pullup
,
1559 .udc_start
= dwc3_gadget_start
,
1560 .udc_stop
= dwc3_gadget_stop
,
1563 /* -------------------------------------------------------------------------- */
1565 static int __devinit
dwc3_gadget_init_endpoints(struct dwc3
*dwc
)
1567 struct dwc3_ep
*dep
;
1570 INIT_LIST_HEAD(&dwc
->gadget
.ep_list
);
1572 for (epnum
= 0; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
1573 dep
= kzalloc(sizeof(*dep
), GFP_KERNEL
);
1575 dev_err(dwc
->dev
, "can't allocate endpoint %d\n",
1581 dep
->number
= epnum
;
1582 dwc
->eps
[epnum
] = dep
;
1584 snprintf(dep
->name
, sizeof(dep
->name
), "ep%d%s", epnum
>> 1,
1585 (epnum
& 1) ? "in" : "out");
1586 dep
->endpoint
.name
= dep
->name
;
1587 dep
->direction
= (epnum
& 1);
1589 if (epnum
== 0 || epnum
== 1) {
1590 dep
->endpoint
.maxpacket
= 512;
1591 dep
->endpoint
.ops
= &dwc3_gadget_ep0_ops
;
1593 dwc
->gadget
.ep0
= &dep
->endpoint
;
1597 dep
->endpoint
.maxpacket
= 1024;
1598 dep
->endpoint
.max_streams
= 15;
1599 dep
->endpoint
.ops
= &dwc3_gadget_ep_ops
;
1600 list_add_tail(&dep
->endpoint
.ep_list
,
1601 &dwc
->gadget
.ep_list
);
1603 ret
= dwc3_alloc_trb_pool(dep
);
1608 INIT_LIST_HEAD(&dep
->request_list
);
1609 INIT_LIST_HEAD(&dep
->req_queued
);
1615 static void dwc3_gadget_free_endpoints(struct dwc3
*dwc
)
1617 struct dwc3_ep
*dep
;
1620 for (epnum
= 0; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
1621 dep
= dwc
->eps
[epnum
];
1622 dwc3_free_trb_pool(dep
);
1624 if (epnum
!= 0 && epnum
!= 1)
1625 list_del(&dep
->endpoint
.ep_list
);
1631 static void dwc3_gadget_release(struct device
*dev
)
1633 dev_dbg(dev
, "%s\n", __func__
);
1636 /* -------------------------------------------------------------------------- */
1637 static int dwc3_cleanup_done_reqs(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
1638 const struct dwc3_event_depevt
*event
, int status
)
1640 struct dwc3_request
*req
;
1641 struct dwc3_trb
*trb
;
1643 unsigned int s_pkt
= 0;
1644 unsigned int trb_status
;
1647 req
= next_request(&dep
->req_queued
);
1655 if ((trb
->ctrl
& DWC3_TRB_CTRL_HWO
) && status
!= -ESHUTDOWN
)
1657 * We continue despite the error. There is not much we
1658 * can do. If we don't clean it up we loop forever. If
1659 * we skip the TRB then it gets overwritten after a
1660 * while since we use them in a ring buffer. A BUG()
1661 * would help. Lets hope that if this occurs, someone
1662 * fixes the root cause instead of looking away :)
1664 dev_err(dwc
->dev
, "%s's TRB (%p) still owned by HW\n",
1665 dep
->name
, req
->trb
);
1666 count
= trb
->size
& DWC3_TRB_SIZE_MASK
;
1668 if (dep
->direction
) {
1670 trb_status
= DWC3_TRB_SIZE_TRBSTS(trb
->size
);
1671 if (trb_status
== DWC3_TRBSTS_MISSED_ISOC
) {
1672 dev_dbg(dwc
->dev
, "incomplete IN transfer %s\n",
1674 dep
->current_uf
= event
->parameters
&
1675 ~(dep
->interval
- 1);
1676 dep
->flags
|= DWC3_EP_MISSED_ISOC
;
1678 dev_err(dwc
->dev
, "incomplete IN transfer %s\n",
1680 status
= -ECONNRESET
;
1684 if (count
&& (event
->status
& DEPEVT_STATUS_SHORT
))
1689 * We assume here we will always receive the entire data block
1690 * which we should receive. Meaning, if we program RX to
1691 * receive 4K but we receive only 2K, we assume that's all we
1692 * should receive and we simply bounce the request back to the
1693 * gadget driver for further processing.
1695 req
->request
.actual
+= req
->request
.length
- count
;
1696 dwc3_gadget_giveback(dep
, req
, status
);
1699 if ((event
->status
& DEPEVT_STATUS_LST
) &&
1700 (trb
->ctrl
& (DWC3_TRB_CTRL_LST
|
1701 DWC3_TRB_CTRL_HWO
)))
1703 if ((event
->status
& DEPEVT_STATUS_IOC
) &&
1704 (trb
->ctrl
& DWC3_TRB_CTRL_IOC
))
1708 if ((event
->status
& DEPEVT_STATUS_IOC
) &&
1709 (trb
->ctrl
& DWC3_TRB_CTRL_IOC
))
1714 static void dwc3_endpoint_transfer_complete(struct dwc3
*dwc
,
1715 struct dwc3_ep
*dep
, const struct dwc3_event_depevt
*event
,
1718 unsigned status
= 0;
1721 if (event
->status
& DEPEVT_STATUS_BUSERR
)
1722 status
= -ECONNRESET
;
1724 clean_busy
= dwc3_cleanup_done_reqs(dwc
, dep
, event
, status
);
1726 dep
->flags
&= ~DWC3_EP_BUSY
;
1729 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1730 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1732 if (dwc
->revision
< DWC3_REVISION_183A
) {
1736 for (i
= 0; i
< DWC3_ENDPOINTS_NUM
; i
++) {
1739 if (!(dep
->flags
& DWC3_EP_ENABLED
))
1742 if (!list_empty(&dep
->req_queued
))
1746 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1748 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1754 static void dwc3_endpoint_interrupt(struct dwc3
*dwc
,
1755 const struct dwc3_event_depevt
*event
)
1757 struct dwc3_ep
*dep
;
1758 u8 epnum
= event
->endpoint_number
;
1760 dep
= dwc
->eps
[epnum
];
1762 if (!(dep
->flags
& DWC3_EP_ENABLED
))
1765 dev_vdbg(dwc
->dev
, "%s: %s\n", dep
->name
,
1766 dwc3_ep_event_string(event
->endpoint_event
));
1768 if (epnum
== 0 || epnum
== 1) {
1769 dwc3_ep0_interrupt(dwc
, event
);
1773 switch (event
->endpoint_event
) {
1774 case DWC3_DEPEVT_XFERCOMPLETE
:
1775 dep
->resource_index
= 0;
1777 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1778 dev_dbg(dwc
->dev
, "%s is an Isochronous endpoint\n",
1783 dwc3_endpoint_transfer_complete(dwc
, dep
, event
, 1);
1785 case DWC3_DEPEVT_XFERINPROGRESS
:
1786 if (!usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1787 dev_dbg(dwc
->dev
, "%s is not an Isochronous endpoint\n",
1792 dwc3_endpoint_transfer_complete(dwc
, dep
, event
, 0);
1794 case DWC3_DEPEVT_XFERNOTREADY
:
1795 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1796 dwc3_gadget_start_isoc(dwc
, dep
, event
);
1800 dev_vdbg(dwc
->dev
, "%s: reason %s\n",
1801 dep
->name
, event
->status
&
1802 DEPEVT_STATUS_TRANSFER_ACTIVE
1804 : "Transfer Not Active");
1806 ret
= __dwc3_gadget_kick_transfer(dep
, 0, 1);
1807 if (!ret
|| ret
== -EBUSY
)
1810 dev_dbg(dwc
->dev
, "%s: failed to kick transfers\n",
1815 case DWC3_DEPEVT_STREAMEVT
:
1816 if (!usb_endpoint_xfer_bulk(dep
->endpoint
.desc
)) {
1817 dev_err(dwc
->dev
, "Stream event for non-Bulk %s\n",
1822 switch (event
->status
) {
1823 case DEPEVT_STREAMEVT_FOUND
:
1824 dev_vdbg(dwc
->dev
, "Stream %d found and started\n",
1828 case DEPEVT_STREAMEVT_NOTFOUND
:
1831 dev_dbg(dwc
->dev
, "Couldn't find suitable stream\n");
1834 case DWC3_DEPEVT_RXTXFIFOEVT
:
1835 dev_dbg(dwc
->dev
, "%s FIFO Overrun\n", dep
->name
);
1837 case DWC3_DEPEVT_EPCMDCMPLT
:
1838 dev_vdbg(dwc
->dev
, "Endpoint Command Complete\n");
1843 static void dwc3_disconnect_gadget(struct dwc3
*dwc
)
1845 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->disconnect
) {
1846 spin_unlock(&dwc
->lock
);
1847 dwc
->gadget_driver
->disconnect(&dwc
->gadget
);
1848 spin_lock(&dwc
->lock
);
1852 static void dwc3_stop_active_transfer(struct dwc3
*dwc
, u32 epnum
)
1854 struct dwc3_ep
*dep
;
1855 struct dwc3_gadget_ep_cmd_params params
;
1859 dep
= dwc
->eps
[epnum
];
1861 if (!dep
->resource_index
)
1865 * NOTICE: We are violating what the Databook says about the
1866 * EndTransfer command. Ideally we would _always_ wait for the
1867 * EndTransfer Command Completion IRQ, but that's causing too
1868 * much trouble synchronizing between us and gadget driver.
1870 * We have discussed this with the IP Provider and it was
1871 * suggested to giveback all requests here, but give HW some
1872 * extra time to synchronize with the interconnect. We're using
1873 * an arbitraty 100us delay for that.
1875 * Note also that a similar handling was tested by Synopsys
1876 * (thanks a lot Paul) and nothing bad has come out of it.
1877 * In short, what we're doing is:
1879 * - Issue EndTransfer WITH CMDIOC bit set
1883 cmd
= DWC3_DEPCMD_ENDTRANSFER
;
1884 cmd
|= DWC3_DEPCMD_HIPRI_FORCERM
| DWC3_DEPCMD_CMDIOC
;
1885 cmd
|= DWC3_DEPCMD_PARAM(dep
->resource_index
);
1886 memset(¶ms
, 0, sizeof(params
));
1887 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
, cmd
, ¶ms
);
1889 dep
->resource_index
= 0;
1894 static void dwc3_stop_active_transfers(struct dwc3
*dwc
)
1898 for (epnum
= 2; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
1899 struct dwc3_ep
*dep
;
1901 dep
= dwc
->eps
[epnum
];
1902 if (!(dep
->flags
& DWC3_EP_ENABLED
))
1905 dwc3_remove_requests(dwc
, dep
);
1909 static void dwc3_clear_stall_all_ep(struct dwc3
*dwc
)
1913 for (epnum
= 1; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
1914 struct dwc3_ep
*dep
;
1915 struct dwc3_gadget_ep_cmd_params params
;
1918 dep
= dwc
->eps
[epnum
];
1920 if (!(dep
->flags
& DWC3_EP_STALL
))
1923 dep
->flags
&= ~DWC3_EP_STALL
;
1925 memset(¶ms
, 0, sizeof(params
));
1926 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
1927 DWC3_DEPCMD_CLEARSTALL
, ¶ms
);
1932 static void dwc3_gadget_disconnect_interrupt(struct dwc3
*dwc
)
1936 dev_vdbg(dwc
->dev
, "%s\n", __func__
);
1938 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1939 reg
&= ~DWC3_DCTL_INITU1ENA
;
1940 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1942 reg
&= ~DWC3_DCTL_INITU2ENA
;
1943 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1945 dwc3_disconnect_gadget(dwc
);
1946 dwc
->start_config_issued
= false;
1948 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
1949 dwc
->setup_packet_pending
= false;
1952 static void dwc3_gadget_usb3_phy_suspend(struct dwc3
*dwc
, int suspend
)
1956 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB3PIPECTL(0));
1959 reg
|= DWC3_GUSB3PIPECTL_SUSPHY
;
1961 reg
&= ~DWC3_GUSB3PIPECTL_SUSPHY
;
1963 dwc3_writel(dwc
->regs
, DWC3_GUSB3PIPECTL(0), reg
);
1966 static void dwc3_gadget_usb2_phy_suspend(struct dwc3
*dwc
, int suspend
)
1970 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
1973 reg
|= DWC3_GUSB2PHYCFG_SUSPHY
;
1975 reg
&= ~DWC3_GUSB2PHYCFG_SUSPHY
;
1977 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
1980 static void dwc3_gadget_reset_interrupt(struct dwc3
*dwc
)
1984 dev_vdbg(dwc
->dev
, "%s\n", __func__
);
1987 * WORKAROUND: DWC3 revisions <1.88a have an issue which
1988 * would cause a missing Disconnect Event if there's a
1989 * pending Setup Packet in the FIFO.
1991 * There's no suggested workaround on the official Bug
1992 * report, which states that "unless the driver/application
1993 * is doing any special handling of a disconnect event,
1994 * there is no functional issue".
1996 * Unfortunately, it turns out that we _do_ some special
1997 * handling of a disconnect event, namely complete all
1998 * pending transfers, notify gadget driver of the
1999 * disconnection, and so on.
2001 * Our suggested workaround is to follow the Disconnect
2002 * Event steps here, instead, based on a setup_packet_pending
2003 * flag. Such flag gets set whenever we have a XferNotReady
2004 * event on EP0 and gets cleared on XferComplete for the
2009 * STAR#9000466709: RTL: Device : Disconnect event not
2010 * generated if setup packet pending in FIFO
2012 if (dwc
->revision
< DWC3_REVISION_188A
) {
2013 if (dwc
->setup_packet_pending
)
2014 dwc3_gadget_disconnect_interrupt(dwc
);
2017 /* after reset -> Default State */
2018 dwc
->dev_state
= DWC3_DEFAULT_STATE
;
2020 /* Recent versions support automatic phy suspend and don't need this */
2021 if (dwc
->revision
< DWC3_REVISION_194A
) {
2023 dwc3_gadget_usb2_phy_suspend(dwc
, false);
2024 dwc3_gadget_usb3_phy_suspend(dwc
, false);
2027 if (dwc
->gadget
.speed
!= USB_SPEED_UNKNOWN
)
2028 dwc3_disconnect_gadget(dwc
);
2030 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2031 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
2032 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2033 dwc
->test_mode
= false;
2035 dwc3_stop_active_transfers(dwc
);
2036 dwc3_clear_stall_all_ep(dwc
);
2037 dwc
->start_config_issued
= false;
2039 /* Reset device address to zero */
2040 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2041 reg
&= ~(DWC3_DCFG_DEVADDR_MASK
);
2042 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2045 static void dwc3_update_ram_clk_sel(struct dwc3
*dwc
, u32 speed
)
2048 u32 usb30_clock
= DWC3_GCTL_CLK_BUS
;
2051 * We change the clock only at SS but I dunno why I would want to do
2052 * this. Maybe it becomes part of the power saving plan.
2055 if (speed
!= DWC3_DSTS_SUPERSPEED
)
2059 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2060 * each time on Connect Done.
2065 reg
= dwc3_readl(dwc
->regs
, DWC3_GCTL
);
2066 reg
|= DWC3_GCTL_RAMCLKSEL(usb30_clock
);
2067 dwc3_writel(dwc
->regs
, DWC3_GCTL
, reg
);
2070 static void dwc3_gadget_phy_suspend(struct dwc3
*dwc
, u8 speed
)
2073 case USB_SPEED_SUPER
:
2074 dwc3_gadget_usb2_phy_suspend(dwc
, true);
2076 case USB_SPEED_HIGH
:
2077 case USB_SPEED_FULL
:
2079 dwc3_gadget_usb3_phy_suspend(dwc
, true);
2084 static void dwc3_gadget_conndone_interrupt(struct dwc3
*dwc
)
2086 struct dwc3_gadget_ep_cmd_params params
;
2087 struct dwc3_ep
*dep
;
2092 dev_vdbg(dwc
->dev
, "%s\n", __func__
);
2094 memset(¶ms
, 0x00, sizeof(params
));
2096 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
2097 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
2100 dwc3_update_ram_clk_sel(dwc
, speed
);
2103 case DWC3_DCFG_SUPERSPEED
:
2105 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2106 * would cause a missing USB3 Reset event.
2108 * In such situations, we should force a USB3 Reset
2109 * event by calling our dwc3_gadget_reset_interrupt()
2114 * STAR#9000483510: RTL: SS : USB3 reset event may
2115 * not be generated always when the link enters poll
2117 if (dwc
->revision
< DWC3_REVISION_190A
)
2118 dwc3_gadget_reset_interrupt(dwc
);
2120 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
2121 dwc
->gadget
.ep0
->maxpacket
= 512;
2122 dwc
->gadget
.speed
= USB_SPEED_SUPER
;
2124 case DWC3_DCFG_HIGHSPEED
:
2125 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2126 dwc
->gadget
.ep0
->maxpacket
= 64;
2127 dwc
->gadget
.speed
= USB_SPEED_HIGH
;
2129 case DWC3_DCFG_FULLSPEED2
:
2130 case DWC3_DCFG_FULLSPEED1
:
2131 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2132 dwc
->gadget
.ep0
->maxpacket
= 64;
2133 dwc
->gadget
.speed
= USB_SPEED_FULL
;
2135 case DWC3_DCFG_LOWSPEED
:
2136 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(8);
2137 dwc
->gadget
.ep0
->maxpacket
= 8;
2138 dwc
->gadget
.speed
= USB_SPEED_LOW
;
2142 /* Recent versions support automatic phy suspend and don't need this */
2143 if (dwc
->revision
< DWC3_REVISION_194A
) {
2144 /* Suspend unneeded PHY */
2145 dwc3_gadget_phy_suspend(dwc
, dwc
->gadget
.speed
);
2149 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, true);
2151 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2156 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, true);
2158 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2163 * Configure PHY via GUSB3PIPECTLn if required.
2165 * Update GTXFIFOSIZn
2167 * In both cases reset values should be sufficient.
2171 static void dwc3_gadget_wakeup_interrupt(struct dwc3
*dwc
)
2173 dev_vdbg(dwc
->dev
, "%s\n", __func__
);
2176 * TODO take core out of low power mode when that's
2180 dwc
->gadget_driver
->resume(&dwc
->gadget
);
2183 static void dwc3_gadget_linksts_change_interrupt(struct dwc3
*dwc
,
2184 unsigned int evtinfo
)
2186 enum dwc3_link_state next
= evtinfo
& DWC3_LINK_STATE_MASK
;
2189 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2190 * on the link partner, the USB session might do multiple entry/exit
2191 * of low power states before a transfer takes place.
2193 * Due to this problem, we might experience lower throughput. The
2194 * suggested workaround is to disable DCTL[12:9] bits if we're
2195 * transitioning from U1/U2 to U0 and enable those bits again
2196 * after a transfer completes and there are no pending transfers
2197 * on any of the enabled endpoints.
2199 * This is the first half of that workaround.
2203 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2204 * core send LGO_Ux entering U0
2206 if (dwc
->revision
< DWC3_REVISION_183A
) {
2207 if (next
== DWC3_LINK_STATE_U0
) {
2211 switch (dwc
->link_state
) {
2212 case DWC3_LINK_STATE_U1
:
2213 case DWC3_LINK_STATE_U2
:
2214 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2215 u1u2
= reg
& (DWC3_DCTL_INITU2ENA
2216 | DWC3_DCTL_ACCEPTU2ENA
2217 | DWC3_DCTL_INITU1ENA
2218 | DWC3_DCTL_ACCEPTU1ENA
);
2221 dwc
->u1u2
= reg
& u1u2
;
2225 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2234 dwc
->link_state
= next
;
2236 dev_vdbg(dwc
->dev
, "%s link %d\n", __func__
, dwc
->link_state
);
2239 static void dwc3_gadget_interrupt(struct dwc3
*dwc
,
2240 const struct dwc3_event_devt
*event
)
2242 switch (event
->type
) {
2243 case DWC3_DEVICE_EVENT_DISCONNECT
:
2244 dwc3_gadget_disconnect_interrupt(dwc
);
2246 case DWC3_DEVICE_EVENT_RESET
:
2247 dwc3_gadget_reset_interrupt(dwc
);
2249 case DWC3_DEVICE_EVENT_CONNECT_DONE
:
2250 dwc3_gadget_conndone_interrupt(dwc
);
2252 case DWC3_DEVICE_EVENT_WAKEUP
:
2253 dwc3_gadget_wakeup_interrupt(dwc
);
2255 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE
:
2256 dwc3_gadget_linksts_change_interrupt(dwc
, event
->event_info
);
2258 case DWC3_DEVICE_EVENT_EOPF
:
2259 dev_vdbg(dwc
->dev
, "End of Periodic Frame\n");
2261 case DWC3_DEVICE_EVENT_SOF
:
2262 dev_vdbg(dwc
->dev
, "Start of Periodic Frame\n");
2264 case DWC3_DEVICE_EVENT_ERRATIC_ERROR
:
2265 dev_vdbg(dwc
->dev
, "Erratic Error\n");
2267 case DWC3_DEVICE_EVENT_CMD_CMPL
:
2268 dev_vdbg(dwc
->dev
, "Command Complete\n");
2270 case DWC3_DEVICE_EVENT_OVERFLOW
:
2271 dev_vdbg(dwc
->dev
, "Overflow\n");
2274 dev_dbg(dwc
->dev
, "UNKNOWN IRQ %d\n", event
->type
);
2278 static void dwc3_process_event_entry(struct dwc3
*dwc
,
2279 const union dwc3_event
*event
)
2281 /* Endpoint IRQ, handle it and return early */
2282 if (event
->type
.is_devspec
== 0) {
2284 return dwc3_endpoint_interrupt(dwc
, &event
->depevt
);
2287 switch (event
->type
.type
) {
2288 case DWC3_EVENT_TYPE_DEV
:
2289 dwc3_gadget_interrupt(dwc
, &event
->devt
);
2291 /* REVISIT what to do with Carkit and I2C events ? */
2293 dev_err(dwc
->dev
, "UNKNOWN IRQ type %d\n", event
->raw
);
2297 static irqreturn_t
dwc3_process_event_buf(struct dwc3
*dwc
, u32 buf
)
2299 struct dwc3_event_buffer
*evt
;
2303 count
= dwc3_readl(dwc
->regs
, DWC3_GEVNTCOUNT(buf
));
2304 count
&= DWC3_GEVNTCOUNT_MASK
;
2308 evt
= dwc
->ev_buffs
[buf
];
2312 union dwc3_event event
;
2314 event
.raw
= *(u32
*) (evt
->buf
+ evt
->lpos
);
2316 dwc3_process_event_entry(dwc
, &event
);
2318 * XXX we wrap around correctly to the next entry as almost all
2319 * entries are 4 bytes in size. There is one entry which has 12
2320 * bytes which is a regular entry followed by 8 bytes data. ATM
2321 * I don't know how things are organized if were get next to the
2322 * a boundary so I worry about that once we try to handle that.
2324 evt
->lpos
= (evt
->lpos
+ 4) % DWC3_EVENT_BUFFERS_SIZE
;
2327 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(buf
), 4);
2333 static irqreturn_t
dwc3_interrupt(int irq
, void *_dwc
)
2335 struct dwc3
*dwc
= _dwc
;
2337 irqreturn_t ret
= IRQ_NONE
;
2339 spin_lock(&dwc
->lock
);
2341 for (i
= 0; i
< dwc
->num_event_buffers
; i
++) {
2344 status
= dwc3_process_event_buf(dwc
, i
);
2345 if (status
== IRQ_HANDLED
)
2349 spin_unlock(&dwc
->lock
);
2355 * dwc3_gadget_init - Initializes gadget related registers
2356 * @dwc: pointer to our controller context structure
2358 * Returns 0 on success otherwise negative errno.
2360 int __devinit
dwc3_gadget_init(struct dwc3
*dwc
)
2366 dwc
->ctrl_req
= dma_alloc_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
2367 &dwc
->ctrl_req_addr
, GFP_KERNEL
);
2368 if (!dwc
->ctrl_req
) {
2369 dev_err(dwc
->dev
, "failed to allocate ctrl request\n");
2374 dwc
->ep0_trb
= dma_alloc_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
),
2375 &dwc
->ep0_trb_addr
, GFP_KERNEL
);
2376 if (!dwc
->ep0_trb
) {
2377 dev_err(dwc
->dev
, "failed to allocate ep0 trb\n");
2382 dwc
->setup_buf
= kzalloc(DWC3_EP0_BOUNCE_SIZE
, GFP_KERNEL
);
2383 if (!dwc
->setup_buf
) {
2384 dev_err(dwc
->dev
, "failed to allocate setup buffer\n");
2389 dwc
->ep0_bounce
= dma_alloc_coherent(dwc
->dev
,
2390 DWC3_EP0_BOUNCE_SIZE
, &dwc
->ep0_bounce_addr
,
2392 if (!dwc
->ep0_bounce
) {
2393 dev_err(dwc
->dev
, "failed to allocate ep0 bounce buffer\n");
2398 dev_set_name(&dwc
->gadget
.dev
, "gadget");
2400 dwc
->gadget
.ops
= &dwc3_gadget_ops
;
2401 dwc
->gadget
.max_speed
= USB_SPEED_SUPER
;
2402 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2403 dwc
->gadget
.dev
.parent
= dwc
->dev
;
2404 dwc
->gadget
.sg_supported
= true;
2406 dma_set_coherent_mask(&dwc
->gadget
.dev
, dwc
->dev
->coherent_dma_mask
);
2408 dwc
->gadget
.dev
.dma_parms
= dwc
->dev
->dma_parms
;
2409 dwc
->gadget
.dev
.dma_mask
= dwc
->dev
->dma_mask
;
2410 dwc
->gadget
.dev
.release
= dwc3_gadget_release
;
2411 dwc
->gadget
.name
= "dwc3-gadget";
2414 * REVISIT: Here we should clear all pending IRQs to be
2415 * sure we're starting from a well known location.
2418 ret
= dwc3_gadget_init_endpoints(dwc
);
2422 irq
= platform_get_irq(to_platform_device(dwc
->dev
), 0);
2424 ret
= request_irq(irq
, dwc3_interrupt
, IRQF_SHARED
,
2427 dev_err(dwc
->dev
, "failed to request irq #%d --> %d\n",
2432 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2433 reg
|= DWC3_DCFG_LPM_CAP
;
2434 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2436 /* Enable all but Start and End of Frame IRQs */
2437 reg
= (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN
|
2438 DWC3_DEVTEN_EVNTOVERFLOWEN
|
2439 DWC3_DEVTEN_CMDCMPLTEN
|
2440 DWC3_DEVTEN_ERRTICERREN
|
2441 DWC3_DEVTEN_WKUPEVTEN
|
2442 DWC3_DEVTEN_ULSTCNGEN
|
2443 DWC3_DEVTEN_CONNECTDONEEN
|
2444 DWC3_DEVTEN_USBRSTEN
|
2445 DWC3_DEVTEN_DISCONNEVTEN
);
2446 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, reg
);
2448 /* Enable USB2 LPM and automatic phy suspend only on recent versions */
2449 if (dwc
->revision
>= DWC3_REVISION_194A
) {
2450 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2451 reg
|= DWC3_DCFG_LPM_CAP
;
2452 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2454 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2455 reg
&= ~(DWC3_DCTL_HIRD_THRES_MASK
| DWC3_DCTL_L1_HIBER_EN
);
2457 /* TODO: This should be configurable */
2458 reg
|= DWC3_DCTL_HIRD_THRES(28);
2460 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2462 dwc3_gadget_usb2_phy_suspend(dwc
, false);
2463 dwc3_gadget_usb3_phy_suspend(dwc
, false);
2466 ret
= device_register(&dwc
->gadget
.dev
);
2468 dev_err(dwc
->dev
, "failed to register gadget device\n");
2469 put_device(&dwc
->gadget
.dev
);
2473 ret
= usb_add_gadget_udc(dwc
->dev
, &dwc
->gadget
);
2475 dev_err(dwc
->dev
, "failed to register udc\n");
2482 device_unregister(&dwc
->gadget
.dev
);
2485 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, 0x00);
2489 dwc3_gadget_free_endpoints(dwc
);
2492 dma_free_coherent(dwc
->dev
, DWC3_EP0_BOUNCE_SIZE
,
2493 dwc
->ep0_bounce
, dwc
->ep0_bounce_addr
);
2496 kfree(dwc
->setup_buf
);
2499 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
),
2500 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
2503 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
2504 dwc
->ctrl_req
, dwc
->ctrl_req_addr
);
2510 void dwc3_gadget_exit(struct dwc3
*dwc
)
2514 usb_del_gadget_udc(&dwc
->gadget
);
2515 irq
= platform_get_irq(to_platform_device(dwc
->dev
), 0);
2517 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, 0x00);
2520 dwc3_gadget_free_endpoints(dwc
);
2522 dma_free_coherent(dwc
->dev
, DWC3_EP0_BOUNCE_SIZE
,
2523 dwc
->ep0_bounce
, dwc
->ep0_bounce_addr
);
2525 kfree(dwc
->setup_buf
);
2527 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
),
2528 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
2530 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
2531 dwc
->ctrl_req
, dwc
->ctrl_req_addr
);
2533 device_unregister(&dwc
->gadget
.dev
);