2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/interrupt.h>
27 #include <linux/list.h>
28 #include <linux/dma-mapping.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
47 int dwc3_gadget_set_test_mode(struct dwc3
*dwc
, int mode
)
51 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
52 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
66 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
78 int dwc3_gadget_get_link_state(struct dwc3
*dwc
)
82 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
84 return DWC3_DSTS_USBLNKST(reg
);
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
92 * Caller should take care of locking. This function will
93 * return 0 on success or -ETIMEDOUT.
95 int dwc3_gadget_set_link_state(struct dwc3
*dwc
, enum dwc3_link_state state
)
101 * Wait until device controller is ready. Only applies to 1.94a and
104 if (dwc
->revision
>= DWC3_REVISION_194A
) {
106 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
107 if (reg
& DWC3_DSTS_DCNRD
)
117 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
118 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
120 /* set requested state */
121 reg
|= DWC3_DCTL_ULSTCHNGREQ(state
);
122 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
128 if (dwc
->revision
>= DWC3_REVISION_194A
)
131 /* wait for a change in DSTS */
134 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
136 if (DWC3_DSTS_USBLNKST(reg
) == state
)
142 dev_vdbg(dwc
->dev
, "link state change request timed out\n");
148 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
149 * @dwc: pointer to our context structure
151 * This function will a best effort FIFO allocation in order
152 * to improve FIFO usage and throughput, while still allowing
153 * us to enable as many endpoints as possible.
155 * Keep in mind that this operation will be highly dependent
156 * on the configured size for RAM1 - which contains TxFifo -,
157 * the amount of endpoints enabled on coreConsultant tool, and
158 * the width of the Master Bus.
160 * In the ideal world, we would always be able to satisfy the
161 * following equation:
163 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
164 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
166 * Unfortunately, due to many variables that's not always the case.
168 int dwc3_gadget_resize_tx_fifos(struct dwc3
*dwc
)
170 int last_fifo_depth
= 0;
176 if (!dwc
->needs_fifo_resize
)
179 ram1_depth
= DWC3_RAM1_DEPTH(dwc
->hwparams
.hwparams7
);
180 mdwidth
= DWC3_MDWIDTH(dwc
->hwparams
.hwparams0
);
182 /* MDWIDTH is represented in bits, we need it in bytes */
186 * FIXME For now we will only allocate 1 wMaxPacketSize space
187 * for each enabled endpoint, later patches will come to
188 * improve this algorithm so that we better use the internal
191 for (num
= 0; num
< dwc
->num_in_eps
; num
++) {
192 /* bit0 indicates direction; 1 means IN ep */
193 struct dwc3_ep
*dep
= dwc
->eps
[(num
<< 1) | 1];
197 if (!(dep
->flags
& DWC3_EP_ENABLED
))
200 if (usb_endpoint_xfer_bulk(dep
->endpoint
.desc
)
201 || usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
205 * REVISIT: the following assumes we will always have enough
206 * space available on the FIFO RAM for all possible use cases.
207 * Make sure that's true somehow and change FIFO allocation
210 * If we have Bulk or Isochronous endpoints, we want
211 * them to be able to be very, very fast. So we're giving
212 * those endpoints a fifo_size which is enough for 3 full
215 tmp
= mult
* (dep
->endpoint
.maxpacket
+ mdwidth
);
218 fifo_size
= DIV_ROUND_UP(tmp
, mdwidth
);
220 fifo_size
|= (last_fifo_depth
<< 16);
222 dev_vdbg(dwc
->dev
, "%s: Fifo Addr %04x Size %d\n",
223 dep
->name
, last_fifo_depth
, fifo_size
& 0xffff);
225 dwc3_writel(dwc
->regs
, DWC3_GTXFIFOSIZ(num
), fifo_size
);
227 last_fifo_depth
+= (fifo_size
& 0xffff);
233 void dwc3_gadget_giveback(struct dwc3_ep
*dep
, struct dwc3_request
*req
,
236 struct dwc3
*dwc
= dep
->dwc
;
244 * Skip LINK TRB. We can't use req->trb and check for
245 * DWC3_TRBCTL_LINK_TRB because it points the TRB we
246 * just completed (not the LINK TRB).
248 if (((dep
->busy_slot
& DWC3_TRB_MASK
) ==
250 usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
252 } while(++i
< req
->request
.num_mapped_sgs
);
255 list_del(&req
->list
);
258 if (req
->request
.status
== -EINPROGRESS
)
259 req
->request
.status
= status
;
261 if (dwc
->ep0_bounced
&& dep
->number
== 0)
262 dwc
->ep0_bounced
= false;
264 usb_gadget_unmap_request(&dwc
->gadget
, &req
->request
,
267 dev_dbg(dwc
->dev
, "request %p from %s completed %d/%d ===> %d\n",
268 req
, dep
->name
, req
->request
.actual
,
269 req
->request
.length
, status
);
270 trace_dwc3_gadget_giveback(req
);
272 spin_unlock(&dwc
->lock
);
273 usb_gadget_giveback_request(&dep
->endpoint
, &req
->request
);
274 spin_lock(&dwc
->lock
);
277 int dwc3_send_gadget_generic_command(struct dwc3
*dwc
, unsigned cmd
, u32 param
)
282 trace_dwc3_gadget_generic_cmd(cmd
, param
);
284 dwc3_writel(dwc
->regs
, DWC3_DGCMDPAR
, param
);
285 dwc3_writel(dwc
->regs
, DWC3_DGCMD
, cmd
| DWC3_DGCMD_CMDACT
);
288 reg
= dwc3_readl(dwc
->regs
, DWC3_DGCMD
);
289 if (!(reg
& DWC3_DGCMD_CMDACT
)) {
290 dev_vdbg(dwc
->dev
, "Command Complete --> %d\n",
291 DWC3_DGCMD_STATUS(reg
));
296 * We can't sleep here, because it's also called from
306 int dwc3_send_gadget_ep_cmd(struct dwc3
*dwc
, unsigned ep
,
307 unsigned cmd
, struct dwc3_gadget_ep_cmd_params
*params
)
309 struct dwc3_ep
*dep
= dwc
->eps
[ep
];
313 trace_dwc3_gadget_ep_cmd(dep
, cmd
, params
);
315 dwc3_writel(dwc
->regs
, DWC3_DEPCMDPAR0(ep
), params
->param0
);
316 dwc3_writel(dwc
->regs
, DWC3_DEPCMDPAR1(ep
), params
->param1
);
317 dwc3_writel(dwc
->regs
, DWC3_DEPCMDPAR2(ep
), params
->param2
);
319 dwc3_writel(dwc
->regs
, DWC3_DEPCMD(ep
), cmd
| DWC3_DEPCMD_CMDACT
);
321 reg
= dwc3_readl(dwc
->regs
, DWC3_DEPCMD(ep
));
322 if (!(reg
& DWC3_DEPCMD_CMDACT
)) {
323 dev_vdbg(dwc
->dev
, "Command Complete --> %d\n",
324 DWC3_DEPCMD_STATUS(reg
));
329 * We can't sleep here, because it is also called from
340 static dma_addr_t
dwc3_trb_dma_offset(struct dwc3_ep
*dep
,
341 struct dwc3_trb
*trb
)
343 u32 offset
= (char *) trb
- (char *) dep
->trb_pool
;
345 return dep
->trb_pool_dma
+ offset
;
348 static int dwc3_alloc_trb_pool(struct dwc3_ep
*dep
)
350 struct dwc3
*dwc
= dep
->dwc
;
355 if (dep
->number
== 0 || dep
->number
== 1)
358 dep
->trb_pool
= dma_alloc_coherent(dwc
->dev
,
359 sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
360 &dep
->trb_pool_dma
, GFP_KERNEL
);
361 if (!dep
->trb_pool
) {
362 dev_err(dep
->dwc
->dev
, "failed to allocate trb pool for %s\n",
370 static void dwc3_free_trb_pool(struct dwc3_ep
*dep
)
372 struct dwc3
*dwc
= dep
->dwc
;
374 dma_free_coherent(dwc
->dev
, sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
375 dep
->trb_pool
, dep
->trb_pool_dma
);
377 dep
->trb_pool
= NULL
;
378 dep
->trb_pool_dma
= 0;
381 static int dwc3_gadget_start_config(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
383 struct dwc3_gadget_ep_cmd_params params
;
386 memset(¶ms
, 0x00, sizeof(params
));
388 if (dep
->number
!= 1) {
389 cmd
= DWC3_DEPCMD_DEPSTARTCFG
;
390 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
391 if (dep
->number
> 1) {
392 if (dwc
->start_config_issued
)
394 dwc
->start_config_issued
= true;
395 cmd
|= DWC3_DEPCMD_PARAM(2);
398 return dwc3_send_gadget_ep_cmd(dwc
, 0, cmd
, ¶ms
);
404 static int dwc3_gadget_set_ep_config(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
405 const struct usb_endpoint_descriptor
*desc
,
406 const struct usb_ss_ep_comp_descriptor
*comp_desc
,
407 bool ignore
, bool restore
)
409 struct dwc3_gadget_ep_cmd_params params
;
411 memset(¶ms
, 0x00, sizeof(params
));
413 params
.param0
= DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc
))
414 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc
));
416 /* Burst size is only needed in SuperSpeed mode */
417 if (dwc
->gadget
.speed
== USB_SPEED_SUPER
) {
418 u32 burst
= dep
->endpoint
.maxburst
- 1;
420 params
.param0
|= DWC3_DEPCFG_BURST_SIZE(burst
);
424 params
.param0
|= DWC3_DEPCFG_IGN_SEQ_NUM
;
427 params
.param0
|= DWC3_DEPCFG_ACTION_RESTORE
;
428 params
.param2
|= dep
->saved_state
;
431 params
.param1
= DWC3_DEPCFG_XFER_COMPLETE_EN
432 | DWC3_DEPCFG_XFER_NOT_READY_EN
;
434 if (usb_ss_max_streams(comp_desc
) && usb_endpoint_xfer_bulk(desc
)) {
435 params
.param1
|= DWC3_DEPCFG_STREAM_CAPABLE
436 | DWC3_DEPCFG_STREAM_EVENT_EN
;
437 dep
->stream_capable
= true;
440 if (!usb_endpoint_xfer_control(desc
))
441 params
.param1
|= DWC3_DEPCFG_XFER_IN_PROGRESS_EN
;
444 * We are doing 1:1 mapping for endpoints, meaning
445 * Physical Endpoints 2 maps to Logical Endpoint 2 and
446 * so on. We consider the direction bit as part of the physical
447 * endpoint number. So USB endpoint 0x81 is 0x03.
449 params
.param1
|= DWC3_DEPCFG_EP_NUMBER(dep
->number
);
452 * We must use the lower 16 TX FIFOs even though
456 params
.param0
|= DWC3_DEPCFG_FIFO_NUMBER(dep
->number
>> 1);
458 if (desc
->bInterval
) {
459 params
.param1
|= DWC3_DEPCFG_BINTERVAL_M1(desc
->bInterval
- 1);
460 dep
->interval
= 1 << (desc
->bInterval
- 1);
463 return dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
464 DWC3_DEPCMD_SETEPCONFIG
, ¶ms
);
467 static int dwc3_gadget_set_xfer_resource(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
469 struct dwc3_gadget_ep_cmd_params params
;
471 memset(¶ms
, 0x00, sizeof(params
));
473 params
.param0
= DWC3_DEPXFERCFG_NUM_XFER_RES(1);
475 return dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
476 DWC3_DEPCMD_SETTRANSFRESOURCE
, ¶ms
);
480 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
481 * @dep: endpoint to be initialized
482 * @desc: USB Endpoint Descriptor
484 * Caller should take care of locking
486 static int __dwc3_gadget_ep_enable(struct dwc3_ep
*dep
,
487 const struct usb_endpoint_descriptor
*desc
,
488 const struct usb_ss_ep_comp_descriptor
*comp_desc
,
489 bool ignore
, bool restore
)
491 struct dwc3
*dwc
= dep
->dwc
;
495 dev_vdbg(dwc
->dev
, "Enabling %s\n", dep
->name
);
497 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
498 ret
= dwc3_gadget_start_config(dwc
, dep
);
503 ret
= dwc3_gadget_set_ep_config(dwc
, dep
, desc
, comp_desc
, ignore
,
508 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
509 struct dwc3_trb
*trb_st_hw
;
510 struct dwc3_trb
*trb_link
;
512 ret
= dwc3_gadget_set_xfer_resource(dwc
, dep
);
516 dep
->endpoint
.desc
= desc
;
517 dep
->comp_desc
= comp_desc
;
518 dep
->type
= usb_endpoint_type(desc
);
519 dep
->flags
|= DWC3_EP_ENABLED
;
521 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
522 reg
|= DWC3_DALEPENA_EP(dep
->number
);
523 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
525 if (!usb_endpoint_xfer_isoc(desc
))
528 /* Link TRB for ISOC. The HWO bit is never reset */
529 trb_st_hw
= &dep
->trb_pool
[0];
531 trb_link
= &dep
->trb_pool
[DWC3_TRB_NUM
- 1];
532 memset(trb_link
, 0, sizeof(*trb_link
));
534 trb_link
->bpl
= lower_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
535 trb_link
->bph
= upper_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
536 trb_link
->ctrl
|= DWC3_TRBCTL_LINK_TRB
;
537 trb_link
->ctrl
|= DWC3_TRB_CTRL_HWO
;
543 static void dwc3_stop_active_transfer(struct dwc3
*dwc
, u32 epnum
, bool force
);
544 static void dwc3_remove_requests(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
546 struct dwc3_request
*req
;
548 if (!list_empty(&dep
->req_queued
)) {
549 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
551 /* - giveback all requests to gadget driver */
552 while (!list_empty(&dep
->req_queued
)) {
553 req
= next_request(&dep
->req_queued
);
555 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
559 while (!list_empty(&dep
->request_list
)) {
560 req
= next_request(&dep
->request_list
);
562 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
567 * __dwc3_gadget_ep_disable - Disables a HW endpoint
568 * @dep: the endpoint to disable
570 * This function also removes requests which are currently processed ny the
571 * hardware and those which are not yet scheduled.
572 * Caller should take care of locking.
574 static int __dwc3_gadget_ep_disable(struct dwc3_ep
*dep
)
576 struct dwc3
*dwc
= dep
->dwc
;
579 dwc3_remove_requests(dwc
, dep
);
581 /* make sure HW endpoint isn't stalled */
582 if (dep
->flags
& DWC3_EP_STALL
)
583 __dwc3_gadget_ep_set_halt(dep
, 0, false);
585 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
586 reg
&= ~DWC3_DALEPENA_EP(dep
->number
);
587 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
589 dep
->stream_capable
= false;
590 dep
->endpoint
.desc
= NULL
;
591 dep
->comp_desc
= NULL
;
598 /* -------------------------------------------------------------------------- */
600 static int dwc3_gadget_ep0_enable(struct usb_ep
*ep
,
601 const struct usb_endpoint_descriptor
*desc
)
606 static int dwc3_gadget_ep0_disable(struct usb_ep
*ep
)
611 /* -------------------------------------------------------------------------- */
613 static int dwc3_gadget_ep_enable(struct usb_ep
*ep
,
614 const struct usb_endpoint_descriptor
*desc
)
621 if (!ep
|| !desc
|| desc
->bDescriptorType
!= USB_DT_ENDPOINT
) {
622 pr_debug("dwc3: invalid parameters\n");
626 if (!desc
->wMaxPacketSize
) {
627 pr_debug("dwc3: missing wMaxPacketSize\n");
631 dep
= to_dwc3_ep(ep
);
634 if (dep
->flags
& DWC3_EP_ENABLED
) {
635 dev_WARN_ONCE(dwc
->dev
, true, "%s is already enabled\n",
640 switch (usb_endpoint_type(desc
)) {
641 case USB_ENDPOINT_XFER_CONTROL
:
642 strlcat(dep
->name
, "-control", sizeof(dep
->name
));
644 case USB_ENDPOINT_XFER_ISOC
:
645 strlcat(dep
->name
, "-isoc", sizeof(dep
->name
));
647 case USB_ENDPOINT_XFER_BULK
:
648 strlcat(dep
->name
, "-bulk", sizeof(dep
->name
));
650 case USB_ENDPOINT_XFER_INT
:
651 strlcat(dep
->name
, "-int", sizeof(dep
->name
));
654 dev_err(dwc
->dev
, "invalid endpoint transfer type\n");
657 spin_lock_irqsave(&dwc
->lock
, flags
);
658 ret
= __dwc3_gadget_ep_enable(dep
, desc
, ep
->comp_desc
, false, false);
659 spin_unlock_irqrestore(&dwc
->lock
, flags
);
664 static int dwc3_gadget_ep_disable(struct usb_ep
*ep
)
672 pr_debug("dwc3: invalid parameters\n");
676 dep
= to_dwc3_ep(ep
);
679 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
680 dev_WARN_ONCE(dwc
->dev
, true, "%s is already disabled\n",
685 snprintf(dep
->name
, sizeof(dep
->name
), "ep%d%s",
687 (dep
->number
& 1) ? "in" : "out");
689 spin_lock_irqsave(&dwc
->lock
, flags
);
690 ret
= __dwc3_gadget_ep_disable(dep
);
691 spin_unlock_irqrestore(&dwc
->lock
, flags
);
696 static struct usb_request
*dwc3_gadget_ep_alloc_request(struct usb_ep
*ep
,
699 struct dwc3_request
*req
;
700 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
702 req
= kzalloc(sizeof(*req
), gfp_flags
);
706 req
->epnum
= dep
->number
;
709 trace_dwc3_alloc_request(req
);
711 return &req
->request
;
714 static void dwc3_gadget_ep_free_request(struct usb_ep
*ep
,
715 struct usb_request
*request
)
717 struct dwc3_request
*req
= to_dwc3_request(request
);
719 trace_dwc3_free_request(req
);
724 * dwc3_prepare_one_trb - setup one TRB from one request
725 * @dep: endpoint for which this request is prepared
726 * @req: dwc3_request pointer
728 static void dwc3_prepare_one_trb(struct dwc3_ep
*dep
,
729 struct dwc3_request
*req
, dma_addr_t dma
,
730 unsigned length
, unsigned last
, unsigned chain
, unsigned node
)
732 struct dwc3
*dwc
= dep
->dwc
;
733 struct dwc3_trb
*trb
;
735 dev_vdbg(dwc
->dev
, "%s: req %p dma %08llx length %d%s%s\n",
736 dep
->name
, req
, (unsigned long long) dma
,
737 length
, last
? " last" : "",
738 chain
? " chain" : "");
741 trb
= &dep
->trb_pool
[dep
->free_slot
& DWC3_TRB_MASK
];
744 dwc3_gadget_move_request_queued(req
);
746 req
->trb_dma
= dwc3_trb_dma_offset(dep
, trb
);
747 req
->start_slot
= dep
->free_slot
& DWC3_TRB_MASK
;
751 /* Skip the LINK-TRB on ISOC */
752 if (((dep
->free_slot
& DWC3_TRB_MASK
) == DWC3_TRB_NUM
- 1) &&
753 usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
756 trb
->size
= DWC3_TRB_SIZE_LENGTH(length
);
757 trb
->bpl
= lower_32_bits(dma
);
758 trb
->bph
= upper_32_bits(dma
);
760 switch (usb_endpoint_type(dep
->endpoint
.desc
)) {
761 case USB_ENDPOINT_XFER_CONTROL
:
762 trb
->ctrl
= DWC3_TRBCTL_CONTROL_SETUP
;
765 case USB_ENDPOINT_XFER_ISOC
:
767 trb
->ctrl
= DWC3_TRBCTL_ISOCHRONOUS_FIRST
;
769 trb
->ctrl
= DWC3_TRBCTL_ISOCHRONOUS
;
772 case USB_ENDPOINT_XFER_BULK
:
773 case USB_ENDPOINT_XFER_INT
:
774 trb
->ctrl
= DWC3_TRBCTL_NORMAL
;
778 * This is only possible with faulty memory because we
779 * checked it already :)
784 if (!req
->request
.no_interrupt
&& !chain
)
785 trb
->ctrl
|= DWC3_TRB_CTRL_IOC
;
787 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
788 trb
->ctrl
|= DWC3_TRB_CTRL_ISP_IMI
;
789 trb
->ctrl
|= DWC3_TRB_CTRL_CSP
;
791 trb
->ctrl
|= DWC3_TRB_CTRL_LST
;
795 trb
->ctrl
|= DWC3_TRB_CTRL_CHN
;
797 if (usb_endpoint_xfer_bulk(dep
->endpoint
.desc
) && dep
->stream_capable
)
798 trb
->ctrl
|= DWC3_TRB_CTRL_SID_SOFN(req
->request
.stream_id
);
800 trb
->ctrl
|= DWC3_TRB_CTRL_HWO
;
802 trace_dwc3_prepare_trb(dep
, trb
);
806 * dwc3_prepare_trbs - setup TRBs from requests
807 * @dep: endpoint for which requests are being prepared
808 * @starting: true if the endpoint is idle and no requests are queued.
810 * The function goes through the requests list and sets up TRBs for the
811 * transfers. The function returns once there are no more TRBs available or
812 * it runs out of requests.
814 static void dwc3_prepare_trbs(struct dwc3_ep
*dep
, bool starting
)
816 struct dwc3_request
*req
, *n
;
819 unsigned int last_one
= 0;
821 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM
);
823 /* the first request must not be queued */
824 trbs_left
= (dep
->busy_slot
- dep
->free_slot
) & DWC3_TRB_MASK
;
826 /* Can't wrap around on a non-isoc EP since there's no link TRB */
827 if (!usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
828 max
= DWC3_TRB_NUM
- (dep
->free_slot
& DWC3_TRB_MASK
);
834 * If busy & slot are equal than it is either full or empty. If we are
835 * starting to process requests then we are empty. Otherwise we are
836 * full and don't do anything
841 trbs_left
= DWC3_TRB_NUM
;
843 * In case we start from scratch, we queue the ISOC requests
844 * starting from slot 1. This is done because we use ring
845 * buffer and have no LST bit to stop us. Instead, we place
846 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
847 * after the first request so we start at slot 1 and have
848 * 7 requests proceed before we hit the first IOC.
849 * Other transfer types don't use the ring buffer and are
850 * processed from the first TRB until the last one. Since we
851 * don't wrap around we have to start at the beginning.
853 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
862 /* The last TRB is a link TRB, not used for xfer */
863 if ((trbs_left
<= 1) && usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
866 list_for_each_entry_safe(req
, n
, &dep
->request_list
, list
) {
871 if (req
->request
.num_mapped_sgs
> 0) {
872 struct usb_request
*request
= &req
->request
;
873 struct scatterlist
*sg
= request
->sg
;
874 struct scatterlist
*s
;
877 for_each_sg(sg
, s
, request
->num_mapped_sgs
, i
) {
878 unsigned chain
= true;
880 length
= sg_dma_len(s
);
881 dma
= sg_dma_address(s
);
883 if (i
== (request
->num_mapped_sgs
- 1) ||
885 if (list_empty(&dep
->request_list
))
897 dwc3_prepare_one_trb(dep
, req
, dma
, length
,
904 dma
= req
->request
.dma
;
905 length
= req
->request
.length
;
911 /* Is this the last request? */
912 if (list_is_last(&req
->list
, &dep
->request_list
))
915 dwc3_prepare_one_trb(dep
, req
, dma
, length
,
924 static int __dwc3_gadget_kick_transfer(struct dwc3_ep
*dep
, u16 cmd_param
,
927 struct dwc3_gadget_ep_cmd_params params
;
928 struct dwc3_request
*req
;
929 struct dwc3
*dwc
= dep
->dwc
;
933 if (start_new
&& (dep
->flags
& DWC3_EP_BUSY
)) {
934 dev_vdbg(dwc
->dev
, "%s: endpoint busy\n", dep
->name
);
937 dep
->flags
&= ~DWC3_EP_PENDING_REQUEST
;
940 * If we are getting here after a short-out-packet we don't enqueue any
941 * new requests as we try to set the IOC bit only on the last request.
944 if (list_empty(&dep
->req_queued
))
945 dwc3_prepare_trbs(dep
, start_new
);
947 /* req points to the first request which will be sent */
948 req
= next_request(&dep
->req_queued
);
950 dwc3_prepare_trbs(dep
, start_new
);
953 * req points to the first request where HWO changed from 0 to 1
955 req
= next_request(&dep
->req_queued
);
958 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
962 memset(¶ms
, 0, sizeof(params
));
965 params
.param0
= upper_32_bits(req
->trb_dma
);
966 params
.param1
= lower_32_bits(req
->trb_dma
);
967 cmd
= DWC3_DEPCMD_STARTTRANSFER
;
969 cmd
= DWC3_DEPCMD_UPDATETRANSFER
;
972 cmd
|= DWC3_DEPCMD_PARAM(cmd_param
);
973 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
, cmd
, ¶ms
);
975 dev_dbg(dwc
->dev
, "failed to send STARTTRANSFER command\n");
978 * FIXME we need to iterate over the list of requests
979 * here and stop, unmap, free and del each of the linked
980 * requests instead of what we do now.
982 usb_gadget_unmap_request(&dwc
->gadget
, &req
->request
,
984 list_del(&req
->list
);
988 dep
->flags
|= DWC3_EP_BUSY
;
991 dep
->resource_index
= dwc3_gadget_ep_get_transfer_index(dwc
,
993 WARN_ON_ONCE(!dep
->resource_index
);
999 static void __dwc3_gadget_start_isoc(struct dwc3
*dwc
,
1000 struct dwc3_ep
*dep
, u32 cur_uf
)
1004 if (list_empty(&dep
->request_list
)) {
1005 dev_vdbg(dwc
->dev
, "ISOC ep %s run out for requests.\n",
1007 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
1011 /* 4 micro frames in the future */
1012 uf
= cur_uf
+ dep
->interval
* 4;
1014 __dwc3_gadget_kick_transfer(dep
, uf
, 1);
1017 static void dwc3_gadget_start_isoc(struct dwc3
*dwc
,
1018 struct dwc3_ep
*dep
, const struct dwc3_event_depevt
*event
)
1022 mask
= ~(dep
->interval
- 1);
1023 cur_uf
= event
->parameters
& mask
;
1025 __dwc3_gadget_start_isoc(dwc
, dep
, cur_uf
);
1028 static int __dwc3_gadget_ep_queue(struct dwc3_ep
*dep
, struct dwc3_request
*req
)
1030 struct dwc3
*dwc
= dep
->dwc
;
1033 req
->request
.actual
= 0;
1034 req
->request
.status
= -EINPROGRESS
;
1035 req
->direction
= dep
->direction
;
1036 req
->epnum
= dep
->number
;
1039 * We only add to our list of requests now and
1040 * start consuming the list once we get XferNotReady
1043 * That way, we avoid doing anything that we don't need
1044 * to do now and defer it until the point we receive a
1045 * particular token from the Host side.
1047 * This will also avoid Host cancelling URBs due to too
1050 ret
= usb_gadget_map_request(&dwc
->gadget
, &req
->request
,
1055 list_add_tail(&req
->list
, &dep
->request_list
);
1058 * There are a few special cases:
1060 * 1. XferNotReady with empty list of requests. We need to kick the
1061 * transfer here in that situation, otherwise we will be NAKing
1062 * forever. If we get XferNotReady before gadget driver has a
1063 * chance to queue a request, we will ACK the IRQ but won't be
1064 * able to receive the data until the next request is queued.
1065 * The following code is handling exactly that.
1068 if (dep
->flags
& DWC3_EP_PENDING_REQUEST
) {
1070 * If xfernotready is already elapsed and it is a case
1071 * of isoc transfer, then issue END TRANSFER, so that
1072 * you can receive xfernotready again and can have
1073 * notion of current microframe.
1075 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1076 if (list_empty(&dep
->req_queued
)) {
1077 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
1078 dep
->flags
= DWC3_EP_ENABLED
;
1083 ret
= __dwc3_gadget_kick_transfer(dep
, 0, true);
1084 if (ret
&& ret
!= -EBUSY
)
1085 dev_dbg(dwc
->dev
, "%s: failed to kick transfers\n",
1091 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1092 * kick the transfer here after queuing a request, otherwise the
1093 * core may not see the modified TRB(s).
1095 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) &&
1096 (dep
->flags
& DWC3_EP_BUSY
) &&
1097 !(dep
->flags
& DWC3_EP_MISSED_ISOC
)) {
1098 WARN_ON_ONCE(!dep
->resource_index
);
1099 ret
= __dwc3_gadget_kick_transfer(dep
, dep
->resource_index
,
1101 if (ret
&& ret
!= -EBUSY
)
1102 dev_dbg(dwc
->dev
, "%s: failed to kick transfers\n",
1108 * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1109 * right away, otherwise host will not know we have streams to be
1112 if (dep
->stream_capable
) {
1115 ret
= __dwc3_gadget_kick_transfer(dep
, 0, true);
1116 if (ret
&& ret
!= -EBUSY
) {
1117 struct dwc3
*dwc
= dep
->dwc
;
1119 dev_dbg(dwc
->dev
, "%s: failed to kick transfers\n",
1127 static int dwc3_gadget_ep_queue(struct usb_ep
*ep
, struct usb_request
*request
,
1130 struct dwc3_request
*req
= to_dwc3_request(request
);
1131 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1132 struct dwc3
*dwc
= dep
->dwc
;
1134 unsigned long flags
;
1138 spin_lock_irqsave(&dwc
->lock
, flags
);
1139 if (!dep
->endpoint
.desc
) {
1140 dev_dbg(dwc
->dev
, "trying to queue request %p to disabled %s\n",
1146 if (WARN(req
->dep
!= dep
, "request %p belongs to '%s'\n",
1147 request
, req
->dep
->name
)) {
1152 dev_vdbg(dwc
->dev
, "queing request %p to %s length %d\n",
1153 request
, ep
->name
, request
->length
);
1154 trace_dwc3_ep_queue(req
);
1156 ret
= __dwc3_gadget_ep_queue(dep
, req
);
1159 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1164 static int dwc3_gadget_ep_dequeue(struct usb_ep
*ep
,
1165 struct usb_request
*request
)
1167 struct dwc3_request
*req
= to_dwc3_request(request
);
1168 struct dwc3_request
*r
= NULL
;
1170 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1171 struct dwc3
*dwc
= dep
->dwc
;
1173 unsigned long flags
;
1176 trace_dwc3_ep_dequeue(req
);
1178 spin_lock_irqsave(&dwc
->lock
, flags
);
1180 list_for_each_entry(r
, &dep
->request_list
, list
) {
1186 list_for_each_entry(r
, &dep
->req_queued
, list
) {
1191 /* wait until it is processed */
1192 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
1195 dev_err(dwc
->dev
, "request %p was not queued to %s\n",
1202 /* giveback the request */
1203 dwc3_gadget_giveback(dep
, req
, -ECONNRESET
);
1206 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1211 int __dwc3_gadget_ep_set_halt(struct dwc3_ep
*dep
, int value
, int protocol
)
1213 struct dwc3_gadget_ep_cmd_params params
;
1214 struct dwc3
*dwc
= dep
->dwc
;
1217 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1218 dev_err(dwc
->dev
, "%s is of Isochronous type\n", dep
->name
);
1222 memset(¶ms
, 0x00, sizeof(params
));
1225 if (!protocol
&& ((dep
->direction
&& dep
->flags
& DWC3_EP_BUSY
) ||
1226 (!list_empty(&dep
->req_queued
) ||
1227 !list_empty(&dep
->request_list
)))) {
1228 dev_dbg(dwc
->dev
, "%s: pending request, cannot halt\n",
1233 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
1234 DWC3_DEPCMD_SETSTALL
, ¶ms
);
1236 dev_err(dwc
->dev
, "failed to set STALL on %s\n",
1239 dep
->flags
|= DWC3_EP_STALL
;
1241 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
1242 DWC3_DEPCMD_CLEARSTALL
, ¶ms
);
1244 dev_err(dwc
->dev
, "failed to clear STALL on %s\n",
1247 dep
->flags
&= ~(DWC3_EP_STALL
| DWC3_EP_WEDGE
);
1253 static int dwc3_gadget_ep_set_halt(struct usb_ep
*ep
, int value
)
1255 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1256 struct dwc3
*dwc
= dep
->dwc
;
1258 unsigned long flags
;
1262 spin_lock_irqsave(&dwc
->lock
, flags
);
1263 ret
= __dwc3_gadget_ep_set_halt(dep
, value
, false);
1264 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1269 static int dwc3_gadget_ep_set_wedge(struct usb_ep
*ep
)
1271 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1272 struct dwc3
*dwc
= dep
->dwc
;
1273 unsigned long flags
;
1276 spin_lock_irqsave(&dwc
->lock
, flags
);
1277 dep
->flags
|= DWC3_EP_WEDGE
;
1279 if (dep
->number
== 0 || dep
->number
== 1)
1280 ret
= __dwc3_gadget_ep0_set_halt(ep
, 1);
1282 ret
= __dwc3_gadget_ep_set_halt(dep
, 1, false);
1283 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1288 /* -------------------------------------------------------------------------- */
1290 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc
= {
1291 .bLength
= USB_DT_ENDPOINT_SIZE
,
1292 .bDescriptorType
= USB_DT_ENDPOINT
,
1293 .bmAttributes
= USB_ENDPOINT_XFER_CONTROL
,
1296 static const struct usb_ep_ops dwc3_gadget_ep0_ops
= {
1297 .enable
= dwc3_gadget_ep0_enable
,
1298 .disable
= dwc3_gadget_ep0_disable
,
1299 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1300 .free_request
= dwc3_gadget_ep_free_request
,
1301 .queue
= dwc3_gadget_ep0_queue
,
1302 .dequeue
= dwc3_gadget_ep_dequeue
,
1303 .set_halt
= dwc3_gadget_ep0_set_halt
,
1304 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1307 static const struct usb_ep_ops dwc3_gadget_ep_ops
= {
1308 .enable
= dwc3_gadget_ep_enable
,
1309 .disable
= dwc3_gadget_ep_disable
,
1310 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1311 .free_request
= dwc3_gadget_ep_free_request
,
1312 .queue
= dwc3_gadget_ep_queue
,
1313 .dequeue
= dwc3_gadget_ep_dequeue
,
1314 .set_halt
= dwc3_gadget_ep_set_halt
,
1315 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1318 /* -------------------------------------------------------------------------- */
1320 static int dwc3_gadget_get_frame(struct usb_gadget
*g
)
1322 struct dwc3
*dwc
= gadget_to_dwc(g
);
1325 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1326 return DWC3_DSTS_SOFFN(reg
);
1329 static int dwc3_gadget_wakeup(struct usb_gadget
*g
)
1331 struct dwc3
*dwc
= gadget_to_dwc(g
);
1333 unsigned long timeout
;
1334 unsigned long flags
;
1343 spin_lock_irqsave(&dwc
->lock
, flags
);
1346 * According to the Databook Remote wakeup request should
1347 * be issued only when the device is in early suspend state.
1349 * We can check that via USB Link State bits in DSTS register.
1351 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1353 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
1354 if (speed
== DWC3_DSTS_SUPERSPEED
) {
1355 dev_dbg(dwc
->dev
, "no wakeup on SuperSpeed\n");
1360 link_state
= DWC3_DSTS_USBLNKST(reg
);
1362 switch (link_state
) {
1363 case DWC3_LINK_STATE_RX_DET
: /* in HS, means Early Suspend */
1364 case DWC3_LINK_STATE_U3
: /* in HS, means SUSPEND */
1367 dev_dbg(dwc
->dev
, "can't wakeup from link state %d\n",
1373 ret
= dwc3_gadget_set_link_state(dwc
, DWC3_LINK_STATE_RECOV
);
1375 dev_err(dwc
->dev
, "failed to put link in Recovery\n");
1379 /* Recent versions do this automatically */
1380 if (dwc
->revision
< DWC3_REVISION_194A
) {
1381 /* write zeroes to Link Change Request */
1382 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1383 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
1384 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1387 /* poll until Link State changes to ON */
1388 timeout
= jiffies
+ msecs_to_jiffies(100);
1390 while (!time_after(jiffies
, timeout
)) {
1391 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1393 /* in HS, means ON */
1394 if (DWC3_DSTS_USBLNKST(reg
) == DWC3_LINK_STATE_U0
)
1398 if (DWC3_DSTS_USBLNKST(reg
) != DWC3_LINK_STATE_U0
) {
1399 dev_err(dwc
->dev
, "failed to send remote wakeup\n");
1404 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1409 static int dwc3_gadget_set_selfpowered(struct usb_gadget
*g
,
1412 struct dwc3
*dwc
= gadget_to_dwc(g
);
1413 unsigned long flags
;
1415 spin_lock_irqsave(&dwc
->lock
, flags
);
1416 dwc
->is_selfpowered
= !!is_selfpowered
;
1417 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1422 static int dwc3_gadget_run_stop(struct dwc3
*dwc
, int is_on
, int suspend
)
1427 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1429 if (dwc
->revision
<= DWC3_REVISION_187A
) {
1430 reg
&= ~DWC3_DCTL_TRGTULST_MASK
;
1431 reg
|= DWC3_DCTL_TRGTULST_RX_DET
;
1434 if (dwc
->revision
>= DWC3_REVISION_194A
)
1435 reg
&= ~DWC3_DCTL_KEEP_CONNECT
;
1436 reg
|= DWC3_DCTL_RUN_STOP
;
1438 if (dwc
->has_hibernation
)
1439 reg
|= DWC3_DCTL_KEEP_CONNECT
;
1441 dwc
->pullups_connected
= true;
1443 reg
&= ~DWC3_DCTL_RUN_STOP
;
1445 if (dwc
->has_hibernation
&& !suspend
)
1446 reg
&= ~DWC3_DCTL_KEEP_CONNECT
;
1448 dwc
->pullups_connected
= false;
1451 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1454 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1456 if (!(reg
& DWC3_DSTS_DEVCTRLHLT
))
1459 if (reg
& DWC3_DSTS_DEVCTRLHLT
)
1468 dev_vdbg(dwc
->dev
, "gadget %s data soft-%s\n",
1470 ? dwc
->gadget_driver
->function
: "no-function",
1471 is_on
? "connect" : "disconnect");
1476 static int dwc3_gadget_pullup(struct usb_gadget
*g
, int is_on
)
1478 struct dwc3
*dwc
= gadget_to_dwc(g
);
1479 unsigned long flags
;
1484 spin_lock_irqsave(&dwc
->lock
, flags
);
1485 ret
= dwc3_gadget_run_stop(dwc
, is_on
, false);
1486 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1491 static void dwc3_gadget_enable_irq(struct dwc3
*dwc
)
1495 /* Enable all but Start and End of Frame IRQs */
1496 reg
= (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN
|
1497 DWC3_DEVTEN_EVNTOVERFLOWEN
|
1498 DWC3_DEVTEN_CMDCMPLTEN
|
1499 DWC3_DEVTEN_ERRTICERREN
|
1500 DWC3_DEVTEN_WKUPEVTEN
|
1501 DWC3_DEVTEN_ULSTCNGEN
|
1502 DWC3_DEVTEN_CONNECTDONEEN
|
1503 DWC3_DEVTEN_USBRSTEN
|
1504 DWC3_DEVTEN_DISCONNEVTEN
);
1506 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, reg
);
1509 static void dwc3_gadget_disable_irq(struct dwc3
*dwc
)
1511 /* mask all interrupts */
1512 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, 0x00);
1515 static irqreturn_t
dwc3_interrupt(int irq
, void *_dwc
);
1516 static irqreturn_t
dwc3_thread_interrupt(int irq
, void *_dwc
);
1518 static int dwc3_gadget_start(struct usb_gadget
*g
,
1519 struct usb_gadget_driver
*driver
)
1521 struct dwc3
*dwc
= gadget_to_dwc(g
);
1522 struct dwc3_ep
*dep
;
1523 unsigned long flags
;
1528 irq
= platform_get_irq(to_platform_device(dwc
->dev
), 0);
1529 ret
= request_threaded_irq(irq
, dwc3_interrupt
, dwc3_thread_interrupt
,
1530 IRQF_SHARED
, "dwc3", dwc
);
1532 dev_err(dwc
->dev
, "failed to request irq #%d --> %d\n",
1537 spin_lock_irqsave(&dwc
->lock
, flags
);
1539 if (dwc
->gadget_driver
) {
1540 dev_err(dwc
->dev
, "%s is already bound to %s\n",
1542 dwc
->gadget_driver
->driver
.name
);
1547 dwc
->gadget_driver
= driver
;
1549 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
1550 reg
&= ~(DWC3_DCFG_SPEED_MASK
);
1553 * WORKAROUND: DWC3 revision < 2.20a have an issue
1554 * which would cause metastability state on Run/Stop
1555 * bit if we try to force the IP to USB2-only mode.
1557 * Because of that, we cannot configure the IP to any
1558 * speed other than the SuperSpeed
1562 * STAR#9000525659: Clock Domain Crossing on DCTL in
1565 if (dwc
->revision
< DWC3_REVISION_220A
) {
1566 reg
|= DWC3_DCFG_SUPERSPEED
;
1568 switch (dwc
->maximum_speed
) {
1570 reg
|= DWC3_DSTS_LOWSPEED
;
1572 case USB_SPEED_FULL
:
1573 reg
|= DWC3_DSTS_FULLSPEED1
;
1575 case USB_SPEED_HIGH
:
1576 reg
|= DWC3_DSTS_HIGHSPEED
;
1578 case USB_SPEED_SUPER
: /* FALLTHROUGH */
1579 case USB_SPEED_UNKNOWN
: /* FALTHROUGH */
1581 reg
|= DWC3_DSTS_SUPERSPEED
;
1584 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
1586 dwc
->start_config_issued
= false;
1588 /* Start with SuperSpeed Default */
1589 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
1592 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, false,
1595 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1600 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, false,
1603 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1607 /* begin to receive SETUP packets */
1608 dwc
->ep0state
= EP0_SETUP_PHASE
;
1609 dwc3_ep0_out_start(dwc
);
1611 dwc3_gadget_enable_irq(dwc
);
1613 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1618 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
1621 dwc
->gadget_driver
= NULL
;
1624 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1632 static int dwc3_gadget_stop(struct usb_gadget
*g
)
1634 struct dwc3
*dwc
= gadget_to_dwc(g
);
1635 unsigned long flags
;
1638 spin_lock_irqsave(&dwc
->lock
, flags
);
1640 dwc3_gadget_disable_irq(dwc
);
1641 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
1642 __dwc3_gadget_ep_disable(dwc
->eps
[1]);
1644 dwc
->gadget_driver
= NULL
;
1646 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1648 irq
= platform_get_irq(to_platform_device(dwc
->dev
), 0);
1654 static const struct usb_gadget_ops dwc3_gadget_ops
= {
1655 .get_frame
= dwc3_gadget_get_frame
,
1656 .wakeup
= dwc3_gadget_wakeup
,
1657 .set_selfpowered
= dwc3_gadget_set_selfpowered
,
1658 .pullup
= dwc3_gadget_pullup
,
1659 .udc_start
= dwc3_gadget_start
,
1660 .udc_stop
= dwc3_gadget_stop
,
1663 /* -------------------------------------------------------------------------- */
1665 static int dwc3_gadget_init_hw_endpoints(struct dwc3
*dwc
,
1666 u8 num
, u32 direction
)
1668 struct dwc3_ep
*dep
;
1671 for (i
= 0; i
< num
; i
++) {
1672 u8 epnum
= (i
<< 1) | (!!direction
);
1674 dep
= kzalloc(sizeof(*dep
), GFP_KERNEL
);
1679 dep
->number
= epnum
;
1680 dep
->direction
= !!direction
;
1681 dwc
->eps
[epnum
] = dep
;
1683 snprintf(dep
->name
, sizeof(dep
->name
), "ep%d%s", epnum
>> 1,
1684 (epnum
& 1) ? "in" : "out");
1686 dep
->endpoint
.name
= dep
->name
;
1688 dev_vdbg(dwc
->dev
, "initializing %s\n", dep
->name
);
1690 if (epnum
== 0 || epnum
== 1) {
1691 usb_ep_set_maxpacket_limit(&dep
->endpoint
, 512);
1692 dep
->endpoint
.maxburst
= 1;
1693 dep
->endpoint
.ops
= &dwc3_gadget_ep0_ops
;
1695 dwc
->gadget
.ep0
= &dep
->endpoint
;
1699 usb_ep_set_maxpacket_limit(&dep
->endpoint
, 1024);
1700 dep
->endpoint
.max_streams
= 15;
1701 dep
->endpoint
.ops
= &dwc3_gadget_ep_ops
;
1702 list_add_tail(&dep
->endpoint
.ep_list
,
1703 &dwc
->gadget
.ep_list
);
1705 ret
= dwc3_alloc_trb_pool(dep
);
1710 INIT_LIST_HEAD(&dep
->request_list
);
1711 INIT_LIST_HEAD(&dep
->req_queued
);
1717 static int dwc3_gadget_init_endpoints(struct dwc3
*dwc
)
1721 INIT_LIST_HEAD(&dwc
->gadget
.ep_list
);
1723 ret
= dwc3_gadget_init_hw_endpoints(dwc
, dwc
->num_out_eps
, 0);
1725 dev_vdbg(dwc
->dev
, "failed to allocate OUT endpoints\n");
1729 ret
= dwc3_gadget_init_hw_endpoints(dwc
, dwc
->num_in_eps
, 1);
1731 dev_vdbg(dwc
->dev
, "failed to allocate IN endpoints\n");
1738 static void dwc3_gadget_free_endpoints(struct dwc3
*dwc
)
1740 struct dwc3_ep
*dep
;
1743 for (epnum
= 0; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
1744 dep
= dwc
->eps
[epnum
];
1748 * Physical endpoints 0 and 1 are special; they form the
1749 * bi-directional USB endpoint 0.
1751 * For those two physical endpoints, we don't allocate a TRB
1752 * pool nor do we add them the endpoints list. Due to that, we
1753 * shouldn't do these two operations otherwise we would end up
1754 * with all sorts of bugs when removing dwc3.ko.
1756 if (epnum
!= 0 && epnum
!= 1) {
1757 dwc3_free_trb_pool(dep
);
1758 list_del(&dep
->endpoint
.ep_list
);
1765 /* -------------------------------------------------------------------------- */
1767 static int __dwc3_cleanup_done_trbs(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
1768 struct dwc3_request
*req
, struct dwc3_trb
*trb
,
1769 const struct dwc3_event_depevt
*event
, int status
)
1772 unsigned int s_pkt
= 0;
1773 unsigned int trb_status
;
1775 trace_dwc3_complete_trb(dep
, trb
);
1777 if ((trb
->ctrl
& DWC3_TRB_CTRL_HWO
) && status
!= -ESHUTDOWN
)
1779 * We continue despite the error. There is not much we
1780 * can do. If we don't clean it up we loop forever. If
1781 * we skip the TRB then it gets overwritten after a
1782 * while since we use them in a ring buffer. A BUG()
1783 * would help. Lets hope that if this occurs, someone
1784 * fixes the root cause instead of looking away :)
1786 dev_err(dwc
->dev
, "%s's TRB (%p) still owned by HW\n",
1788 count
= trb
->size
& DWC3_TRB_SIZE_MASK
;
1790 if (dep
->direction
) {
1792 trb_status
= DWC3_TRB_SIZE_TRBSTS(trb
->size
);
1793 if (trb_status
== DWC3_TRBSTS_MISSED_ISOC
) {
1794 dev_dbg(dwc
->dev
, "incomplete IN transfer %s\n",
1797 * If missed isoc occurred and there is
1798 * no request queued then issue END
1799 * TRANSFER, so that core generates
1800 * next xfernotready and we will issue
1801 * a fresh START TRANSFER.
1802 * If there are still queued request
1803 * then wait, do not issue either END
1804 * or UPDATE TRANSFER, just attach next
1805 * request in request_list during
1806 * giveback.If any future queued request
1807 * is successfully transferred then we
1808 * will issue UPDATE TRANSFER for all
1809 * request in the request_list.
1811 dep
->flags
|= DWC3_EP_MISSED_ISOC
;
1813 dev_err(dwc
->dev
, "incomplete IN transfer %s\n",
1815 status
= -ECONNRESET
;
1818 dep
->flags
&= ~DWC3_EP_MISSED_ISOC
;
1821 if (count
&& (event
->status
& DEPEVT_STATUS_SHORT
))
1826 * We assume here we will always receive the entire data block
1827 * which we should receive. Meaning, if we program RX to
1828 * receive 4K but we receive only 2K, we assume that's all we
1829 * should receive and we simply bounce the request back to the
1830 * gadget driver for further processing.
1832 req
->request
.actual
+= req
->request
.length
- count
;
1835 if ((event
->status
& DEPEVT_STATUS_LST
) &&
1836 (trb
->ctrl
& (DWC3_TRB_CTRL_LST
|
1837 DWC3_TRB_CTRL_HWO
)))
1839 if ((event
->status
& DEPEVT_STATUS_IOC
) &&
1840 (trb
->ctrl
& DWC3_TRB_CTRL_IOC
))
1845 static int dwc3_cleanup_done_reqs(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
1846 const struct dwc3_event_depevt
*event
, int status
)
1848 struct dwc3_request
*req
;
1849 struct dwc3_trb
*trb
;
1855 req
= next_request(&dep
->req_queued
);
1862 slot
= req
->start_slot
+ i
;
1863 if ((slot
== DWC3_TRB_NUM
- 1) &&
1864 usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
1866 slot
%= DWC3_TRB_NUM
;
1867 trb
= &dep
->trb_pool
[slot
];
1869 ret
= __dwc3_cleanup_done_trbs(dwc
, dep
, req
, trb
,
1873 }while (++i
< req
->request
.num_mapped_sgs
);
1875 dwc3_gadget_giveback(dep
, req
, status
);
1881 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) &&
1882 list_empty(&dep
->req_queued
)) {
1883 if (list_empty(&dep
->request_list
)) {
1885 * If there is no entry in request list then do
1886 * not issue END TRANSFER now. Just set PENDING
1887 * flag, so that END TRANSFER is issued when an
1888 * entry is added into request list.
1890 dep
->flags
= DWC3_EP_PENDING_REQUEST
;
1892 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
1893 dep
->flags
= DWC3_EP_ENABLED
;
1901 static void dwc3_endpoint_transfer_complete(struct dwc3
*dwc
,
1902 struct dwc3_ep
*dep
, const struct dwc3_event_depevt
*event
)
1904 unsigned status
= 0;
1907 if (event
->status
& DEPEVT_STATUS_BUSERR
)
1908 status
= -ECONNRESET
;
1910 clean_busy
= dwc3_cleanup_done_reqs(dwc
, dep
, event
, status
);
1912 dep
->flags
&= ~DWC3_EP_BUSY
;
1915 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1916 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1918 if (dwc
->revision
< DWC3_REVISION_183A
) {
1922 for (i
= 0; i
< DWC3_ENDPOINTS_NUM
; i
++) {
1925 if (!(dep
->flags
& DWC3_EP_ENABLED
))
1928 if (!list_empty(&dep
->req_queued
))
1932 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1934 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1940 static void dwc3_endpoint_interrupt(struct dwc3
*dwc
,
1941 const struct dwc3_event_depevt
*event
)
1943 struct dwc3_ep
*dep
;
1944 u8 epnum
= event
->endpoint_number
;
1946 dep
= dwc
->eps
[epnum
];
1948 if (!(dep
->flags
& DWC3_EP_ENABLED
))
1951 if (epnum
== 0 || epnum
== 1) {
1952 dwc3_ep0_interrupt(dwc
, event
);
1956 switch (event
->endpoint_event
) {
1957 case DWC3_DEPEVT_XFERCOMPLETE
:
1958 dep
->resource_index
= 0;
1960 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1961 dev_dbg(dwc
->dev
, "%s is an Isochronous endpoint\n",
1966 dwc3_endpoint_transfer_complete(dwc
, dep
, event
);
1968 case DWC3_DEPEVT_XFERINPROGRESS
:
1969 dwc3_endpoint_transfer_complete(dwc
, dep
, event
);
1971 case DWC3_DEPEVT_XFERNOTREADY
:
1972 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1973 dwc3_gadget_start_isoc(dwc
, dep
, event
);
1977 dev_vdbg(dwc
->dev
, "%s: reason %s\n",
1978 dep
->name
, event
->status
&
1979 DEPEVT_STATUS_TRANSFER_ACTIVE
1981 : "Transfer Not Active");
1983 ret
= __dwc3_gadget_kick_transfer(dep
, 0, 1);
1984 if (!ret
|| ret
== -EBUSY
)
1987 dev_dbg(dwc
->dev
, "%s: failed to kick transfers\n",
1992 case DWC3_DEPEVT_STREAMEVT
:
1993 if (!usb_endpoint_xfer_bulk(dep
->endpoint
.desc
)) {
1994 dev_err(dwc
->dev
, "Stream event for non-Bulk %s\n",
1999 switch (event
->status
) {
2000 case DEPEVT_STREAMEVT_FOUND
:
2001 dev_vdbg(dwc
->dev
, "Stream %d found and started\n",
2005 case DEPEVT_STREAMEVT_NOTFOUND
:
2008 dev_dbg(dwc
->dev
, "Couldn't find suitable stream\n");
2011 case DWC3_DEPEVT_RXTXFIFOEVT
:
2012 dev_dbg(dwc
->dev
, "%s FIFO Overrun\n", dep
->name
);
2014 case DWC3_DEPEVT_EPCMDCMPLT
:
2015 dev_vdbg(dwc
->dev
, "Endpoint Command Complete\n");
2020 static void dwc3_disconnect_gadget(struct dwc3
*dwc
)
2022 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->disconnect
) {
2023 spin_unlock(&dwc
->lock
);
2024 dwc
->gadget_driver
->disconnect(&dwc
->gadget
);
2025 spin_lock(&dwc
->lock
);
2029 static void dwc3_suspend_gadget(struct dwc3
*dwc
)
2031 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->suspend
) {
2032 spin_unlock(&dwc
->lock
);
2033 dwc
->gadget_driver
->suspend(&dwc
->gadget
);
2034 spin_lock(&dwc
->lock
);
2038 static void dwc3_resume_gadget(struct dwc3
*dwc
)
2040 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->resume
) {
2041 spin_unlock(&dwc
->lock
);
2042 dwc
->gadget_driver
->resume(&dwc
->gadget
);
2046 static void dwc3_reset_gadget(struct dwc3
*dwc
)
2048 if (!dwc
->gadget_driver
)
2051 if (dwc
->gadget
.speed
!= USB_SPEED_UNKNOWN
) {
2052 spin_unlock(&dwc
->lock
);
2053 usb_gadget_udc_reset(&dwc
->gadget
, dwc
->gadget_driver
);
2054 spin_lock(&dwc
->lock
);
2058 static void dwc3_stop_active_transfer(struct dwc3
*dwc
, u32 epnum
, bool force
)
2060 struct dwc3_ep
*dep
;
2061 struct dwc3_gadget_ep_cmd_params params
;
2065 dep
= dwc
->eps
[epnum
];
2067 if (!dep
->resource_index
)
2071 * NOTICE: We are violating what the Databook says about the
2072 * EndTransfer command. Ideally we would _always_ wait for the
2073 * EndTransfer Command Completion IRQ, but that's causing too
2074 * much trouble synchronizing between us and gadget driver.
2076 * We have discussed this with the IP Provider and it was
2077 * suggested to giveback all requests here, but give HW some
2078 * extra time to synchronize with the interconnect. We're using
2079 * an arbitraty 100us delay for that.
2081 * Note also that a similar handling was tested by Synopsys
2082 * (thanks a lot Paul) and nothing bad has come out of it.
2083 * In short, what we're doing is:
2085 * - Issue EndTransfer WITH CMDIOC bit set
2089 cmd
= DWC3_DEPCMD_ENDTRANSFER
;
2090 cmd
|= force
? DWC3_DEPCMD_HIPRI_FORCERM
: 0;
2091 cmd
|= DWC3_DEPCMD_CMDIOC
;
2092 cmd
|= DWC3_DEPCMD_PARAM(dep
->resource_index
);
2093 memset(¶ms
, 0, sizeof(params
));
2094 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
, cmd
, ¶ms
);
2096 dep
->resource_index
= 0;
2097 dep
->flags
&= ~DWC3_EP_BUSY
;
2101 static void dwc3_stop_active_transfers(struct dwc3
*dwc
)
2105 for (epnum
= 2; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
2106 struct dwc3_ep
*dep
;
2108 dep
= dwc
->eps
[epnum
];
2112 if (!(dep
->flags
& DWC3_EP_ENABLED
))
2115 dwc3_remove_requests(dwc
, dep
);
2119 static void dwc3_clear_stall_all_ep(struct dwc3
*dwc
)
2123 for (epnum
= 1; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
2124 struct dwc3_ep
*dep
;
2125 struct dwc3_gadget_ep_cmd_params params
;
2128 dep
= dwc
->eps
[epnum
];
2132 if (!(dep
->flags
& DWC3_EP_STALL
))
2135 dep
->flags
&= ~DWC3_EP_STALL
;
2137 memset(¶ms
, 0, sizeof(params
));
2138 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
2139 DWC3_DEPCMD_CLEARSTALL
, ¶ms
);
2144 static void dwc3_gadget_disconnect_interrupt(struct dwc3
*dwc
)
2148 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2149 reg
&= ~DWC3_DCTL_INITU1ENA
;
2150 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2152 reg
&= ~DWC3_DCTL_INITU2ENA
;
2153 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2155 dwc3_disconnect_gadget(dwc
);
2156 dwc
->start_config_issued
= false;
2158 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2159 dwc
->setup_packet_pending
= false;
2160 usb_gadget_set_state(&dwc
->gadget
, USB_STATE_NOTATTACHED
);
2163 static void dwc3_gadget_reset_interrupt(struct dwc3
*dwc
)
2168 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2169 * would cause a missing Disconnect Event if there's a
2170 * pending Setup Packet in the FIFO.
2172 * There's no suggested workaround on the official Bug
2173 * report, which states that "unless the driver/application
2174 * is doing any special handling of a disconnect event,
2175 * there is no functional issue".
2177 * Unfortunately, it turns out that we _do_ some special
2178 * handling of a disconnect event, namely complete all
2179 * pending transfers, notify gadget driver of the
2180 * disconnection, and so on.
2182 * Our suggested workaround is to follow the Disconnect
2183 * Event steps here, instead, based on a setup_packet_pending
2184 * flag. Such flag gets set whenever we have a XferNotReady
2185 * event on EP0 and gets cleared on XferComplete for the
2190 * STAR#9000466709: RTL: Device : Disconnect event not
2191 * generated if setup packet pending in FIFO
2193 if (dwc
->revision
< DWC3_REVISION_188A
) {
2194 if (dwc
->setup_packet_pending
)
2195 dwc3_gadget_disconnect_interrupt(dwc
);
2198 dwc3_reset_gadget(dwc
);
2200 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2201 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
2202 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2203 dwc
->test_mode
= false;
2205 dwc3_stop_active_transfers(dwc
);
2206 dwc3_clear_stall_all_ep(dwc
);
2207 dwc
->start_config_issued
= false;
2209 /* Reset device address to zero */
2210 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2211 reg
&= ~(DWC3_DCFG_DEVADDR_MASK
);
2212 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2215 static void dwc3_update_ram_clk_sel(struct dwc3
*dwc
, u32 speed
)
2218 u32 usb30_clock
= DWC3_GCTL_CLK_BUS
;
2221 * We change the clock only at SS but I dunno why I would want to do
2222 * this. Maybe it becomes part of the power saving plan.
2225 if (speed
!= DWC3_DSTS_SUPERSPEED
)
2229 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2230 * each time on Connect Done.
2235 reg
= dwc3_readl(dwc
->regs
, DWC3_GCTL
);
2236 reg
|= DWC3_GCTL_RAMCLKSEL(usb30_clock
);
2237 dwc3_writel(dwc
->regs
, DWC3_GCTL
, reg
);
2240 static void dwc3_gadget_conndone_interrupt(struct dwc3
*dwc
)
2242 struct dwc3_ep
*dep
;
2247 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
2248 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
2251 dwc3_update_ram_clk_sel(dwc
, speed
);
2254 case DWC3_DCFG_SUPERSPEED
:
2256 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2257 * would cause a missing USB3 Reset event.
2259 * In such situations, we should force a USB3 Reset
2260 * event by calling our dwc3_gadget_reset_interrupt()
2265 * STAR#9000483510: RTL: SS : USB3 reset event may
2266 * not be generated always when the link enters poll
2268 if (dwc
->revision
< DWC3_REVISION_190A
)
2269 dwc3_gadget_reset_interrupt(dwc
);
2271 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
2272 dwc
->gadget
.ep0
->maxpacket
= 512;
2273 dwc
->gadget
.speed
= USB_SPEED_SUPER
;
2275 case DWC3_DCFG_HIGHSPEED
:
2276 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2277 dwc
->gadget
.ep0
->maxpacket
= 64;
2278 dwc
->gadget
.speed
= USB_SPEED_HIGH
;
2280 case DWC3_DCFG_FULLSPEED2
:
2281 case DWC3_DCFG_FULLSPEED1
:
2282 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2283 dwc
->gadget
.ep0
->maxpacket
= 64;
2284 dwc
->gadget
.speed
= USB_SPEED_FULL
;
2286 case DWC3_DCFG_LOWSPEED
:
2287 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(8);
2288 dwc
->gadget
.ep0
->maxpacket
= 8;
2289 dwc
->gadget
.speed
= USB_SPEED_LOW
;
2293 /* Enable USB2 LPM Capability */
2295 if ((dwc
->revision
> DWC3_REVISION_194A
)
2296 && (speed
!= DWC3_DCFG_SUPERSPEED
)) {
2297 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2298 reg
|= DWC3_DCFG_LPM_CAP
;
2299 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2301 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2302 reg
&= ~(DWC3_DCTL_HIRD_THRES_MASK
| DWC3_DCTL_L1_HIBER_EN
);
2304 reg
|= DWC3_DCTL_HIRD_THRES(dwc
->hird_threshold
);
2307 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2308 * DCFG.LPMCap is set, core responses with an ACK and the
2309 * BESL value in the LPM token is less than or equal to LPM
2312 WARN_ONCE(dwc
->revision
< DWC3_REVISION_240A
2313 && dwc
->has_lpm_erratum
,
2314 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2316 if (dwc
->has_lpm_erratum
&& dwc
->revision
>= DWC3_REVISION_240A
)
2317 reg
|= DWC3_DCTL_LPM_ERRATA(dwc
->lpm_nyet_threshold
);
2319 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2321 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2322 reg
&= ~DWC3_DCTL_HIRD_THRES_MASK
;
2323 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2327 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, true,
2330 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2335 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, true,
2338 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2343 * Configure PHY via GUSB3PIPECTLn if required.
2345 * Update GTXFIFOSIZn
2347 * In both cases reset values should be sufficient.
2351 static void dwc3_gadget_wakeup_interrupt(struct dwc3
*dwc
)
2354 * TODO take core out of low power mode when that's
2358 dwc
->gadget_driver
->resume(&dwc
->gadget
);
2361 static void dwc3_gadget_linksts_change_interrupt(struct dwc3
*dwc
,
2362 unsigned int evtinfo
)
2364 enum dwc3_link_state next
= evtinfo
& DWC3_LINK_STATE_MASK
;
2365 unsigned int pwropt
;
2368 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2369 * Hibernation mode enabled which would show up when device detects
2370 * host-initiated U3 exit.
2372 * In that case, device will generate a Link State Change Interrupt
2373 * from U3 to RESUME which is only necessary if Hibernation is
2376 * There are no functional changes due to such spurious event and we
2377 * just need to ignore it.
2381 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2384 pwropt
= DWC3_GHWPARAMS1_EN_PWROPT(dwc
->hwparams
.hwparams1
);
2385 if ((dwc
->revision
< DWC3_REVISION_250A
) &&
2386 (pwropt
!= DWC3_GHWPARAMS1_EN_PWROPT_HIB
)) {
2387 if ((dwc
->link_state
== DWC3_LINK_STATE_U3
) &&
2388 (next
== DWC3_LINK_STATE_RESUME
)) {
2389 dev_vdbg(dwc
->dev
, "ignoring transition U3 -> Resume\n");
2395 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2396 * on the link partner, the USB session might do multiple entry/exit
2397 * of low power states before a transfer takes place.
2399 * Due to this problem, we might experience lower throughput. The
2400 * suggested workaround is to disable DCTL[12:9] bits if we're
2401 * transitioning from U1/U2 to U0 and enable those bits again
2402 * after a transfer completes and there are no pending transfers
2403 * on any of the enabled endpoints.
2405 * This is the first half of that workaround.
2409 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2410 * core send LGO_Ux entering U0
2412 if (dwc
->revision
< DWC3_REVISION_183A
) {
2413 if (next
== DWC3_LINK_STATE_U0
) {
2417 switch (dwc
->link_state
) {
2418 case DWC3_LINK_STATE_U1
:
2419 case DWC3_LINK_STATE_U2
:
2420 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2421 u1u2
= reg
& (DWC3_DCTL_INITU2ENA
2422 | DWC3_DCTL_ACCEPTU2ENA
2423 | DWC3_DCTL_INITU1ENA
2424 | DWC3_DCTL_ACCEPTU1ENA
);
2427 dwc
->u1u2
= reg
& u1u2
;
2431 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2441 case DWC3_LINK_STATE_U1
:
2442 if (dwc
->speed
== USB_SPEED_SUPER
)
2443 dwc3_suspend_gadget(dwc
);
2445 case DWC3_LINK_STATE_U2
:
2446 case DWC3_LINK_STATE_U3
:
2447 dwc3_suspend_gadget(dwc
);
2449 case DWC3_LINK_STATE_RESUME
:
2450 dwc3_resume_gadget(dwc
);
2457 dwc
->link_state
= next
;
2460 static void dwc3_gadget_hibernation_interrupt(struct dwc3
*dwc
,
2461 unsigned int evtinfo
)
2463 unsigned int is_ss
= evtinfo
& BIT(4);
2466 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2467 * have a known issue which can cause USB CV TD.9.23 to fail
2470 * Because of this issue, core could generate bogus hibernation
2471 * events which SW needs to ignore.
2475 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2476 * Device Fallback from SuperSpeed
2478 if (is_ss
^ (dwc
->speed
== USB_SPEED_SUPER
))
2481 /* enter hibernation here */
2484 static void dwc3_gadget_interrupt(struct dwc3
*dwc
,
2485 const struct dwc3_event_devt
*event
)
2487 switch (event
->type
) {
2488 case DWC3_DEVICE_EVENT_DISCONNECT
:
2489 dwc3_gadget_disconnect_interrupt(dwc
);
2491 case DWC3_DEVICE_EVENT_RESET
:
2492 dwc3_gadget_reset_interrupt(dwc
);
2494 case DWC3_DEVICE_EVENT_CONNECT_DONE
:
2495 dwc3_gadget_conndone_interrupt(dwc
);
2497 case DWC3_DEVICE_EVENT_WAKEUP
:
2498 dwc3_gadget_wakeup_interrupt(dwc
);
2500 case DWC3_DEVICE_EVENT_HIBER_REQ
:
2501 if (dev_WARN_ONCE(dwc
->dev
, !dwc
->has_hibernation
,
2502 "unexpected hibernation event\n"))
2505 dwc3_gadget_hibernation_interrupt(dwc
, event
->event_info
);
2507 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE
:
2508 dwc3_gadget_linksts_change_interrupt(dwc
, event
->event_info
);
2510 case DWC3_DEVICE_EVENT_EOPF
:
2511 dev_vdbg(dwc
->dev
, "End of Periodic Frame\n");
2513 case DWC3_DEVICE_EVENT_SOF
:
2514 dev_vdbg(dwc
->dev
, "Start of Periodic Frame\n");
2516 case DWC3_DEVICE_EVENT_ERRATIC_ERROR
:
2517 dev_vdbg(dwc
->dev
, "Erratic Error\n");
2519 case DWC3_DEVICE_EVENT_CMD_CMPL
:
2520 dev_vdbg(dwc
->dev
, "Command Complete\n");
2522 case DWC3_DEVICE_EVENT_OVERFLOW
:
2523 dev_vdbg(dwc
->dev
, "Overflow\n");
2526 dev_dbg(dwc
->dev
, "UNKNOWN IRQ %d\n", event
->type
);
2530 static void dwc3_process_event_entry(struct dwc3
*dwc
,
2531 const union dwc3_event
*event
)
2533 trace_dwc3_event(event
->raw
);
2535 /* Endpoint IRQ, handle it and return early */
2536 if (event
->type
.is_devspec
== 0) {
2538 return dwc3_endpoint_interrupt(dwc
, &event
->depevt
);
2541 switch (event
->type
.type
) {
2542 case DWC3_EVENT_TYPE_DEV
:
2543 dwc3_gadget_interrupt(dwc
, &event
->devt
);
2545 /* REVISIT what to do with Carkit and I2C events ? */
2547 dev_err(dwc
->dev
, "UNKNOWN IRQ type %d\n", event
->raw
);
2551 static irqreturn_t
dwc3_process_event_buf(struct dwc3
*dwc
, u32 buf
)
2553 struct dwc3_event_buffer
*evt
;
2554 irqreturn_t ret
= IRQ_NONE
;
2558 evt
= dwc
->ev_buffs
[buf
];
2561 if (!(evt
->flags
& DWC3_EVENT_PENDING
))
2565 union dwc3_event event
;
2567 event
.raw
= *(u32
*) (evt
->buf
+ evt
->lpos
);
2569 dwc3_process_event_entry(dwc
, &event
);
2572 * FIXME we wrap around correctly to the next entry as
2573 * almost all entries are 4 bytes in size. There is one
2574 * entry which has 12 bytes which is a regular entry
2575 * followed by 8 bytes data. ATM I don't know how
2576 * things are organized if we get next to the a
2577 * boundary so I worry about that once we try to handle
2580 evt
->lpos
= (evt
->lpos
+ 4) % DWC3_EVENT_BUFFERS_SIZE
;
2583 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(buf
), 4);
2587 evt
->flags
&= ~DWC3_EVENT_PENDING
;
2590 /* Unmask interrupt */
2591 reg
= dwc3_readl(dwc
->regs
, DWC3_GEVNTSIZ(buf
));
2592 reg
&= ~DWC3_GEVNTSIZ_INTMASK
;
2593 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(buf
), reg
);
2598 static irqreturn_t
dwc3_thread_interrupt(int irq
, void *_dwc
)
2600 struct dwc3
*dwc
= _dwc
;
2601 unsigned long flags
;
2602 irqreturn_t ret
= IRQ_NONE
;
2605 spin_lock_irqsave(&dwc
->lock
, flags
);
2607 for (i
= 0; i
< dwc
->num_event_buffers
; i
++)
2608 ret
|= dwc3_process_event_buf(dwc
, i
);
2610 spin_unlock_irqrestore(&dwc
->lock
, flags
);
2615 static irqreturn_t
dwc3_check_event_buf(struct dwc3
*dwc
, u32 buf
)
2617 struct dwc3_event_buffer
*evt
;
2621 evt
= dwc
->ev_buffs
[buf
];
2623 count
= dwc3_readl(dwc
->regs
, DWC3_GEVNTCOUNT(buf
));
2624 count
&= DWC3_GEVNTCOUNT_MASK
;
2629 evt
->flags
|= DWC3_EVENT_PENDING
;
2631 /* Mask interrupt */
2632 reg
= dwc3_readl(dwc
->regs
, DWC3_GEVNTSIZ(buf
));
2633 reg
|= DWC3_GEVNTSIZ_INTMASK
;
2634 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(buf
), reg
);
2636 return IRQ_WAKE_THREAD
;
2639 static irqreturn_t
dwc3_interrupt(int irq
, void *_dwc
)
2641 struct dwc3
*dwc
= _dwc
;
2643 irqreturn_t ret
= IRQ_NONE
;
2645 spin_lock(&dwc
->lock
);
2647 for (i
= 0; i
< dwc
->num_event_buffers
; i
++) {
2650 status
= dwc3_check_event_buf(dwc
, i
);
2651 if (status
== IRQ_WAKE_THREAD
)
2655 spin_unlock(&dwc
->lock
);
2661 * dwc3_gadget_init - Initializes gadget related registers
2662 * @dwc: pointer to our controller context structure
2664 * Returns 0 on success otherwise negative errno.
2666 int dwc3_gadget_init(struct dwc3
*dwc
)
2670 dwc
->ctrl_req
= dma_alloc_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
2671 &dwc
->ctrl_req_addr
, GFP_KERNEL
);
2672 if (!dwc
->ctrl_req
) {
2673 dev_err(dwc
->dev
, "failed to allocate ctrl request\n");
2678 dwc
->ep0_trb
= dma_alloc_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
),
2679 &dwc
->ep0_trb_addr
, GFP_KERNEL
);
2680 if (!dwc
->ep0_trb
) {
2681 dev_err(dwc
->dev
, "failed to allocate ep0 trb\n");
2686 dwc
->setup_buf
= kzalloc(DWC3_EP0_BOUNCE_SIZE
, GFP_KERNEL
);
2687 if (!dwc
->setup_buf
) {
2692 dwc
->ep0_bounce
= dma_alloc_coherent(dwc
->dev
,
2693 DWC3_EP0_BOUNCE_SIZE
, &dwc
->ep0_bounce_addr
,
2695 if (!dwc
->ep0_bounce
) {
2696 dev_err(dwc
->dev
, "failed to allocate ep0 bounce buffer\n");
2701 dwc
->gadget
.ops
= &dwc3_gadget_ops
;
2702 dwc
->gadget
.max_speed
= USB_SPEED_SUPER
;
2703 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2704 dwc
->gadget
.sg_supported
= true;
2705 dwc
->gadget
.name
= "dwc3-gadget";
2708 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2711 dwc
->gadget
.quirk_ep_out_aligned_size
= true;
2714 * REVISIT: Here we should clear all pending IRQs to be
2715 * sure we're starting from a well known location.
2718 ret
= dwc3_gadget_init_endpoints(dwc
);
2722 ret
= usb_add_gadget_udc(dwc
->dev
, &dwc
->gadget
);
2724 dev_err(dwc
->dev
, "failed to register udc\n");
2731 dwc3_gadget_free_endpoints(dwc
);
2732 dma_free_coherent(dwc
->dev
, DWC3_EP0_BOUNCE_SIZE
,
2733 dwc
->ep0_bounce
, dwc
->ep0_bounce_addr
);
2736 kfree(dwc
->setup_buf
);
2739 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
),
2740 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
2743 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
2744 dwc
->ctrl_req
, dwc
->ctrl_req_addr
);
2750 /* -------------------------------------------------------------------------- */
2752 void dwc3_gadget_exit(struct dwc3
*dwc
)
2754 usb_del_gadget_udc(&dwc
->gadget
);
2756 dwc3_gadget_free_endpoints(dwc
);
2758 dma_free_coherent(dwc
->dev
, DWC3_EP0_BOUNCE_SIZE
,
2759 dwc
->ep0_bounce
, dwc
->ep0_bounce_addr
);
2761 kfree(dwc
->setup_buf
);
2763 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
),
2764 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
2766 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
2767 dwc
->ctrl_req
, dwc
->ctrl_req_addr
);
2770 int dwc3_gadget_suspend(struct dwc3
*dwc
)
2772 if (dwc
->pullups_connected
) {
2773 dwc3_gadget_disable_irq(dwc
);
2774 dwc3_gadget_run_stop(dwc
, true, true);
2777 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
2778 __dwc3_gadget_ep_disable(dwc
->eps
[1]);
2780 dwc
->dcfg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2785 int dwc3_gadget_resume(struct dwc3
*dwc
)
2787 struct dwc3_ep
*dep
;
2790 /* Start with SuperSpeed Default */
2791 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
2794 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, false,
2800 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, false,
2805 /* begin to receive SETUP packets */
2806 dwc
->ep0state
= EP0_SETUP_PHASE
;
2807 dwc3_ep0_out_start(dwc
);
2809 dwc3_writel(dwc
->regs
, DWC3_DCFG
, dwc
->dcfg
);
2811 if (dwc
->pullups_connected
) {
2812 dwc3_gadget_enable_irq(dwc
);
2813 dwc3_gadget_run_stop(dwc
, true, false);
2819 __dwc3_gadget_ep_disable(dwc
->eps
[0]);