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usb: remove use of __devexit
[mirror_ubuntu-bionic-kernel.git] / drivers / usb / gadget / mv_udc_core.c
1 /*
2 * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
3 * Author: Chao Xie <chao.xie@marvell.com>
4 * Neil Zhang <zhangwm@marvell.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12 #include <linux/module.h>
13 #include <linux/pci.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/dmapool.h>
16 #include <linux/kernel.h>
17 #include <linux/delay.h>
18 #include <linux/ioport.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/errno.h>
22 #include <linux/err.h>
23 #include <linux/init.h>
24 #include <linux/timer.h>
25 #include <linux/list.h>
26 #include <linux/interrupt.h>
27 #include <linux/moduleparam.h>
28 #include <linux/device.h>
29 #include <linux/usb/ch9.h>
30 #include <linux/usb/gadget.h>
31 #include <linux/usb/otg.h>
32 #include <linux/pm.h>
33 #include <linux/io.h>
34 #include <linux/irq.h>
35 #include <linux/platform_device.h>
36 #include <linux/clk.h>
37 #include <linux/platform_data/mv_usb.h>
38 #include <asm/unaligned.h>
39
40 #include "mv_udc.h"
41
42 #define DRIVER_DESC "Marvell PXA USB Device Controller driver"
43 #define DRIVER_VERSION "8 Nov 2010"
44
45 #define ep_dir(ep) (((ep)->ep_num == 0) ? \
46 ((ep)->udc->ep0_dir) : ((ep)->direction))
47
48 /* timeout value -- usec */
49 #define RESET_TIMEOUT 10000
50 #define FLUSH_TIMEOUT 10000
51 #define EPSTATUS_TIMEOUT 10000
52 #define PRIME_TIMEOUT 10000
53 #define READSAFE_TIMEOUT 1000
54
55 #define LOOPS_USEC_SHIFT 1
56 #define LOOPS_USEC (1 << LOOPS_USEC_SHIFT)
57 #define LOOPS(timeout) ((timeout) >> LOOPS_USEC_SHIFT)
58
59 static DECLARE_COMPLETION(release_done);
60
61 static const char driver_name[] = "mv_udc";
62 static const char driver_desc[] = DRIVER_DESC;
63
64 /* controller device global variable */
65 static struct mv_udc *the_controller;
66
67 static void nuke(struct mv_ep *ep, int status);
68 static void stop_activity(struct mv_udc *udc, struct usb_gadget_driver *driver);
69
70 /* for endpoint 0 operations */
71 static const struct usb_endpoint_descriptor mv_ep0_desc = {
72 .bLength = USB_DT_ENDPOINT_SIZE,
73 .bDescriptorType = USB_DT_ENDPOINT,
74 .bEndpointAddress = 0,
75 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
76 .wMaxPacketSize = EP0_MAX_PKT_SIZE,
77 };
78
79 static void ep0_reset(struct mv_udc *udc)
80 {
81 struct mv_ep *ep;
82 u32 epctrlx;
83 int i = 0;
84
85 /* ep0 in and out */
86 for (i = 0; i < 2; i++) {
87 ep = &udc->eps[i];
88 ep->udc = udc;
89
90 /* ep0 dQH */
91 ep->dqh = &udc->ep_dqh[i];
92
93 /* configure ep0 endpoint capabilities in dQH */
94 ep->dqh->max_packet_length =
95 (EP0_MAX_PKT_SIZE << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
96 | EP_QUEUE_HEAD_IOS;
97
98 ep->dqh->next_dtd_ptr = EP_QUEUE_HEAD_NEXT_TERMINATE;
99
100 epctrlx = readl(&udc->op_regs->epctrlx[0]);
101 if (i) { /* TX */
102 epctrlx |= EPCTRL_TX_ENABLE
103 | (USB_ENDPOINT_XFER_CONTROL
104 << EPCTRL_TX_EP_TYPE_SHIFT);
105
106 } else { /* RX */
107 epctrlx |= EPCTRL_RX_ENABLE
108 | (USB_ENDPOINT_XFER_CONTROL
109 << EPCTRL_RX_EP_TYPE_SHIFT);
110 }
111
112 writel(epctrlx, &udc->op_regs->epctrlx[0]);
113 }
114 }
115
116 /* protocol ep0 stall, will automatically be cleared on new transaction */
117 static void ep0_stall(struct mv_udc *udc)
118 {
119 u32 epctrlx;
120
121 /* set TX and RX to stall */
122 epctrlx = readl(&udc->op_regs->epctrlx[0]);
123 epctrlx |= EPCTRL_RX_EP_STALL | EPCTRL_TX_EP_STALL;
124 writel(epctrlx, &udc->op_regs->epctrlx[0]);
125
126 /* update ep0 state */
127 udc->ep0_state = WAIT_FOR_SETUP;
128 udc->ep0_dir = EP_DIR_OUT;
129 }
130
131 static int process_ep_req(struct mv_udc *udc, int index,
132 struct mv_req *curr_req)
133 {
134 struct mv_dtd *curr_dtd;
135 struct mv_dqh *curr_dqh;
136 int td_complete, actual, remaining_length;
137 int i, direction;
138 int retval = 0;
139 u32 errors;
140 u32 bit_pos;
141
142 curr_dqh = &udc->ep_dqh[index];
143 direction = index % 2;
144
145 curr_dtd = curr_req->head;
146 td_complete = 0;
147 actual = curr_req->req.length;
148
149 for (i = 0; i < curr_req->dtd_count; i++) {
150 if (curr_dtd->size_ioc_sts & DTD_STATUS_ACTIVE) {
151 dev_dbg(&udc->dev->dev, "%s, dTD not completed\n",
152 udc->eps[index].name);
153 return 1;
154 }
155
156 errors = curr_dtd->size_ioc_sts & DTD_ERROR_MASK;
157 if (!errors) {
158 remaining_length =
159 (curr_dtd->size_ioc_sts & DTD_PACKET_SIZE)
160 >> DTD_LENGTH_BIT_POS;
161 actual -= remaining_length;
162
163 if (remaining_length) {
164 if (direction) {
165 dev_dbg(&udc->dev->dev,
166 "TX dTD remains data\n");
167 retval = -EPROTO;
168 break;
169 } else
170 break;
171 }
172 } else {
173 dev_info(&udc->dev->dev,
174 "complete_tr error: ep=%d %s: error = 0x%x\n",
175 index >> 1, direction ? "SEND" : "RECV",
176 errors);
177 if (errors & DTD_STATUS_HALTED) {
178 /* Clear the errors and Halt condition */
179 curr_dqh->size_ioc_int_sts &= ~errors;
180 retval = -EPIPE;
181 } else if (errors & DTD_STATUS_DATA_BUFF_ERR) {
182 retval = -EPROTO;
183 } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
184 retval = -EILSEQ;
185 }
186 }
187 if (i != curr_req->dtd_count - 1)
188 curr_dtd = (struct mv_dtd *)curr_dtd->next_dtd_virt;
189 }
190 if (retval)
191 return retval;
192
193 if (direction == EP_DIR_OUT)
194 bit_pos = 1 << curr_req->ep->ep_num;
195 else
196 bit_pos = 1 << (16 + curr_req->ep->ep_num);
197
198 while ((curr_dqh->curr_dtd_ptr == curr_dtd->td_dma)) {
199 if (curr_dtd->dtd_next == EP_QUEUE_HEAD_NEXT_TERMINATE) {
200 while (readl(&udc->op_regs->epstatus) & bit_pos)
201 udelay(1);
202 break;
203 }
204 udelay(1);
205 }
206
207 curr_req->req.actual = actual;
208
209 return 0;
210 }
211
212 /*
213 * done() - retire a request; caller blocked irqs
214 * @status : request status to be set, only works when
215 * request is still in progress.
216 */
217 static void done(struct mv_ep *ep, struct mv_req *req, int status)
218 {
219 struct mv_udc *udc = NULL;
220 unsigned char stopped = ep->stopped;
221 struct mv_dtd *curr_td, *next_td;
222 int j;
223
224 udc = (struct mv_udc *)ep->udc;
225 /* Removed the req from fsl_ep->queue */
226 list_del_init(&req->queue);
227
228 /* req.status should be set as -EINPROGRESS in ep_queue() */
229 if (req->req.status == -EINPROGRESS)
230 req->req.status = status;
231 else
232 status = req->req.status;
233
234 /* Free dtd for the request */
235 next_td = req->head;
236 for (j = 0; j < req->dtd_count; j++) {
237 curr_td = next_td;
238 if (j != req->dtd_count - 1)
239 next_td = curr_td->next_dtd_virt;
240 dma_pool_free(udc->dtd_pool, curr_td, curr_td->td_dma);
241 }
242
243 if (req->mapped) {
244 dma_unmap_single(ep->udc->gadget.dev.parent,
245 req->req.dma, req->req.length,
246 ((ep_dir(ep) == EP_DIR_IN) ?
247 DMA_TO_DEVICE : DMA_FROM_DEVICE));
248 req->req.dma = DMA_ADDR_INVALID;
249 req->mapped = 0;
250 } else
251 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
252 req->req.dma, req->req.length,
253 ((ep_dir(ep) == EP_DIR_IN) ?
254 DMA_TO_DEVICE : DMA_FROM_DEVICE));
255
256 if (status && (status != -ESHUTDOWN))
257 dev_info(&udc->dev->dev, "complete %s req %p stat %d len %u/%u",
258 ep->ep.name, &req->req, status,
259 req->req.actual, req->req.length);
260
261 ep->stopped = 1;
262
263 spin_unlock(&ep->udc->lock);
264 /*
265 * complete() is from gadget layer,
266 * eg fsg->bulk_in_complete()
267 */
268 if (req->req.complete)
269 req->req.complete(&ep->ep, &req->req);
270
271 spin_lock(&ep->udc->lock);
272 ep->stopped = stopped;
273 }
274
275 static int queue_dtd(struct mv_ep *ep, struct mv_req *req)
276 {
277 struct mv_udc *udc;
278 struct mv_dqh *dqh;
279 u32 bit_pos, direction;
280 u32 usbcmd, epstatus;
281 unsigned int loops;
282 int retval = 0;
283
284 udc = ep->udc;
285 direction = ep_dir(ep);
286 dqh = &(udc->ep_dqh[ep->ep_num * 2 + direction]);
287 bit_pos = 1 << (((direction == EP_DIR_OUT) ? 0 : 16) + ep->ep_num);
288
289 /* check if the pipe is empty */
290 if (!(list_empty(&ep->queue))) {
291 struct mv_req *lastreq;
292 lastreq = list_entry(ep->queue.prev, struct mv_req, queue);
293 lastreq->tail->dtd_next =
294 req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
295
296 wmb();
297
298 if (readl(&udc->op_regs->epprime) & bit_pos)
299 goto done;
300
301 loops = LOOPS(READSAFE_TIMEOUT);
302 while (1) {
303 /* start with setting the semaphores */
304 usbcmd = readl(&udc->op_regs->usbcmd);
305 usbcmd |= USBCMD_ATDTW_TRIPWIRE_SET;
306 writel(usbcmd, &udc->op_regs->usbcmd);
307
308 /* read the endpoint status */
309 epstatus = readl(&udc->op_regs->epstatus) & bit_pos;
310
311 /*
312 * Reread the ATDTW semaphore bit to check if it is
313 * cleared. When hardware see a hazard, it will clear
314 * the bit or else we remain set to 1 and we can
315 * proceed with priming of endpoint if not already
316 * primed.
317 */
318 if (readl(&udc->op_regs->usbcmd)
319 & USBCMD_ATDTW_TRIPWIRE_SET)
320 break;
321
322 loops--;
323 if (loops == 0) {
324 dev_err(&udc->dev->dev,
325 "Timeout for ATDTW_TRIPWIRE...\n");
326 retval = -ETIME;
327 goto done;
328 }
329 udelay(LOOPS_USEC);
330 }
331
332 /* Clear the semaphore */
333 usbcmd = readl(&udc->op_regs->usbcmd);
334 usbcmd &= USBCMD_ATDTW_TRIPWIRE_CLEAR;
335 writel(usbcmd, &udc->op_regs->usbcmd);
336
337 if (epstatus)
338 goto done;
339 }
340
341 /* Write dQH next pointer and terminate bit to 0 */
342 dqh->next_dtd_ptr = req->head->td_dma
343 & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
344
345 /* clear active and halt bit, in case set from a previous error */
346 dqh->size_ioc_int_sts &= ~(DTD_STATUS_ACTIVE | DTD_STATUS_HALTED);
347
348 /* Ensure that updates to the QH will occure before priming. */
349 wmb();
350
351 /* Prime the Endpoint */
352 writel(bit_pos, &udc->op_regs->epprime);
353
354 done:
355 return retval;
356 }
357
358 static struct mv_dtd *build_dtd(struct mv_req *req, unsigned *length,
359 dma_addr_t *dma, int *is_last)
360 {
361 struct mv_dtd *dtd;
362 struct mv_udc *udc;
363 struct mv_dqh *dqh;
364 u32 temp, mult = 0;
365
366 /* how big will this transfer be? */
367 if (usb_endpoint_xfer_isoc(req->ep->ep.desc)) {
368 dqh = req->ep->dqh;
369 mult = (dqh->max_packet_length >> EP_QUEUE_HEAD_MULT_POS)
370 & 0x3;
371 *length = min(req->req.length - req->req.actual,
372 (unsigned)(mult * req->ep->ep.maxpacket));
373 } else
374 *length = min(req->req.length - req->req.actual,
375 (unsigned)EP_MAX_LENGTH_TRANSFER);
376
377 udc = req->ep->udc;
378
379 /*
380 * Be careful that no _GFP_HIGHMEM is set,
381 * or we can not use dma_to_virt
382 */
383 dtd = dma_pool_alloc(udc->dtd_pool, GFP_ATOMIC, dma);
384 if (dtd == NULL)
385 return dtd;
386
387 dtd->td_dma = *dma;
388 /* initialize buffer page pointers */
389 temp = (u32)(req->req.dma + req->req.actual);
390 dtd->buff_ptr0 = cpu_to_le32(temp);
391 temp &= ~0xFFF;
392 dtd->buff_ptr1 = cpu_to_le32(temp + 0x1000);
393 dtd->buff_ptr2 = cpu_to_le32(temp + 0x2000);
394 dtd->buff_ptr3 = cpu_to_le32(temp + 0x3000);
395 dtd->buff_ptr4 = cpu_to_le32(temp + 0x4000);
396
397 req->req.actual += *length;
398
399 /* zlp is needed if req->req.zero is set */
400 if (req->req.zero) {
401 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
402 *is_last = 1;
403 else
404 *is_last = 0;
405 } else if (req->req.length == req->req.actual)
406 *is_last = 1;
407 else
408 *is_last = 0;
409
410 /* Fill in the transfer size; set active bit */
411 temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
412
413 /* Enable interrupt for the last dtd of a request */
414 if (*is_last && !req->req.no_interrupt)
415 temp |= DTD_IOC;
416
417 temp |= mult << 10;
418
419 dtd->size_ioc_sts = temp;
420
421 mb();
422
423 return dtd;
424 }
425
426 /* generate dTD linked list for a request */
427 static int req_to_dtd(struct mv_req *req)
428 {
429 unsigned count;
430 int is_last, is_first = 1;
431 struct mv_dtd *dtd, *last_dtd = NULL;
432 struct mv_udc *udc;
433 dma_addr_t dma;
434
435 udc = req->ep->udc;
436
437 do {
438 dtd = build_dtd(req, &count, &dma, &is_last);
439 if (dtd == NULL)
440 return -ENOMEM;
441
442 if (is_first) {
443 is_first = 0;
444 req->head = dtd;
445 } else {
446 last_dtd->dtd_next = dma;
447 last_dtd->next_dtd_virt = dtd;
448 }
449 last_dtd = dtd;
450 req->dtd_count++;
451 } while (!is_last);
452
453 /* set terminate bit to 1 for the last dTD */
454 dtd->dtd_next = DTD_NEXT_TERMINATE;
455
456 req->tail = dtd;
457
458 return 0;
459 }
460
461 static int mv_ep_enable(struct usb_ep *_ep,
462 const struct usb_endpoint_descriptor *desc)
463 {
464 struct mv_udc *udc;
465 struct mv_ep *ep;
466 struct mv_dqh *dqh;
467 u16 max = 0;
468 u32 bit_pos, epctrlx, direction;
469 unsigned char zlt = 0, ios = 0, mult = 0;
470 unsigned long flags;
471
472 ep = container_of(_ep, struct mv_ep, ep);
473 udc = ep->udc;
474
475 if (!_ep || !desc
476 || desc->bDescriptorType != USB_DT_ENDPOINT)
477 return -EINVAL;
478
479 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
480 return -ESHUTDOWN;
481
482 direction = ep_dir(ep);
483 max = usb_endpoint_maxp(desc);
484
485 /*
486 * disable HW zero length termination select
487 * driver handles zero length packet through req->req.zero
488 */
489 zlt = 1;
490
491 bit_pos = 1 << ((direction == EP_DIR_OUT ? 0 : 16) + ep->ep_num);
492
493 /* Check if the Endpoint is Primed */
494 if ((readl(&udc->op_regs->epprime) & bit_pos)
495 || (readl(&udc->op_regs->epstatus) & bit_pos)) {
496 dev_info(&udc->dev->dev,
497 "ep=%d %s: Init ERROR: ENDPTPRIME=0x%x,"
498 " ENDPTSTATUS=0x%x, bit_pos=0x%x\n",
499 (unsigned)ep->ep_num, direction ? "SEND" : "RECV",
500 (unsigned)readl(&udc->op_regs->epprime),
501 (unsigned)readl(&udc->op_regs->epstatus),
502 (unsigned)bit_pos);
503 goto en_done;
504 }
505 /* Set the max packet length, interrupt on Setup and Mult fields */
506 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
507 case USB_ENDPOINT_XFER_BULK:
508 zlt = 1;
509 mult = 0;
510 break;
511 case USB_ENDPOINT_XFER_CONTROL:
512 ios = 1;
513 case USB_ENDPOINT_XFER_INT:
514 mult = 0;
515 break;
516 case USB_ENDPOINT_XFER_ISOC:
517 /* Calculate transactions needed for high bandwidth iso */
518 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
519 max = max & 0x7ff; /* bit 0~10 */
520 /* 3 transactions at most */
521 if (mult > 3)
522 goto en_done;
523 break;
524 default:
525 goto en_done;
526 }
527
528 spin_lock_irqsave(&udc->lock, flags);
529 /* Get the endpoint queue head address */
530 dqh = ep->dqh;
531 dqh->max_packet_length = (max << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
532 | (mult << EP_QUEUE_HEAD_MULT_POS)
533 | (zlt ? EP_QUEUE_HEAD_ZLT_SEL : 0)
534 | (ios ? EP_QUEUE_HEAD_IOS : 0);
535 dqh->next_dtd_ptr = 1;
536 dqh->size_ioc_int_sts = 0;
537
538 ep->ep.maxpacket = max;
539 ep->ep.desc = desc;
540 ep->stopped = 0;
541
542 /* Enable the endpoint for Rx or Tx and set the endpoint type */
543 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
544 if (direction == EP_DIR_IN) {
545 epctrlx &= ~EPCTRL_TX_ALL_MASK;
546 epctrlx |= EPCTRL_TX_ENABLE | EPCTRL_TX_DATA_TOGGLE_RST
547 | ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
548 << EPCTRL_TX_EP_TYPE_SHIFT);
549 } else {
550 epctrlx &= ~EPCTRL_RX_ALL_MASK;
551 epctrlx |= EPCTRL_RX_ENABLE | EPCTRL_RX_DATA_TOGGLE_RST
552 | ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
553 << EPCTRL_RX_EP_TYPE_SHIFT);
554 }
555 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
556
557 /*
558 * Implement Guideline (GL# USB-7) The unused endpoint type must
559 * be programmed to bulk.
560 */
561 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
562 if ((epctrlx & EPCTRL_RX_ENABLE) == 0) {
563 epctrlx |= (USB_ENDPOINT_XFER_BULK
564 << EPCTRL_RX_EP_TYPE_SHIFT);
565 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
566 }
567
568 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
569 if ((epctrlx & EPCTRL_TX_ENABLE) == 0) {
570 epctrlx |= (USB_ENDPOINT_XFER_BULK
571 << EPCTRL_TX_EP_TYPE_SHIFT);
572 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
573 }
574
575 spin_unlock_irqrestore(&udc->lock, flags);
576
577 return 0;
578 en_done:
579 return -EINVAL;
580 }
581
582 static int mv_ep_disable(struct usb_ep *_ep)
583 {
584 struct mv_udc *udc;
585 struct mv_ep *ep;
586 struct mv_dqh *dqh;
587 u32 bit_pos, epctrlx, direction;
588 unsigned long flags;
589
590 ep = container_of(_ep, struct mv_ep, ep);
591 if ((_ep == NULL) || !ep->ep.desc)
592 return -EINVAL;
593
594 udc = ep->udc;
595
596 /* Get the endpoint queue head address */
597 dqh = ep->dqh;
598
599 spin_lock_irqsave(&udc->lock, flags);
600
601 direction = ep_dir(ep);
602 bit_pos = 1 << ((direction == EP_DIR_OUT ? 0 : 16) + ep->ep_num);
603
604 /* Reset the max packet length and the interrupt on Setup */
605 dqh->max_packet_length = 0;
606
607 /* Disable the endpoint for Rx or Tx and reset the endpoint type */
608 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
609 epctrlx &= ~((direction == EP_DIR_IN)
610 ? (EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE)
611 : (EPCTRL_RX_ENABLE | EPCTRL_RX_TYPE));
612 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
613
614 /* nuke all pending requests (does flush) */
615 nuke(ep, -ESHUTDOWN);
616
617 ep->ep.desc = NULL;
618 ep->stopped = 1;
619
620 spin_unlock_irqrestore(&udc->lock, flags);
621
622 return 0;
623 }
624
625 static struct usb_request *
626 mv_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
627 {
628 struct mv_req *req = NULL;
629
630 req = kzalloc(sizeof *req, gfp_flags);
631 if (!req)
632 return NULL;
633
634 req->req.dma = DMA_ADDR_INVALID;
635 INIT_LIST_HEAD(&req->queue);
636
637 return &req->req;
638 }
639
640 static void mv_free_request(struct usb_ep *_ep, struct usb_request *_req)
641 {
642 struct mv_req *req = NULL;
643
644 req = container_of(_req, struct mv_req, req);
645
646 if (_req)
647 kfree(req);
648 }
649
650 static void mv_ep_fifo_flush(struct usb_ep *_ep)
651 {
652 struct mv_udc *udc;
653 u32 bit_pos, direction;
654 struct mv_ep *ep;
655 unsigned int loops;
656
657 if (!_ep)
658 return;
659
660 ep = container_of(_ep, struct mv_ep, ep);
661 if (!ep->ep.desc)
662 return;
663
664 udc = ep->udc;
665 direction = ep_dir(ep);
666
667 if (ep->ep_num == 0)
668 bit_pos = (1 << 16) | 1;
669 else if (direction == EP_DIR_OUT)
670 bit_pos = 1 << ep->ep_num;
671 else
672 bit_pos = 1 << (16 + ep->ep_num);
673
674 loops = LOOPS(EPSTATUS_TIMEOUT);
675 do {
676 unsigned int inter_loops;
677
678 if (loops == 0) {
679 dev_err(&udc->dev->dev,
680 "TIMEOUT for ENDPTSTATUS=0x%x, bit_pos=0x%x\n",
681 (unsigned)readl(&udc->op_regs->epstatus),
682 (unsigned)bit_pos);
683 return;
684 }
685 /* Write 1 to the Flush register */
686 writel(bit_pos, &udc->op_regs->epflush);
687
688 /* Wait until flushing completed */
689 inter_loops = LOOPS(FLUSH_TIMEOUT);
690 while (readl(&udc->op_regs->epflush)) {
691 /*
692 * ENDPTFLUSH bit should be cleared to indicate this
693 * operation is complete
694 */
695 if (inter_loops == 0) {
696 dev_err(&udc->dev->dev,
697 "TIMEOUT for ENDPTFLUSH=0x%x,"
698 "bit_pos=0x%x\n",
699 (unsigned)readl(&udc->op_regs->epflush),
700 (unsigned)bit_pos);
701 return;
702 }
703 inter_loops--;
704 udelay(LOOPS_USEC);
705 }
706 loops--;
707 } while (readl(&udc->op_regs->epstatus) & bit_pos);
708 }
709
710 /* queues (submits) an I/O request to an endpoint */
711 static int
712 mv_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
713 {
714 struct mv_ep *ep = container_of(_ep, struct mv_ep, ep);
715 struct mv_req *req = container_of(_req, struct mv_req, req);
716 struct mv_udc *udc = ep->udc;
717 unsigned long flags;
718 int retval;
719
720 /* catch various bogus parameters */
721 if (!_req || !req->req.complete || !req->req.buf
722 || !list_empty(&req->queue)) {
723 dev_err(&udc->dev->dev, "%s, bad params", __func__);
724 return -EINVAL;
725 }
726 if (unlikely(!_ep || !ep->ep.desc)) {
727 dev_err(&udc->dev->dev, "%s, bad ep", __func__);
728 return -EINVAL;
729 }
730
731 udc = ep->udc;
732 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
733 return -ESHUTDOWN;
734
735 req->ep = ep;
736
737 /* map virtual address to hardware */
738 if (req->req.dma == DMA_ADDR_INVALID) {
739 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
740 req->req.buf,
741 req->req.length, ep_dir(ep)
742 ? DMA_TO_DEVICE
743 : DMA_FROM_DEVICE);
744 req->mapped = 1;
745 } else {
746 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
747 req->req.dma, req->req.length,
748 ep_dir(ep)
749 ? DMA_TO_DEVICE
750 : DMA_FROM_DEVICE);
751 req->mapped = 0;
752 }
753
754 req->req.status = -EINPROGRESS;
755 req->req.actual = 0;
756 req->dtd_count = 0;
757
758 spin_lock_irqsave(&udc->lock, flags);
759
760 /* build dtds and push them to device queue */
761 if (!req_to_dtd(req)) {
762 retval = queue_dtd(ep, req);
763 if (retval) {
764 spin_unlock_irqrestore(&udc->lock, flags);
765 dev_err(&udc->dev->dev, "Failed to queue dtd\n");
766 goto err_unmap_dma;
767 }
768 } else {
769 spin_unlock_irqrestore(&udc->lock, flags);
770 dev_err(&udc->dev->dev, "Failed to dma_pool_alloc\n");
771 retval = -ENOMEM;
772 goto err_unmap_dma;
773 }
774
775 /* Update ep0 state */
776 if (ep->ep_num == 0)
777 udc->ep0_state = DATA_STATE_XMIT;
778
779 /* irq handler advances the queue */
780 list_add_tail(&req->queue, &ep->queue);
781 spin_unlock_irqrestore(&udc->lock, flags);
782
783 return 0;
784
785 err_unmap_dma:
786 if (req->mapped) {
787 dma_unmap_single(ep->udc->gadget.dev.parent,
788 req->req.dma, req->req.length,
789 ((ep_dir(ep) == EP_DIR_IN) ?
790 DMA_TO_DEVICE : DMA_FROM_DEVICE));
791 req->req.dma = DMA_ADDR_INVALID;
792 req->mapped = 0;
793 } else
794 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
795 req->req.dma, req->req.length,
796 ((ep_dir(ep) == EP_DIR_IN) ?
797 DMA_TO_DEVICE : DMA_FROM_DEVICE));
798
799 return retval;
800 }
801
802 static void mv_prime_ep(struct mv_ep *ep, struct mv_req *req)
803 {
804 struct mv_dqh *dqh = ep->dqh;
805 u32 bit_pos;
806
807 /* Write dQH next pointer and terminate bit to 0 */
808 dqh->next_dtd_ptr = req->head->td_dma
809 & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
810
811 /* clear active and halt bit, in case set from a previous error */
812 dqh->size_ioc_int_sts &= ~(DTD_STATUS_ACTIVE | DTD_STATUS_HALTED);
813
814 /* Ensure that updates to the QH will occure before priming. */
815 wmb();
816
817 bit_pos = 1 << (((ep_dir(ep) == EP_DIR_OUT) ? 0 : 16) + ep->ep_num);
818
819 /* Prime the Endpoint */
820 writel(bit_pos, &ep->udc->op_regs->epprime);
821 }
822
823 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
824 static int mv_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
825 {
826 struct mv_ep *ep = container_of(_ep, struct mv_ep, ep);
827 struct mv_req *req;
828 struct mv_udc *udc = ep->udc;
829 unsigned long flags;
830 int stopped, ret = 0;
831 u32 epctrlx;
832
833 if (!_ep || !_req)
834 return -EINVAL;
835
836 spin_lock_irqsave(&ep->udc->lock, flags);
837 stopped = ep->stopped;
838
839 /* Stop the ep before we deal with the queue */
840 ep->stopped = 1;
841 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
842 if (ep_dir(ep) == EP_DIR_IN)
843 epctrlx &= ~EPCTRL_TX_ENABLE;
844 else
845 epctrlx &= ~EPCTRL_RX_ENABLE;
846 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
847
848 /* make sure it's actually queued on this endpoint */
849 list_for_each_entry(req, &ep->queue, queue) {
850 if (&req->req == _req)
851 break;
852 }
853 if (&req->req != _req) {
854 ret = -EINVAL;
855 goto out;
856 }
857
858 /* The request is in progress, or completed but not dequeued */
859 if (ep->queue.next == &req->queue) {
860 _req->status = -ECONNRESET;
861 mv_ep_fifo_flush(_ep); /* flush current transfer */
862
863 /* The request isn't the last request in this ep queue */
864 if (req->queue.next != &ep->queue) {
865 struct mv_req *next_req;
866
867 next_req = list_entry(req->queue.next,
868 struct mv_req, queue);
869
870 /* Point the QH to the first TD of next request */
871 mv_prime_ep(ep, next_req);
872 } else {
873 struct mv_dqh *qh;
874
875 qh = ep->dqh;
876 qh->next_dtd_ptr = 1;
877 qh->size_ioc_int_sts = 0;
878 }
879
880 /* The request hasn't been processed, patch up the TD chain */
881 } else {
882 struct mv_req *prev_req;
883
884 prev_req = list_entry(req->queue.prev, struct mv_req, queue);
885 writel(readl(&req->tail->dtd_next),
886 &prev_req->tail->dtd_next);
887
888 }
889
890 done(ep, req, -ECONNRESET);
891
892 /* Enable EP */
893 out:
894 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
895 if (ep_dir(ep) == EP_DIR_IN)
896 epctrlx |= EPCTRL_TX_ENABLE;
897 else
898 epctrlx |= EPCTRL_RX_ENABLE;
899 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
900 ep->stopped = stopped;
901
902 spin_unlock_irqrestore(&ep->udc->lock, flags);
903 return ret;
904 }
905
906 static void ep_set_stall(struct mv_udc *udc, u8 ep_num, u8 direction, int stall)
907 {
908 u32 epctrlx;
909
910 epctrlx = readl(&udc->op_regs->epctrlx[ep_num]);
911
912 if (stall) {
913 if (direction == EP_DIR_IN)
914 epctrlx |= EPCTRL_TX_EP_STALL;
915 else
916 epctrlx |= EPCTRL_RX_EP_STALL;
917 } else {
918 if (direction == EP_DIR_IN) {
919 epctrlx &= ~EPCTRL_TX_EP_STALL;
920 epctrlx |= EPCTRL_TX_DATA_TOGGLE_RST;
921 } else {
922 epctrlx &= ~EPCTRL_RX_EP_STALL;
923 epctrlx |= EPCTRL_RX_DATA_TOGGLE_RST;
924 }
925 }
926 writel(epctrlx, &udc->op_regs->epctrlx[ep_num]);
927 }
928
929 static int ep_is_stall(struct mv_udc *udc, u8 ep_num, u8 direction)
930 {
931 u32 epctrlx;
932
933 epctrlx = readl(&udc->op_regs->epctrlx[ep_num]);
934
935 if (direction == EP_DIR_OUT)
936 return (epctrlx & EPCTRL_RX_EP_STALL) ? 1 : 0;
937 else
938 return (epctrlx & EPCTRL_TX_EP_STALL) ? 1 : 0;
939 }
940
941 static int mv_ep_set_halt_wedge(struct usb_ep *_ep, int halt, int wedge)
942 {
943 struct mv_ep *ep;
944 unsigned long flags = 0;
945 int status = 0;
946 struct mv_udc *udc;
947
948 ep = container_of(_ep, struct mv_ep, ep);
949 udc = ep->udc;
950 if (!_ep || !ep->ep.desc) {
951 status = -EINVAL;
952 goto out;
953 }
954
955 if (ep->ep.desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
956 status = -EOPNOTSUPP;
957 goto out;
958 }
959
960 /*
961 * Attempt to halt IN ep will fail if any transfer requests
962 * are still queue
963 */
964 if (halt && (ep_dir(ep) == EP_DIR_IN) && !list_empty(&ep->queue)) {
965 status = -EAGAIN;
966 goto out;
967 }
968
969 spin_lock_irqsave(&ep->udc->lock, flags);
970 ep_set_stall(udc, ep->ep_num, ep_dir(ep), halt);
971 if (halt && wedge)
972 ep->wedge = 1;
973 else if (!halt)
974 ep->wedge = 0;
975 spin_unlock_irqrestore(&ep->udc->lock, flags);
976
977 if (ep->ep_num == 0) {
978 udc->ep0_state = WAIT_FOR_SETUP;
979 udc->ep0_dir = EP_DIR_OUT;
980 }
981 out:
982 return status;
983 }
984
985 static int mv_ep_set_halt(struct usb_ep *_ep, int halt)
986 {
987 return mv_ep_set_halt_wedge(_ep, halt, 0);
988 }
989
990 static int mv_ep_set_wedge(struct usb_ep *_ep)
991 {
992 return mv_ep_set_halt_wedge(_ep, 1, 1);
993 }
994
995 static struct usb_ep_ops mv_ep_ops = {
996 .enable = mv_ep_enable,
997 .disable = mv_ep_disable,
998
999 .alloc_request = mv_alloc_request,
1000 .free_request = mv_free_request,
1001
1002 .queue = mv_ep_queue,
1003 .dequeue = mv_ep_dequeue,
1004
1005 .set_wedge = mv_ep_set_wedge,
1006 .set_halt = mv_ep_set_halt,
1007 .fifo_flush = mv_ep_fifo_flush, /* flush fifo */
1008 };
1009
1010 static void udc_clock_enable(struct mv_udc *udc)
1011 {
1012 unsigned int i;
1013
1014 for (i = 0; i < udc->clknum; i++)
1015 clk_enable(udc->clk[i]);
1016 }
1017
1018 static void udc_clock_disable(struct mv_udc *udc)
1019 {
1020 unsigned int i;
1021
1022 for (i = 0; i < udc->clknum; i++)
1023 clk_disable(udc->clk[i]);
1024 }
1025
1026 static void udc_stop(struct mv_udc *udc)
1027 {
1028 u32 tmp;
1029
1030 /* Disable interrupts */
1031 tmp = readl(&udc->op_regs->usbintr);
1032 tmp &= ~(USBINTR_INT_EN | USBINTR_ERR_INT_EN |
1033 USBINTR_PORT_CHANGE_DETECT_EN | USBINTR_RESET_EN);
1034 writel(tmp, &udc->op_regs->usbintr);
1035
1036 udc->stopped = 1;
1037
1038 /* Reset the Run the bit in the command register to stop VUSB */
1039 tmp = readl(&udc->op_regs->usbcmd);
1040 tmp &= ~USBCMD_RUN_STOP;
1041 writel(tmp, &udc->op_regs->usbcmd);
1042 }
1043
1044 static void udc_start(struct mv_udc *udc)
1045 {
1046 u32 usbintr;
1047
1048 usbintr = USBINTR_INT_EN | USBINTR_ERR_INT_EN
1049 | USBINTR_PORT_CHANGE_DETECT_EN
1050 | USBINTR_RESET_EN | USBINTR_DEVICE_SUSPEND;
1051 /* Enable interrupts */
1052 writel(usbintr, &udc->op_regs->usbintr);
1053
1054 udc->stopped = 0;
1055
1056 /* Set the Run bit in the command register */
1057 writel(USBCMD_RUN_STOP, &udc->op_regs->usbcmd);
1058 }
1059
1060 static int udc_reset(struct mv_udc *udc)
1061 {
1062 unsigned int loops;
1063 u32 tmp, portsc;
1064
1065 /* Stop the controller */
1066 tmp = readl(&udc->op_regs->usbcmd);
1067 tmp &= ~USBCMD_RUN_STOP;
1068 writel(tmp, &udc->op_regs->usbcmd);
1069
1070 /* Reset the controller to get default values */
1071 writel(USBCMD_CTRL_RESET, &udc->op_regs->usbcmd);
1072
1073 /* wait for reset to complete */
1074 loops = LOOPS(RESET_TIMEOUT);
1075 while (readl(&udc->op_regs->usbcmd) & USBCMD_CTRL_RESET) {
1076 if (loops == 0) {
1077 dev_err(&udc->dev->dev,
1078 "Wait for RESET completed TIMEOUT\n");
1079 return -ETIMEDOUT;
1080 }
1081 loops--;
1082 udelay(LOOPS_USEC);
1083 }
1084
1085 /* set controller to device mode */
1086 tmp = readl(&udc->op_regs->usbmode);
1087 tmp |= USBMODE_CTRL_MODE_DEVICE;
1088
1089 /* turn setup lockout off, require setup tripwire in usbcmd */
1090 tmp |= USBMODE_SETUP_LOCK_OFF;
1091
1092 writel(tmp, &udc->op_regs->usbmode);
1093
1094 writel(0x0, &udc->op_regs->epsetupstat);
1095
1096 /* Configure the Endpoint List Address */
1097 writel(udc->ep_dqh_dma & USB_EP_LIST_ADDRESS_MASK,
1098 &udc->op_regs->eplistaddr);
1099
1100 portsc = readl(&udc->op_regs->portsc[0]);
1101 if (readl(&udc->cap_regs->hcsparams) & HCSPARAMS_PPC)
1102 portsc &= (~PORTSCX_W1C_BITS | ~PORTSCX_PORT_POWER);
1103
1104 if (udc->force_fs)
1105 portsc |= PORTSCX_FORCE_FULL_SPEED_CONNECT;
1106 else
1107 portsc &= (~PORTSCX_FORCE_FULL_SPEED_CONNECT);
1108
1109 writel(portsc, &udc->op_regs->portsc[0]);
1110
1111 tmp = readl(&udc->op_regs->epctrlx[0]);
1112 tmp &= ~(EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL);
1113 writel(tmp, &udc->op_regs->epctrlx[0]);
1114
1115 return 0;
1116 }
1117
1118 static int mv_udc_enable_internal(struct mv_udc *udc)
1119 {
1120 int retval;
1121
1122 if (udc->active)
1123 return 0;
1124
1125 dev_dbg(&udc->dev->dev, "enable udc\n");
1126 udc_clock_enable(udc);
1127 if (udc->pdata->phy_init) {
1128 retval = udc->pdata->phy_init(udc->phy_regs);
1129 if (retval) {
1130 dev_err(&udc->dev->dev,
1131 "init phy error %d\n", retval);
1132 udc_clock_disable(udc);
1133 return retval;
1134 }
1135 }
1136 udc->active = 1;
1137
1138 return 0;
1139 }
1140
1141 static int mv_udc_enable(struct mv_udc *udc)
1142 {
1143 if (udc->clock_gating)
1144 return mv_udc_enable_internal(udc);
1145
1146 return 0;
1147 }
1148
1149 static void mv_udc_disable_internal(struct mv_udc *udc)
1150 {
1151 if (udc->active) {
1152 dev_dbg(&udc->dev->dev, "disable udc\n");
1153 if (udc->pdata->phy_deinit)
1154 udc->pdata->phy_deinit(udc->phy_regs);
1155 udc_clock_disable(udc);
1156 udc->active = 0;
1157 }
1158 }
1159
1160 static void mv_udc_disable(struct mv_udc *udc)
1161 {
1162 if (udc->clock_gating)
1163 mv_udc_disable_internal(udc);
1164 }
1165
1166 static int mv_udc_get_frame(struct usb_gadget *gadget)
1167 {
1168 struct mv_udc *udc;
1169 u16 retval;
1170
1171 if (!gadget)
1172 return -ENODEV;
1173
1174 udc = container_of(gadget, struct mv_udc, gadget);
1175
1176 retval = readl(&udc->op_regs->frindex) & USB_FRINDEX_MASKS;
1177
1178 return retval;
1179 }
1180
1181 /* Tries to wake up the host connected to this gadget */
1182 static int mv_udc_wakeup(struct usb_gadget *gadget)
1183 {
1184 struct mv_udc *udc = container_of(gadget, struct mv_udc, gadget);
1185 u32 portsc;
1186
1187 /* Remote wakeup feature not enabled by host */
1188 if (!udc->remote_wakeup)
1189 return -ENOTSUPP;
1190
1191 portsc = readl(&udc->op_regs->portsc);
1192 /* not suspended? */
1193 if (!(portsc & PORTSCX_PORT_SUSPEND))
1194 return 0;
1195 /* trigger force resume */
1196 portsc |= PORTSCX_PORT_FORCE_RESUME;
1197 writel(portsc, &udc->op_regs->portsc[0]);
1198 return 0;
1199 }
1200
1201 static int mv_udc_vbus_session(struct usb_gadget *gadget, int is_active)
1202 {
1203 struct mv_udc *udc;
1204 unsigned long flags;
1205 int retval = 0;
1206
1207 udc = container_of(gadget, struct mv_udc, gadget);
1208 spin_lock_irqsave(&udc->lock, flags);
1209
1210 udc->vbus_active = (is_active != 0);
1211
1212 dev_dbg(&udc->dev->dev, "%s: softconnect %d, vbus_active %d\n",
1213 __func__, udc->softconnect, udc->vbus_active);
1214
1215 if (udc->driver && udc->softconnect && udc->vbus_active) {
1216 retval = mv_udc_enable(udc);
1217 if (retval == 0) {
1218 /* Clock is disabled, need re-init registers */
1219 udc_reset(udc);
1220 ep0_reset(udc);
1221 udc_start(udc);
1222 }
1223 } else if (udc->driver && udc->softconnect) {
1224 if (!udc->active)
1225 goto out;
1226
1227 /* stop all the transfer in queue*/
1228 stop_activity(udc, udc->driver);
1229 udc_stop(udc);
1230 mv_udc_disable(udc);
1231 }
1232
1233 out:
1234 spin_unlock_irqrestore(&udc->lock, flags);
1235 return retval;
1236 }
1237
1238 static int mv_udc_pullup(struct usb_gadget *gadget, int is_on)
1239 {
1240 struct mv_udc *udc;
1241 unsigned long flags;
1242 int retval = 0;
1243
1244 udc = container_of(gadget, struct mv_udc, gadget);
1245 spin_lock_irqsave(&udc->lock, flags);
1246
1247 udc->softconnect = (is_on != 0);
1248
1249 dev_dbg(&udc->dev->dev, "%s: softconnect %d, vbus_active %d\n",
1250 __func__, udc->softconnect, udc->vbus_active);
1251
1252 if (udc->driver && udc->softconnect && udc->vbus_active) {
1253 retval = mv_udc_enable(udc);
1254 if (retval == 0) {
1255 /* Clock is disabled, need re-init registers */
1256 udc_reset(udc);
1257 ep0_reset(udc);
1258 udc_start(udc);
1259 }
1260 } else if (udc->driver && udc->vbus_active) {
1261 /* stop all the transfer in queue*/
1262 stop_activity(udc, udc->driver);
1263 udc_stop(udc);
1264 mv_udc_disable(udc);
1265 }
1266
1267 spin_unlock_irqrestore(&udc->lock, flags);
1268 return retval;
1269 }
1270
1271 static int mv_udc_start(struct usb_gadget_driver *driver,
1272 int (*bind)(struct usb_gadget *, struct usb_gadget_driver *));
1273 static int mv_udc_stop(struct usb_gadget_driver *driver);
1274 /* device controller usb_gadget_ops structure */
1275 static const struct usb_gadget_ops mv_ops = {
1276
1277 /* returns the current frame number */
1278 .get_frame = mv_udc_get_frame,
1279
1280 /* tries to wake up the host connected to this gadget */
1281 .wakeup = mv_udc_wakeup,
1282
1283 /* notify controller that VBUS is powered or not */
1284 .vbus_session = mv_udc_vbus_session,
1285
1286 /* D+ pullup, software-controlled connect/disconnect to USB host */
1287 .pullup = mv_udc_pullup,
1288 .start = mv_udc_start,
1289 .stop = mv_udc_stop,
1290 };
1291
1292 static int eps_init(struct mv_udc *udc)
1293 {
1294 struct mv_ep *ep;
1295 char name[14];
1296 int i;
1297
1298 /* initialize ep0 */
1299 ep = &udc->eps[0];
1300 ep->udc = udc;
1301 strncpy(ep->name, "ep0", sizeof(ep->name));
1302 ep->ep.name = ep->name;
1303 ep->ep.ops = &mv_ep_ops;
1304 ep->wedge = 0;
1305 ep->stopped = 0;
1306 ep->ep.maxpacket = EP0_MAX_PKT_SIZE;
1307 ep->ep_num = 0;
1308 ep->ep.desc = &mv_ep0_desc;
1309 INIT_LIST_HEAD(&ep->queue);
1310
1311 ep->ep_type = USB_ENDPOINT_XFER_CONTROL;
1312
1313 /* initialize other endpoints */
1314 for (i = 2; i < udc->max_eps * 2; i++) {
1315 ep = &udc->eps[i];
1316 if (i % 2) {
1317 snprintf(name, sizeof(name), "ep%din", i / 2);
1318 ep->direction = EP_DIR_IN;
1319 } else {
1320 snprintf(name, sizeof(name), "ep%dout", i / 2);
1321 ep->direction = EP_DIR_OUT;
1322 }
1323 ep->udc = udc;
1324 strncpy(ep->name, name, sizeof(ep->name));
1325 ep->ep.name = ep->name;
1326
1327 ep->ep.ops = &mv_ep_ops;
1328 ep->stopped = 0;
1329 ep->ep.maxpacket = (unsigned short) ~0;
1330 ep->ep_num = i / 2;
1331
1332 INIT_LIST_HEAD(&ep->queue);
1333 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
1334
1335 ep->dqh = &udc->ep_dqh[i];
1336 }
1337
1338 return 0;
1339 }
1340
1341 /* delete all endpoint requests, called with spinlock held */
1342 static void nuke(struct mv_ep *ep, int status)
1343 {
1344 /* called with spinlock held */
1345 ep->stopped = 1;
1346
1347 /* endpoint fifo flush */
1348 mv_ep_fifo_flush(&ep->ep);
1349
1350 while (!list_empty(&ep->queue)) {
1351 struct mv_req *req = NULL;
1352 req = list_entry(ep->queue.next, struct mv_req, queue);
1353 done(ep, req, status);
1354 }
1355 }
1356
1357 /* stop all USB activities */
1358 static void stop_activity(struct mv_udc *udc, struct usb_gadget_driver *driver)
1359 {
1360 struct mv_ep *ep;
1361
1362 nuke(&udc->eps[0], -ESHUTDOWN);
1363
1364 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
1365 nuke(ep, -ESHUTDOWN);
1366 }
1367
1368 /* report disconnect; the driver is already quiesced */
1369 if (driver) {
1370 spin_unlock(&udc->lock);
1371 driver->disconnect(&udc->gadget);
1372 spin_lock(&udc->lock);
1373 }
1374 }
1375
1376 static int mv_udc_start(struct usb_gadget_driver *driver,
1377 int (*bind)(struct usb_gadget *, struct usb_gadget_driver *))
1378 {
1379 struct mv_udc *udc = the_controller;
1380 int retval = 0;
1381 unsigned long flags;
1382
1383 if (!udc)
1384 return -ENODEV;
1385
1386 if (udc->driver)
1387 return -EBUSY;
1388
1389 spin_lock_irqsave(&udc->lock, flags);
1390
1391 /* hook up the driver ... */
1392 driver->driver.bus = NULL;
1393 udc->driver = driver;
1394 udc->gadget.dev.driver = &driver->driver;
1395
1396 udc->usb_state = USB_STATE_ATTACHED;
1397 udc->ep0_state = WAIT_FOR_SETUP;
1398 udc->ep0_dir = EP_DIR_OUT;
1399
1400 spin_unlock_irqrestore(&udc->lock, flags);
1401
1402 retval = bind(&udc->gadget, driver);
1403 if (retval) {
1404 dev_err(&udc->dev->dev, "bind to driver %s --> %d\n",
1405 driver->driver.name, retval);
1406 udc->driver = NULL;
1407 udc->gadget.dev.driver = NULL;
1408 return retval;
1409 }
1410
1411 if (!IS_ERR_OR_NULL(udc->transceiver)) {
1412 retval = otg_set_peripheral(udc->transceiver->otg,
1413 &udc->gadget);
1414 if (retval) {
1415 dev_err(&udc->dev->dev,
1416 "unable to register peripheral to otg\n");
1417 if (driver->unbind) {
1418 driver->unbind(&udc->gadget);
1419 udc->gadget.dev.driver = NULL;
1420 udc->driver = NULL;
1421 }
1422 return retval;
1423 }
1424 }
1425
1426 /* pullup is always on */
1427 mv_udc_pullup(&udc->gadget, 1);
1428
1429 /* When boot with cable attached, there will be no vbus irq occurred */
1430 if (udc->qwork)
1431 queue_work(udc->qwork, &udc->vbus_work);
1432
1433 return 0;
1434 }
1435
1436 static int mv_udc_stop(struct usb_gadget_driver *driver)
1437 {
1438 struct mv_udc *udc = the_controller;
1439 unsigned long flags;
1440
1441 if (!udc)
1442 return -ENODEV;
1443
1444 spin_lock_irqsave(&udc->lock, flags);
1445
1446 mv_udc_enable(udc);
1447 udc_stop(udc);
1448
1449 /* stop all usb activities */
1450 udc->gadget.speed = USB_SPEED_UNKNOWN;
1451 stop_activity(udc, driver);
1452 mv_udc_disable(udc);
1453
1454 spin_unlock_irqrestore(&udc->lock, flags);
1455
1456 /* unbind gadget driver */
1457 driver->unbind(&udc->gadget);
1458 udc->gadget.dev.driver = NULL;
1459 udc->driver = NULL;
1460
1461 return 0;
1462 }
1463
1464 static void mv_set_ptc(struct mv_udc *udc, u32 mode)
1465 {
1466 u32 portsc;
1467
1468 portsc = readl(&udc->op_regs->portsc[0]);
1469 portsc |= mode << 16;
1470 writel(portsc, &udc->op_regs->portsc[0]);
1471 }
1472
1473 static void prime_status_complete(struct usb_ep *ep, struct usb_request *_req)
1474 {
1475 struct mv_udc *udc = the_controller;
1476 struct mv_req *req = container_of(_req, struct mv_req, req);
1477 unsigned long flags;
1478
1479 dev_info(&udc->dev->dev, "switch to test mode %d\n", req->test_mode);
1480
1481 spin_lock_irqsave(&udc->lock, flags);
1482 if (req->test_mode) {
1483 mv_set_ptc(udc, req->test_mode);
1484 req->test_mode = 0;
1485 }
1486 spin_unlock_irqrestore(&udc->lock, flags);
1487 }
1488
1489 static int
1490 udc_prime_status(struct mv_udc *udc, u8 direction, u16 status, bool empty)
1491 {
1492 int retval = 0;
1493 struct mv_req *req;
1494 struct mv_ep *ep;
1495
1496 ep = &udc->eps[0];
1497 udc->ep0_dir = direction;
1498 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1499
1500 req = udc->status_req;
1501
1502 /* fill in the reqest structure */
1503 if (empty == false) {
1504 *((u16 *) req->req.buf) = cpu_to_le16(status);
1505 req->req.length = 2;
1506 } else
1507 req->req.length = 0;
1508
1509 req->ep = ep;
1510 req->req.status = -EINPROGRESS;
1511 req->req.actual = 0;
1512 if (udc->test_mode) {
1513 req->req.complete = prime_status_complete;
1514 req->test_mode = udc->test_mode;
1515 udc->test_mode = 0;
1516 } else
1517 req->req.complete = NULL;
1518 req->dtd_count = 0;
1519
1520 if (req->req.dma == DMA_ADDR_INVALID) {
1521 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1522 req->req.buf, req->req.length,
1523 ep_dir(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1524 req->mapped = 1;
1525 }
1526
1527 /* prime the data phase */
1528 if (!req_to_dtd(req)) {
1529 retval = queue_dtd(ep, req);
1530 if (retval) {
1531 dev_err(&udc->dev->dev,
1532 "Failed to queue dtd when prime status\n");
1533 goto out;
1534 }
1535 } else{ /* no mem */
1536 retval = -ENOMEM;
1537 dev_err(&udc->dev->dev,
1538 "Failed to dma_pool_alloc when prime status\n");
1539 goto out;
1540 }
1541
1542 list_add_tail(&req->queue, &ep->queue);
1543
1544 return 0;
1545 out:
1546 if (req->mapped) {
1547 dma_unmap_single(ep->udc->gadget.dev.parent,
1548 req->req.dma, req->req.length,
1549 ((ep_dir(ep) == EP_DIR_IN) ?
1550 DMA_TO_DEVICE : DMA_FROM_DEVICE));
1551 req->req.dma = DMA_ADDR_INVALID;
1552 req->mapped = 0;
1553 }
1554
1555 return retval;
1556 }
1557
1558 static void mv_udc_testmode(struct mv_udc *udc, u16 index)
1559 {
1560 if (index <= TEST_FORCE_EN) {
1561 udc->test_mode = index;
1562 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1563 ep0_stall(udc);
1564 } else
1565 dev_err(&udc->dev->dev,
1566 "This test mode(%d) is not supported\n", index);
1567 }
1568
1569 static void ch9setaddress(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1570 {
1571 udc->dev_addr = (u8)setup->wValue;
1572
1573 /* update usb state */
1574 udc->usb_state = USB_STATE_ADDRESS;
1575
1576 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1577 ep0_stall(udc);
1578 }
1579
1580 static void ch9getstatus(struct mv_udc *udc, u8 ep_num,
1581 struct usb_ctrlrequest *setup)
1582 {
1583 u16 status = 0;
1584 int retval;
1585
1586 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1587 != (USB_DIR_IN | USB_TYPE_STANDARD))
1588 return;
1589
1590 if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1591 status = 1 << USB_DEVICE_SELF_POWERED;
1592 status |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1593 } else if ((setup->bRequestType & USB_RECIP_MASK)
1594 == USB_RECIP_INTERFACE) {
1595 /* get interface status */
1596 status = 0;
1597 } else if ((setup->bRequestType & USB_RECIP_MASK)
1598 == USB_RECIP_ENDPOINT) {
1599 u8 ep_num, direction;
1600
1601 ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1602 direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1603 ? EP_DIR_IN : EP_DIR_OUT;
1604 status = ep_is_stall(udc, ep_num, direction)
1605 << USB_ENDPOINT_HALT;
1606 }
1607
1608 retval = udc_prime_status(udc, EP_DIR_IN, status, false);
1609 if (retval)
1610 ep0_stall(udc);
1611 else
1612 udc->ep0_state = DATA_STATE_XMIT;
1613 }
1614
1615 static void ch9clearfeature(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1616 {
1617 u8 ep_num;
1618 u8 direction;
1619 struct mv_ep *ep;
1620
1621 if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1622 == ((USB_TYPE_STANDARD | USB_RECIP_DEVICE))) {
1623 switch (setup->wValue) {
1624 case USB_DEVICE_REMOTE_WAKEUP:
1625 udc->remote_wakeup = 0;
1626 break;
1627 default:
1628 goto out;
1629 }
1630 } else if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1631 == ((USB_TYPE_STANDARD | USB_RECIP_ENDPOINT))) {
1632 switch (setup->wValue) {
1633 case USB_ENDPOINT_HALT:
1634 ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1635 direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1636 ? EP_DIR_IN : EP_DIR_OUT;
1637 if (setup->wValue != 0 || setup->wLength != 0
1638 || ep_num > udc->max_eps)
1639 goto out;
1640 ep = &udc->eps[ep_num * 2 + direction];
1641 if (ep->wedge == 1)
1642 break;
1643 spin_unlock(&udc->lock);
1644 ep_set_stall(udc, ep_num, direction, 0);
1645 spin_lock(&udc->lock);
1646 break;
1647 default:
1648 goto out;
1649 }
1650 } else
1651 goto out;
1652
1653 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1654 ep0_stall(udc);
1655 out:
1656 return;
1657 }
1658
1659 static void ch9setfeature(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1660 {
1661 u8 ep_num;
1662 u8 direction;
1663
1664 if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1665 == ((USB_TYPE_STANDARD | USB_RECIP_DEVICE))) {
1666 switch (setup->wValue) {
1667 case USB_DEVICE_REMOTE_WAKEUP:
1668 udc->remote_wakeup = 1;
1669 break;
1670 case USB_DEVICE_TEST_MODE:
1671 if (setup->wIndex & 0xFF
1672 || udc->gadget.speed != USB_SPEED_HIGH)
1673 ep0_stall(udc);
1674
1675 if (udc->usb_state != USB_STATE_CONFIGURED
1676 && udc->usb_state != USB_STATE_ADDRESS
1677 && udc->usb_state != USB_STATE_DEFAULT)
1678 ep0_stall(udc);
1679
1680 mv_udc_testmode(udc, (setup->wIndex >> 8));
1681 goto out;
1682 default:
1683 goto out;
1684 }
1685 } else if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1686 == ((USB_TYPE_STANDARD | USB_RECIP_ENDPOINT))) {
1687 switch (setup->wValue) {
1688 case USB_ENDPOINT_HALT:
1689 ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1690 direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1691 ? EP_DIR_IN : EP_DIR_OUT;
1692 if (setup->wValue != 0 || setup->wLength != 0
1693 || ep_num > udc->max_eps)
1694 goto out;
1695 spin_unlock(&udc->lock);
1696 ep_set_stall(udc, ep_num, direction, 1);
1697 spin_lock(&udc->lock);
1698 break;
1699 default:
1700 goto out;
1701 }
1702 } else
1703 goto out;
1704
1705 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1706 ep0_stall(udc);
1707 out:
1708 return;
1709 }
1710
1711 static void handle_setup_packet(struct mv_udc *udc, u8 ep_num,
1712 struct usb_ctrlrequest *setup)
1713 {
1714 bool delegate = false;
1715
1716 nuke(&udc->eps[ep_num * 2 + EP_DIR_OUT], -ESHUTDOWN);
1717
1718 dev_dbg(&udc->dev->dev, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1719 setup->bRequestType, setup->bRequest,
1720 setup->wValue, setup->wIndex, setup->wLength);
1721 /* We process some stardard setup requests here */
1722 if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1723 switch (setup->bRequest) {
1724 case USB_REQ_GET_STATUS:
1725 ch9getstatus(udc, ep_num, setup);
1726 break;
1727
1728 case USB_REQ_SET_ADDRESS:
1729 ch9setaddress(udc, setup);
1730 break;
1731
1732 case USB_REQ_CLEAR_FEATURE:
1733 ch9clearfeature(udc, setup);
1734 break;
1735
1736 case USB_REQ_SET_FEATURE:
1737 ch9setfeature(udc, setup);
1738 break;
1739
1740 default:
1741 delegate = true;
1742 }
1743 } else
1744 delegate = true;
1745
1746 /* delegate USB standard requests to the gadget driver */
1747 if (delegate == true) {
1748 /* USB requests handled by gadget */
1749 if (setup->wLength) {
1750 /* DATA phase from gadget, STATUS phase from udc */
1751 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1752 ? EP_DIR_IN : EP_DIR_OUT;
1753 spin_unlock(&udc->lock);
1754 if (udc->driver->setup(&udc->gadget,
1755 &udc->local_setup_buff) < 0)
1756 ep0_stall(udc);
1757 spin_lock(&udc->lock);
1758 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1759 ? DATA_STATE_XMIT : DATA_STATE_RECV;
1760 } else {
1761 /* no DATA phase, IN STATUS phase from gadget */
1762 udc->ep0_dir = EP_DIR_IN;
1763 spin_unlock(&udc->lock);
1764 if (udc->driver->setup(&udc->gadget,
1765 &udc->local_setup_buff) < 0)
1766 ep0_stall(udc);
1767 spin_lock(&udc->lock);
1768 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1769 }
1770 }
1771 }
1772
1773 /* complete DATA or STATUS phase of ep0 prime status phase if needed */
1774 static void ep0_req_complete(struct mv_udc *udc,
1775 struct mv_ep *ep0, struct mv_req *req)
1776 {
1777 u32 new_addr;
1778
1779 if (udc->usb_state == USB_STATE_ADDRESS) {
1780 /* set the new address */
1781 new_addr = (u32)udc->dev_addr;
1782 writel(new_addr << USB_DEVICE_ADDRESS_BIT_SHIFT,
1783 &udc->op_regs->deviceaddr);
1784 }
1785
1786 done(ep0, req, 0);
1787
1788 switch (udc->ep0_state) {
1789 case DATA_STATE_XMIT:
1790 /* receive status phase */
1791 if (udc_prime_status(udc, EP_DIR_OUT, 0, true))
1792 ep0_stall(udc);
1793 break;
1794 case DATA_STATE_RECV:
1795 /* send status phase */
1796 if (udc_prime_status(udc, EP_DIR_IN, 0 , true))
1797 ep0_stall(udc);
1798 break;
1799 case WAIT_FOR_OUT_STATUS:
1800 udc->ep0_state = WAIT_FOR_SETUP;
1801 break;
1802 case WAIT_FOR_SETUP:
1803 dev_err(&udc->dev->dev, "unexpect ep0 packets\n");
1804 break;
1805 default:
1806 ep0_stall(udc);
1807 break;
1808 }
1809 }
1810
1811 static void get_setup_data(struct mv_udc *udc, u8 ep_num, u8 *buffer_ptr)
1812 {
1813 u32 temp;
1814 struct mv_dqh *dqh;
1815
1816 dqh = &udc->ep_dqh[ep_num * 2 + EP_DIR_OUT];
1817
1818 /* Clear bit in ENDPTSETUPSTAT */
1819 writel((1 << ep_num), &udc->op_regs->epsetupstat);
1820
1821 /* while a hazard exists when setup package arrives */
1822 do {
1823 /* Set Setup Tripwire */
1824 temp = readl(&udc->op_regs->usbcmd);
1825 writel(temp | USBCMD_SETUP_TRIPWIRE_SET, &udc->op_regs->usbcmd);
1826
1827 /* Copy the setup packet to local buffer */
1828 memcpy(buffer_ptr, (u8 *) dqh->setup_buffer, 8);
1829 } while (!(readl(&udc->op_regs->usbcmd) & USBCMD_SETUP_TRIPWIRE_SET));
1830
1831 /* Clear Setup Tripwire */
1832 temp = readl(&udc->op_regs->usbcmd);
1833 writel(temp & ~USBCMD_SETUP_TRIPWIRE_SET, &udc->op_regs->usbcmd);
1834 }
1835
1836 static void irq_process_tr_complete(struct mv_udc *udc)
1837 {
1838 u32 tmp, bit_pos;
1839 int i, ep_num = 0, direction = 0;
1840 struct mv_ep *curr_ep;
1841 struct mv_req *curr_req, *temp_req;
1842 int status;
1843
1844 /*
1845 * We use separate loops for ENDPTSETUPSTAT and ENDPTCOMPLETE
1846 * because the setup packets are to be read ASAP
1847 */
1848
1849 /* Process all Setup packet received interrupts */
1850 tmp = readl(&udc->op_regs->epsetupstat);
1851
1852 if (tmp) {
1853 for (i = 0; i < udc->max_eps; i++) {
1854 if (tmp & (1 << i)) {
1855 get_setup_data(udc, i,
1856 (u8 *)(&udc->local_setup_buff));
1857 handle_setup_packet(udc, i,
1858 &udc->local_setup_buff);
1859 }
1860 }
1861 }
1862
1863 /* Don't clear the endpoint setup status register here.
1864 * It is cleared as a setup packet is read out of the buffer
1865 */
1866
1867 /* Process non-setup transaction complete interrupts */
1868 tmp = readl(&udc->op_regs->epcomplete);
1869
1870 if (!tmp)
1871 return;
1872
1873 writel(tmp, &udc->op_regs->epcomplete);
1874
1875 for (i = 0; i < udc->max_eps * 2; i++) {
1876 ep_num = i >> 1;
1877 direction = i % 2;
1878
1879 bit_pos = 1 << (ep_num + 16 * direction);
1880
1881 if (!(bit_pos & tmp))
1882 continue;
1883
1884 if (i == 1)
1885 curr_ep = &udc->eps[0];
1886 else
1887 curr_ep = &udc->eps[i];
1888 /* process the req queue until an uncomplete request */
1889 list_for_each_entry_safe(curr_req, temp_req,
1890 &curr_ep->queue, queue) {
1891 status = process_ep_req(udc, i, curr_req);
1892 if (status)
1893 break;
1894
1895 /* write back status to req */
1896 curr_req->req.status = status;
1897
1898 /* ep0 request completion */
1899 if (ep_num == 0) {
1900 ep0_req_complete(udc, curr_ep, curr_req);
1901 break;
1902 } else {
1903 done(curr_ep, curr_req, status);
1904 }
1905 }
1906 }
1907 }
1908
1909 void irq_process_reset(struct mv_udc *udc)
1910 {
1911 u32 tmp;
1912 unsigned int loops;
1913
1914 udc->ep0_dir = EP_DIR_OUT;
1915 udc->ep0_state = WAIT_FOR_SETUP;
1916 udc->remote_wakeup = 0; /* default to 0 on reset */
1917
1918 /* The address bits are past bit 25-31. Set the address */
1919 tmp = readl(&udc->op_regs->deviceaddr);
1920 tmp &= ~(USB_DEVICE_ADDRESS_MASK);
1921 writel(tmp, &udc->op_regs->deviceaddr);
1922
1923 /* Clear all the setup token semaphores */
1924 tmp = readl(&udc->op_regs->epsetupstat);
1925 writel(tmp, &udc->op_regs->epsetupstat);
1926
1927 /* Clear all the endpoint complete status bits */
1928 tmp = readl(&udc->op_regs->epcomplete);
1929 writel(tmp, &udc->op_regs->epcomplete);
1930
1931 /* wait until all endptprime bits cleared */
1932 loops = LOOPS(PRIME_TIMEOUT);
1933 while (readl(&udc->op_regs->epprime) & 0xFFFFFFFF) {
1934 if (loops == 0) {
1935 dev_err(&udc->dev->dev,
1936 "Timeout for ENDPTPRIME = 0x%x\n",
1937 readl(&udc->op_regs->epprime));
1938 break;
1939 }
1940 loops--;
1941 udelay(LOOPS_USEC);
1942 }
1943
1944 /* Write 1s to the Flush register */
1945 writel((u32)~0, &udc->op_regs->epflush);
1946
1947 if (readl(&udc->op_regs->portsc[0]) & PORTSCX_PORT_RESET) {
1948 dev_info(&udc->dev->dev, "usb bus reset\n");
1949 udc->usb_state = USB_STATE_DEFAULT;
1950 /* reset all the queues, stop all USB activities */
1951 stop_activity(udc, udc->driver);
1952 } else {
1953 dev_info(&udc->dev->dev, "USB reset portsc 0x%x\n",
1954 readl(&udc->op_regs->portsc));
1955
1956 /*
1957 * re-initialize
1958 * controller reset
1959 */
1960 udc_reset(udc);
1961
1962 /* reset all the queues, stop all USB activities */
1963 stop_activity(udc, udc->driver);
1964
1965 /* reset ep0 dQH and endptctrl */
1966 ep0_reset(udc);
1967
1968 /* enable interrupt and set controller to run state */
1969 udc_start(udc);
1970
1971 udc->usb_state = USB_STATE_ATTACHED;
1972 }
1973 }
1974
1975 static void handle_bus_resume(struct mv_udc *udc)
1976 {
1977 udc->usb_state = udc->resume_state;
1978 udc->resume_state = 0;
1979
1980 /* report resume to the driver */
1981 if (udc->driver) {
1982 if (udc->driver->resume) {
1983 spin_unlock(&udc->lock);
1984 udc->driver->resume(&udc->gadget);
1985 spin_lock(&udc->lock);
1986 }
1987 }
1988 }
1989
1990 static void irq_process_suspend(struct mv_udc *udc)
1991 {
1992 udc->resume_state = udc->usb_state;
1993 udc->usb_state = USB_STATE_SUSPENDED;
1994
1995 if (udc->driver->suspend) {
1996 spin_unlock(&udc->lock);
1997 udc->driver->suspend(&udc->gadget);
1998 spin_lock(&udc->lock);
1999 }
2000 }
2001
2002 static void irq_process_port_change(struct mv_udc *udc)
2003 {
2004 u32 portsc;
2005
2006 portsc = readl(&udc->op_regs->portsc[0]);
2007 if (!(portsc & PORTSCX_PORT_RESET)) {
2008 /* Get the speed */
2009 u32 speed = portsc & PORTSCX_PORT_SPEED_MASK;
2010 switch (speed) {
2011 case PORTSCX_PORT_SPEED_HIGH:
2012 udc->gadget.speed = USB_SPEED_HIGH;
2013 break;
2014 case PORTSCX_PORT_SPEED_FULL:
2015 udc->gadget.speed = USB_SPEED_FULL;
2016 break;
2017 case PORTSCX_PORT_SPEED_LOW:
2018 udc->gadget.speed = USB_SPEED_LOW;
2019 break;
2020 default:
2021 udc->gadget.speed = USB_SPEED_UNKNOWN;
2022 break;
2023 }
2024 }
2025
2026 if (portsc & PORTSCX_PORT_SUSPEND) {
2027 udc->resume_state = udc->usb_state;
2028 udc->usb_state = USB_STATE_SUSPENDED;
2029 if (udc->driver->suspend) {
2030 spin_unlock(&udc->lock);
2031 udc->driver->suspend(&udc->gadget);
2032 spin_lock(&udc->lock);
2033 }
2034 }
2035
2036 if (!(portsc & PORTSCX_PORT_SUSPEND)
2037 && udc->usb_state == USB_STATE_SUSPENDED) {
2038 handle_bus_resume(udc);
2039 }
2040
2041 if (!udc->resume_state)
2042 udc->usb_state = USB_STATE_DEFAULT;
2043 }
2044
2045 static void irq_process_error(struct mv_udc *udc)
2046 {
2047 /* Increment the error count */
2048 udc->errors++;
2049 }
2050
2051 static irqreturn_t mv_udc_irq(int irq, void *dev)
2052 {
2053 struct mv_udc *udc = (struct mv_udc *)dev;
2054 u32 status, intr;
2055
2056 /* Disable ISR when stopped bit is set */
2057 if (udc->stopped)
2058 return IRQ_NONE;
2059
2060 spin_lock(&udc->lock);
2061
2062 status = readl(&udc->op_regs->usbsts);
2063 intr = readl(&udc->op_regs->usbintr);
2064 status &= intr;
2065
2066 if (status == 0) {
2067 spin_unlock(&udc->lock);
2068 return IRQ_NONE;
2069 }
2070
2071 /* Clear all the interrupts occurred */
2072 writel(status, &udc->op_regs->usbsts);
2073
2074 if (status & USBSTS_ERR)
2075 irq_process_error(udc);
2076
2077 if (status & USBSTS_RESET)
2078 irq_process_reset(udc);
2079
2080 if (status & USBSTS_PORT_CHANGE)
2081 irq_process_port_change(udc);
2082
2083 if (status & USBSTS_INT)
2084 irq_process_tr_complete(udc);
2085
2086 if (status & USBSTS_SUSPEND)
2087 irq_process_suspend(udc);
2088
2089 spin_unlock(&udc->lock);
2090
2091 return IRQ_HANDLED;
2092 }
2093
2094 static irqreturn_t mv_udc_vbus_irq(int irq, void *dev)
2095 {
2096 struct mv_udc *udc = (struct mv_udc *)dev;
2097
2098 /* polling VBUS and init phy may cause too much time*/
2099 if (udc->qwork)
2100 queue_work(udc->qwork, &udc->vbus_work);
2101
2102 return IRQ_HANDLED;
2103 }
2104
2105 static void mv_udc_vbus_work(struct work_struct *work)
2106 {
2107 struct mv_udc *udc;
2108 unsigned int vbus;
2109
2110 udc = container_of(work, struct mv_udc, vbus_work);
2111 if (!udc->pdata->vbus)
2112 return;
2113
2114 vbus = udc->pdata->vbus->poll();
2115 dev_info(&udc->dev->dev, "vbus is %d\n", vbus);
2116
2117 if (vbus == VBUS_HIGH)
2118 mv_udc_vbus_session(&udc->gadget, 1);
2119 else if (vbus == VBUS_LOW)
2120 mv_udc_vbus_session(&udc->gadget, 0);
2121 }
2122
2123 /* release device structure */
2124 static void gadget_release(struct device *_dev)
2125 {
2126 struct mv_udc *udc = the_controller;
2127
2128 complete(udc->done);
2129 }
2130
2131 static int mv_udc_remove(struct platform_device *dev)
2132 {
2133 struct mv_udc *udc = the_controller;
2134 int clk_i;
2135
2136 usb_del_gadget_udc(&udc->gadget);
2137
2138 if (udc->qwork) {
2139 flush_workqueue(udc->qwork);
2140 destroy_workqueue(udc->qwork);
2141 }
2142
2143 /*
2144 * If we have transceiver inited,
2145 * then vbus irq will not be requested in udc driver.
2146 */
2147 if (udc->pdata && udc->pdata->vbus
2148 && udc->clock_gating && IS_ERR_OR_NULL(udc->transceiver))
2149 free_irq(udc->pdata->vbus->irq, &dev->dev);
2150
2151 /* free memory allocated in probe */
2152 if (udc->dtd_pool)
2153 dma_pool_destroy(udc->dtd_pool);
2154
2155 if (udc->ep_dqh)
2156 dma_free_coherent(&dev->dev, udc->ep_dqh_size,
2157 udc->ep_dqh, udc->ep_dqh_dma);
2158
2159 kfree(udc->eps);
2160
2161 if (udc->irq)
2162 free_irq(udc->irq, &dev->dev);
2163
2164 mv_udc_disable(udc);
2165
2166 if (udc->cap_regs)
2167 iounmap(udc->cap_regs);
2168
2169 if (udc->phy_regs)
2170 iounmap(udc->phy_regs);
2171
2172 if (udc->status_req) {
2173 kfree(udc->status_req->req.buf);
2174 kfree(udc->status_req);
2175 }
2176
2177 for (clk_i = 0; clk_i <= udc->clknum; clk_i++)
2178 clk_put(udc->clk[clk_i]);
2179
2180 device_unregister(&udc->gadget.dev);
2181
2182 /* free dev, wait for the release() finished */
2183 wait_for_completion(udc->done);
2184 kfree(udc);
2185
2186 the_controller = NULL;
2187
2188 return 0;
2189 }
2190
2191 static int mv_udc_probe(struct platform_device *dev)
2192 {
2193 struct mv_usb_platform_data *pdata = dev->dev.platform_data;
2194 struct mv_udc *udc;
2195 int retval = 0;
2196 int clk_i = 0;
2197 struct resource *r;
2198 size_t size;
2199
2200 if (pdata == NULL) {
2201 dev_err(&dev->dev, "missing platform_data\n");
2202 return -ENODEV;
2203 }
2204
2205 size = sizeof(*udc) + sizeof(struct clk *) * pdata->clknum;
2206 udc = kzalloc(size, GFP_KERNEL);
2207 if (udc == NULL) {
2208 dev_err(&dev->dev, "failed to allocate memory for udc\n");
2209 return -ENOMEM;
2210 }
2211
2212 the_controller = udc;
2213 udc->done = &release_done;
2214 udc->pdata = dev->dev.platform_data;
2215 spin_lock_init(&udc->lock);
2216
2217 udc->dev = dev;
2218
2219 #ifdef CONFIG_USB_OTG_UTILS
2220 if (pdata->mode == MV_USB_MODE_OTG)
2221 udc->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
2222 #endif
2223
2224 udc->clknum = pdata->clknum;
2225 for (clk_i = 0; clk_i < udc->clknum; clk_i++) {
2226 udc->clk[clk_i] = clk_get(&dev->dev, pdata->clkname[clk_i]);
2227 if (IS_ERR(udc->clk[clk_i])) {
2228 retval = PTR_ERR(udc->clk[clk_i]);
2229 goto err_put_clk;
2230 }
2231 }
2232
2233 r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "capregs");
2234 if (r == NULL) {
2235 dev_err(&dev->dev, "no I/O memory resource defined\n");
2236 retval = -ENODEV;
2237 goto err_put_clk;
2238 }
2239
2240 udc->cap_regs = (struct mv_cap_regs __iomem *)
2241 ioremap(r->start, resource_size(r));
2242 if (udc->cap_regs == NULL) {
2243 dev_err(&dev->dev, "failed to map I/O memory\n");
2244 retval = -EBUSY;
2245 goto err_put_clk;
2246 }
2247
2248 r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "phyregs");
2249 if (r == NULL) {
2250 dev_err(&dev->dev, "no phy I/O memory resource defined\n");
2251 retval = -ENODEV;
2252 goto err_iounmap_capreg;
2253 }
2254
2255 udc->phy_regs = ioremap(r->start, resource_size(r));
2256 if (udc->phy_regs == NULL) {
2257 dev_err(&dev->dev, "failed to map phy I/O memory\n");
2258 retval = -EBUSY;
2259 goto err_iounmap_capreg;
2260 }
2261
2262 /* we will acces controller register, so enable the clk */
2263 retval = mv_udc_enable_internal(udc);
2264 if (retval)
2265 goto err_iounmap_phyreg;
2266
2267 udc->op_regs =
2268 (struct mv_op_regs __iomem *)((unsigned long)udc->cap_regs
2269 + (readl(&udc->cap_regs->caplength_hciversion)
2270 & CAPLENGTH_MASK));
2271 udc->max_eps = readl(&udc->cap_regs->dccparams) & DCCPARAMS_DEN_MASK;
2272
2273 /*
2274 * some platform will use usb to download image, it may not disconnect
2275 * usb gadget before loading kernel. So first stop udc here.
2276 */
2277 udc_stop(udc);
2278 writel(0xFFFFFFFF, &udc->op_regs->usbsts);
2279
2280 size = udc->max_eps * sizeof(struct mv_dqh) *2;
2281 size = (size + DQH_ALIGNMENT - 1) & ~(DQH_ALIGNMENT - 1);
2282 udc->ep_dqh = dma_alloc_coherent(&dev->dev, size,
2283 &udc->ep_dqh_dma, GFP_KERNEL);
2284
2285 if (udc->ep_dqh == NULL) {
2286 dev_err(&dev->dev, "allocate dQH memory failed\n");
2287 retval = -ENOMEM;
2288 goto err_disable_clock;
2289 }
2290 udc->ep_dqh_size = size;
2291
2292 /* create dTD dma_pool resource */
2293 udc->dtd_pool = dma_pool_create("mv_dtd",
2294 &dev->dev,
2295 sizeof(struct mv_dtd),
2296 DTD_ALIGNMENT,
2297 DMA_BOUNDARY);
2298
2299 if (!udc->dtd_pool) {
2300 retval = -ENOMEM;
2301 goto err_free_dma;
2302 }
2303
2304 size = udc->max_eps * sizeof(struct mv_ep) *2;
2305 udc->eps = kzalloc(size, GFP_KERNEL);
2306 if (udc->eps == NULL) {
2307 dev_err(&dev->dev, "allocate ep memory failed\n");
2308 retval = -ENOMEM;
2309 goto err_destroy_dma;
2310 }
2311
2312 /* initialize ep0 status request structure */
2313 udc->status_req = kzalloc(sizeof(struct mv_req), GFP_KERNEL);
2314 if (!udc->status_req) {
2315 dev_err(&dev->dev, "allocate status_req memory failed\n");
2316 retval = -ENOMEM;
2317 goto err_free_eps;
2318 }
2319 INIT_LIST_HEAD(&udc->status_req->queue);
2320
2321 /* allocate a small amount of memory to get valid address */
2322 udc->status_req->req.buf = kzalloc(8, GFP_KERNEL);
2323 udc->status_req->req.dma = DMA_ADDR_INVALID;
2324
2325 udc->resume_state = USB_STATE_NOTATTACHED;
2326 udc->usb_state = USB_STATE_POWERED;
2327 udc->ep0_dir = EP_DIR_OUT;
2328 udc->remote_wakeup = 0;
2329
2330 r = platform_get_resource(udc->dev, IORESOURCE_IRQ, 0);
2331 if (r == NULL) {
2332 dev_err(&dev->dev, "no IRQ resource defined\n");
2333 retval = -ENODEV;
2334 goto err_free_status_req;
2335 }
2336 udc->irq = r->start;
2337 if (request_irq(udc->irq, mv_udc_irq,
2338 IRQF_SHARED, driver_name, udc)) {
2339 dev_err(&dev->dev, "Request irq %d for UDC failed\n",
2340 udc->irq);
2341 retval = -ENODEV;
2342 goto err_free_status_req;
2343 }
2344
2345 /* initialize gadget structure */
2346 udc->gadget.ops = &mv_ops; /* usb_gadget_ops */
2347 udc->gadget.ep0 = &udc->eps[0].ep; /* gadget ep0 */
2348 INIT_LIST_HEAD(&udc->gadget.ep_list); /* ep_list */
2349 udc->gadget.speed = USB_SPEED_UNKNOWN; /* speed */
2350 udc->gadget.max_speed = USB_SPEED_HIGH; /* support dual speed */
2351
2352 /* the "gadget" abstracts/virtualizes the controller */
2353 dev_set_name(&udc->gadget.dev, "gadget");
2354 udc->gadget.dev.parent = &dev->dev;
2355 udc->gadget.dev.dma_mask = dev->dev.dma_mask;
2356 udc->gadget.dev.release = gadget_release;
2357 udc->gadget.name = driver_name; /* gadget name */
2358
2359 retval = device_register(&udc->gadget.dev);
2360 if (retval)
2361 goto err_free_irq;
2362
2363 eps_init(udc);
2364
2365 /* VBUS detect: we can disable/enable clock on demand.*/
2366 if (!IS_ERR_OR_NULL(udc->transceiver))
2367 udc->clock_gating = 1;
2368 else if (pdata->vbus) {
2369 udc->clock_gating = 1;
2370 retval = request_threaded_irq(pdata->vbus->irq, NULL,
2371 mv_udc_vbus_irq, IRQF_ONESHOT, "vbus", udc);
2372 if (retval) {
2373 dev_info(&dev->dev,
2374 "Can not request irq for VBUS, "
2375 "disable clock gating\n");
2376 udc->clock_gating = 0;
2377 }
2378
2379 udc->qwork = create_singlethread_workqueue("mv_udc_queue");
2380 if (!udc->qwork) {
2381 dev_err(&dev->dev, "cannot create workqueue\n");
2382 retval = -ENOMEM;
2383 goto err_unregister;
2384 }
2385
2386 INIT_WORK(&udc->vbus_work, mv_udc_vbus_work);
2387 }
2388
2389 /*
2390 * When clock gating is supported, we can disable clk and phy.
2391 * If not, it means that VBUS detection is not supported, we
2392 * have to enable vbus active all the time to let controller work.
2393 */
2394 if (udc->clock_gating)
2395 mv_udc_disable_internal(udc);
2396 else
2397 udc->vbus_active = 1;
2398
2399 retval = usb_add_gadget_udc(&dev->dev, &udc->gadget);
2400 if (retval)
2401 goto err_unregister;
2402
2403 dev_info(&dev->dev, "successful probe UDC device %s clock gating.\n",
2404 udc->clock_gating ? "with" : "without");
2405
2406 return 0;
2407
2408 err_unregister:
2409 if (udc->pdata && udc->pdata->vbus
2410 && udc->clock_gating && IS_ERR_OR_NULL(udc->transceiver))
2411 free_irq(pdata->vbus->irq, &dev->dev);
2412 device_unregister(&udc->gadget.dev);
2413 err_free_irq:
2414 free_irq(udc->irq, &dev->dev);
2415 err_free_status_req:
2416 kfree(udc->status_req->req.buf);
2417 kfree(udc->status_req);
2418 err_free_eps:
2419 kfree(udc->eps);
2420 err_destroy_dma:
2421 dma_pool_destroy(udc->dtd_pool);
2422 err_free_dma:
2423 dma_free_coherent(&dev->dev, udc->ep_dqh_size,
2424 udc->ep_dqh, udc->ep_dqh_dma);
2425 err_disable_clock:
2426 mv_udc_disable_internal(udc);
2427 err_iounmap_phyreg:
2428 iounmap(udc->phy_regs);
2429 err_iounmap_capreg:
2430 iounmap(udc->cap_regs);
2431 err_put_clk:
2432 for (clk_i--; clk_i >= 0; clk_i--)
2433 clk_put(udc->clk[clk_i]);
2434 the_controller = NULL;
2435 kfree(udc);
2436 return retval;
2437 }
2438
2439 #ifdef CONFIG_PM
2440 static int mv_udc_suspend(struct device *_dev)
2441 {
2442 struct mv_udc *udc = the_controller;
2443
2444 /* if OTG is enabled, the following will be done in OTG driver*/
2445 if (!IS_ERR_OR_NULL(udc->transceiver))
2446 return 0;
2447
2448 if (udc->pdata->vbus && udc->pdata->vbus->poll)
2449 if (udc->pdata->vbus->poll() == VBUS_HIGH) {
2450 dev_info(&udc->dev->dev, "USB cable is connected!\n");
2451 return -EAGAIN;
2452 }
2453
2454 /*
2455 * only cable is unplugged, udc can suspend.
2456 * So do not care about clock_gating == 1.
2457 */
2458 if (!udc->clock_gating) {
2459 udc_stop(udc);
2460
2461 spin_lock_irq(&udc->lock);
2462 /* stop all usb activities */
2463 stop_activity(udc, udc->driver);
2464 spin_unlock_irq(&udc->lock);
2465
2466 mv_udc_disable_internal(udc);
2467 }
2468
2469 return 0;
2470 }
2471
2472 static int mv_udc_resume(struct device *_dev)
2473 {
2474 struct mv_udc *udc = the_controller;
2475 int retval;
2476
2477 /* if OTG is enabled, the following will be done in OTG driver*/
2478 if (!IS_ERR_OR_NULL(udc->transceiver))
2479 return 0;
2480
2481 if (!udc->clock_gating) {
2482 retval = mv_udc_enable_internal(udc);
2483 if (retval)
2484 return retval;
2485
2486 if (udc->driver && udc->softconnect) {
2487 udc_reset(udc);
2488 ep0_reset(udc);
2489 udc_start(udc);
2490 }
2491 }
2492
2493 return 0;
2494 }
2495
2496 static const struct dev_pm_ops mv_udc_pm_ops = {
2497 .suspend = mv_udc_suspend,
2498 .resume = mv_udc_resume,
2499 };
2500 #endif
2501
2502 static void mv_udc_shutdown(struct platform_device *dev)
2503 {
2504 struct mv_udc *udc = the_controller;
2505 u32 mode;
2506
2507 /* reset controller mode to IDLE */
2508 mv_udc_enable(udc);
2509 mode = readl(&udc->op_regs->usbmode);
2510 mode &= ~3;
2511 writel(mode, &udc->op_regs->usbmode);
2512 mv_udc_disable(udc);
2513 }
2514
2515 static struct platform_driver udc_driver = {
2516 .probe = mv_udc_probe,
2517 .remove = __exit_p(mv_udc_remove),
2518 .shutdown = mv_udc_shutdown,
2519 .driver = {
2520 .owner = THIS_MODULE,
2521 .name = "mv-udc",
2522 #ifdef CONFIG_PM
2523 .pm = &mv_udc_pm_ops,
2524 #endif
2525 },
2526 };
2527
2528 module_platform_driver(udc_driver);
2529 MODULE_ALIAS("platform:mv-udc");
2530 MODULE_DESCRIPTION(DRIVER_DESC);
2531 MODULE_AUTHOR("Chao Xie <chao.xie@marvell.com>");
2532 MODULE_VERSION(DRIVER_VERSION);
2533 MODULE_LICENSE("GPL");
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