2 * linux/drivers/usb/gadget/s3c-hsotg.c
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Copyright 2008 Openmoko, Inc.
8 * Copyright 2008 Simtec Electronics
9 * Ben Dooks <ben@simtec.co.uk>
10 * http://armlinux.simtec.co.uk/
12 * S3C USB2.0 High-speed / OtG driver
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/spinlock.h>
22 #include <linux/interrupt.h>
23 #include <linux/platform_device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/debugfs.h>
26 #include <linux/seq_file.h>
27 #include <linux/delay.h>
29 #include <linux/slab.h>
30 #include <linux/clk.h>
31 #include <linux/regulator/consumer.h>
33 #include <linux/usb/ch9.h>
34 #include <linux/usb/gadget.h>
35 #include <linux/platform_data/s3c-hsotg.h>
39 #include "s3c-hsotg.h"
41 #define DMA_ADDR_INVALID (~((dma_addr_t)0))
43 static const char * const s3c_hsotg_supply_names
[] = {
44 "vusb_d", /* digital USB supply, 1.2V */
45 "vusb_a", /* analog USB supply, 1.1V */
51 * Unfortunately there seems to be a limit of the amount of data that can
52 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
53 * packets (which practically means 1 packet and 63 bytes of data) when the
56 * This means if we are wanting to move >127 bytes of data, we need to
57 * split the transactions up, but just doing one packet at a time does
58 * not work (this may be an implicit DATA0 PID on first packet of the
59 * transaction) and doing 2 packets is outside the controller's limits.
61 * If we try to lower the MPS size for EP0, then no transfers work properly
62 * for EP0, and the system will fail basic enumeration. As no cause for this
63 * has currently been found, we cannot support any large IN transfers for
66 #define EP0_MPS_LIMIT 64
72 * struct s3c_hsotg_ep - driver endpoint definition.
73 * @ep: The gadget layer representation of the endpoint.
74 * @name: The driver generated name for the endpoint.
75 * @queue: Queue of requests for this endpoint.
76 * @parent: Reference back to the parent device structure.
77 * @req: The current request that the endpoint is processing. This is
78 * used to indicate an request has been loaded onto the endpoint
79 * and has yet to be completed (maybe due to data move, or simply
80 * awaiting an ack from the core all the data has been completed).
81 * @debugfs: File entry for debugfs file for this endpoint.
82 * @lock: State lock to protect contents of endpoint.
83 * @dir_in: Set to true if this endpoint is of the IN direction, which
84 * means that it is sending data to the Host.
85 * @index: The index for the endpoint registers.
86 * @name: The name array passed to the USB core.
87 * @halted: Set if the endpoint has been halted.
88 * @periodic: Set if this is a periodic ep, such as Interrupt
89 * @sent_zlp: Set if we've sent a zero-length packet.
90 * @total_data: The total number of data bytes done.
91 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
92 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
93 * @last_load: The offset of data for the last start of request.
94 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
96 * This is the driver's state for each registered enpoint, allowing it
97 * to keep track of transactions that need doing. Each endpoint has a
98 * lock to protect the state, to try and avoid using an overall lock
99 * for the host controller as much as possible.
101 * For periodic IN endpoints, we have fifo_size and fifo_load to try
102 * and keep track of the amount of data in the periodic FIFO for each
103 * of these as we don't have a status register that tells us how much
104 * is in each of them. (note, this may actually be useless information
105 * as in shared-fifo mode periodic in acts like a single-frame packet
106 * buffer than a fifo)
108 struct s3c_hsotg_ep
{
110 struct list_head queue
;
111 struct s3c_hsotg
*parent
;
112 struct s3c_hsotg_req
*req
;
113 struct dentry
*debugfs
;
116 unsigned long total_data
;
117 unsigned int size_loaded
;
118 unsigned int last_load
;
119 unsigned int fifo_load
;
120 unsigned short fifo_size
;
122 unsigned char dir_in
;
125 unsigned int halted
:1;
126 unsigned int periodic
:1;
127 unsigned int sent_zlp
:1;
133 * struct s3c_hsotg - driver state.
134 * @dev: The parent device supplied to the probe function
135 * @driver: USB gadget driver
136 * @plat: The platform specific configuration data.
137 * @regs: The memory area mapped for accessing registers.
138 * @irq: The IRQ number we are using
139 * @supplies: Definition of USB power supplies
140 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
141 * @num_of_eps: Number of available EPs (excluding EP0)
142 * @debug_root: root directrory for debugfs.
143 * @debug_file: main status file for debugfs.
144 * @debug_fifo: FIFO status file for debugfs.
145 * @ep0_reply: Request used for ep0 reply.
146 * @ep0_buff: Buffer for EP0 reply data, if needed.
147 * @ctrl_buff: Buffer for EP0 control requests.
148 * @ctrl_req: Request for EP0 control packets.
149 * @setup: NAK management for EP0 SETUP
150 * @last_rst: Time of last reset
151 * @eps: The endpoints being supplied to the gadget framework
155 struct usb_gadget_driver
*driver
;
156 struct s3c_hsotg_plat
*plat
;
164 struct regulator_bulk_data supplies
[ARRAY_SIZE(s3c_hsotg_supply_names
)];
166 unsigned int dedicated_fifos
:1;
167 unsigned char num_of_eps
;
169 struct dentry
*debug_root
;
170 struct dentry
*debug_file
;
171 struct dentry
*debug_fifo
;
173 struct usb_request
*ep0_reply
;
174 struct usb_request
*ctrl_req
;
178 struct usb_gadget gadget
;
180 unsigned long last_rst
;
181 struct s3c_hsotg_ep
*eps
;
185 * struct s3c_hsotg_req - data transfer request
186 * @req: The USB gadget request
187 * @queue: The list of requests for the endpoint this is queued for.
188 * @in_progress: Has already had size/packets written to core
189 * @mapped: DMA buffer for this request has been mapped via dma_map_single().
191 struct s3c_hsotg_req
{
192 struct usb_request req
;
193 struct list_head queue
;
194 unsigned char in_progress
;
195 unsigned char mapped
;
198 /* conversion functions */
199 static inline struct s3c_hsotg_req
*our_req(struct usb_request
*req
)
201 return container_of(req
, struct s3c_hsotg_req
, req
);
204 static inline struct s3c_hsotg_ep
*our_ep(struct usb_ep
*ep
)
206 return container_of(ep
, struct s3c_hsotg_ep
, ep
);
209 static inline struct s3c_hsotg
*to_hsotg(struct usb_gadget
*gadget
)
211 return container_of(gadget
, struct s3c_hsotg
, gadget
);
214 static inline void __orr32(void __iomem
*ptr
, u32 val
)
216 writel(readl(ptr
) | val
, ptr
);
219 static inline void __bic32(void __iomem
*ptr
, u32 val
)
221 writel(readl(ptr
) & ~val
, ptr
);
224 /* forward decleration of functions */
225 static void s3c_hsotg_dump(struct s3c_hsotg
*hsotg
);
228 * using_dma - return the DMA status of the driver.
229 * @hsotg: The driver state.
231 * Return true if we're using DMA.
233 * Currently, we have the DMA support code worked into everywhere
234 * that needs it, but the AMBA DMA implementation in the hardware can
235 * only DMA from 32bit aligned addresses. This means that gadgets such
236 * as the CDC Ethernet cannot work as they often pass packets which are
239 * Unfortunately the choice to use DMA or not is global to the controller
240 * and seems to be only settable when the controller is being put through
241 * a core reset. This means we either need to fix the gadgets to take
242 * account of DMA alignment, or add bounce buffers (yuerk).
244 * Until this issue is sorted out, we always return 'false'.
246 static inline bool using_dma(struct s3c_hsotg
*hsotg
)
248 return false; /* support is not complete */
252 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
253 * @hsotg: The device state
254 * @ints: A bitmask of the interrupts to enable
256 static void s3c_hsotg_en_gsint(struct s3c_hsotg
*hsotg
, u32 ints
)
258 u32 gsintmsk
= readl(hsotg
->regs
+ GINTMSK
);
261 new_gsintmsk
= gsintmsk
| ints
;
263 if (new_gsintmsk
!= gsintmsk
) {
264 dev_dbg(hsotg
->dev
, "gsintmsk now 0x%08x\n", new_gsintmsk
);
265 writel(new_gsintmsk
, hsotg
->regs
+ GINTMSK
);
270 * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
271 * @hsotg: The device state
272 * @ints: A bitmask of the interrupts to enable
274 static void s3c_hsotg_disable_gsint(struct s3c_hsotg
*hsotg
, u32 ints
)
276 u32 gsintmsk
= readl(hsotg
->regs
+ GINTMSK
);
279 new_gsintmsk
= gsintmsk
& ~ints
;
281 if (new_gsintmsk
!= gsintmsk
)
282 writel(new_gsintmsk
, hsotg
->regs
+ GINTMSK
);
286 * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
287 * @hsotg: The device state
288 * @ep: The endpoint index
289 * @dir_in: True if direction is in.
290 * @en: The enable value, true to enable
292 * Set or clear the mask for an individual endpoint's interrupt
295 static void s3c_hsotg_ctrl_epint(struct s3c_hsotg
*hsotg
,
296 unsigned int ep
, unsigned int dir_in
,
306 local_irq_save(flags
);
307 daint
= readl(hsotg
->regs
+ DAINTMSK
);
312 writel(daint
, hsotg
->regs
+ DAINTMSK
);
313 local_irq_restore(flags
);
317 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
318 * @hsotg: The device instance.
320 static void s3c_hsotg_init_fifo(struct s3c_hsotg
*hsotg
)
328 /* set FIFO sizes to 2048/1024 */
330 writel(2048, hsotg
->regs
+ GRXFSIZ
);
331 writel(GNPTXFSIZ_NPTxFStAddr(2048) |
332 GNPTXFSIZ_NPTxFDep(1024),
333 hsotg
->regs
+ GNPTXFSIZ
);
336 * arange all the rest of the TX FIFOs, as some versions of this
337 * block have overlapping default addresses. This also ensures
338 * that if the settings have been changed, then they are set to
342 /* start at the end of the GNPTXFSIZ, rounded up */
347 * currently we allocate TX FIFOs for all possible endpoints,
348 * and assume that they are all the same size.
351 for (ep
= 1; ep
<= 15; ep
++) {
353 val
|= size
<< DPTXFSIZn_DPTxFSize_SHIFT
;
356 writel(val
, hsotg
->regs
+ DPTXFSIZn(ep
));
360 * according to p428 of the design guide, we need to ensure that
361 * all fifos are flushed before continuing
364 writel(GRSTCTL_TxFNum(0x10) | GRSTCTL_TxFFlsh
|
365 GRSTCTL_RxFFlsh
, hsotg
->regs
+ GRSTCTL
);
367 /* wait until the fifos are both flushed */
370 val
= readl(hsotg
->regs
+ GRSTCTL
);
372 if ((val
& (GRSTCTL_TxFFlsh
| GRSTCTL_RxFFlsh
)) == 0)
375 if (--timeout
== 0) {
377 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
384 dev_dbg(hsotg
->dev
, "FIFOs reset, timeout at %d\n", timeout
);
388 * @ep: USB endpoint to allocate request for.
389 * @flags: Allocation flags
391 * Allocate a new USB request structure appropriate for the specified endpoint
393 static struct usb_request
*s3c_hsotg_ep_alloc_request(struct usb_ep
*ep
,
396 struct s3c_hsotg_req
*req
;
398 req
= kzalloc(sizeof(struct s3c_hsotg_req
), flags
);
402 INIT_LIST_HEAD(&req
->queue
);
404 req
->req
.dma
= DMA_ADDR_INVALID
;
409 * is_ep_periodic - return true if the endpoint is in periodic mode.
410 * @hs_ep: The endpoint to query.
412 * Returns true if the endpoint is in periodic mode, meaning it is being
413 * used for an Interrupt or ISO transfer.
415 static inline int is_ep_periodic(struct s3c_hsotg_ep
*hs_ep
)
417 return hs_ep
->periodic
;
421 * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
422 * @hsotg: The device state.
423 * @hs_ep: The endpoint for the request
424 * @hs_req: The request being processed.
426 * This is the reverse of s3c_hsotg_map_dma(), called for the completion
427 * of a request to ensure the buffer is ready for access by the caller.
429 static void s3c_hsotg_unmap_dma(struct s3c_hsotg
*hsotg
,
430 struct s3c_hsotg_ep
*hs_ep
,
431 struct s3c_hsotg_req
*hs_req
)
433 struct usb_request
*req
= &hs_req
->req
;
434 enum dma_data_direction dir
;
436 dir
= hs_ep
->dir_in
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
438 /* ignore this if we're not moving any data */
439 if (hs_req
->req
.length
== 0)
442 if (hs_req
->mapped
) {
443 /* we mapped this, so unmap and remove the dma */
445 dma_unmap_single(hsotg
->dev
, req
->dma
, req
->length
, dir
);
447 req
->dma
= DMA_ADDR_INVALID
;
450 dma_sync_single_for_cpu(hsotg
->dev
, req
->dma
, req
->length
, dir
);
455 * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
456 * @hsotg: The controller state.
457 * @hs_ep: The endpoint we're going to write for.
458 * @hs_req: The request to write data for.
460 * This is called when the TxFIFO has some space in it to hold a new
461 * transmission and we have something to give it. The actual setup of
462 * the data size is done elsewhere, so all we have to do is to actually
465 * The return value is zero if there is more space (or nothing was done)
466 * otherwise -ENOSPC is returned if the FIFO space was used up.
468 * This routine is only needed for PIO
470 static int s3c_hsotg_write_fifo(struct s3c_hsotg
*hsotg
,
471 struct s3c_hsotg_ep
*hs_ep
,
472 struct s3c_hsotg_req
*hs_req
)
474 bool periodic
= is_ep_periodic(hs_ep
);
475 u32 gnptxsts
= readl(hsotg
->regs
+ GNPTXSTS
);
476 int buf_pos
= hs_req
->req
.actual
;
477 int to_write
= hs_ep
->size_loaded
;
482 to_write
-= (buf_pos
- hs_ep
->last_load
);
484 /* if there's nothing to write, get out early */
488 if (periodic
&& !hsotg
->dedicated_fifos
) {
489 u32 epsize
= readl(hsotg
->regs
+ DIEPTSIZ(hs_ep
->index
));
494 * work out how much data was loaded so we can calculate
495 * how much data is left in the fifo.
498 size_left
= DxEPTSIZ_XferSize_GET(epsize
);
501 * if shared fifo, we cannot write anything until the
502 * previous data has been completely sent.
504 if (hs_ep
->fifo_load
!= 0) {
505 s3c_hsotg_en_gsint(hsotg
, GINTSTS_PTxFEmp
);
509 dev_dbg(hsotg
->dev
, "%s: left=%d, load=%d, fifo=%d, size %d\n",
511 hs_ep
->size_loaded
, hs_ep
->fifo_load
, hs_ep
->fifo_size
);
513 /* how much of the data has moved */
514 size_done
= hs_ep
->size_loaded
- size_left
;
516 /* how much data is left in the fifo */
517 can_write
= hs_ep
->fifo_load
- size_done
;
518 dev_dbg(hsotg
->dev
, "%s: => can_write1=%d\n",
519 __func__
, can_write
);
521 can_write
= hs_ep
->fifo_size
- can_write
;
522 dev_dbg(hsotg
->dev
, "%s: => can_write2=%d\n",
523 __func__
, can_write
);
525 if (can_write
<= 0) {
526 s3c_hsotg_en_gsint(hsotg
, GINTSTS_PTxFEmp
);
529 } else if (hsotg
->dedicated_fifos
&& hs_ep
->index
!= 0) {
530 can_write
= readl(hsotg
->regs
+ DTXFSTS(hs_ep
->index
));
535 if (GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts
) == 0) {
537 "%s: no queue slots available (0x%08x)\n",
540 s3c_hsotg_en_gsint(hsotg
, GINTSTS_NPTxFEmp
);
544 can_write
= GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts
);
545 can_write
*= 4; /* fifo size is in 32bit quantities. */
548 dev_dbg(hsotg
->dev
, "%s: GNPTXSTS=%08x, can=%d, to=%d, mps %d\n",
549 __func__
, gnptxsts
, can_write
, to_write
, hs_ep
->ep
.maxpacket
);
552 * limit to 512 bytes of data, it seems at least on the non-periodic
553 * FIFO, requests of >512 cause the endpoint to get stuck with a
554 * fragment of the end of the transfer in it.
560 * limit the write to one max-packet size worth of data, but allow
561 * the transfer to return that it did not run out of fifo space
564 if (to_write
> hs_ep
->ep
.maxpacket
) {
565 to_write
= hs_ep
->ep
.maxpacket
;
567 s3c_hsotg_en_gsint(hsotg
,
568 periodic
? GINTSTS_PTxFEmp
:
572 /* see if we can write data */
574 if (to_write
> can_write
) {
575 to_write
= can_write
;
576 pkt_round
= to_write
% hs_ep
->ep
.maxpacket
;
579 * Round the write down to an
580 * exact number of packets.
582 * Note, we do not currently check to see if we can ever
583 * write a full packet or not to the FIFO.
587 to_write
-= pkt_round
;
590 * enable correct FIFO interrupt to alert us when there
594 s3c_hsotg_en_gsint(hsotg
,
595 periodic
? GINTSTS_PTxFEmp
:
599 dev_dbg(hsotg
->dev
, "write %d/%d, can_write %d, done %d\n",
600 to_write
, hs_req
->req
.length
, can_write
, buf_pos
);
605 hs_req
->req
.actual
= buf_pos
+ to_write
;
606 hs_ep
->total_data
+= to_write
;
609 hs_ep
->fifo_load
+= to_write
;
611 to_write
= DIV_ROUND_UP(to_write
, 4);
612 data
= hs_req
->req
.buf
+ buf_pos
;
614 writesl(hsotg
->regs
+ EPFIFO(hs_ep
->index
), data
, to_write
);
616 return (to_write
>= can_write
) ? -ENOSPC
: 0;
620 * get_ep_limit - get the maximum data legnth for this endpoint
621 * @hs_ep: The endpoint
623 * Return the maximum data that can be queued in one go on a given endpoint
624 * so that transfers that are too long can be split.
626 static unsigned get_ep_limit(struct s3c_hsotg_ep
*hs_ep
)
628 int index
= hs_ep
->index
;
633 maxsize
= DxEPTSIZ_XferSize_LIMIT
+ 1;
634 maxpkt
= DxEPTSIZ_PktCnt_LIMIT
+ 1;
638 maxpkt
= DIEPTSIZ0_PktCnt_LIMIT
+ 1;
643 /* we made the constant loading easier above by using +1 */
648 * constrain by packet count if maxpkts*pktsize is greater
649 * than the length register size.
652 if ((maxpkt
* hs_ep
->ep
.maxpacket
) < maxsize
)
653 maxsize
= maxpkt
* hs_ep
->ep
.maxpacket
;
659 * s3c_hsotg_start_req - start a USB request from an endpoint's queue
660 * @hsotg: The controller state.
661 * @hs_ep: The endpoint to process a request for
662 * @hs_req: The request to start.
663 * @continuing: True if we are doing more for the current request.
665 * Start the given request running by setting the endpoint registers
666 * appropriately, and writing any data to the FIFOs.
668 static void s3c_hsotg_start_req(struct s3c_hsotg
*hsotg
,
669 struct s3c_hsotg_ep
*hs_ep
,
670 struct s3c_hsotg_req
*hs_req
,
673 struct usb_request
*ureq
= &hs_req
->req
;
674 int index
= hs_ep
->index
;
675 int dir_in
= hs_ep
->dir_in
;
685 if (hs_ep
->req
&& !continuing
) {
686 dev_err(hsotg
->dev
, "%s: active request\n", __func__
);
689 } else if (hs_ep
->req
!= hs_req
&& continuing
) {
691 "%s: continue different req\n", __func__
);
697 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
698 epsize_reg
= dir_in
? DIEPTSIZ(index
) : DOEPTSIZ(index
);
700 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
701 __func__
, readl(hsotg
->regs
+ epctrl_reg
), index
,
702 hs_ep
->dir_in
? "in" : "out");
704 /* If endpoint is stalled, we will restart request later */
705 ctrl
= readl(hsotg
->regs
+ epctrl_reg
);
707 if (ctrl
& DxEPCTL_Stall
) {
708 dev_warn(hsotg
->dev
, "%s: ep%d is stalled\n", __func__
, index
);
712 length
= ureq
->length
- ureq
->actual
;
713 dev_dbg(hsotg
->dev
, "ureq->length:%d ureq->actual:%d\n",
714 ureq
->length
, ureq
->actual
);
717 "REQ buf %p len %d dma 0x%08x noi=%d zp=%d snok=%d\n",
718 ureq
->buf
, length
, ureq
->dma
,
719 ureq
->no_interrupt
, ureq
->zero
, ureq
->short_not_ok
);
721 maxreq
= get_ep_limit(hs_ep
);
722 if (length
> maxreq
) {
723 int round
= maxreq
% hs_ep
->ep
.maxpacket
;
725 dev_dbg(hsotg
->dev
, "%s: length %d, max-req %d, r %d\n",
726 __func__
, length
, maxreq
, round
);
728 /* round down to multiple of packets */
736 packets
= DIV_ROUND_UP(length
, hs_ep
->ep
.maxpacket
);
738 packets
= 1; /* send one packet if length is zero. */
740 if (dir_in
&& index
!= 0)
741 epsize
= DxEPTSIZ_MC(1);
745 if (index
!= 0 && ureq
->zero
) {
747 * test for the packets being exactly right for the
751 if (length
== (packets
* hs_ep
->ep
.maxpacket
))
755 epsize
|= DxEPTSIZ_PktCnt(packets
);
756 epsize
|= DxEPTSIZ_XferSize(length
);
758 dev_dbg(hsotg
->dev
, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
759 __func__
, packets
, length
, ureq
->length
, epsize
, epsize_reg
);
761 /* store the request as the current one we're doing */
764 /* write size / packets */
765 writel(epsize
, hsotg
->regs
+ epsize_reg
);
767 if (using_dma(hsotg
) && !continuing
) {
768 unsigned int dma_reg
;
771 * write DMA address to control register, buffer already
772 * synced by s3c_hsotg_ep_queue().
775 dma_reg
= dir_in
? DIEPDMA(index
) : DOEPDMA(index
);
776 writel(ureq
->dma
, hsotg
->regs
+ dma_reg
);
778 dev_dbg(hsotg
->dev
, "%s: 0x%08x => 0x%08x\n",
779 __func__
, ureq
->dma
, dma_reg
);
782 ctrl
|= DxEPCTL_EPEna
; /* ensure ep enabled */
783 ctrl
|= DxEPCTL_USBActEp
;
785 dev_dbg(hsotg
->dev
, "setup req:%d\n", hsotg
->setup
);
787 /* For Setup request do not clear NAK */
788 if (hsotg
->setup
&& index
== 0)
791 ctrl
|= DxEPCTL_CNAK
; /* clear NAK set by core */
794 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n", __func__
, ctrl
);
795 writel(ctrl
, hsotg
->regs
+ epctrl_reg
);
798 * set these, it seems that DMA support increments past the end
799 * of the packet buffer so we need to calculate the length from
802 hs_ep
->size_loaded
= length
;
803 hs_ep
->last_load
= ureq
->actual
;
805 if (dir_in
&& !using_dma(hsotg
)) {
806 /* set these anyway, we may need them for non-periodic in */
807 hs_ep
->fifo_load
= 0;
809 s3c_hsotg_write_fifo(hsotg
, hs_ep
, hs_req
);
813 * clear the INTknTXFEmpMsk when we start request, more as a aide
814 * to debugging to see what is going on.
817 writel(DIEPMSK_INTknTXFEmpMsk
,
818 hsotg
->regs
+ DIEPINT(index
));
821 * Note, trying to clear the NAK here causes problems with transmit
822 * on the S3C6400 ending up with the TXFIFO becoming full.
825 /* check ep is enabled */
826 if (!(readl(hsotg
->regs
+ epctrl_reg
) & DxEPCTL_EPEna
))
828 "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n",
829 index
, readl(hsotg
->regs
+ epctrl_reg
));
831 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n",
832 __func__
, readl(hsotg
->regs
+ epctrl_reg
));
836 * s3c_hsotg_map_dma - map the DMA memory being used for the request
837 * @hsotg: The device state.
838 * @hs_ep: The endpoint the request is on.
839 * @req: The request being processed.
841 * We've been asked to queue a request, so ensure that the memory buffer
842 * is correctly setup for DMA. If we've been passed an extant DMA address
843 * then ensure the buffer has been synced to memory. If our buffer has no
844 * DMA memory, then we map the memory and mark our request to allow us to
845 * cleanup on completion.
847 static int s3c_hsotg_map_dma(struct s3c_hsotg
*hsotg
,
848 struct s3c_hsotg_ep
*hs_ep
,
849 struct usb_request
*req
)
851 enum dma_data_direction dir
;
852 struct s3c_hsotg_req
*hs_req
= our_req(req
);
854 dir
= hs_ep
->dir_in
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
856 /* if the length is zero, ignore the DMA data */
857 if (hs_req
->req
.length
== 0)
860 if (req
->dma
== DMA_ADDR_INVALID
) {
863 dma
= dma_map_single(hsotg
->dev
, req
->buf
, req
->length
, dir
);
865 if (unlikely(dma_mapping_error(hsotg
->dev
, dma
)))
869 dev_err(hsotg
->dev
, "%s: unaligned dma buffer\n",
872 dma_unmap_single(hsotg
->dev
, dma
, req
->length
, dir
);
879 dma_sync_single_for_cpu(hsotg
->dev
, req
->dma
, req
->length
, dir
);
886 dev_err(hsotg
->dev
, "%s: failed to map buffer %p, %d bytes\n",
887 __func__
, req
->buf
, req
->length
);
892 static int s3c_hsotg_ep_queue(struct usb_ep
*ep
, struct usb_request
*req
,
895 struct s3c_hsotg_req
*hs_req
= our_req(req
);
896 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
897 struct s3c_hsotg
*hs
= hs_ep
->parent
;
900 dev_dbg(hs
->dev
, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
901 ep
->name
, req
, req
->length
, req
->buf
, req
->no_interrupt
,
902 req
->zero
, req
->short_not_ok
);
904 /* initialise status of the request */
905 INIT_LIST_HEAD(&hs_req
->queue
);
907 req
->status
= -EINPROGRESS
;
909 /* if we're using DMA, sync the buffers as necessary */
911 int ret
= s3c_hsotg_map_dma(hs
, hs_ep
, req
);
916 first
= list_empty(&hs_ep
->queue
);
917 list_add_tail(&hs_req
->queue
, &hs_ep
->queue
);
920 s3c_hsotg_start_req(hs
, hs_ep
, hs_req
, false);
925 static int s3c_hsotg_ep_queue_lock(struct usb_ep
*ep
, struct usb_request
*req
,
928 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
929 struct s3c_hsotg
*hs
= hs_ep
->parent
;
930 unsigned long flags
= 0;
933 spin_lock_irqsave(&hs
->lock
, flags
);
934 ret
= s3c_hsotg_ep_queue(ep
, req
, gfp_flags
);
935 spin_unlock_irqrestore(&hs
->lock
, flags
);
940 static void s3c_hsotg_ep_free_request(struct usb_ep
*ep
,
941 struct usb_request
*req
)
943 struct s3c_hsotg_req
*hs_req
= our_req(req
);
949 * s3c_hsotg_complete_oursetup - setup completion callback
950 * @ep: The endpoint the request was on.
951 * @req: The request completed.
953 * Called on completion of any requests the driver itself
954 * submitted that need cleaning up.
956 static void s3c_hsotg_complete_oursetup(struct usb_ep
*ep
,
957 struct usb_request
*req
)
959 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
960 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
962 dev_dbg(hsotg
->dev
, "%s: ep %p, req %p\n", __func__
, ep
, req
);
964 s3c_hsotg_ep_free_request(ep
, req
);
968 * ep_from_windex - convert control wIndex value to endpoint
969 * @hsotg: The driver state.
970 * @windex: The control request wIndex field (in host order).
972 * Convert the given wIndex into a pointer to an driver endpoint
973 * structure, or return NULL if it is not a valid endpoint.
975 static struct s3c_hsotg_ep
*ep_from_windex(struct s3c_hsotg
*hsotg
,
978 struct s3c_hsotg_ep
*ep
= &hsotg
->eps
[windex
& 0x7F];
979 int dir
= (windex
& USB_DIR_IN
) ? 1 : 0;
980 int idx
= windex
& 0x7F;
985 if (idx
> hsotg
->num_of_eps
)
988 if (idx
&& ep
->dir_in
!= dir
)
995 * s3c_hsotg_send_reply - send reply to control request
996 * @hsotg: The device state
998 * @buff: Buffer for request
999 * @length: Length of reply.
1001 * Create a request and queue it on the given endpoint. This is useful as
1002 * an internal method of sending replies to certain control requests, etc.
1004 static int s3c_hsotg_send_reply(struct s3c_hsotg
*hsotg
,
1005 struct s3c_hsotg_ep
*ep
,
1009 struct usb_request
*req
;
1012 dev_dbg(hsotg
->dev
, "%s: buff %p, len %d\n", __func__
, buff
, length
);
1014 req
= s3c_hsotg_ep_alloc_request(&ep
->ep
, GFP_ATOMIC
);
1015 hsotg
->ep0_reply
= req
;
1017 dev_warn(hsotg
->dev
, "%s: cannot alloc req\n", __func__
);
1021 req
->buf
= hsotg
->ep0_buff
;
1022 req
->length
= length
;
1023 req
->zero
= 1; /* always do zero-length final transfer */
1024 req
->complete
= s3c_hsotg_complete_oursetup
;
1027 memcpy(req
->buf
, buff
, length
);
1031 ret
= s3c_hsotg_ep_queue(&ep
->ep
, req
, GFP_ATOMIC
);
1033 dev_warn(hsotg
->dev
, "%s: cannot queue req\n", __func__
);
1041 * s3c_hsotg_process_req_status - process request GET_STATUS
1042 * @hsotg: The device state
1043 * @ctrl: USB control request
1045 static int s3c_hsotg_process_req_status(struct s3c_hsotg
*hsotg
,
1046 struct usb_ctrlrequest
*ctrl
)
1048 struct s3c_hsotg_ep
*ep0
= &hsotg
->eps
[0];
1049 struct s3c_hsotg_ep
*ep
;
1053 dev_dbg(hsotg
->dev
, "%s: USB_REQ_GET_STATUS\n", __func__
);
1056 dev_warn(hsotg
->dev
, "%s: direction out?\n", __func__
);
1060 switch (ctrl
->bRequestType
& USB_RECIP_MASK
) {
1061 case USB_RECIP_DEVICE
:
1062 reply
= cpu_to_le16(0); /* bit 0 => self powered,
1063 * bit 1 => remote wakeup */
1066 case USB_RECIP_INTERFACE
:
1067 /* currently, the data result should be zero */
1068 reply
= cpu_to_le16(0);
1071 case USB_RECIP_ENDPOINT
:
1072 ep
= ep_from_windex(hsotg
, le16_to_cpu(ctrl
->wIndex
));
1076 reply
= cpu_to_le16(ep
->halted
? 1 : 0);
1083 if (le16_to_cpu(ctrl
->wLength
) != 2)
1086 ret
= s3c_hsotg_send_reply(hsotg
, ep0
, &reply
, 2);
1088 dev_err(hsotg
->dev
, "%s: failed to send reply\n", __func__
);
1095 static int s3c_hsotg_ep_sethalt(struct usb_ep
*ep
, int value
);
1098 * get_ep_head - return the first request on the endpoint
1099 * @hs_ep: The controller endpoint to get
1101 * Get the first request on the endpoint.
1103 static struct s3c_hsotg_req
*get_ep_head(struct s3c_hsotg_ep
*hs_ep
)
1105 if (list_empty(&hs_ep
->queue
))
1108 return list_first_entry(&hs_ep
->queue
, struct s3c_hsotg_req
, queue
);
1112 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
1113 * @hsotg: The device state
1114 * @ctrl: USB control request
1116 static int s3c_hsotg_process_req_feature(struct s3c_hsotg
*hsotg
,
1117 struct usb_ctrlrequest
*ctrl
)
1119 struct s3c_hsotg_ep
*ep0
= &hsotg
->eps
[0];
1120 struct s3c_hsotg_req
*hs_req
;
1122 bool set
= (ctrl
->bRequest
== USB_REQ_SET_FEATURE
);
1123 struct s3c_hsotg_ep
*ep
;
1126 dev_dbg(hsotg
->dev
, "%s: %s_FEATURE\n",
1127 __func__
, set
? "SET" : "CLEAR");
1129 if (ctrl
->bRequestType
== USB_RECIP_ENDPOINT
) {
1130 ep
= ep_from_windex(hsotg
, le16_to_cpu(ctrl
->wIndex
));
1132 dev_dbg(hsotg
->dev
, "%s: no endpoint for 0x%04x\n",
1133 __func__
, le16_to_cpu(ctrl
->wIndex
));
1137 switch (le16_to_cpu(ctrl
->wValue
)) {
1138 case USB_ENDPOINT_HALT
:
1139 s3c_hsotg_ep_sethalt(&ep
->ep
, set
);
1141 ret
= s3c_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1144 "%s: failed to send reply\n", __func__
);
1150 * If we have request in progress,
1156 list_del_init(&hs_req
->queue
);
1157 hs_req
->req
.complete(&ep
->ep
,
1161 /* If we have pending request, then start it */
1162 restart
= !list_empty(&ep
->queue
);
1164 hs_req
= get_ep_head(ep
);
1165 s3c_hsotg_start_req(hsotg
, ep
,
1176 return -ENOENT
; /* currently only deal with endpoint */
1182 * s3c_hsotg_process_control - process a control request
1183 * @hsotg: The device state
1184 * @ctrl: The control request received
1186 * The controller has received the SETUP phase of a control request, and
1187 * needs to work out what to do next (and whether to pass it on to the
1190 static void s3c_hsotg_process_control(struct s3c_hsotg
*hsotg
,
1191 struct usb_ctrlrequest
*ctrl
)
1193 struct s3c_hsotg_ep
*ep0
= &hsotg
->eps
[0];
1199 dev_dbg(hsotg
->dev
, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1200 ctrl
->bRequest
, ctrl
->bRequestType
,
1201 ctrl
->wValue
, ctrl
->wLength
);
1204 * record the direction of the request, for later use when enquing
1208 ep0
->dir_in
= (ctrl
->bRequestType
& USB_DIR_IN
) ? 1 : 0;
1209 dev_dbg(hsotg
->dev
, "ctrl: dir_in=%d\n", ep0
->dir_in
);
1212 * if we've no data with this request, then the last part of the
1213 * transaction is going to implicitly be IN.
1215 if (ctrl
->wLength
== 0)
1218 if ((ctrl
->bRequestType
& USB_TYPE_MASK
) == USB_TYPE_STANDARD
) {
1219 switch (ctrl
->bRequest
) {
1220 case USB_REQ_SET_ADDRESS
:
1221 dcfg
= readl(hsotg
->regs
+ DCFG
);
1222 dcfg
&= ~DCFG_DevAddr_MASK
;
1223 dcfg
|= ctrl
->wValue
<< DCFG_DevAddr_SHIFT
;
1224 writel(dcfg
, hsotg
->regs
+ DCFG
);
1226 dev_info(hsotg
->dev
, "new address %d\n", ctrl
->wValue
);
1228 ret
= s3c_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1231 case USB_REQ_GET_STATUS
:
1232 ret
= s3c_hsotg_process_req_status(hsotg
, ctrl
);
1235 case USB_REQ_CLEAR_FEATURE
:
1236 case USB_REQ_SET_FEATURE
:
1237 ret
= s3c_hsotg_process_req_feature(hsotg
, ctrl
);
1242 /* as a fallback, try delivering it to the driver to deal with */
1244 if (ret
== 0 && hsotg
->driver
) {
1245 ret
= hsotg
->driver
->setup(&hsotg
->gadget
, ctrl
);
1247 dev_dbg(hsotg
->dev
, "driver->setup() ret %d\n", ret
);
1251 * the request is either unhandlable, or is not formatted correctly
1252 * so respond with a STALL for the status stage to indicate failure.
1259 dev_dbg(hsotg
->dev
, "ep0 stall (dir=%d)\n", ep0
->dir_in
);
1260 reg
= (ep0
->dir_in
) ? DIEPCTL0
: DOEPCTL0
;
1263 * DxEPCTL_Stall will be cleared by EP once it has
1264 * taken effect, so no need to clear later.
1267 ctrl
= readl(hsotg
->regs
+ reg
);
1268 ctrl
|= DxEPCTL_Stall
;
1269 ctrl
|= DxEPCTL_CNAK
;
1270 writel(ctrl
, hsotg
->regs
+ reg
);
1273 "written DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n",
1274 ctrl
, reg
, readl(hsotg
->regs
+ reg
));
1277 * don't believe we need to anything more to get the EP
1278 * to reply with a STALL packet
1283 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg
*hsotg
);
1286 * s3c_hsotg_complete_setup - completion of a setup transfer
1287 * @ep: The endpoint the request was on.
1288 * @req: The request completed.
1290 * Called on completion of any requests the driver itself submitted for
1293 static void s3c_hsotg_complete_setup(struct usb_ep
*ep
,
1294 struct usb_request
*req
)
1296 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
1297 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
1299 if (req
->status
< 0) {
1300 dev_dbg(hsotg
->dev
, "%s: failed %d\n", __func__
, req
->status
);
1304 if (req
->actual
== 0)
1305 s3c_hsotg_enqueue_setup(hsotg
);
1307 s3c_hsotg_process_control(hsotg
, req
->buf
);
1311 * s3c_hsotg_enqueue_setup - start a request for EP0 packets
1312 * @hsotg: The device state.
1314 * Enqueue a request on EP0 if necessary to received any SETUP packets
1315 * received from the host.
1317 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg
*hsotg
)
1319 struct usb_request
*req
= hsotg
->ctrl_req
;
1320 struct s3c_hsotg_req
*hs_req
= our_req(req
);
1323 dev_dbg(hsotg
->dev
, "%s: queueing setup request\n", __func__
);
1327 req
->buf
= hsotg
->ctrl_buff
;
1328 req
->complete
= s3c_hsotg_complete_setup
;
1330 if (!list_empty(&hs_req
->queue
)) {
1331 dev_dbg(hsotg
->dev
, "%s already queued???\n", __func__
);
1335 hsotg
->eps
[0].dir_in
= 0;
1337 ret
= s3c_hsotg_ep_queue(&hsotg
->eps
[0].ep
, req
, GFP_ATOMIC
);
1339 dev_err(hsotg
->dev
, "%s: failed queue (%d)\n", __func__
, ret
);
1341 * Don't think there's much we can do other than watch the
1348 * s3c_hsotg_complete_request - complete a request given to us
1349 * @hsotg: The device state.
1350 * @hs_ep: The endpoint the request was on.
1351 * @hs_req: The request to complete.
1352 * @result: The result code (0 => Ok, otherwise errno)
1354 * The given request has finished, so call the necessary completion
1355 * if it has one and then look to see if we can start a new request
1358 * Note, expects the ep to already be locked as appropriate.
1360 static void s3c_hsotg_complete_request(struct s3c_hsotg
*hsotg
,
1361 struct s3c_hsotg_ep
*hs_ep
,
1362 struct s3c_hsotg_req
*hs_req
,
1368 dev_dbg(hsotg
->dev
, "%s: nothing to complete?\n", __func__
);
1372 dev_dbg(hsotg
->dev
, "complete: ep %p %s, req %p, %d => %p\n",
1373 hs_ep
, hs_ep
->ep
.name
, hs_req
, result
, hs_req
->req
.complete
);
1376 * only replace the status if we've not already set an error
1377 * from a previous transaction
1380 if (hs_req
->req
.status
== -EINPROGRESS
)
1381 hs_req
->req
.status
= result
;
1384 list_del_init(&hs_req
->queue
);
1386 if (using_dma(hsotg
))
1387 s3c_hsotg_unmap_dma(hsotg
, hs_ep
, hs_req
);
1390 * call the complete request with the locks off, just in case the
1391 * request tries to queue more work for this endpoint.
1394 if (hs_req
->req
.complete
) {
1395 spin_unlock(&hsotg
->lock
);
1396 hs_req
->req
.complete(&hs_ep
->ep
, &hs_req
->req
);
1397 spin_lock(&hsotg
->lock
);
1401 * Look to see if there is anything else to do. Note, the completion
1402 * of the previous request may have caused a new request to be started
1403 * so be careful when doing this.
1406 if (!hs_ep
->req
&& result
>= 0) {
1407 restart
= !list_empty(&hs_ep
->queue
);
1409 hs_req
= get_ep_head(hs_ep
);
1410 s3c_hsotg_start_req(hsotg
, hs_ep
, hs_req
, false);
1416 * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
1417 * @hsotg: The device state.
1418 * @ep_idx: The endpoint index for the data
1419 * @size: The size of data in the fifo, in bytes
1421 * The FIFO status shows there is data to read from the FIFO for a given
1422 * endpoint, so sort out whether we need to read the data into a request
1423 * that has been made for that endpoint.
1425 static void s3c_hsotg_rx_data(struct s3c_hsotg
*hsotg
, int ep_idx
, int size
)
1427 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[ep_idx
];
1428 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1429 void __iomem
*fifo
= hsotg
->regs
+ EPFIFO(ep_idx
);
1436 u32 epctl
= readl(hsotg
->regs
+ DOEPCTL(ep_idx
));
1439 dev_warn(hsotg
->dev
,
1440 "%s: FIFO %d bytes on ep%d but no req (DxEPCTl=0x%08x)\n",
1441 __func__
, size
, ep_idx
, epctl
);
1443 /* dump the data from the FIFO, we've nothing we can do */
1444 for (ptr
= 0; ptr
< size
; ptr
+= 4)
1451 read_ptr
= hs_req
->req
.actual
;
1452 max_req
= hs_req
->req
.length
- read_ptr
;
1454 dev_dbg(hsotg
->dev
, "%s: read %d/%d, done %d/%d\n",
1455 __func__
, to_read
, max_req
, read_ptr
, hs_req
->req
.length
);
1457 if (to_read
> max_req
) {
1459 * more data appeared than we where willing
1460 * to deal with in this request.
1463 /* currently we don't deal this */
1467 hs_ep
->total_data
+= to_read
;
1468 hs_req
->req
.actual
+= to_read
;
1469 to_read
= DIV_ROUND_UP(to_read
, 4);
1472 * note, we might over-write the buffer end by 3 bytes depending on
1473 * alignment of the data.
1475 readsl(fifo
, hs_req
->req
.buf
+ read_ptr
, to_read
);
1479 * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
1480 * @hsotg: The device instance
1481 * @req: The request currently on this endpoint
1483 * Generate a zero-length IN packet request for terminating a SETUP
1486 * Note, since we don't write any data to the TxFIFO, then it is
1487 * currently believed that we do not need to wait for any space in
1490 static void s3c_hsotg_send_zlp(struct s3c_hsotg
*hsotg
,
1491 struct s3c_hsotg_req
*req
)
1496 dev_warn(hsotg
->dev
, "%s: no request?\n", __func__
);
1500 if (req
->req
.length
== 0) {
1501 hsotg
->eps
[0].sent_zlp
= 1;
1502 s3c_hsotg_enqueue_setup(hsotg
);
1506 hsotg
->eps
[0].dir_in
= 1;
1507 hsotg
->eps
[0].sent_zlp
= 1;
1509 dev_dbg(hsotg
->dev
, "sending zero-length packet\n");
1511 /* issue a zero-sized packet to terminate this */
1512 writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) |
1513 DxEPTSIZ_XferSize(0), hsotg
->regs
+ DIEPTSIZ(0));
1515 ctrl
= readl(hsotg
->regs
+ DIEPCTL0
);
1516 ctrl
|= DxEPCTL_CNAK
; /* clear NAK set by core */
1517 ctrl
|= DxEPCTL_EPEna
; /* ensure ep enabled */
1518 ctrl
|= DxEPCTL_USBActEp
;
1519 writel(ctrl
, hsotg
->regs
+ DIEPCTL0
);
1523 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1524 * @hsotg: The device instance
1525 * @epnum: The endpoint received from
1526 * @was_setup: Set if processing a SetupDone event.
1528 * The RXFIFO has delivered an OutDone event, which means that the data
1529 * transfer for an OUT endpoint has been completed, either by a short
1530 * packet or by the finish of a transfer.
1532 static void s3c_hsotg_handle_outdone(struct s3c_hsotg
*hsotg
,
1533 int epnum
, bool was_setup
)
1535 u32 epsize
= readl(hsotg
->regs
+ DOEPTSIZ(epnum
));
1536 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[epnum
];
1537 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1538 struct usb_request
*req
= &hs_req
->req
;
1539 unsigned size_left
= DxEPTSIZ_XferSize_GET(epsize
);
1543 dev_dbg(hsotg
->dev
, "%s: no request active\n", __func__
);
1547 if (using_dma(hsotg
)) {
1551 * Calculate the size of the transfer by checking how much
1552 * is left in the endpoint size register and then working it
1553 * out from the amount we loaded for the transfer.
1555 * We need to do this as DMA pointers are always 32bit aligned
1556 * so may overshoot/undershoot the transfer.
1559 size_done
= hs_ep
->size_loaded
- size_left
;
1560 size_done
+= hs_ep
->last_load
;
1562 req
->actual
= size_done
;
1565 /* if there is more request to do, schedule new transfer */
1566 if (req
->actual
< req
->length
&& size_left
== 0) {
1567 s3c_hsotg_start_req(hsotg
, hs_ep
, hs_req
, true);
1569 } else if (epnum
== 0) {
1571 * After was_setup = 1 =>
1572 * set CNAK for non Setup requests
1574 hsotg
->setup
= was_setup
? 0 : 1;
1577 if (req
->actual
< req
->length
&& req
->short_not_ok
) {
1578 dev_dbg(hsotg
->dev
, "%s: got %d/%d (short not ok) => error\n",
1579 __func__
, req
->actual
, req
->length
);
1582 * todo - what should we return here? there's no one else
1583 * even bothering to check the status.
1589 * Condition req->complete != s3c_hsotg_complete_setup says:
1590 * send ZLP when we have an asynchronous request from gadget
1592 if (!was_setup
&& req
->complete
!= s3c_hsotg_complete_setup
)
1593 s3c_hsotg_send_zlp(hsotg
, hs_req
);
1596 s3c_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, result
);
1600 * s3c_hsotg_read_frameno - read current frame number
1601 * @hsotg: The device instance
1603 * Return the current frame number
1605 static u32
s3c_hsotg_read_frameno(struct s3c_hsotg
*hsotg
)
1609 dsts
= readl(hsotg
->regs
+ DSTS
);
1610 dsts
&= DSTS_SOFFN_MASK
;
1611 dsts
>>= DSTS_SOFFN_SHIFT
;
1617 * s3c_hsotg_handle_rx - RX FIFO has data
1618 * @hsotg: The device instance
1620 * The IRQ handler has detected that the RX FIFO has some data in it
1621 * that requires processing, so find out what is in there and do the
1624 * The RXFIFO is a true FIFO, the packets coming out are still in packet
1625 * chunks, so if you have x packets received on an endpoint you'll get x
1626 * FIFO events delivered, each with a packet's worth of data in it.
1628 * When using DMA, we should not be processing events from the RXFIFO
1629 * as the actual data should be sent to the memory directly and we turn
1630 * on the completion interrupts to get notifications of transfer completion.
1632 static void s3c_hsotg_handle_rx(struct s3c_hsotg
*hsotg
)
1634 u32 grxstsr
= readl(hsotg
->regs
+ GRXSTSP
);
1635 u32 epnum
, status
, size
;
1637 WARN_ON(using_dma(hsotg
));
1639 epnum
= grxstsr
& GRXSTS_EPNum_MASK
;
1640 status
= grxstsr
& GRXSTS_PktSts_MASK
;
1642 size
= grxstsr
& GRXSTS_ByteCnt_MASK
;
1643 size
>>= GRXSTS_ByteCnt_SHIFT
;
1646 dev_dbg(hsotg
->dev
, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1647 __func__
, grxstsr
, size
, epnum
);
1649 #define __status(x) ((x) >> GRXSTS_PktSts_SHIFT)
1651 switch (status
>> GRXSTS_PktSts_SHIFT
) {
1652 case __status(GRXSTS_PktSts_GlobalOutNAK
):
1653 dev_dbg(hsotg
->dev
, "GlobalOutNAK\n");
1656 case __status(GRXSTS_PktSts_OutDone
):
1657 dev_dbg(hsotg
->dev
, "OutDone (Frame=0x%08x)\n",
1658 s3c_hsotg_read_frameno(hsotg
));
1660 if (!using_dma(hsotg
))
1661 s3c_hsotg_handle_outdone(hsotg
, epnum
, false);
1664 case __status(GRXSTS_PktSts_SetupDone
):
1666 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1667 s3c_hsotg_read_frameno(hsotg
),
1668 readl(hsotg
->regs
+ DOEPCTL(0)));
1670 s3c_hsotg_handle_outdone(hsotg
, epnum
, true);
1673 case __status(GRXSTS_PktSts_OutRX
):
1674 s3c_hsotg_rx_data(hsotg
, epnum
, size
);
1677 case __status(GRXSTS_PktSts_SetupRX
):
1679 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1680 s3c_hsotg_read_frameno(hsotg
),
1681 readl(hsotg
->regs
+ DOEPCTL(0)));
1683 s3c_hsotg_rx_data(hsotg
, epnum
, size
);
1687 dev_warn(hsotg
->dev
, "%s: unknown status %08x\n",
1690 s3c_hsotg_dump(hsotg
);
1696 * s3c_hsotg_ep0_mps - turn max packet size into register setting
1697 * @mps: The maximum packet size in bytes.
1699 static u32
s3c_hsotg_ep0_mps(unsigned int mps
)
1703 return D0EPCTL_MPS_64
;
1705 return D0EPCTL_MPS_32
;
1707 return D0EPCTL_MPS_16
;
1709 return D0EPCTL_MPS_8
;
1712 /* bad max packet size, warn and return invalid result */
1718 * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1719 * @hsotg: The driver state.
1720 * @ep: The index number of the endpoint
1721 * @mps: The maximum packet size in bytes
1723 * Configure the maximum packet size for the given endpoint, updating
1724 * the hardware control registers to reflect this.
1726 static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg
*hsotg
,
1727 unsigned int ep
, unsigned int mps
)
1729 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[ep
];
1730 void __iomem
*regs
= hsotg
->regs
;
1735 /* EP0 is a special case */
1736 mpsval
= s3c_hsotg_ep0_mps(mps
);
1740 if (mps
>= DxEPCTL_MPS_LIMIT
+1)
1746 hs_ep
->ep
.maxpacket
= mps
;
1749 * update both the in and out endpoint controldir_ registers, even
1750 * if one of the directions may not be in use.
1753 reg
= readl(regs
+ DIEPCTL(ep
));
1754 reg
&= ~DxEPCTL_MPS_MASK
;
1756 writel(reg
, regs
+ DIEPCTL(ep
));
1759 reg
= readl(regs
+ DOEPCTL(ep
));
1760 reg
&= ~DxEPCTL_MPS_MASK
;
1762 writel(reg
, regs
+ DOEPCTL(ep
));
1768 dev_err(hsotg
->dev
, "ep%d: bad mps of %d\n", ep
, mps
);
1772 * s3c_hsotg_txfifo_flush - flush Tx FIFO
1773 * @hsotg: The driver state
1774 * @idx: The index for the endpoint (0..15)
1776 static void s3c_hsotg_txfifo_flush(struct s3c_hsotg
*hsotg
, unsigned int idx
)
1781 writel(GRSTCTL_TxFNum(idx
) | GRSTCTL_TxFFlsh
,
1782 hsotg
->regs
+ GRSTCTL
);
1784 /* wait until the fifo is flushed */
1788 val
= readl(hsotg
->regs
+ GRSTCTL
);
1790 if ((val
& (GRSTCTL_TxFFlsh
)) == 0)
1793 if (--timeout
== 0) {
1795 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1804 * s3c_hsotg_trytx - check to see if anything needs transmitting
1805 * @hsotg: The driver state
1806 * @hs_ep: The driver endpoint to check.
1808 * Check to see if there is a request that has data to send, and if so
1809 * make an attempt to write data into the FIFO.
1811 static int s3c_hsotg_trytx(struct s3c_hsotg
*hsotg
,
1812 struct s3c_hsotg_ep
*hs_ep
)
1814 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1816 if (!hs_ep
->dir_in
|| !hs_req
)
1819 if (hs_req
->req
.actual
< hs_req
->req
.length
) {
1820 dev_dbg(hsotg
->dev
, "trying to write more for ep%d\n",
1822 return s3c_hsotg_write_fifo(hsotg
, hs_ep
, hs_req
);
1829 * s3c_hsotg_complete_in - complete IN transfer
1830 * @hsotg: The device state.
1831 * @hs_ep: The endpoint that has just completed.
1833 * An IN transfer has been completed, update the transfer's state and then
1834 * call the relevant completion routines.
1836 static void s3c_hsotg_complete_in(struct s3c_hsotg
*hsotg
,
1837 struct s3c_hsotg_ep
*hs_ep
)
1839 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1840 u32 epsize
= readl(hsotg
->regs
+ DIEPTSIZ(hs_ep
->index
));
1841 int size_left
, size_done
;
1844 dev_dbg(hsotg
->dev
, "XferCompl but no req\n");
1848 /* Finish ZLP handling for IN EP0 transactions */
1849 if (hsotg
->eps
[0].sent_zlp
) {
1850 dev_dbg(hsotg
->dev
, "zlp packet received\n");
1851 s3c_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, 0);
1856 * Calculate the size of the transfer by checking how much is left
1857 * in the endpoint size register and then working it out from
1858 * the amount we loaded for the transfer.
1860 * We do this even for DMA, as the transfer may have incremented
1861 * past the end of the buffer (DMA transfers are always 32bit
1865 size_left
= DxEPTSIZ_XferSize_GET(epsize
);
1867 size_done
= hs_ep
->size_loaded
- size_left
;
1868 size_done
+= hs_ep
->last_load
;
1870 if (hs_req
->req
.actual
!= size_done
)
1871 dev_dbg(hsotg
->dev
, "%s: adjusting size done %d => %d\n",
1872 __func__
, hs_req
->req
.actual
, size_done
);
1874 hs_req
->req
.actual
= size_done
;
1875 dev_dbg(hsotg
->dev
, "req->length:%d req->actual:%d req->zero:%d\n",
1876 hs_req
->req
.length
, hs_req
->req
.actual
, hs_req
->req
.zero
);
1879 * Check if dealing with Maximum Packet Size(MPS) IN transfer at EP0
1880 * When sent data is a multiple MPS size (e.g. 64B ,128B ,192B
1881 * ,256B ... ), after last MPS sized packet send IN ZLP packet to
1882 * inform the host that no more data is available.
1883 * The state of req.zero member is checked to be sure that the value to
1884 * send is smaller than wValue expected from host.
1885 * Check req.length to NOT send another ZLP when the current one is
1886 * under completion (the one for which this completion has been called).
1888 if (hs_req
->req
.length
&& hs_ep
->index
== 0 && hs_req
->req
.zero
&&
1889 hs_req
->req
.length
== hs_req
->req
.actual
&&
1890 !(hs_req
->req
.length
% hs_ep
->ep
.maxpacket
)) {
1892 dev_dbg(hsotg
->dev
, "ep0 zlp IN packet sent\n");
1893 s3c_hsotg_send_zlp(hsotg
, hs_req
);
1898 if (!size_left
&& hs_req
->req
.actual
< hs_req
->req
.length
) {
1899 dev_dbg(hsotg
->dev
, "%s trying more for req...\n", __func__
);
1900 s3c_hsotg_start_req(hsotg
, hs_ep
, hs_req
, true);
1902 s3c_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, 0);
1906 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1907 * @hsotg: The driver state
1908 * @idx: The index for the endpoint (0..15)
1909 * @dir_in: Set if this is an IN endpoint
1911 * Process and clear any interrupt pending for an individual endpoint
1913 static void s3c_hsotg_epint(struct s3c_hsotg
*hsotg
, unsigned int idx
,
1916 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[idx
];
1917 u32 epint_reg
= dir_in
? DIEPINT(idx
) : DOEPINT(idx
);
1918 u32 epctl_reg
= dir_in
? DIEPCTL(idx
) : DOEPCTL(idx
);
1919 u32 epsiz_reg
= dir_in
? DIEPTSIZ(idx
) : DOEPTSIZ(idx
);
1922 ints
= readl(hsotg
->regs
+ epint_reg
);
1924 /* Clear endpoint interrupts */
1925 writel(ints
, hsotg
->regs
+ epint_reg
);
1927 dev_dbg(hsotg
->dev
, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1928 __func__
, idx
, dir_in
? "in" : "out", ints
);
1930 if (ints
& DxEPINT_XferCompl
) {
1932 "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n",
1933 __func__
, readl(hsotg
->regs
+ epctl_reg
),
1934 readl(hsotg
->regs
+ epsiz_reg
));
1937 * we get OutDone from the FIFO, so we only need to look
1938 * at completing IN requests here
1941 s3c_hsotg_complete_in(hsotg
, hs_ep
);
1943 if (idx
== 0 && !hs_ep
->req
)
1944 s3c_hsotg_enqueue_setup(hsotg
);
1945 } else if (using_dma(hsotg
)) {
1947 * We're using DMA, we need to fire an OutDone here
1948 * as we ignore the RXFIFO.
1951 s3c_hsotg_handle_outdone(hsotg
, idx
, false);
1955 if (ints
& DxEPINT_EPDisbld
) {
1956 dev_dbg(hsotg
->dev
, "%s: EPDisbld\n", __func__
);
1959 int epctl
= readl(hsotg
->regs
+ epctl_reg
);
1961 s3c_hsotg_txfifo_flush(hsotg
, idx
);
1963 if ((epctl
& DxEPCTL_Stall
) &&
1964 (epctl
& DxEPCTL_EPType_Bulk
)) {
1965 int dctl
= readl(hsotg
->regs
+ DCTL
);
1967 dctl
|= DCTL_CGNPInNAK
;
1968 writel(dctl
, hsotg
->regs
+ DCTL
);
1973 if (ints
& DxEPINT_AHBErr
)
1974 dev_dbg(hsotg
->dev
, "%s: AHBErr\n", __func__
);
1976 if (ints
& DxEPINT_Setup
) { /* Setup or Timeout */
1977 dev_dbg(hsotg
->dev
, "%s: Setup/Timeout\n", __func__
);
1979 if (using_dma(hsotg
) && idx
== 0) {
1981 * this is the notification we've received a
1982 * setup packet. In non-DMA mode we'd get this
1983 * from the RXFIFO, instead we need to process
1990 s3c_hsotg_handle_outdone(hsotg
, 0, true);
1994 if (ints
& DxEPINT_Back2BackSetup
)
1995 dev_dbg(hsotg
->dev
, "%s: B2BSetup/INEPNakEff\n", __func__
);
1998 /* not sure if this is important, but we'll clear it anyway */
1999 if (ints
& DIEPMSK_INTknTXFEmpMsk
) {
2000 dev_dbg(hsotg
->dev
, "%s: ep%d: INTknTXFEmpMsk\n",
2004 /* this probably means something bad is happening */
2005 if (ints
& DIEPMSK_INTknEPMisMsk
) {
2006 dev_warn(hsotg
->dev
, "%s: ep%d: INTknEP\n",
2010 /* FIFO has space or is empty (see GAHBCFG) */
2011 if (hsotg
->dedicated_fifos
&&
2012 ints
& DIEPMSK_TxFIFOEmpty
) {
2013 dev_dbg(hsotg
->dev
, "%s: ep%d: TxFIFOEmpty\n",
2015 if (!using_dma(hsotg
))
2016 s3c_hsotg_trytx(hsotg
, hs_ep
);
2022 * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
2023 * @hsotg: The device state.
2025 * Handle updating the device settings after the enumeration phase has
2028 static void s3c_hsotg_irq_enumdone(struct s3c_hsotg
*hsotg
)
2030 u32 dsts
= readl(hsotg
->regs
+ DSTS
);
2031 int ep0_mps
= 0, ep_mps
;
2034 * This should signal the finish of the enumeration phase
2035 * of the USB handshaking, so we should now know what rate
2039 dev_dbg(hsotg
->dev
, "EnumDone (DSTS=0x%08x)\n", dsts
);
2042 * note, since we're limited by the size of transfer on EP0, and
2043 * it seems IN transfers must be a even number of packets we do
2044 * not advertise a 64byte MPS on EP0.
2047 /* catch both EnumSpd_FS and EnumSpd_FS48 */
2048 switch (dsts
& DSTS_EnumSpd_MASK
) {
2049 case DSTS_EnumSpd_FS
:
2050 case DSTS_EnumSpd_FS48
:
2051 hsotg
->gadget
.speed
= USB_SPEED_FULL
;
2052 ep0_mps
= EP0_MPS_LIMIT
;
2056 case DSTS_EnumSpd_HS
:
2057 hsotg
->gadget
.speed
= USB_SPEED_HIGH
;
2058 ep0_mps
= EP0_MPS_LIMIT
;
2062 case DSTS_EnumSpd_LS
:
2063 hsotg
->gadget
.speed
= USB_SPEED_LOW
;
2065 * note, we don't actually support LS in this driver at the
2066 * moment, and the documentation seems to imply that it isn't
2067 * supported by the PHYs on some of the devices.
2071 dev_info(hsotg
->dev
, "new device is %s\n",
2072 usb_speed_string(hsotg
->gadget
.speed
));
2075 * we should now know the maximum packet size for an
2076 * endpoint, so set the endpoints to a default value.
2081 s3c_hsotg_set_ep_maxpacket(hsotg
, 0, ep0_mps
);
2082 for (i
= 1; i
< hsotg
->num_of_eps
; i
++)
2083 s3c_hsotg_set_ep_maxpacket(hsotg
, i
, ep_mps
);
2086 /* ensure after enumeration our EP0 is active */
2088 s3c_hsotg_enqueue_setup(hsotg
);
2090 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2091 readl(hsotg
->regs
+ DIEPCTL0
),
2092 readl(hsotg
->regs
+ DOEPCTL0
));
2096 * kill_all_requests - remove all requests from the endpoint's queue
2097 * @hsotg: The device state.
2098 * @ep: The endpoint the requests may be on.
2099 * @result: The result code to use.
2100 * @force: Force removal of any current requests
2102 * Go through the requests on the given endpoint and mark them
2103 * completed with the given result code.
2105 static void kill_all_requests(struct s3c_hsotg
*hsotg
,
2106 struct s3c_hsotg_ep
*ep
,
2107 int result
, bool force
)
2109 struct s3c_hsotg_req
*req
, *treq
;
2111 list_for_each_entry_safe(req
, treq
, &ep
->queue
, queue
) {
2113 * currently, we can't do much about an already
2114 * running request on an in endpoint
2117 if (ep
->req
== req
&& ep
->dir_in
&& !force
)
2120 s3c_hsotg_complete_request(hsotg
, ep
, req
,
2125 #define call_gadget(_hs, _entry) \
2126 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
2127 (_hs)->driver && (_hs)->driver->_entry) { \
2128 spin_unlock(&_hs->lock); \
2129 (_hs)->driver->_entry(&(_hs)->gadget); \
2130 spin_lock(&_hs->lock); \
2134 * s3c_hsotg_disconnect - disconnect service
2135 * @hsotg: The device state.
2137 * The device has been disconnected. Remove all current
2138 * transactions and signal the gadget driver that this
2141 static void s3c_hsotg_disconnect(struct s3c_hsotg
*hsotg
)
2145 for (ep
= 0; ep
< hsotg
->num_of_eps
; ep
++)
2146 kill_all_requests(hsotg
, &hsotg
->eps
[ep
], -ESHUTDOWN
, true);
2148 call_gadget(hsotg
, disconnect
);
2152 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2153 * @hsotg: The device state:
2154 * @periodic: True if this is a periodic FIFO interrupt
2156 static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg
*hsotg
, bool periodic
)
2158 struct s3c_hsotg_ep
*ep
;
2161 /* look through for any more data to transmit */
2163 for (epno
= 0; epno
< hsotg
->num_of_eps
; epno
++) {
2164 ep
= &hsotg
->eps
[epno
];
2169 if ((periodic
&& !ep
->periodic
) ||
2170 (!periodic
&& ep
->periodic
))
2173 ret
= s3c_hsotg_trytx(hsotg
, ep
);
2179 /* IRQ flags which will trigger a retry around the IRQ loop */
2180 #define IRQ_RETRY_MASK (GINTSTS_NPTxFEmp | \
2185 * s3c_hsotg_corereset - issue softreset to the core
2186 * @hsotg: The device state
2188 * Issue a soft reset to the core, and await the core finishing it.
2190 static int s3c_hsotg_corereset(struct s3c_hsotg
*hsotg
)
2195 dev_dbg(hsotg
->dev
, "resetting core\n");
2197 /* issue soft reset */
2198 writel(GRSTCTL_CSftRst
, hsotg
->regs
+ GRSTCTL
);
2202 grstctl
= readl(hsotg
->regs
+ GRSTCTL
);
2203 } while ((grstctl
& GRSTCTL_CSftRst
) && timeout
-- > 0);
2205 if (grstctl
& GRSTCTL_CSftRst
) {
2206 dev_err(hsotg
->dev
, "Failed to get CSftRst asserted\n");
2213 u32 grstctl
= readl(hsotg
->regs
+ GRSTCTL
);
2215 if (timeout
-- < 0) {
2216 dev_info(hsotg
->dev
,
2217 "%s: reset failed, GRSTCTL=%08x\n",
2222 if (!(grstctl
& GRSTCTL_AHBIdle
))
2225 break; /* reset done */
2228 dev_dbg(hsotg
->dev
, "reset successful\n");
2233 * s3c_hsotg_core_init - issue softreset to the core
2234 * @hsotg: The device state
2236 * Issue a soft reset to the core, and await the core finishing it.
2238 static void s3c_hsotg_core_init(struct s3c_hsotg
*hsotg
)
2240 s3c_hsotg_corereset(hsotg
);
2243 * we must now enable ep0 ready for host detection and then
2244 * set configuration.
2247 /* set the PLL on, remove the HNP/SRP and set the PHY */
2248 writel(GUSBCFG_PHYIf16
| GUSBCFG_TOutCal(7) |
2249 (0x5 << 10), hsotg
->regs
+ GUSBCFG
);
2251 s3c_hsotg_init_fifo(hsotg
);
2253 __orr32(hsotg
->regs
+ DCTL
, DCTL_SftDiscon
);
2255 writel(1 << 18 | DCFG_DevSpd_HS
, hsotg
->regs
+ DCFG
);
2257 /* Clear any pending OTG interrupts */
2258 writel(0xffffffff, hsotg
->regs
+ GOTGINT
);
2260 /* Clear any pending interrupts */
2261 writel(0xffffffff, hsotg
->regs
+ GINTSTS
);
2263 writel(GINTSTS_ErlySusp
| GINTSTS_SessReqInt
|
2264 GINTSTS_GOUTNakEff
| GINTSTS_GINNakEff
|
2265 GINTSTS_ConIDStsChng
| GINTSTS_USBRst
|
2266 GINTSTS_EnumDone
| GINTSTS_OTGInt
|
2267 GINTSTS_USBSusp
| GINTSTS_WkUpInt
,
2268 hsotg
->regs
+ GINTMSK
);
2270 if (using_dma(hsotg
))
2271 writel(GAHBCFG_GlblIntrEn
| GAHBCFG_DMAEn
|
2272 GAHBCFG_HBstLen_Incr4
,
2273 hsotg
->regs
+ GAHBCFG
);
2275 writel(GAHBCFG_GlblIntrEn
, hsotg
->regs
+ GAHBCFG
);
2278 * Enabling INTknTXFEmpMsk here seems to be a big mistake, we end
2279 * up being flooded with interrupts if the host is polling the
2280 * endpoint to try and read data.
2283 writel(((hsotg
->dedicated_fifos
) ? DIEPMSK_TxFIFOEmpty
: 0) |
2284 DIEPMSK_EPDisbldMsk
| DIEPMSK_XferComplMsk
|
2285 DIEPMSK_TimeOUTMsk
| DIEPMSK_AHBErrMsk
|
2286 DIEPMSK_INTknEPMisMsk
,
2287 hsotg
->regs
+ DIEPMSK
);
2290 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2291 * DMA mode we may need this.
2293 writel((using_dma(hsotg
) ? (DIEPMSK_XferComplMsk
|
2294 DIEPMSK_TimeOUTMsk
) : 0) |
2295 DOEPMSK_EPDisbldMsk
| DOEPMSK_AHBErrMsk
|
2297 hsotg
->regs
+ DOEPMSK
);
2299 writel(0, hsotg
->regs
+ DAINTMSK
);
2301 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2302 readl(hsotg
->regs
+ DIEPCTL0
),
2303 readl(hsotg
->regs
+ DOEPCTL0
));
2305 /* enable in and out endpoint interrupts */
2306 s3c_hsotg_en_gsint(hsotg
, GINTSTS_OEPInt
| GINTSTS_IEPInt
);
2309 * Enable the RXFIFO when in slave mode, as this is how we collect
2310 * the data. In DMA mode, we get events from the FIFO but also
2311 * things we cannot process, so do not use it.
2313 if (!using_dma(hsotg
))
2314 s3c_hsotg_en_gsint(hsotg
, GINTSTS_RxFLvl
);
2316 /* Enable interrupts for EP0 in and out */
2317 s3c_hsotg_ctrl_epint(hsotg
, 0, 0, 1);
2318 s3c_hsotg_ctrl_epint(hsotg
, 0, 1, 1);
2320 __orr32(hsotg
->regs
+ DCTL
, DCTL_PWROnPrgDone
);
2321 udelay(10); /* see openiboot */
2322 __bic32(hsotg
->regs
+ DCTL
, DCTL_PWROnPrgDone
);
2324 dev_dbg(hsotg
->dev
, "DCTL=0x%08x\n", readl(hsotg
->regs
+ DCTL
));
2327 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
2328 * writing to the EPCTL register..
2331 /* set to read 1 8byte packet */
2332 writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) |
2333 DxEPTSIZ_XferSize(8), hsotg
->regs
+ DOEPTSIZ0
);
2335 writel(s3c_hsotg_ep0_mps(hsotg
->eps
[0].ep
.maxpacket
) |
2336 DxEPCTL_CNAK
| DxEPCTL_EPEna
|
2338 hsotg
->regs
+ DOEPCTL0
);
2340 /* enable, but don't activate EP0in */
2341 writel(s3c_hsotg_ep0_mps(hsotg
->eps
[0].ep
.maxpacket
) |
2342 DxEPCTL_USBActEp
, hsotg
->regs
+ DIEPCTL0
);
2344 s3c_hsotg_enqueue_setup(hsotg
);
2346 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2347 readl(hsotg
->regs
+ DIEPCTL0
),
2348 readl(hsotg
->regs
+ DOEPCTL0
));
2350 /* clear global NAKs */
2351 writel(DCTL_CGOUTNak
| DCTL_CGNPInNAK
,
2352 hsotg
->regs
+ DCTL
);
2354 /* must be at-least 3ms to allow bus to see disconnect */
2357 /* remove the soft-disconnect and let's go */
2358 __bic32(hsotg
->regs
+ DCTL
, DCTL_SftDiscon
);
2362 * s3c_hsotg_irq - handle device interrupt
2363 * @irq: The IRQ number triggered
2364 * @pw: The pw value when registered the handler.
2366 static irqreturn_t
s3c_hsotg_irq(int irq
, void *pw
)
2368 struct s3c_hsotg
*hsotg
= pw
;
2369 int retry_count
= 8;
2373 spin_lock(&hsotg
->lock
);
2375 gintsts
= readl(hsotg
->regs
+ GINTSTS
);
2376 gintmsk
= readl(hsotg
->regs
+ GINTMSK
);
2378 dev_dbg(hsotg
->dev
, "%s: %08x %08x (%08x) retry %d\n",
2379 __func__
, gintsts
, gintsts
& gintmsk
, gintmsk
, retry_count
);
2383 if (gintsts
& GINTSTS_OTGInt
) {
2384 u32 otgint
= readl(hsotg
->regs
+ GOTGINT
);
2386 dev_info(hsotg
->dev
, "OTGInt: %08x\n", otgint
);
2388 writel(otgint
, hsotg
->regs
+ GOTGINT
);
2391 if (gintsts
& GINTSTS_SessReqInt
) {
2392 dev_dbg(hsotg
->dev
, "%s: SessReqInt\n", __func__
);
2393 writel(GINTSTS_SessReqInt
, hsotg
->regs
+ GINTSTS
);
2396 if (gintsts
& GINTSTS_EnumDone
) {
2397 writel(GINTSTS_EnumDone
, hsotg
->regs
+ GINTSTS
);
2399 s3c_hsotg_irq_enumdone(hsotg
);
2402 if (gintsts
& GINTSTS_ConIDStsChng
) {
2403 dev_dbg(hsotg
->dev
, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
2404 readl(hsotg
->regs
+ DSTS
),
2405 readl(hsotg
->regs
+ GOTGCTL
));
2407 writel(GINTSTS_ConIDStsChng
, hsotg
->regs
+ GINTSTS
);
2410 if (gintsts
& (GINTSTS_OEPInt
| GINTSTS_IEPInt
)) {
2411 u32 daint
= readl(hsotg
->regs
+ DAINT
);
2412 u32 daint_out
= daint
>> DAINT_OutEP_SHIFT
;
2413 u32 daint_in
= daint
& ~(daint_out
<< DAINT_OutEP_SHIFT
);
2416 dev_dbg(hsotg
->dev
, "%s: daint=%08x\n", __func__
, daint
);
2418 for (ep
= 0; ep
< 15 && daint_out
; ep
++, daint_out
>>= 1) {
2420 s3c_hsotg_epint(hsotg
, ep
, 0);
2423 for (ep
= 0; ep
< 15 && daint_in
; ep
++, daint_in
>>= 1) {
2425 s3c_hsotg_epint(hsotg
, ep
, 1);
2429 if (gintsts
& GINTSTS_USBRst
) {
2431 u32 usb_status
= readl(hsotg
->regs
+ GOTGCTL
);
2433 dev_info(hsotg
->dev
, "%s: USBRst\n", __func__
);
2434 dev_dbg(hsotg
->dev
, "GNPTXSTS=%08x\n",
2435 readl(hsotg
->regs
+ GNPTXSTS
));
2437 writel(GINTSTS_USBRst
, hsotg
->regs
+ GINTSTS
);
2439 if (usb_status
& GOTGCTL_BSESVLD
) {
2440 if (time_after(jiffies
, hsotg
->last_rst
+
2441 msecs_to_jiffies(200))) {
2443 kill_all_requests(hsotg
, &hsotg
->eps
[0],
2446 s3c_hsotg_core_init(hsotg
);
2447 hsotg
->last_rst
= jiffies
;
2452 /* check both FIFOs */
2454 if (gintsts
& GINTSTS_NPTxFEmp
) {
2455 dev_dbg(hsotg
->dev
, "NPTxFEmp\n");
2458 * Disable the interrupt to stop it happening again
2459 * unless one of these endpoint routines decides that
2460 * it needs re-enabling
2463 s3c_hsotg_disable_gsint(hsotg
, GINTSTS_NPTxFEmp
);
2464 s3c_hsotg_irq_fifoempty(hsotg
, false);
2467 if (gintsts
& GINTSTS_PTxFEmp
) {
2468 dev_dbg(hsotg
->dev
, "PTxFEmp\n");
2470 /* See note in GINTSTS_NPTxFEmp */
2472 s3c_hsotg_disable_gsint(hsotg
, GINTSTS_PTxFEmp
);
2473 s3c_hsotg_irq_fifoempty(hsotg
, true);
2476 if (gintsts
& GINTSTS_RxFLvl
) {
2478 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2479 * we need to retry s3c_hsotg_handle_rx if this is still
2483 s3c_hsotg_handle_rx(hsotg
);
2486 if (gintsts
& GINTSTS_ModeMis
) {
2487 dev_warn(hsotg
->dev
, "warning, mode mismatch triggered\n");
2488 writel(GINTSTS_ModeMis
, hsotg
->regs
+ GINTSTS
);
2491 if (gintsts
& GINTSTS_USBSusp
) {
2492 dev_info(hsotg
->dev
, "GINTSTS_USBSusp\n");
2493 writel(GINTSTS_USBSusp
, hsotg
->regs
+ GINTSTS
);
2495 call_gadget(hsotg
, suspend
);
2496 s3c_hsotg_disconnect(hsotg
);
2499 if (gintsts
& GINTSTS_WkUpInt
) {
2500 dev_info(hsotg
->dev
, "GINTSTS_WkUpIn\n");
2501 writel(GINTSTS_WkUpInt
, hsotg
->regs
+ GINTSTS
);
2503 call_gadget(hsotg
, resume
);
2506 if (gintsts
& GINTSTS_ErlySusp
) {
2507 dev_dbg(hsotg
->dev
, "GINTSTS_ErlySusp\n");
2508 writel(GINTSTS_ErlySusp
, hsotg
->regs
+ GINTSTS
);
2510 s3c_hsotg_disconnect(hsotg
);
2514 * these next two seem to crop-up occasionally causing the core
2515 * to shutdown the USB transfer, so try clearing them and logging
2519 if (gintsts
& GINTSTS_GOUTNakEff
) {
2520 dev_info(hsotg
->dev
, "GOUTNakEff triggered\n");
2522 writel(DCTL_CGOUTNak
, hsotg
->regs
+ DCTL
);
2524 s3c_hsotg_dump(hsotg
);
2527 if (gintsts
& GINTSTS_GINNakEff
) {
2528 dev_info(hsotg
->dev
, "GINNakEff triggered\n");
2530 writel(DCTL_CGNPInNAK
, hsotg
->regs
+ DCTL
);
2532 s3c_hsotg_dump(hsotg
);
2536 * if we've had fifo events, we should try and go around the
2537 * loop again to see if there's any point in returning yet.
2540 if (gintsts
& IRQ_RETRY_MASK
&& --retry_count
> 0)
2543 spin_unlock(&hsotg
->lock
);
2549 * s3c_hsotg_ep_enable - enable the given endpoint
2550 * @ep: The USB endpint to configure
2551 * @desc: The USB endpoint descriptor to configure with.
2553 * This is called from the USB gadget code's usb_ep_enable().
2555 static int s3c_hsotg_ep_enable(struct usb_ep
*ep
,
2556 const struct usb_endpoint_descriptor
*desc
)
2558 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2559 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
2560 unsigned long flags
;
2561 int index
= hs_ep
->index
;
2569 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2570 __func__
, ep
->name
, desc
->bEndpointAddress
, desc
->bmAttributes
,
2571 desc
->wMaxPacketSize
, desc
->bInterval
);
2573 /* not to be called for EP0 */
2574 WARN_ON(index
== 0);
2576 dir_in
= (desc
->bEndpointAddress
& USB_ENDPOINT_DIR_MASK
) ? 1 : 0;
2577 if (dir_in
!= hs_ep
->dir_in
) {
2578 dev_err(hsotg
->dev
, "%s: direction mismatch!\n", __func__
);
2582 mps
= usb_endpoint_maxp(desc
);
2584 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2586 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
2587 epctrl
= readl(hsotg
->regs
+ epctrl_reg
);
2589 dev_dbg(hsotg
->dev
, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2590 __func__
, epctrl
, epctrl_reg
);
2592 spin_lock_irqsave(&hsotg
->lock
, flags
);
2594 epctrl
&= ~(DxEPCTL_EPType_MASK
| DxEPCTL_MPS_MASK
);
2595 epctrl
|= DxEPCTL_MPS(mps
);
2598 * mark the endpoint as active, otherwise the core may ignore
2599 * transactions entirely for this endpoint
2601 epctrl
|= DxEPCTL_USBActEp
;
2604 * set the NAK status on the endpoint, otherwise we might try and
2605 * do something with data that we've yet got a request to process
2606 * since the RXFIFO will take data for an endpoint even if the
2607 * size register hasn't been set.
2610 epctrl
|= DxEPCTL_SNAK
;
2612 /* update the endpoint state */
2613 hs_ep
->ep
.maxpacket
= mps
;
2615 /* default, set to non-periodic */
2616 hs_ep
->periodic
= 0;
2618 switch (desc
->bmAttributes
& USB_ENDPOINT_XFERTYPE_MASK
) {
2619 case USB_ENDPOINT_XFER_ISOC
:
2620 dev_err(hsotg
->dev
, "no current ISOC support\n");
2624 case USB_ENDPOINT_XFER_BULK
:
2625 epctrl
|= DxEPCTL_EPType_Bulk
;
2628 case USB_ENDPOINT_XFER_INT
:
2631 * Allocate our TxFNum by simply using the index
2632 * of the endpoint for the moment. We could do
2633 * something better if the host indicates how
2634 * many FIFOs we are expecting to use.
2637 hs_ep
->periodic
= 1;
2638 epctrl
|= DxEPCTL_TxFNum(index
);
2641 epctrl
|= DxEPCTL_EPType_Intterupt
;
2644 case USB_ENDPOINT_XFER_CONTROL
:
2645 epctrl
|= DxEPCTL_EPType_Control
;
2650 * if the hardware has dedicated fifos, we must give each IN EP
2651 * a unique tx-fifo even if it is non-periodic.
2653 if (dir_in
&& hsotg
->dedicated_fifos
)
2654 epctrl
|= DxEPCTL_TxFNum(index
);
2656 /* for non control endpoints, set PID to D0 */
2658 epctrl
|= DxEPCTL_SetD0PID
;
2660 dev_dbg(hsotg
->dev
, "%s: write DxEPCTL=0x%08x\n",
2663 writel(epctrl
, hsotg
->regs
+ epctrl_reg
);
2664 dev_dbg(hsotg
->dev
, "%s: read DxEPCTL=0x%08x\n",
2665 __func__
, readl(hsotg
->regs
+ epctrl_reg
));
2667 /* enable the endpoint interrupt */
2668 s3c_hsotg_ctrl_epint(hsotg
, index
, dir_in
, 1);
2671 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2676 * s3c_hsotg_ep_disable - disable given endpoint
2677 * @ep: The endpoint to disable.
2679 static int s3c_hsotg_ep_disable(struct usb_ep
*ep
)
2681 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2682 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
2683 int dir_in
= hs_ep
->dir_in
;
2684 int index
= hs_ep
->index
;
2685 unsigned long flags
;
2689 dev_info(hsotg
->dev
, "%s(ep %p)\n", __func__
, ep
);
2691 if (ep
== &hsotg
->eps
[0].ep
) {
2692 dev_err(hsotg
->dev
, "%s: called for ep0\n", __func__
);
2696 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
2698 spin_lock_irqsave(&hsotg
->lock
, flags
);
2699 /* terminate all requests with shutdown */
2700 kill_all_requests(hsotg
, hs_ep
, -ESHUTDOWN
, false);
2703 ctrl
= readl(hsotg
->regs
+ epctrl_reg
);
2704 ctrl
&= ~DxEPCTL_EPEna
;
2705 ctrl
&= ~DxEPCTL_USBActEp
;
2706 ctrl
|= DxEPCTL_SNAK
;
2708 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n", __func__
, ctrl
);
2709 writel(ctrl
, hsotg
->regs
+ epctrl_reg
);
2711 /* disable endpoint interrupts */
2712 s3c_hsotg_ctrl_epint(hsotg
, hs_ep
->index
, hs_ep
->dir_in
, 0);
2714 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2719 * on_list - check request is on the given endpoint
2720 * @ep: The endpoint to check.
2721 * @test: The request to test if it is on the endpoint.
2723 static bool on_list(struct s3c_hsotg_ep
*ep
, struct s3c_hsotg_req
*test
)
2725 struct s3c_hsotg_req
*req
, *treq
;
2727 list_for_each_entry_safe(req
, treq
, &ep
->queue
, queue
) {
2736 * s3c_hsotg_ep_dequeue - dequeue given endpoint
2737 * @ep: The endpoint to dequeue.
2738 * @req: The request to be removed from a queue.
2740 static int s3c_hsotg_ep_dequeue(struct usb_ep
*ep
, struct usb_request
*req
)
2742 struct s3c_hsotg_req
*hs_req
= our_req(req
);
2743 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2744 struct s3c_hsotg
*hs
= hs_ep
->parent
;
2745 unsigned long flags
;
2747 dev_info(hs
->dev
, "ep_dequeue(%p,%p)\n", ep
, req
);
2749 spin_lock_irqsave(&hs
->lock
, flags
);
2751 if (!on_list(hs_ep
, hs_req
)) {
2752 spin_unlock_irqrestore(&hs
->lock
, flags
);
2756 s3c_hsotg_complete_request(hs
, hs_ep
, hs_req
, -ECONNRESET
);
2757 spin_unlock_irqrestore(&hs
->lock
, flags
);
2763 * s3c_hsotg_ep_sethalt - set halt on a given endpoint
2764 * @ep: The endpoint to set halt.
2765 * @value: Set or unset the halt.
2767 static int s3c_hsotg_ep_sethalt(struct usb_ep
*ep
, int value
)
2769 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2770 struct s3c_hsotg
*hs
= hs_ep
->parent
;
2771 int index
= hs_ep
->index
;
2776 dev_info(hs
->dev
, "%s(ep %p %s, %d)\n", __func__
, ep
, ep
->name
, value
);
2778 /* write both IN and OUT control registers */
2780 epreg
= DIEPCTL(index
);
2781 epctl
= readl(hs
->regs
+ epreg
);
2784 epctl
|= DxEPCTL_Stall
+ DxEPCTL_SNAK
;
2785 if (epctl
& DxEPCTL_EPEna
)
2786 epctl
|= DxEPCTL_EPDis
;
2788 epctl
&= ~DxEPCTL_Stall
;
2789 xfertype
= epctl
& DxEPCTL_EPType_MASK
;
2790 if (xfertype
== DxEPCTL_EPType_Bulk
||
2791 xfertype
== DxEPCTL_EPType_Intterupt
)
2792 epctl
|= DxEPCTL_SetD0PID
;
2795 writel(epctl
, hs
->regs
+ epreg
);
2797 epreg
= DOEPCTL(index
);
2798 epctl
= readl(hs
->regs
+ epreg
);
2801 epctl
|= DxEPCTL_Stall
;
2803 epctl
&= ~DxEPCTL_Stall
;
2804 xfertype
= epctl
& DxEPCTL_EPType_MASK
;
2805 if (xfertype
== DxEPCTL_EPType_Bulk
||
2806 xfertype
== DxEPCTL_EPType_Intterupt
)
2807 epctl
|= DxEPCTL_SetD0PID
;
2810 writel(epctl
, hs
->regs
+ epreg
);
2816 * s3c_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
2817 * @ep: The endpoint to set halt.
2818 * @value: Set or unset the halt.
2820 static int s3c_hsotg_ep_sethalt_lock(struct usb_ep
*ep
, int value
)
2822 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2823 struct s3c_hsotg
*hs
= hs_ep
->parent
;
2824 unsigned long flags
= 0;
2827 spin_lock_irqsave(&hs
->lock
, flags
);
2828 ret
= s3c_hsotg_ep_sethalt(ep
, value
);
2829 spin_unlock_irqrestore(&hs
->lock
, flags
);
2834 static struct usb_ep_ops s3c_hsotg_ep_ops
= {
2835 .enable
= s3c_hsotg_ep_enable
,
2836 .disable
= s3c_hsotg_ep_disable
,
2837 .alloc_request
= s3c_hsotg_ep_alloc_request
,
2838 .free_request
= s3c_hsotg_ep_free_request
,
2839 .queue
= s3c_hsotg_ep_queue_lock
,
2840 .dequeue
= s3c_hsotg_ep_dequeue
,
2841 .set_halt
= s3c_hsotg_ep_sethalt_lock
,
2842 /* note, don't believe we have any call for the fifo routines */
2846 * s3c_hsotg_phy_enable - enable platform phy dev
2847 * @hsotg: The driver state
2849 * A wrapper for platform code responsible for controlling
2850 * low-level USB code
2852 static void s3c_hsotg_phy_enable(struct s3c_hsotg
*hsotg
)
2854 struct platform_device
*pdev
= to_platform_device(hsotg
->dev
);
2856 dev_dbg(hsotg
->dev
, "pdev 0x%p\n", pdev
);
2857 if (hsotg
->plat
->phy_init
)
2858 hsotg
->plat
->phy_init(pdev
, hsotg
->plat
->phy_type
);
2862 * s3c_hsotg_phy_disable - disable platform phy dev
2863 * @hsotg: The driver state
2865 * A wrapper for platform code responsible for controlling
2866 * low-level USB code
2868 static void s3c_hsotg_phy_disable(struct s3c_hsotg
*hsotg
)
2870 struct platform_device
*pdev
= to_platform_device(hsotg
->dev
);
2872 if (hsotg
->plat
->phy_exit
)
2873 hsotg
->plat
->phy_exit(pdev
, hsotg
->plat
->phy_type
);
2877 * s3c_hsotg_init - initalize the usb core
2878 * @hsotg: The driver state
2880 static void s3c_hsotg_init(struct s3c_hsotg
*hsotg
)
2882 /* unmask subset of endpoint interrupts */
2884 writel(DIEPMSK_TimeOUTMsk
| DIEPMSK_AHBErrMsk
|
2885 DIEPMSK_EPDisbldMsk
| DIEPMSK_XferComplMsk
,
2886 hsotg
->regs
+ DIEPMSK
);
2888 writel(DOEPMSK_SetupMsk
| DOEPMSK_AHBErrMsk
|
2889 DOEPMSK_EPDisbldMsk
| DOEPMSK_XferComplMsk
,
2890 hsotg
->regs
+ DOEPMSK
);
2892 writel(0, hsotg
->regs
+ DAINTMSK
);
2894 /* Be in disconnected state until gadget is registered */
2895 __orr32(hsotg
->regs
+ DCTL
, DCTL_SftDiscon
);
2898 /* post global nak until we're ready */
2899 writel(DCTL_SGNPInNAK
| DCTL_SGOUTNak
,
2900 hsotg
->regs
+ DCTL
);
2905 dev_dbg(hsotg
->dev
, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2906 readl(hsotg
->regs
+ GRXFSIZ
),
2907 readl(hsotg
->regs
+ GNPTXFSIZ
));
2909 s3c_hsotg_init_fifo(hsotg
);
2911 /* set the PLL on, remove the HNP/SRP and set the PHY */
2912 writel(GUSBCFG_PHYIf16
| GUSBCFG_TOutCal(7) | (0x5 << 10),
2913 hsotg
->regs
+ GUSBCFG
);
2915 writel(using_dma(hsotg
) ? GAHBCFG_DMAEn
: 0x0,
2916 hsotg
->regs
+ GAHBCFG
);
2920 * s3c_hsotg_udc_start - prepare the udc for work
2921 * @gadget: The usb gadget state
2922 * @driver: The usb gadget driver
2924 * Perform initialization to prepare udc device and driver
2927 static int s3c_hsotg_udc_start(struct usb_gadget
*gadget
,
2928 struct usb_gadget_driver
*driver
)
2930 struct s3c_hsotg
*hsotg
= to_hsotg(gadget
);
2934 printk(KERN_ERR
"%s: called with no device\n", __func__
);
2939 dev_err(hsotg
->dev
, "%s: no driver\n", __func__
);
2943 if (driver
->max_speed
< USB_SPEED_FULL
)
2944 dev_err(hsotg
->dev
, "%s: bad speed\n", __func__
);
2946 if (!driver
->setup
) {
2947 dev_err(hsotg
->dev
, "%s: missing entry points\n", __func__
);
2951 WARN_ON(hsotg
->driver
);
2953 driver
->driver
.bus
= NULL
;
2954 hsotg
->driver
= driver
;
2955 hsotg
->gadget
.dev
.driver
= &driver
->driver
;
2956 hsotg
->gadget
.dev
.of_node
= hsotg
->dev
->of_node
;
2957 hsotg
->gadget
.dev
.dma_mask
= hsotg
->dev
->dma_mask
;
2958 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2960 ret
= regulator_bulk_enable(ARRAY_SIZE(hsotg
->supplies
),
2963 dev_err(hsotg
->dev
, "failed to enable supplies: %d\n", ret
);
2967 hsotg
->last_rst
= jiffies
;
2968 dev_info(hsotg
->dev
, "bound driver %s\n", driver
->driver
.name
);
2972 hsotg
->driver
= NULL
;
2973 hsotg
->gadget
.dev
.driver
= NULL
;
2978 * s3c_hsotg_udc_stop - stop the udc
2979 * @gadget: The usb gadget state
2980 * @driver: The usb gadget driver
2982 * Stop udc hw block and stay tunned for future transmissions
2984 static int s3c_hsotg_udc_stop(struct usb_gadget
*gadget
,
2985 struct usb_gadget_driver
*driver
)
2987 struct s3c_hsotg
*hsotg
= to_hsotg(gadget
);
2988 unsigned long flags
= 0;
2994 if (!driver
|| driver
!= hsotg
->driver
|| !driver
->unbind
)
2997 /* all endpoints should be shutdown */
2998 for (ep
= 0; ep
< hsotg
->num_of_eps
; ep
++)
2999 s3c_hsotg_ep_disable(&hsotg
->eps
[ep
].ep
);
3001 spin_lock_irqsave(&hsotg
->lock
, flags
);
3003 s3c_hsotg_phy_disable(hsotg
);
3004 regulator_bulk_disable(ARRAY_SIZE(hsotg
->supplies
), hsotg
->supplies
);
3006 hsotg
->driver
= NULL
;
3007 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
3008 hsotg
->gadget
.dev
.driver
= NULL
;
3010 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3012 dev_info(hsotg
->dev
, "unregistered gadget driver '%s'\n",
3013 driver
->driver
.name
);
3019 * s3c_hsotg_gadget_getframe - read the frame number
3020 * @gadget: The usb gadget state
3022 * Read the {micro} frame number
3024 static int s3c_hsotg_gadget_getframe(struct usb_gadget
*gadget
)
3026 return s3c_hsotg_read_frameno(to_hsotg(gadget
));
3030 * s3c_hsotg_pullup - connect/disconnect the USB PHY
3031 * @gadget: The usb gadget state
3032 * @is_on: Current state of the USB PHY
3034 * Connect/Disconnect the USB PHY pullup
3036 static int s3c_hsotg_pullup(struct usb_gadget
*gadget
, int is_on
)
3038 struct s3c_hsotg
*hsotg
= to_hsotg(gadget
);
3039 unsigned long flags
= 0;
3041 dev_dbg(hsotg
->dev
, "%s: is_in: %d\n", __func__
, is_on
);
3043 spin_lock_irqsave(&hsotg
->lock
, flags
);
3045 s3c_hsotg_phy_enable(hsotg
);
3046 s3c_hsotg_core_init(hsotg
);
3048 s3c_hsotg_disconnect(hsotg
);
3049 s3c_hsotg_phy_disable(hsotg
);
3052 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
3053 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3058 static struct usb_gadget_ops s3c_hsotg_gadget_ops
= {
3059 .get_frame
= s3c_hsotg_gadget_getframe
,
3060 .udc_start
= s3c_hsotg_udc_start
,
3061 .udc_stop
= s3c_hsotg_udc_stop
,
3062 .pullup
= s3c_hsotg_pullup
,
3066 * s3c_hsotg_initep - initialise a single endpoint
3067 * @hsotg: The device state.
3068 * @hs_ep: The endpoint to be initialised.
3069 * @epnum: The endpoint number
3071 * Initialise the given endpoint (as part of the probe and device state
3072 * creation) to give to the gadget driver. Setup the endpoint name, any
3073 * direction information and other state that may be required.
3075 static void __devinit
s3c_hsotg_initep(struct s3c_hsotg
*hsotg
,
3076 struct s3c_hsotg_ep
*hs_ep
,
3084 else if ((epnum
% 2) == 0) {
3091 hs_ep
->index
= epnum
;
3093 snprintf(hs_ep
->name
, sizeof(hs_ep
->name
), "ep%d%s", epnum
, dir
);
3095 INIT_LIST_HEAD(&hs_ep
->queue
);
3096 INIT_LIST_HEAD(&hs_ep
->ep
.ep_list
);
3098 /* add to the list of endpoints known by the gadget driver */
3100 list_add_tail(&hs_ep
->ep
.ep_list
, &hsotg
->gadget
.ep_list
);
3102 hs_ep
->parent
= hsotg
;
3103 hs_ep
->ep
.name
= hs_ep
->name
;
3104 hs_ep
->ep
.maxpacket
= epnum
? 512 : EP0_MPS_LIMIT
;
3105 hs_ep
->ep
.ops
= &s3c_hsotg_ep_ops
;
3108 * Read the FIFO size for the Periodic TX FIFO, even if we're
3109 * an OUT endpoint, we may as well do this if in future the
3110 * code is changed to make each endpoint's direction changeable.
3113 ptxfifo
= readl(hsotg
->regs
+ DPTXFSIZn(epnum
));
3114 hs_ep
->fifo_size
= DPTXFSIZn_DPTxFSize_GET(ptxfifo
) * 4;
3117 * if we're using dma, we need to set the next-endpoint pointer
3118 * to be something valid.
3121 if (using_dma(hsotg
)) {
3122 u32 next
= DxEPCTL_NextEp((epnum
+ 1) % 15);
3123 writel(next
, hsotg
->regs
+ DIEPCTL(epnum
));
3124 writel(next
, hsotg
->regs
+ DOEPCTL(epnum
));
3129 * s3c_hsotg_hw_cfg - read HW configuration registers
3130 * @param: The device state
3132 * Read the USB core HW configuration registers
3134 static void s3c_hsotg_hw_cfg(struct s3c_hsotg
*hsotg
)
3137 /* check hardware configuration */
3139 cfg2
= readl(hsotg
->regs
+ 0x48);
3140 hsotg
->num_of_eps
= (cfg2
>> 10) & 0xF;
3142 dev_info(hsotg
->dev
, "EPs:%d\n", hsotg
->num_of_eps
);
3144 cfg4
= readl(hsotg
->regs
+ 0x50);
3145 hsotg
->dedicated_fifos
= (cfg4
>> 25) & 1;
3147 dev_info(hsotg
->dev
, "%s fifos\n",
3148 hsotg
->dedicated_fifos
? "dedicated" : "shared");
3152 * s3c_hsotg_dump - dump state of the udc
3153 * @param: The device state
3155 static void s3c_hsotg_dump(struct s3c_hsotg
*hsotg
)
3158 struct device
*dev
= hsotg
->dev
;
3159 void __iomem
*regs
= hsotg
->regs
;
3163 dev_info(dev
, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
3164 readl(regs
+ DCFG
), readl(regs
+ DCTL
),
3165 readl(regs
+ DIEPMSK
));
3167 dev_info(dev
, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
3168 readl(regs
+ GAHBCFG
), readl(regs
+ 0x44));
3170 dev_info(dev
, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3171 readl(regs
+ GRXFSIZ
), readl(regs
+ GNPTXFSIZ
));
3173 /* show periodic fifo settings */
3175 for (idx
= 1; idx
<= 15; idx
++) {
3176 val
= readl(regs
+ DPTXFSIZn(idx
));
3177 dev_info(dev
, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx
,
3178 val
>> DPTXFSIZn_DPTxFSize_SHIFT
,
3179 val
& DPTXFSIZn_DPTxFStAddr_MASK
);
3182 for (idx
= 0; idx
< 15; idx
++) {
3184 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx
,
3185 readl(regs
+ DIEPCTL(idx
)),
3186 readl(regs
+ DIEPTSIZ(idx
)),
3187 readl(regs
+ DIEPDMA(idx
)));
3189 val
= readl(regs
+ DOEPCTL(idx
));
3191 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
3192 idx
, readl(regs
+ DOEPCTL(idx
)),
3193 readl(regs
+ DOEPTSIZ(idx
)),
3194 readl(regs
+ DOEPDMA(idx
)));
3198 dev_info(dev
, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
3199 readl(regs
+ DVBUSDIS
), readl(regs
+ DVBUSPULSE
));
3204 * state_show - debugfs: show overall driver and device state.
3205 * @seq: The seq file to write to.
3206 * @v: Unused parameter.
3208 * This debugfs entry shows the overall state of the hardware and
3209 * some general information about each of the endpoints available
3212 static int state_show(struct seq_file
*seq
, void *v
)
3214 struct s3c_hsotg
*hsotg
= seq
->private;
3215 void __iomem
*regs
= hsotg
->regs
;
3218 seq_printf(seq
, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
3221 readl(regs
+ DSTS
));
3223 seq_printf(seq
, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
3224 readl(regs
+ DIEPMSK
), readl(regs
+ DOEPMSK
));
3226 seq_printf(seq
, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
3227 readl(regs
+ GINTMSK
),
3228 readl(regs
+ GINTSTS
));
3230 seq_printf(seq
, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
3231 readl(regs
+ DAINTMSK
),
3232 readl(regs
+ DAINT
));
3234 seq_printf(seq
, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
3235 readl(regs
+ GNPTXSTS
),
3236 readl(regs
+ GRXSTSR
));
3238 seq_printf(seq
, "\nEndpoint status:\n");
3240 for (idx
= 0; idx
< 15; idx
++) {
3243 in
= readl(regs
+ DIEPCTL(idx
));
3244 out
= readl(regs
+ DOEPCTL(idx
));
3246 seq_printf(seq
, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
3249 in
= readl(regs
+ DIEPTSIZ(idx
));
3250 out
= readl(regs
+ DOEPTSIZ(idx
));
3252 seq_printf(seq
, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
3255 seq_printf(seq
, "\n");
3261 static int state_open(struct inode
*inode
, struct file
*file
)
3263 return single_open(file
, state_show
, inode
->i_private
);
3266 static const struct file_operations state_fops
= {
3267 .owner
= THIS_MODULE
,
3270 .llseek
= seq_lseek
,
3271 .release
= single_release
,
3275 * fifo_show - debugfs: show the fifo information
3276 * @seq: The seq_file to write data to.
3277 * @v: Unused parameter.
3279 * Show the FIFO information for the overall fifo and all the
3280 * periodic transmission FIFOs.
3282 static int fifo_show(struct seq_file
*seq
, void *v
)
3284 struct s3c_hsotg
*hsotg
= seq
->private;
3285 void __iomem
*regs
= hsotg
->regs
;
3289 seq_printf(seq
, "Non-periodic FIFOs:\n");
3290 seq_printf(seq
, "RXFIFO: Size %d\n", readl(regs
+ GRXFSIZ
));
3292 val
= readl(regs
+ GNPTXFSIZ
);
3293 seq_printf(seq
, "NPTXFIFO: Size %d, Start 0x%08x\n",
3294 val
>> GNPTXFSIZ_NPTxFDep_SHIFT
,
3295 val
& GNPTXFSIZ_NPTxFStAddr_MASK
);
3297 seq_printf(seq
, "\nPeriodic TXFIFOs:\n");
3299 for (idx
= 1; idx
<= 15; idx
++) {
3300 val
= readl(regs
+ DPTXFSIZn(idx
));
3302 seq_printf(seq
, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx
,
3303 val
>> DPTXFSIZn_DPTxFSize_SHIFT
,
3304 val
& DPTXFSIZn_DPTxFStAddr_MASK
);
3310 static int fifo_open(struct inode
*inode
, struct file
*file
)
3312 return single_open(file
, fifo_show
, inode
->i_private
);
3315 static const struct file_operations fifo_fops
= {
3316 .owner
= THIS_MODULE
,
3319 .llseek
= seq_lseek
,
3320 .release
= single_release
,
3324 static const char *decode_direction(int is_in
)
3326 return is_in
? "in" : "out";
3330 * ep_show - debugfs: show the state of an endpoint.
3331 * @seq: The seq_file to write data to.
3332 * @v: Unused parameter.
3334 * This debugfs entry shows the state of the given endpoint (one is
3335 * registered for each available).
3337 static int ep_show(struct seq_file
*seq
, void *v
)
3339 struct s3c_hsotg_ep
*ep
= seq
->private;
3340 struct s3c_hsotg
*hsotg
= ep
->parent
;
3341 struct s3c_hsotg_req
*req
;
3342 void __iomem
*regs
= hsotg
->regs
;
3343 int index
= ep
->index
;
3344 int show_limit
= 15;
3345 unsigned long flags
;
3347 seq_printf(seq
, "Endpoint index %d, named %s, dir %s:\n",
3348 ep
->index
, ep
->ep
.name
, decode_direction(ep
->dir_in
));
3350 /* first show the register state */
3352 seq_printf(seq
, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
3353 readl(regs
+ DIEPCTL(index
)),
3354 readl(regs
+ DOEPCTL(index
)));
3356 seq_printf(seq
, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
3357 readl(regs
+ DIEPDMA(index
)),
3358 readl(regs
+ DOEPDMA(index
)));
3360 seq_printf(seq
, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
3361 readl(regs
+ DIEPINT(index
)),
3362 readl(regs
+ DOEPINT(index
)));
3364 seq_printf(seq
, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
3365 readl(regs
+ DIEPTSIZ(index
)),
3366 readl(regs
+ DOEPTSIZ(index
)));
3368 seq_printf(seq
, "\n");
3369 seq_printf(seq
, "mps %d\n", ep
->ep
.maxpacket
);
3370 seq_printf(seq
, "total_data=%ld\n", ep
->total_data
);
3372 seq_printf(seq
, "request list (%p,%p):\n",
3373 ep
->queue
.next
, ep
->queue
.prev
);
3375 spin_lock_irqsave(&hsotg
->lock
, flags
);
3377 list_for_each_entry(req
, &ep
->queue
, queue
) {
3378 if (--show_limit
< 0) {
3379 seq_printf(seq
, "not showing more requests...\n");
3383 seq_printf(seq
, "%c req %p: %d bytes @%p, ",
3384 req
== ep
->req
? '*' : ' ',
3385 req
, req
->req
.length
, req
->req
.buf
);
3386 seq_printf(seq
, "%d done, res %d\n",
3387 req
->req
.actual
, req
->req
.status
);
3390 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3395 static int ep_open(struct inode
*inode
, struct file
*file
)
3397 return single_open(file
, ep_show
, inode
->i_private
);
3400 static const struct file_operations ep_fops
= {
3401 .owner
= THIS_MODULE
,
3404 .llseek
= seq_lseek
,
3405 .release
= single_release
,
3409 * s3c_hsotg_create_debug - create debugfs directory and files
3410 * @hsotg: The driver state
3412 * Create the debugfs files to allow the user to get information
3413 * about the state of the system. The directory name is created
3414 * with the same name as the device itself, in case we end up
3415 * with multiple blocks in future systems.
3417 static void __devinit
s3c_hsotg_create_debug(struct s3c_hsotg
*hsotg
)
3419 struct dentry
*root
;
3422 root
= debugfs_create_dir(dev_name(hsotg
->dev
), NULL
);
3423 hsotg
->debug_root
= root
;
3425 dev_err(hsotg
->dev
, "cannot create debug root\n");
3429 /* create general state file */
3431 hsotg
->debug_file
= debugfs_create_file("state", 0444, root
,
3432 hsotg
, &state_fops
);
3434 if (IS_ERR(hsotg
->debug_file
))
3435 dev_err(hsotg
->dev
, "%s: failed to create state\n", __func__
);
3437 hsotg
->debug_fifo
= debugfs_create_file("fifo", 0444, root
,
3440 if (IS_ERR(hsotg
->debug_fifo
))
3441 dev_err(hsotg
->dev
, "%s: failed to create fifo\n", __func__
);
3443 /* create one file for each endpoint */
3445 for (epidx
= 0; epidx
< hsotg
->num_of_eps
; epidx
++) {
3446 struct s3c_hsotg_ep
*ep
= &hsotg
->eps
[epidx
];
3448 ep
->debugfs
= debugfs_create_file(ep
->name
, 0444,
3449 root
, ep
, &ep_fops
);
3451 if (IS_ERR(ep
->debugfs
))
3452 dev_err(hsotg
->dev
, "failed to create %s debug file\n",
3458 * s3c_hsotg_delete_debug - cleanup debugfs entries
3459 * @hsotg: The driver state
3461 * Cleanup (remove) the debugfs files for use on module exit.
3463 static void __devexit
s3c_hsotg_delete_debug(struct s3c_hsotg
*hsotg
)
3467 for (epidx
= 0; epidx
< hsotg
->num_of_eps
; epidx
++) {
3468 struct s3c_hsotg_ep
*ep
= &hsotg
->eps
[epidx
];
3469 debugfs_remove(ep
->debugfs
);
3472 debugfs_remove(hsotg
->debug_file
);
3473 debugfs_remove(hsotg
->debug_fifo
);
3474 debugfs_remove(hsotg
->debug_root
);
3478 * s3c_hsotg_release - release callback for hsotg device
3479 * @dev: Device to for which release is called
3481 static void s3c_hsotg_release(struct device
*dev
)
3483 struct s3c_hsotg
*hsotg
= dev_get_drvdata(dev
);
3489 * s3c_hsotg_probe - probe function for hsotg driver
3490 * @pdev: The platform information for the driver
3493 static int __devinit
s3c_hsotg_probe(struct platform_device
*pdev
)
3495 struct s3c_hsotg_plat
*plat
= pdev
->dev
.platform_data
;
3496 struct device
*dev
= &pdev
->dev
;
3497 struct s3c_hsotg_ep
*eps
;
3498 struct s3c_hsotg
*hsotg
;
3499 struct resource
*res
;
3504 plat
= pdev
->dev
.platform_data
;
3506 dev_err(&pdev
->dev
, "no platform data defined\n");
3510 hsotg
= devm_kzalloc(&pdev
->dev
, sizeof(struct s3c_hsotg
), GFP_KERNEL
);
3512 dev_err(dev
, "cannot get memory\n");
3519 hsotg
->clk
= devm_clk_get(&pdev
->dev
, "otg");
3520 if (IS_ERR(hsotg
->clk
)) {
3521 dev_err(dev
, "cannot get otg clock\n");
3522 return PTR_ERR(hsotg
->clk
);
3525 platform_set_drvdata(pdev
, hsotg
);
3527 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
3529 hsotg
->regs
= devm_request_and_ioremap(&pdev
->dev
, res
);
3531 dev_err(dev
, "cannot map registers\n");
3536 ret
= platform_get_irq(pdev
, 0);
3538 dev_err(dev
, "cannot find IRQ\n");
3542 spin_lock_init(&hsotg
->lock
);
3546 ret
= devm_request_irq(&pdev
->dev
, hsotg
->irq
, s3c_hsotg_irq
, 0,
3547 dev_name(dev
), hsotg
);
3549 dev_err(dev
, "cannot claim IRQ\n");
3553 dev_info(dev
, "regs %p, irq %d\n", hsotg
->regs
, hsotg
->irq
);
3555 device_initialize(&hsotg
->gadget
.dev
);
3557 dev_set_name(&hsotg
->gadget
.dev
, "gadget");
3559 hsotg
->gadget
.max_speed
= USB_SPEED_HIGH
;
3560 hsotg
->gadget
.ops
= &s3c_hsotg_gadget_ops
;
3561 hsotg
->gadget
.name
= dev_name(dev
);
3563 hsotg
->gadget
.dev
.parent
= dev
;
3564 hsotg
->gadget
.dev
.dma_mask
= dev
->dma_mask
;
3565 hsotg
->gadget
.dev
.release
= s3c_hsotg_release
;
3567 /* reset the system */
3569 clk_prepare_enable(hsotg
->clk
);
3573 for (i
= 0; i
< ARRAY_SIZE(hsotg
->supplies
); i
++)
3574 hsotg
->supplies
[i
].supply
= s3c_hsotg_supply_names
[i
];
3576 ret
= regulator_bulk_get(dev
, ARRAY_SIZE(hsotg
->supplies
),
3579 dev_err(dev
, "failed to request supplies: %d\n", ret
);
3583 ret
= regulator_bulk_enable(ARRAY_SIZE(hsotg
->supplies
),
3587 dev_err(hsotg
->dev
, "failed to enable supplies: %d\n", ret
);
3591 /* usb phy enable */
3592 s3c_hsotg_phy_enable(hsotg
);
3594 s3c_hsotg_corereset(hsotg
);
3595 s3c_hsotg_init(hsotg
);
3596 s3c_hsotg_hw_cfg(hsotg
);
3598 /* hsotg->num_of_eps holds number of EPs other than ep0 */
3600 if (hsotg
->num_of_eps
== 0) {
3601 dev_err(dev
, "wrong number of EPs (zero)\n");
3606 eps
= kcalloc(hsotg
->num_of_eps
+ 1, sizeof(struct s3c_hsotg_ep
),
3609 dev_err(dev
, "cannot get memory\n");
3616 /* setup endpoint information */
3618 INIT_LIST_HEAD(&hsotg
->gadget
.ep_list
);
3619 hsotg
->gadget
.ep0
= &hsotg
->eps
[0].ep
;
3621 /* allocate EP0 request */
3623 hsotg
->ctrl_req
= s3c_hsotg_ep_alloc_request(&hsotg
->eps
[0].ep
,
3625 if (!hsotg
->ctrl_req
) {
3626 dev_err(dev
, "failed to allocate ctrl req\n");
3631 /* initialise the endpoints now the core has been initialised */
3632 for (epnum
= 0; epnum
< hsotg
->num_of_eps
; epnum
++)
3633 s3c_hsotg_initep(hsotg
, &hsotg
->eps
[epnum
], epnum
);
3635 /* disable power and clock */
3637 ret
= regulator_bulk_disable(ARRAY_SIZE(hsotg
->supplies
),
3640 dev_err(hsotg
->dev
, "failed to disable supplies: %d\n", ret
);
3644 s3c_hsotg_phy_disable(hsotg
);
3646 ret
= device_add(&hsotg
->gadget
.dev
);
3648 put_device(&hsotg
->gadget
.dev
);
3652 ret
= usb_add_gadget_udc(&pdev
->dev
, &hsotg
->gadget
);
3656 s3c_hsotg_create_debug(hsotg
);
3658 s3c_hsotg_dump(hsotg
);
3665 s3c_hsotg_phy_disable(hsotg
);
3666 regulator_bulk_free(ARRAY_SIZE(hsotg
->supplies
), hsotg
->supplies
);
3669 clk_disable_unprepare(hsotg
->clk
);
3675 * s3c_hsotg_remove - remove function for hsotg driver
3676 * @pdev: The platform information for the driver
3678 static int __devexit
s3c_hsotg_remove(struct platform_device
*pdev
)
3680 struct s3c_hsotg
*hsotg
= platform_get_drvdata(pdev
);
3682 usb_del_gadget_udc(&hsotg
->gadget
);
3684 s3c_hsotg_delete_debug(hsotg
);
3686 if (hsotg
->driver
) {
3687 /* should have been done already by driver model core */
3688 usb_gadget_unregister_driver(hsotg
->driver
);
3691 s3c_hsotg_phy_disable(hsotg
);
3692 regulator_bulk_free(ARRAY_SIZE(hsotg
->supplies
), hsotg
->supplies
);
3694 clk_disable_unprepare(hsotg
->clk
);
3696 device_unregister(&hsotg
->gadget
.dev
);
3701 #define s3c_hsotg_suspend NULL
3702 #define s3c_hsotg_resume NULL
3705 static struct platform_driver s3c_hsotg_driver
= {
3707 .name
= "s3c-hsotg",
3708 .owner
= THIS_MODULE
,
3710 .probe
= s3c_hsotg_probe
,
3711 .remove
= __devexit_p(s3c_hsotg_remove
),
3712 .suspend
= s3c_hsotg_suspend
,
3713 .resume
= s3c_hsotg_resume
,
3716 module_platform_driver(s3c_hsotg_driver
);
3718 MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device");
3719 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3720 MODULE_LICENSE("GPL");
3721 MODULE_ALIAS("platform:s3c-hsotg");