drivers/usb/host/dwc_otg/dwc_otg_core_if.h

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_core_if.h $
   3  * $Revision: #13 $
   4  * $Date: 2012/08/10 $
   5  * $Change: 2047372 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33 #if !defined(__DWC_CORE_IF_H__)
  34 #define __DWC_CORE_IF_H__
  35
  36 #include "dwc_os.h"
  37
  38 /** @file
  39  * This file defines DWC_OTG Core API
  40  */
  41
  42 struct dwc_otg_core_if;
  43 typedef struct dwc_otg_core_if dwc_otg_core_if_t;
  44
  45 /** Maximum number of Periodic FIFOs */
  46 #define MAX_PERIO_FIFOS 15
  47 /** Maximum number of Periodic FIFOs */
  48 #define MAX_TX_FIFOS 15
  49
  50 /** Maximum number of Endpoints/HostChannels */
  51 #define MAX_EPS_CHANNELS 16
  52
  53 extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * _reg_base_addr);
  54 extern void dwc_otg_core_init(dwc_otg_core_if_t * _core_if);
  55 extern void dwc_otg_cil_remove(dwc_otg_core_if_t * _core_if);
  56
  57 extern void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * _core_if);
  58 extern void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * _core_if);
  59
  60 extern uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if);
  61 extern uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if);
  62
  63 extern uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if);
  64
  65 /** This function should be called on every hardware interrupt. */
  66 extern int32_t dwc_otg_handle_common_intr(void *otg_dev);
  67
  68 /** @name OTG Core Parameters */
  69 /** @{ */
  70
  71 /**
  72  * Specifies the OTG capabilities. The driver will automatically
  73  * detect the value for this parameter if none is specified.
  74  * 0 - HNP and SRP capable (default)
  75  * 1 - SRP Only capable
  76  * 2 - No HNP/SRP capable
  77  */
  78 extern int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val);
  79 extern int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if);
  80 #define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
  81 #define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
  82 #define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
  83 #define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
  84
  85 extern int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val);
  86 extern int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if);
  87 #define dwc_param_opt_default 1
  88
  89 /**
  90  * Specifies whether to use slave or DMA mode for accessing the data
  91  * FIFOs. The driver will automatically detect the value for this
  92  * parameter if none is specified.
  93  * 0 - Slave
  94  * 1 - DMA (default, if available)
  95  */
  96 extern int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if,
  97                                         int32_t val);
  98 extern int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if);
  99 #define dwc_param_dma_enable_default 1
 100
 101 /**
 102  * When DMA mode is enabled specifies whether to use
 103  * address DMA or DMA Descritor mode for accessing the data
 104  * FIFOs in device mode. The driver will automatically detect
 105  * the value for this parameter if none is specified.
 106  * 0 - address DMA
 107  * 1 - DMA Descriptor(default, if available)
 108  */
 109 extern int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if,
 110                                              int32_t val);
 111 extern int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if);
 112 //#define dwc_param_dma_desc_enable_default 1
 113 #define dwc_param_dma_desc_enable_default 0 // Broadcom BCM2708
 114
 115 /** The DMA Burst size (applicable only for External DMA
 116  * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
 117  */
 118 extern int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if,
 119                                             int32_t val);
 120 extern int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if);
 121 #define dwc_param_dma_burst_size_default 32
 122
 123 /**
 124  * Specifies the maximum speed of operation in host and device mode.
 125  * The actual speed depends on the speed of the attached device and
 126  * the value of phy_type. The actual speed depends on the speed of the
 127  * attached device.
 128  * 0 - High Speed (default)
 129  * 1 - Full Speed
 130  */
 131 extern int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val);
 132 extern int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if);
 133 #define dwc_param_speed_default 0
 134 #define DWC_SPEED_PARAM_HIGH 0
 135 #define DWC_SPEED_PARAM_FULL 1
 136
 137 /** Specifies whether low power mode is supported when attached
 138  *      to a Full Speed or Low Speed device in host mode.
 139  * 0 - Don't support low power mode (default)
 140  * 1 - Support low power mode
 141  */
 142 extern int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *
 143                                                           core_if, int32_t val);
 144 extern int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t
 145                                                               * core_if);
 146 #define dwc_param_host_support_fs_ls_low_power_default 0
 147
 148 /** Specifies the PHY clock rate in low power mode when connected to a
 149  * Low Speed device in host mode. This parameter is applicable only if
 150  * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
 151  * then defaults to 6 MHZ otherwise 48 MHZ.
 152  *
 153  * 0 - 48 MHz
 154  * 1 - 6 MHz
 155  */
 156 extern int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
 157                                                        core_if, int32_t val);
 158 extern int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
 159                                                            core_if);
 160 #define dwc_param_host_ls_low_power_phy_clk_default 0
 161 #define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
 162 #define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
 163
 164 /**
 165  * 0 - Use cC FIFO size parameters
 166  * 1 - Allow dynamic FIFO sizing (default)
 167  */
 168 extern int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,
 169                                                  int32_t val);
 170 extern int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t *
 171                                                      core_if);
 172 #define dwc_param_enable_dynamic_fifo_default 1
 173
 174 /** Total number of 4-byte words in the data FIFO memory. This
 175  * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
 176  * Tx FIFOs.
 177  * 32 to 32768 (default 8192)
 178  * Note: The total FIFO memory depth in the FPGA configuration is 8192.
 179  */
 180 extern int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if,
 181                                             int32_t val);
 182 extern int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if);
 183 //#define dwc_param_data_fifo_size_default 8192
 184 #define dwc_param_data_fifo_size_default 0xFF0 // Broadcom BCM2708
 185
 186 /** Number of 4-byte words in the Rx FIFO in device mode when dynamic
 187  * FIFO sizing is enabled.
 188  * 16 to 32768 (default 1064)
 189  */
 190 extern int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if,
 191                                               int32_t val);
 192 extern int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if);
 193 #define dwc_param_dev_rx_fifo_size_default 1064
 194
 195 /** Number of 4-byte words in the non-periodic Tx FIFO in device mode
 196  * when dynamic FIFO sizing is enabled.
 197  * 16 to 32768 (default 1024)
 198  */
 199 extern int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
 200                                                      core_if, int32_t val);
 201 extern int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
 202                                                          core_if);
 203 #define dwc_param_dev_nperio_tx_fifo_size_default 1024
 204
 205 /** Number of 4-byte words in each of the periodic Tx FIFOs in device
 206  * mode when dynamic FIFO sizing is enabled.
 207  * 4 to 768 (default 256)
 208  */
 209 extern int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
 210                                                     int32_t val, int fifo_num);
 211 extern int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t *
 212                                                         core_if, int fifo_num);
 213 #define dwc_param_dev_perio_tx_fifo_size_default 256
 214
 215 /** Number of 4-byte words in the Rx FIFO in host mode when dynamic
 216  * FIFO sizing is enabled.
 217  * 16 to 32768 (default 1024)
 218  */
 219 extern int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,
 220                                                int32_t val);
 221 extern int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if);
 222 //#define dwc_param_host_rx_fifo_size_default 1024
 223 #define dwc_param_host_rx_fifo_size_default 774 // Broadcom BCM2708
 224
 225 /** Number of 4-byte words in the non-periodic Tx FIFO in host mode
 226  * when Dynamic FIFO sizing is enabled in the core.
 227  * 16 to 32768 (default 1024)
 228  */
 229 extern int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
 230                                                       core_if, int32_t val);
 231 extern int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
 232                                                           core_if);
 233 //#define dwc_param_host_nperio_tx_fifo_size_default 1024
 234 #define dwc_param_host_nperio_tx_fifo_size_default 0x100 // Broadcom BCM2708
 235
 236 /** Number of 4-byte words in the host periodic Tx FIFO when dynamic
 237  * FIFO sizing is enabled.
 238  * 16 to 32768 (default 1024)
 239  */
 240 extern int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
 241                                                      core_if, int32_t val);
 242 extern int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
 243                                                          core_if);
 244 //#define dwc_param_host_perio_tx_fifo_size_default 1024
 245 #define dwc_param_host_perio_tx_fifo_size_default 0x200 // Broadcom BCM2708
 246
 247 /** The maximum transfer size supported in bytes.
 248  * 2047 to 65,535  (default 65,535)
 249  */
 250 extern int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,
 251                                                int32_t val);
 252 extern int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if);
 253 #define dwc_param_max_transfer_size_default 65535
 254
 255 /** The maximum number of packets in a transfer.
 256  * 15 to 511  (default 511)
 257  */
 258 extern int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if,
 259                                               int32_t val);
 260 extern int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if);
 261 #define dwc_param_max_packet_count_default 511
 262
 263 /** The number of host channel registers to use.
 264  * 1 to 16 (default 12)
 265  * Note: The FPGA configuration supports a maximum of 12 host channels.
 266  */
 267 extern int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if,
 268                                            int32_t val);
 269 extern int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if);
 270 //#define dwc_param_host_channels_default 12
 271 #define dwc_param_host_channels_default 8 // Broadcom BCM2708
 272
 273 /** The number of endpoints in addition to EP0 available for device
 274  * mode operations.
 275  * 1 to 15 (default 6 IN and OUT)
 276  * Note: The FPGA configuration supports a maximum of 6 IN and OUT
 277  * endpoints in addition to EP0.
 278  */
 279 extern int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if,
 280                                            int32_t val);
 281 extern int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if);
 282 #define dwc_param_dev_endpoints_default 6
 283
 284 /**
 285  * Specifies the type of PHY interface to use. By default, the driver
 286  * will automatically detect the phy_type.
 287  *
 288  * 0 - Full Speed PHY
 289  * 1 - UTMI+ (default)
 290  * 2 - ULPI
 291  */
 292 extern int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val);
 293 extern int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if);
 294 #define DWC_PHY_TYPE_PARAM_FS 0
 295 #define DWC_PHY_TYPE_PARAM_UTMI 1
 296 #define DWC_PHY_TYPE_PARAM_ULPI 2
 297 #define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
 298
 299 /**
 300  * Specifies the UTMI+ Data Width. This parameter is
 301  * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
 302  * PHY_TYPE, this parameter indicates the data width between
 303  * the MAC and the ULPI Wrapper.) Also, this parameter is
 304  * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
 305  * to "8 and 16 bits", meaning that the core has been
 306  * configured to work at either data path width.
 307  *
 308  * 8 or 16 bits (default 16)
 309  */
 310 extern int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if,
 311                                             int32_t val);
 312 extern int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if);
 313 //#define dwc_param_phy_utmi_width_default 16
 314 #define dwc_param_phy_utmi_width_default 8 // Broadcom BCM2708
 315
 316 /**
 317  * Specifies whether the ULPI operates at double or single
 318  * data rate. This parameter is only applicable if PHY_TYPE is
 319  * ULPI.
 320  *
 321  * 0 - single data rate ULPI interface with 8 bit wide data
 322  * bus (default)
 323  * 1 - double data rate ULPI interface with 4 bit wide data
 324  * bus
 325  */
 326 extern int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if,
 327                                           int32_t val);
 328 extern int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if);
 329 #define dwc_param_phy_ulpi_ddr_default 0
 330
 331 /**
 332  * Specifies whether to use the internal or external supply to
 333  * drive the vbus with a ULPI phy.
 334  */
 335 extern int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,
 336                                                int32_t val);
 337 extern int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if);
 338 #define DWC_PHY_ULPI_INTERNAL_VBUS 0
 339 #define DWC_PHY_ULPI_EXTERNAL_VBUS 1
 340 #define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
 341
 342 /**
 343  * Specifies whether to use the I2Cinterface for full speed PHY. This
 344  * parameter is only applicable if PHY_TYPE is FS.
 345  * 0 - No (default)
 346  * 1 - Yes
 347  */
 348 extern int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if,
 349                                         int32_t val);
 350 extern int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if);
 351 #define dwc_param_i2c_enable_default 0
 352
 353 extern int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if,
 354                                         int32_t val);
 355 extern int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if);
 356 #define dwc_param_ulpi_fs_ls_default 0
 357
 358 extern int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val);
 359 extern int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if);
 360 #define dwc_param_ts_dline_default 0
 361
 362 /**
 363  * Specifies whether dedicated transmit FIFOs are
 364  * enabled for non periodic IN endpoints in device mode
 365  * 0 - No
 366  * 1 - Yes
 367  */
 368 extern int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,
 369                                                  int32_t val);
 370 extern int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t *
 371                                                      core_if);
 372 #define dwc_param_en_multiple_tx_fifo_default 1
 373
 374 /** Number of 4-byte words in each of the Tx FIFOs in device
 375  * mode when dynamic FIFO sizing is enabled.
 376  * 4 to 768 (default 256)
 377  */
 378 extern int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
 379                                               int fifo_num, int32_t val);
 380 extern int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
 381                                                   int fifo_num);
 382 #define dwc_param_dev_tx_fifo_size_default 768
 383
 384 /** Thresholding enable flag-
 385  * bit 0 - enable non-ISO Tx thresholding
 386  * bit 1 - enable ISO Tx thresholding
 387  * bit 2 - enable Rx thresholding
 388  */
 389 extern int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val);
 390 extern int32_t dwc_otg_get_thr_ctl(dwc_otg_core_if_t * core_if, int fifo_num);
 391 #define dwc_param_thr_ctl_default 0
 392
 393 /** Thresholding length for Tx
 394  * FIFOs in 32 bit DWORDs
 395  */
 396 extern int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if,
 397                                            int32_t val);
 398 extern int32_t dwc_otg_get_tx_thr_length(dwc_otg_core_if_t * core_if);
 399 #define dwc_param_tx_thr_length_default 64
 400
 401 /** Thresholding length for Rx
 402  *      FIFOs in 32 bit DWORDs
 403  */
 404 extern int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if,
 405                                            int32_t val);
 406 extern int32_t dwc_otg_get_rx_thr_length(dwc_otg_core_if_t * core_if);
 407 #define dwc_param_rx_thr_length_default 64
 408
 409 /**
 410  * Specifies whether LPM (Link Power Management) support is enabled
 411  */
 412 extern int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if,
 413                                         int32_t val);
 414 extern int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if);
 415 #define dwc_param_lpm_enable_default 1
 416
 417 /**
 418  * Specifies whether PTI enhancement is enabled
 419  */
 420 extern int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if,
 421                                         int32_t val);
 422 extern int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if);
 423 #define dwc_param_pti_enable_default 0
 424
 425 /**
 426  * Specifies whether MPI enhancement is enabled
 427  */
 428 extern int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if,
 429                                         int32_t val);
 430 extern int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if);
 431 #define dwc_param_mpi_enable_default 0
 432
 433 /**
 434  * Specifies whether ADP capability is enabled
 435  */
 436 extern int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if,
 437                                         int32_t val);
 438 extern int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if);
 439 #define dwc_param_adp_enable_default 0
 440
 441 /**
 442  * Specifies whether IC_USB capability is enabled
 443  */
 444
 445 extern int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if,
 446                                         int32_t val);
 447 extern int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if);
 448 #define dwc_param_ic_usb_cap_default 0
 449
 450 extern int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if,
 451                                            int32_t val);
 452 extern int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if);
 453 #define dwc_param_ahb_thr_ratio_default 0
 454
 455 extern int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if,
 456                                         int32_t val);
 457 extern int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if);
 458 #define dwc_param_power_down_default 0
 459
 460 extern int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if,
 461                                         int32_t val);
 462 extern int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if);
 463 #define dwc_param_reload_ctl_default 0
 464
 465 extern int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if,
 466                                                                                 int32_t val);
 467 extern int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if);
 468 #define dwc_param_dev_out_nak_default 0
 469
 470 extern int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if,
 471                                                                                  int32_t val);
 472 extern int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if);
 473 #define dwc_param_cont_on_bna_default 0
 474
 475 extern int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if,
 476                                                                                  int32_t val);
 477 extern int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if);
 478 #define dwc_param_ahb_single_default 0
 479
 480 extern int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val);
 481 extern int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if);
 482 #define dwc_param_otg_ver_default 0
 483
 484 /** @} */
 485
 486 /** @name Access to registers and bit-fields */
 487
 488 /**
 489  * Dump core registers and SPRAM
 490  */
 491 extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * _core_if);
 492 extern void dwc_otg_dump_spram(dwc_otg_core_if_t * _core_if);
 493 extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t * _core_if);
 494 extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t * _core_if);
 495
 496 /**
 497  * Get host negotiation status.
 498  */
 499 extern uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if);
 500
 501 /**
 502  * Get srp status
 503  */
 504 extern uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if);
 505
 506 /**
 507  * Set hnpreq bit in the GOTGCTL register.
 508  */
 509 extern void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val);
 510
 511 /**
 512  * Get Content of SNPSID register.
 513  */
 514 extern uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if);
 515
 516 /**
 517  * Get current mode.
 518  * Returns 0 if in device mode, and 1 if in host mode.
 519  */
 520 extern uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if);
 521
 522 /**
 523  * Get value of hnpcapable field in the GUSBCFG register
 524  */
 525 extern uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if);
 526 /**
 527  * Set value of hnpcapable field in the GUSBCFG register
 528  */
 529 extern void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
 530
 531 /**
 532  * Get value of srpcapable field in the GUSBCFG register
 533  */
 534 extern uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if);
 535 /**
 536  * Set value of srpcapable field in the GUSBCFG register
 537  */
 538 extern void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
 539
 540 /**
 541  * Get value of devspeed field in the DCFG register
 542  */
 543 extern uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if);
 544 /**
 545  * Set value of devspeed field in the DCFG register
 546  */
 547 extern void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val);
 548
 549 /**
 550  * Get the value of busconnected field from the HPRT0 register
 551  */
 552 extern uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if);
 553
 554 /**
 555  * Gets the device enumeration Speed.
 556  */
 557 extern uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if);
 558
 559 /**
 560  * Get value of prtpwr field from the HPRT0 register
 561  */
 562 extern uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if);
 563
 564 /**
 565  * Get value of flag indicating core state - hibernated or not
 566  */
 567 extern uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if);
 568
 569 /**
 570  * Set value of prtpwr field from the HPRT0 register
 571  */
 572 extern void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val);
 573
 574 /**
 575  * Get value of prtsusp field from the HPRT0 regsiter
 576  */
 577 extern uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if);
 578 /**
 579  * Set value of prtpwr field from the HPRT0 register
 580  */
 581 extern void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val);
 582
 583 /**
 584  * Get value of ModeChTimEn field from the HCFG regsiter
 585  */
 586 extern uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if);
 587 /**
 588  * Set value of ModeChTimEn field from the HCFG regsiter
 589  */
 590 extern void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val);
 591
 592 /**
 593  * Get value of Fram Interval field from the HFIR regsiter
 594  */
 595 extern uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if);
 596 /**
 597  * Set value of Frame Interval field from the HFIR regsiter
 598  */
 599 extern void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val);
 600
 601 /**
 602  * Set value of prtres field from the HPRT0 register
 603  *FIXME Remove?
 604  */
 605 extern void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val);
 606
 607 /**
 608  * Get value of rmtwkupsig bit in DCTL register
 609  */
 610 extern uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if);
 611
 612 /**
 613  * Get value of prt_sleep_sts field from the GLPMCFG register
 614  */
 615 extern uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if);
 616
 617 /**
 618  * Get value of rem_wkup_en field from the GLPMCFG register
 619  */
 620 extern uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if);
 621
 622 /**
 623  * Get value of appl_resp field from the GLPMCFG register
 624  */
 625 extern uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if);
 626 /**
 627  * Set value of appl_resp field from the GLPMCFG register
 628  */
 629 extern void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val);
 630
 631 /**
 632  * Get value of hsic_connect field from the GLPMCFG register
 633  */
 634 extern uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if);
 635 /**
 636  * Set value of hsic_connect field from the GLPMCFG register
 637  */
 638 extern void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val);
 639
 640 /**
 641  * Get value of inv_sel_hsic field from the GLPMCFG register.
 642  */
 643 extern uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if);
 644 /**
 645  * Set value of inv_sel_hsic field from the GLPMFG register.
 646  */
 647 extern void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val);
 648
 649 /*
 650  * Some functions for accessing registers
 651  */
 652
 653 /**
 654  *  GOTGCTL register
 655  */
 656 extern uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if);
 657 extern void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val);
 658
 659 /**
 660  * GUSBCFG register
 661  */
 662 extern uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if);
 663 extern void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val);
 664
 665 /**
 666  * GRXFSIZ register
 667  */
 668 extern uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if);
 669 extern void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
 670
 671 /**
 672  * GNPTXFSIZ register
 673  */
 674 extern uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if);
 675 extern void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
 676
 677 extern uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if);
 678 extern void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val);
 679
 680 /**
 681  * GGPIO register
 682  */
 683 extern uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if);
 684 extern void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val);
 685
 686 /**
 687  * GUID register
 688  */
 689 extern uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if);
 690 extern void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val);
 691
 692 /**
 693  * HPRT0 register
 694  */
 695 extern uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if);
 696 extern void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val);
 697
 698 /**
 699  * GHPTXFSIZE
 700  */
 701 extern uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if);
 702
 703 /** @} */
 704
 705 #endif                          /* __DWC_CORE_IF_H__ */