2 * Copyright (c) 2000-2004 by David Brownell
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/dmapool.h>
22 #include <linux/kernel.h>
23 #include <linux/delay.h>
24 #include <linux/ioport.h>
25 #include <linux/sched.h>
26 #include <linux/slab.h>
27 #include <linux/errno.h>
28 #include <linux/init.h>
29 #include <linux/timer.h>
30 #include <linux/list.h>
31 #include <linux/interrupt.h>
32 #include <linux/reboot.h>
33 #include <linux/usb.h>
34 #include <linux/moduleparam.h>
35 #include <linux/dma-mapping.h>
37 #include "../core/hcd.h"
39 #include <asm/byteorder.h>
42 #include <asm/system.h>
43 #include <asm/unaligned.h>
45 #include <asm/firmware.h>
49 /*-------------------------------------------------------------------------*/
52 * EHCI hc_driver implementation ... experimental, incomplete.
53 * Based on the final 1.0 register interface specification.
55 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
56 * First was PCMCIA, like ISA; then CardBus, which is PCI.
57 * Next comes "CardBay", using USB 2.0 signals.
59 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
60 * Special thanks to Intel and VIA for providing host controllers to
61 * test this driver on, and Cypress (including In-System Design) for
62 * providing early devices for those host controllers to talk to!
66 * 2004-05-10 Root hub and PCI suspend/resume support; remote wakeup. (db)
67 * 2004-02-24 Replace pci_* with generic dma_* API calls (dsaxena@plexity.net)
68 * 2003-12-29 Rewritten high speed iso transfer support (by Michal Sojka,
69 * <sojkam@centrum.cz>, updates by DB).
71 * 2002-11-29 Correct handling for hw async_next register.
72 * 2002-08-06 Handling for bulk and interrupt transfers is mostly shared;
73 * only scheduling is different, no arbitrary limitations.
74 * 2002-07-25 Sanity check PCI reads, mostly for better cardbus support,
75 * clean up HC run state handshaking.
76 * 2002-05-24 Preliminary FS/LS interrupts, using scheduling shortcuts
77 * 2002-05-11 Clear TT errors for FS/LS ctrl/bulk. Fill in some other
78 * missing pieces: enabling 64bit dma, handoff from BIOS/SMM.
79 * 2002-05-07 Some error path cleanups to report better errors; wmb();
80 * use non-CVS version id; better iso bandwidth claim.
81 * 2002-04-19 Control/bulk/interrupt submit no longer uses giveback() on
82 * errors in submit path. Bugfixes to interrupt scheduling/processing.
83 * 2002-03-05 Initial high-speed ISO support; reduce ITD memory; shift
84 * more checking to generic hcd framework (db). Make it work with
85 * Philips EHCI; reduce PCI traffic; shorten IRQ path (Rory Bolt).
86 * 2002-01-14 Minor cleanup; version synch.
87 * 2002-01-08 Fix roothub handoff of FS/LS to companion controllers.
88 * 2002-01-04 Control/Bulk queuing behaves.
90 * 2001-12-12 Initial patch version for Linux 2.5.1 kernel.
91 * 2001-June Works with usb-storage and NEC EHCI on 2.4
94 #define DRIVER_VERSION "10 Dec 2004"
95 #define DRIVER_AUTHOR "David Brownell"
96 #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
98 static const char hcd_name
[] = "ehci_hcd";
101 #undef EHCI_VERBOSE_DEBUG
102 #undef EHCI_URB_TRACE
108 /* magic numbers that can affect system performance */
109 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
110 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
111 #define EHCI_TUNE_RL_TT 0
112 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
113 #define EHCI_TUNE_MULT_TT 1
114 #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
116 #define EHCI_IAA_JIFFIES (HZ/100) /* arbitrary; ~10 msec */
117 #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
118 #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
119 #define EHCI_SHRINK_JIFFIES (HZ/200) /* async qh unlink delay */
121 /* Initial IRQ latency: faster than hw default */
122 static int log2_irq_thresh
= 0; // 0 to 6
123 module_param (log2_irq_thresh
, int, S_IRUGO
);
124 MODULE_PARM_DESC (log2_irq_thresh
, "log2 IRQ latency, 1-64 microframes");
126 /* initial park setting: slower than hw default */
127 static unsigned park
= 0;
128 module_param (park
, uint
, S_IRUGO
);
129 MODULE_PARM_DESC (park
, "park setting; 1-3 back-to-back async packets");
131 /* for flakey hardware, ignore overcurrent indicators */
132 static int ignore_oc
= 0;
133 module_param (ignore_oc
, bool, S_IRUGO
);
134 MODULE_PARM_DESC (ignore_oc
, "ignore bogus hardware overcurrent indications");
136 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
138 /*-------------------------------------------------------------------------*/
141 #include "ehci-dbg.c"
143 /*-------------------------------------------------------------------------*/
146 * handshake - spin reading hc until handshake completes or fails
147 * @ptr: address of hc register to be read
148 * @mask: bits to look at in result of read
149 * @done: value of those bits when handshake succeeds
150 * @usec: timeout in microseconds
152 * Returns negative errno, or zero on success
154 * Success happens when the "mask" bits have the specified value (hardware
155 * handshake done). There are two failure modes: "usec" have passed (major
156 * hardware flakeout), or the register reads as all-ones (hardware removed).
158 * That last failure should_only happen in cases like physical cardbus eject
159 * before driver shutdown. But it also seems to be caused by bugs in cardbus
160 * bridge shutdown: shutting down the bridge before the devices using it.
162 static int handshake (struct ehci_hcd
*ehci
, void __iomem
*ptr
,
163 u32 mask
, u32 done
, int usec
)
168 result
= ehci_readl(ehci
, ptr
);
169 if (result
== ~(u32
)0) /* card removed */
180 /* force HC to halt state from unknown (EHCI spec section 2.3) */
181 static int ehci_halt (struct ehci_hcd
*ehci
)
183 u32 temp
= ehci_readl(ehci
, &ehci
->regs
->status
);
185 /* disable any irqs left enabled by previous code */
186 ehci_writel(ehci
, 0, &ehci
->regs
->intr_enable
);
188 if ((temp
& STS_HALT
) != 0)
191 temp
= ehci_readl(ehci
, &ehci
->regs
->command
);
193 ehci_writel(ehci
, temp
, &ehci
->regs
->command
);
194 return handshake (ehci
, &ehci
->regs
->status
,
195 STS_HALT
, STS_HALT
, 16 * 125);
198 /* put TDI/ARC silicon into EHCI mode */
199 static void tdi_reset (struct ehci_hcd
*ehci
)
201 u32 __iomem
*reg_ptr
;
204 reg_ptr
= (u32 __iomem
*)(((u8 __iomem
*)ehci
->regs
) + 0x68);
205 tmp
= ehci_readl(ehci
, reg_ptr
);
207 ehci_writel(ehci
, tmp
, reg_ptr
);
210 /* reset a non-running (STS_HALT == 1) controller */
211 static int ehci_reset (struct ehci_hcd
*ehci
)
214 u32 command
= ehci_readl(ehci
, &ehci
->regs
->command
);
216 command
|= CMD_RESET
;
217 dbg_cmd (ehci
, "reset", command
);
218 ehci_writel(ehci
, command
, &ehci
->regs
->command
);
219 ehci_to_hcd(ehci
)->state
= HC_STATE_HALT
;
220 ehci
->next_statechange
= jiffies
;
221 retval
= handshake (ehci
, &ehci
->regs
->command
,
222 CMD_RESET
, 0, 250 * 1000);
227 if (ehci_is_TDI(ehci
))
233 /* idle the controller (from running) */
234 static void ehci_quiesce (struct ehci_hcd
*ehci
)
239 if (!HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
))
243 /* wait for any schedule enables/disables to take effect */
244 temp
= ehci_readl(ehci
, &ehci
->regs
->command
) << 10;
245 temp
&= STS_ASS
| STS_PSS
;
246 if (handshake (ehci
, &ehci
->regs
->status
, STS_ASS
| STS_PSS
,
247 temp
, 16 * 125) != 0) {
248 ehci_to_hcd(ehci
)->state
= HC_STATE_HALT
;
252 /* then disable anything that's still active */
253 temp
= ehci_readl(ehci
, &ehci
->regs
->command
);
254 temp
&= ~(CMD_ASE
| CMD_IAAD
| CMD_PSE
);
255 ehci_writel(ehci
, temp
, &ehci
->regs
->command
);
257 /* hardware can take 16 microframes to turn off ... */
258 if (handshake (ehci
, &ehci
->regs
->status
, STS_ASS
| STS_PSS
,
260 ehci_to_hcd(ehci
)->state
= HC_STATE_HALT
;
265 /*-------------------------------------------------------------------------*/
267 static void ehci_work(struct ehci_hcd
*ehci
);
269 #include "ehci-hub.c"
270 #include "ehci-mem.c"
272 #include "ehci-sched.c"
274 /*-------------------------------------------------------------------------*/
276 #ifdef CONFIG_CPU_FREQ
278 #include <linux/cpufreq.h>
280 static void ehci_cpufreq_pause (struct ehci_hcd
*ehci
)
284 spin_lock_irqsave(&ehci
->lock
, flags
);
285 if (!ehci
->cpufreq_changing
++)
286 qh_inactivate_split_intr_qhs(ehci
);
287 spin_unlock_irqrestore(&ehci
->lock
, flags
);
290 static void ehci_cpufreq_unpause (struct ehci_hcd
*ehci
)
294 spin_lock_irqsave(&ehci
->lock
, flags
);
295 if (!--ehci
->cpufreq_changing
)
296 qh_reactivate_split_intr_qhs(ehci
);
297 spin_unlock_irqrestore(&ehci
->lock
, flags
);
301 * ehci_cpufreq_notifier is needed to avoid MMF errors that occur when
302 * EHCI controllers that don't cache many uframes get delayed trying to
303 * read main memory during CPU frequency transitions. This can cause
304 * split interrupt transactions to not be completed in the required uframe.
305 * This has been observed on the Broadcom/ServerWorks HT1000 controller.
307 static int ehci_cpufreq_notifier(struct notifier_block
*nb
, unsigned long val
,
310 struct ehci_hcd
*ehci
= container_of(nb
, struct ehci_hcd
,
314 case CPUFREQ_PRECHANGE
:
315 ehci_cpufreq_pause(ehci
);
317 case CPUFREQ_POSTCHANGE
:
318 ehci_cpufreq_unpause(ehci
);
326 /*-------------------------------------------------------------------------*/
328 static void ehci_watchdog (unsigned long param
)
330 struct ehci_hcd
*ehci
= (struct ehci_hcd
*) param
;
333 spin_lock_irqsave (&ehci
->lock
, flags
);
335 /* lost IAA irqs wedge things badly; seen with a vt8235 */
337 u32 status
= ehci_readl(ehci
, &ehci
->regs
->status
);
338 if (status
& STS_IAA
) {
339 ehci_vdbg (ehci
, "lost IAA\n");
340 COUNT (ehci
->stats
.lost_iaa
);
341 ehci_writel(ehci
, STS_IAA
, &ehci
->regs
->status
);
342 ehci
->reclaim_ready
= 1;
346 /* stop async processing after it's idled a bit */
347 if (test_bit (TIMER_ASYNC_OFF
, &ehci
->actions
))
348 start_unlink_async (ehci
, ehci
->async
);
350 /* ehci could run by timer, without IRQs ... */
353 spin_unlock_irqrestore (&ehci
->lock
, flags
);
356 /* On some systems, leaving remote wakeup enabled prevents system shutdown.
357 * The firmware seems to think that powering off is a wakeup event!
358 * This routine turns off remote wakeup and everything else, on all ports.
360 static void ehci_turn_off_all_ports(struct ehci_hcd
*ehci
)
362 int port
= HCS_N_PORTS(ehci
->hcs_params
);
365 ehci_writel(ehci
, PORT_RWC_BITS
,
366 &ehci
->regs
->port_status
[port
]);
369 /* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
370 * This forcibly disables dma and IRQs, helping kexec and other cases
371 * where the next system software may expect clean state.
374 ehci_shutdown (struct usb_hcd
*hcd
)
376 struct ehci_hcd
*ehci
;
378 ehci
= hcd_to_ehci (hcd
);
379 (void) ehci_halt (ehci
);
380 ehci_turn_off_all_ports(ehci
);
382 /* make BIOS/etc use companion controller during reboot */
383 ehci_writel(ehci
, 0, &ehci
->regs
->configured_flag
);
385 /* unblock posted writes */
386 ehci_readl(ehci
, &ehci
->regs
->configured_flag
);
389 static void ehci_port_power (struct ehci_hcd
*ehci
, int is_on
)
393 if (!HCS_PPC (ehci
->hcs_params
))
396 ehci_dbg (ehci
, "...power%s ports...\n", is_on
? "up" : "down");
397 for (port
= HCS_N_PORTS (ehci
->hcs_params
); port
> 0; )
398 (void) ehci_hub_control(ehci_to_hcd(ehci
),
399 is_on
? SetPortFeature
: ClearPortFeature
,
405 /*-------------------------------------------------------------------------*/
408 * ehci_work is called from some interrupts, timers, and so on.
409 * it calls driver completion functions, after dropping ehci->lock.
411 static void ehci_work (struct ehci_hcd
*ehci
)
413 timer_action_done (ehci
, TIMER_IO_WATCHDOG
);
414 if (ehci
->reclaim_ready
)
415 end_unlink_async (ehci
);
417 /* another CPU may drop ehci->lock during a schedule scan while
418 * it reports urb completions. this flag guards against bogus
419 * attempts at re-entrant schedule scanning.
425 if (ehci
->next_uframe
!= -1)
426 scan_periodic (ehci
);
429 /* the IO watchdog guards against hardware or driver bugs that
430 * misplace IRQs, and should let us run completely without IRQs.
431 * such lossage has been observed on both VT6202 and VT8235.
433 if (HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
) &&
434 (ehci
->async
->qh_next
.ptr
!= NULL
||
435 ehci
->periodic_sched
!= 0))
436 timer_action (ehci
, TIMER_IO_WATCHDOG
);
439 static void ehci_stop (struct usb_hcd
*hcd
)
441 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
443 ehci_dbg (ehci
, "stop\n");
445 /* Turn off port power on all root hub ports. */
446 ehci_port_power (ehci
, 0);
448 /* no more interrupts ... */
449 del_timer_sync (&ehci
->watchdog
);
451 spin_lock_irq(&ehci
->lock
);
452 if (HC_IS_RUNNING (hcd
->state
))
456 ehci_writel(ehci
, 0, &ehci
->regs
->intr_enable
);
457 spin_unlock_irq(&ehci
->lock
);
459 #ifdef CONFIG_CPU_FREQ
460 cpufreq_unregister_notifier(&ehci
->cpufreq_transition
,
461 CPUFREQ_TRANSITION_NOTIFIER
);
463 /* let companion controllers work when we aren't */
464 ehci_writel(ehci
, 0, &ehci
->regs
->configured_flag
);
466 remove_companion_file(ehci
);
467 remove_debug_files (ehci
);
469 /* root hub is shut down separately (first, when possible) */
470 spin_lock_irq (&ehci
->lock
);
473 spin_unlock_irq (&ehci
->lock
);
474 ehci_mem_cleanup (ehci
);
477 ehci_dbg (ehci
, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
478 ehci
->stats
.normal
, ehci
->stats
.error
, ehci
->stats
.reclaim
,
479 ehci
->stats
.lost_iaa
);
480 ehci_dbg (ehci
, "complete %ld unlink %ld\n",
481 ehci
->stats
.complete
, ehci
->stats
.unlink
);
484 dbg_status (ehci
, "ehci_stop completed",
485 ehci_readl(ehci
, &ehci
->regs
->status
));
488 /* one-time init, only for memory state */
489 static int ehci_init(struct usb_hcd
*hcd
)
491 struct ehci_hcd
*ehci
= hcd_to_ehci(hcd
);
496 spin_lock_init(&ehci
->lock
);
498 init_timer(&ehci
->watchdog
);
499 ehci
->watchdog
.function
= ehci_watchdog
;
500 ehci
->watchdog
.data
= (unsigned long) ehci
;
503 * hw default: 1K periodic list heads, one per frame.
504 * periodic_size can shrink by USBCMD update if hcc_params allows.
506 ehci
->periodic_size
= DEFAULT_I_TDPS
;
507 if ((retval
= ehci_mem_init(ehci
, GFP_KERNEL
)) < 0)
510 /* controllers may cache some of the periodic schedule ... */
511 hcc_params
= ehci_readl(ehci
, &ehci
->caps
->hcc_params
);
512 if (HCC_ISOC_CACHE(hcc_params
)) // full frame cache
514 else // N microframes cached
515 ehci
->i_thresh
= 2 + HCC_ISOC_THRES(hcc_params
);
517 ehci
->reclaim
= NULL
;
518 ehci
->reclaim_ready
= 0;
519 ehci
->next_uframe
= -1;
522 * dedicate a qh for the async ring head, since we couldn't unlink
523 * a 'real' qh without stopping the async schedule [4.8]. use it
524 * as the 'reclamation list head' too.
525 * its dummy is used in hw_alt_next of many tds, to prevent the qh
526 * from automatically advancing to the next td after short reads.
528 ehci
->async
->qh_next
.qh
= NULL
;
529 ehci
->async
->hw_next
= QH_NEXT(ehci
->async
->qh_dma
);
530 ehci
->async
->hw_info1
= cpu_to_le32(QH_HEAD
);
531 ehci
->async
->hw_token
= cpu_to_le32(QTD_STS_HALT
);
532 ehci
->async
->hw_qtd_next
= EHCI_LIST_END
;
533 ehci
->async
->qh_state
= QH_STATE_LINKED
;
534 ehci
->async
->hw_alt_next
= QTD_NEXT(ehci
->async
->dummy
->qtd_dma
);
536 /* clear interrupt enables, set irq latency */
537 if (log2_irq_thresh
< 0 || log2_irq_thresh
> 6)
539 temp
= 1 << (16 + log2_irq_thresh
);
540 if (HCC_CANPARK(hcc_params
)) {
541 /* HW default park == 3, on hardware that supports it (like
542 * NVidia and ALI silicon), maximizes throughput on the async
543 * schedule by avoiding QH fetches between transfers.
545 * With fast usb storage devices and NForce2, "park" seems to
546 * make problems: throughput reduction (!), data errors...
549 park
= min(park
, (unsigned) 3);
553 ehci_dbg(ehci
, "park %d\n", park
);
555 if (HCC_PGM_FRAMELISTLEN(hcc_params
)) {
556 /* periodic schedule size can be smaller than default */
558 temp
|= (EHCI_TUNE_FLS
<< 2);
559 switch (EHCI_TUNE_FLS
) {
560 case 0: ehci
->periodic_size
= 1024; break;
561 case 1: ehci
->periodic_size
= 512; break;
562 case 2: ehci
->periodic_size
= 256; break;
566 ehci
->command
= temp
;
568 #ifdef CONFIG_CPU_FREQ
569 INIT_LIST_HEAD(&ehci
->split_intr_qhs
);
571 * If the EHCI controller caches enough uframes, this probably
572 * isn't needed unless there are so many low/full speed devices
573 * that the controller's can't cache it all.
575 ehci
->cpufreq_transition
.notifier_call
= ehci_cpufreq_notifier
;
576 cpufreq_register_notifier(&ehci
->cpufreq_transition
,
577 CPUFREQ_TRANSITION_NOTIFIER
);
582 /* start HC running; it's halted, ehci_init() has been run (once) */
583 static int ehci_run (struct usb_hcd
*hcd
)
585 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
590 hcd
->uses_new_polling
= 1;
593 /* EHCI spec section 4.1 */
594 if ((retval
= ehci_reset(ehci
)) != 0) {
595 ehci_mem_cleanup(ehci
);
598 ehci_writel(ehci
, ehci
->periodic_dma
, &ehci
->regs
->frame_list
);
599 ehci_writel(ehci
, (u32
)ehci
->async
->qh_dma
, &ehci
->regs
->async_next
);
602 * hcc_params controls whether ehci->regs->segment must (!!!)
603 * be used; it constrains QH/ITD/SITD and QTD locations.
604 * pci_pool consistent memory always uses segment zero.
605 * streaming mappings for I/O buffers, like pci_map_single(),
606 * can return segments above 4GB, if the device allows.
608 * NOTE: the dma mask is visible through dma_supported(), so
609 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
610 * Scsi_Host.highmem_io, and so forth. It's readonly to all
611 * host side drivers though.
613 hcc_params
= ehci_readl(ehci
, &ehci
->caps
->hcc_params
);
614 if (HCC_64BIT_ADDR(hcc_params
)) {
615 ehci_writel(ehci
, 0, &ehci
->regs
->segment
);
617 // this is deeply broken on almost all architectures
618 if (!dma_set_mask(hcd
->self
.controller
, DMA_64BIT_MASK
))
619 ehci_info(ehci
, "enabled 64bit DMA\n");
624 // Philips, Intel, and maybe others need CMD_RUN before the
625 // root hub will detect new devices (why?); NEC doesn't
626 ehci
->command
&= ~(CMD_LRESET
|CMD_IAAD
|CMD_PSE
|CMD_ASE
|CMD_RESET
);
627 ehci
->command
|= CMD_RUN
;
628 ehci_writel(ehci
, ehci
->command
, &ehci
->regs
->command
);
629 dbg_cmd (ehci
, "init", ehci
->command
);
632 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
633 * are explicitly handed to companion controller(s), so no TT is
634 * involved with the root hub. (Except where one is integrated,
635 * and there's no companion controller unless maybe for USB OTG.)
637 hcd
->state
= HC_STATE_RUNNING
;
638 ehci_writel(ehci
, FLAG_CF
, &ehci
->regs
->configured_flag
);
639 ehci_readl(ehci
, &ehci
->regs
->command
); /* unblock posted writes */
641 temp
= HC_VERSION(ehci_readl(ehci
, &ehci
->caps
->hc_capbase
));
643 "USB %x.%x started, EHCI %x.%02x, driver %s%s\n",
644 ((ehci
->sbrn
& 0xf0)>>4), (ehci
->sbrn
& 0x0f),
645 temp
>> 8, temp
& 0xff, DRIVER_VERSION
,
646 ignore_oc
? ", overcurrent ignored" : "");
648 ehci_writel(ehci
, INTR_MASK
,
649 &ehci
->regs
->intr_enable
); /* Turn On Interrupts */
651 /* GRR this is run-once init(), being done every time the HC starts.
652 * So long as they're part of class devices, we can't do it init()
653 * since the class device isn't created that early.
655 create_debug_files(ehci
);
656 create_companion_file(ehci
);
661 /*-------------------------------------------------------------------------*/
663 static irqreturn_t
ehci_irq (struct usb_hcd
*hcd
)
665 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
666 u32 status
, pcd_status
= 0;
669 spin_lock (&ehci
->lock
);
671 status
= ehci_readl(ehci
, &ehci
->regs
->status
);
673 /* e.g. cardbus physical eject */
674 if (status
== ~(u32
) 0) {
675 ehci_dbg (ehci
, "device removed\n");
680 if (!status
) { /* irq sharing? */
681 spin_unlock(&ehci
->lock
);
685 /* clear (just) interrupts */
686 ehci_writel(ehci
, status
, &ehci
->regs
->status
);
687 ehci_readl(ehci
, &ehci
->regs
->command
); /* unblock posted write */
690 #ifdef EHCI_VERBOSE_DEBUG
691 /* unrequested/ignored: Frame List Rollover */
692 dbg_status (ehci
, "irq", status
);
695 /* INT, ERR, and IAA interrupt rates can be throttled */
697 /* normal [4.15.1.2] or error [4.15.1.1] completion */
698 if (likely ((status
& (STS_INT
|STS_ERR
)) != 0)) {
699 if (likely ((status
& STS_ERR
) == 0))
700 COUNT (ehci
->stats
.normal
);
702 COUNT (ehci
->stats
.error
);
706 /* complete the unlinking of some qh [4.15.2.3] */
707 if (status
& STS_IAA
) {
708 COUNT (ehci
->stats
.reclaim
);
709 ehci
->reclaim_ready
= 1;
713 /* remote wakeup [4.3.1] */
714 if (status
& STS_PCD
) {
715 unsigned i
= HCS_N_PORTS (ehci
->hcs_params
);
718 /* resume root hub? */
719 if (!(ehci_readl(ehci
, &ehci
->regs
->command
) & CMD_RUN
))
720 usb_hcd_resume_root_hub(hcd
);
723 int pstatus
= ehci_readl(ehci
,
724 &ehci
->regs
->port_status
[i
]);
726 if (pstatus
& PORT_OWNER
)
728 if (!(pstatus
& PORT_RESUME
)
729 || ehci
->reset_done
[i
] != 0)
732 /* start 20 msec resume signaling from this port,
733 * and make khubd collect PORT_STAT_C_SUSPEND to
734 * stop that signaling.
736 ehci
->reset_done
[i
] = jiffies
+ msecs_to_jiffies (20);
737 ehci_dbg (ehci
, "port %d remote wakeup\n", i
+ 1);
738 mod_timer(&hcd
->rh_timer
, ehci
->reset_done
[i
]);
742 /* PCI errors [4.15.2.4] */
743 if (unlikely ((status
& STS_FATAL
) != 0)) {
744 /* bogus "fatal" IRQs appear on some chips... why? */
745 status
= ehci_readl(ehci
, &ehci
->regs
->status
);
746 dbg_cmd (ehci
, "fatal", ehci_readl(ehci
,
747 &ehci
->regs
->command
));
748 dbg_status (ehci
, "fatal", status
);
749 if (status
& STS_HALT
) {
750 ehci_err (ehci
, "fatal error\n");
753 ehci_writel(ehci
, 0, &ehci
->regs
->configured_flag
);
754 /* generic layer kills/unlinks all urbs, then
755 * uses ehci_stop to clean up the rest
763 spin_unlock (&ehci
->lock
);
764 if (pcd_status
& STS_PCD
)
765 usb_hcd_poll_rh_status(hcd
);
769 /*-------------------------------------------------------------------------*/
772 * non-error returns are a promise to giveback() the urb later
773 * we drop ownership so next owner (or urb unlink) can get it
775 * urb + dev is in hcd.self.controller.urb_list
776 * we're queueing TDs onto software and hardware lists
778 * hcd-specific init for hcpriv hasn't been done yet
780 * NOTE: control, bulk, and interrupt share the same code to append TDs
781 * to a (possibly active) QH, and the same QH scanning code.
783 static int ehci_urb_enqueue (
785 struct usb_host_endpoint
*ep
,
789 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
790 struct list_head qtd_list
;
792 INIT_LIST_HEAD (&qtd_list
);
794 switch (usb_pipetype (urb
->pipe
)) {
795 // case PIPE_CONTROL:
798 if (!qh_urb_transaction (ehci
, urb
, &qtd_list
, mem_flags
))
800 return submit_async (ehci
, ep
, urb
, &qtd_list
, mem_flags
);
803 if (!qh_urb_transaction (ehci
, urb
, &qtd_list
, mem_flags
))
805 return intr_submit (ehci
, ep
, urb
, &qtd_list
, mem_flags
);
807 case PIPE_ISOCHRONOUS
:
808 if (urb
->dev
->speed
== USB_SPEED_HIGH
)
809 return itd_submit (ehci
, urb
, mem_flags
);
811 return sitd_submit (ehci
, urb
, mem_flags
);
815 static void unlink_async (struct ehci_hcd
*ehci
, struct ehci_qh
*qh
)
817 /* if we need to use IAA and it's busy, defer */
818 if (qh
->qh_state
== QH_STATE_LINKED
820 && HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
)) {
821 struct ehci_qh
*last
;
823 for (last
= ehci
->reclaim
;
825 last
= last
->reclaim
)
827 qh
->qh_state
= QH_STATE_UNLINK_WAIT
;
830 /* bypass IAA if the hc can't care */
831 } else if (!HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
) && ehci
->reclaim
)
832 end_unlink_async (ehci
);
834 /* something else might have unlinked the qh by now */
835 if (qh
->qh_state
== QH_STATE_LINKED
)
836 start_unlink_async (ehci
, qh
);
839 /* remove from hardware lists
840 * completions normally happen asynchronously
843 static int ehci_urb_dequeue (struct usb_hcd
*hcd
, struct urb
*urb
)
845 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
849 spin_lock_irqsave (&ehci
->lock
, flags
);
850 switch (usb_pipetype (urb
->pipe
)) {
851 // case PIPE_CONTROL:
854 qh
= (struct ehci_qh
*) urb
->hcpriv
;
857 unlink_async (ehci
, qh
);
861 qh
= (struct ehci_qh
*) urb
->hcpriv
;
864 switch (qh
->qh_state
) {
865 case QH_STATE_LINKED
:
866 intr_deschedule (ehci
, qh
);
869 qh_completions (ehci
, qh
);
872 ehci_dbg (ehci
, "bogus qh %p state %d\n",
877 /* reschedule QH iff another request is queued */
878 if (!list_empty (&qh
->qtd_list
)
879 && HC_IS_RUNNING (hcd
->state
)) {
882 status
= qh_schedule (ehci
, qh
);
883 spin_unlock_irqrestore (&ehci
->lock
, flags
);
886 // shouldn't happen often, but ...
887 // FIXME kill those tds' urbs
888 err ("can't reschedule qh %p, err %d",
895 case PIPE_ISOCHRONOUS
:
898 // wait till next completion, do it then.
899 // completion irqs can wait up to 1024 msec,
903 spin_unlock_irqrestore (&ehci
->lock
, flags
);
907 /*-------------------------------------------------------------------------*/
909 // bulk qh holds the data toggle
912 ehci_endpoint_disable (struct usb_hcd
*hcd
, struct usb_host_endpoint
*ep
)
914 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
916 struct ehci_qh
*qh
, *tmp
;
918 /* ASSERT: any requests/urbs are being unlinked */
919 /* ASSERT: nobody can be submitting urbs for this any more */
922 spin_lock_irqsave (&ehci
->lock
, flags
);
927 /* endpoints can be iso streams. for now, we don't
928 * accelerate iso completions ... so spin a while.
930 if (qh
->hw_info1
== 0) {
931 ehci_vdbg (ehci
, "iso delay\n");
935 if (!HC_IS_RUNNING (hcd
->state
))
936 qh
->qh_state
= QH_STATE_IDLE
;
937 switch (qh
->qh_state
) {
938 case QH_STATE_LINKED
:
939 for (tmp
= ehci
->async
->qh_next
.qh
;
941 tmp
= tmp
->qh_next
.qh
)
943 /* periodic qh self-unlinks on empty */
946 unlink_async (ehci
, qh
);
948 case QH_STATE_UNLINK
: /* wait for hw to finish? */
950 spin_unlock_irqrestore (&ehci
->lock
, flags
);
951 schedule_timeout_uninterruptible(1);
953 case QH_STATE_IDLE
: /* fully unlinked */
954 if (list_empty (&qh
->qtd_list
)) {
958 /* else FALL THROUGH */
961 /* caller was supposed to have unlinked any requests;
962 * that's not our job. just leak this memory.
964 ehci_err (ehci
, "qh %p (#%02x) state %d%s\n",
965 qh
, ep
->desc
.bEndpointAddress
, qh
->qh_state
,
966 list_empty (&qh
->qtd_list
) ? "" : "(has tds)");
971 spin_unlock_irqrestore (&ehci
->lock
, flags
);
975 static int ehci_get_frame (struct usb_hcd
*hcd
)
977 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
978 return (ehci_readl(ehci
, &ehci
->regs
->frame_index
) >> 3) %
982 /*-------------------------------------------------------------------------*/
984 #define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC
986 MODULE_DESCRIPTION (DRIVER_INFO
);
987 MODULE_AUTHOR (DRIVER_AUTHOR
);
988 MODULE_LICENSE ("GPL");
991 #include "ehci-pci.c"
992 #define PCI_DRIVER ehci_pci_driver
995 #ifdef CONFIG_MPC834x
996 #include "ehci-fsl.c"
997 #define PLATFORM_DRIVER ehci_fsl_driver
1000 #ifdef CONFIG_SOC_AU1200
1001 #include "ehci-au1xxx.c"
1002 #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver
1005 #ifdef CONFIG_PPC_PS3
1006 #include "ehci-ps3.c"
1007 #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_sb_driver
1010 #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
1011 !defined(PS3_SYSTEM_BUS_DRIVER)
1012 #error "missing bus glue for ehci-hcd"
1015 static int __init
ehci_hcd_init(void)
1019 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
1021 sizeof(struct ehci_qh
), sizeof(struct ehci_qtd
),
1022 sizeof(struct ehci_itd
), sizeof(struct ehci_sitd
));
1024 #ifdef PLATFORM_DRIVER
1025 retval
= platform_driver_register(&PLATFORM_DRIVER
);
1031 retval
= pci_register_driver(&PCI_DRIVER
);
1033 #ifdef PLATFORM_DRIVER
1034 platform_driver_unregister(&PLATFORM_DRIVER
);
1040 #ifdef PS3_SYSTEM_BUS_DRIVER
1041 if (firmware_has_feature(FW_FEATURE_PS3_LV1
)) {
1042 retval
= ps3_system_bus_driver_register(
1043 &PS3_SYSTEM_BUS_DRIVER
);
1045 #ifdef PLATFORM_DRIVER
1046 platform_driver_unregister(&PLATFORM_DRIVER
);
1049 pci_unregister_driver(&PCI_DRIVER
);
1058 module_init(ehci_hcd_init
);
1060 static void __exit
ehci_hcd_cleanup(void)
1062 #ifdef PLATFORM_DRIVER
1063 platform_driver_unregister(&PLATFORM_DRIVER
);
1066 pci_unregister_driver(&PCI_DRIVER
);
1068 #ifdef PS3_SYSTEM_BUS_DRIVER
1069 if (firmware_has_feature(FW_FEATURE_PS3_LV1
))
1070 ps3_system_bus_driver_unregister(&PS3_SYSTEM_BUS_DRIVER
);
1073 module_exit(ehci_hcd_cleanup
);