drivers/usb/host/ehci-pci.c

   1 /*
   2  * EHCI HCD (Host Controller Driver) PCI Bus Glue.
   3  *
   4  * Copyright (c) 2000-2004 by David Brownell
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License as published by the
   8  * Free Software Foundation; either version 2 of the License, or (at your
   9  * option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14  * for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20
  21 #ifndef CONFIG_PCI
  22 #error "This file is PCI bus glue.  CONFIG_PCI must be defined."
  23 #endif
  24
  25 /*-------------------------------------------------------------------------*/
  26
  27 /* called after powerup, by probe or system-pm "wakeup" */
  28 static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
  29 {
  30         u32                     temp;
  31         int                     retval;
  32
  33         /* optional debug port, normally in the first BAR */
  34         temp = pci_find_capability(pdev, 0x0a);
  35         if (temp) {
  36                 pci_read_config_dword(pdev, temp, &temp);
  37                 temp >>= 16;
  38                 if ((temp & (3 << 13)) == (1 << 13)) {
  39                         temp &= 0x1fff;
  40                         ehci->debug = ehci_to_hcd(ehci)->regs + temp;
  41                         temp = ehci_readl(ehci, &ehci->debug->control);
  42                         ehci_info(ehci, "debug port %d%s\n",
  43                                 HCS_DEBUG_PORT(ehci->hcs_params),
  44                                 (temp & DBGP_ENABLED)
  45                                         ? " IN USE"
  46                                         : "");
  47                         if (!(temp & DBGP_ENABLED))
  48                                 ehci->debug = NULL;
  49                 }
  50         }
  51
  52         /* we expect static quirk code to handle the "extended capabilities"
  53          * (currently just BIOS handoff) allowed starting with EHCI 0.96
  54          */
  55
  56         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  57         retval = pci_set_mwi(pdev);
  58         if (!retval)
  59                 ehci_dbg(ehci, "MWI active\n");
  60
  61         return 0;
  62 }
  63
  64 /* called during probe() after chip reset completes */
  65 static int ehci_pci_setup(struct usb_hcd *hcd)
  66 {
  67         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
  68         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
  69         struct pci_dev          *p_smbus;
  70         u8                      rev;
  71         u32                     temp;
  72         int                     retval;
  73
  74         switch (pdev->vendor) {
  75         case PCI_VENDOR_ID_TOSHIBA_2:
  76                 /* celleb's companion chip */
  77                 if (pdev->device == 0x01b5) {
  78 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
  79                         ehci->big_endian_mmio = 1;
  80 #else
  81                         ehci_warn(ehci,
  82                                   "unsupported big endian Toshiba quirk\n");
  83 #endif
  84                 }
  85                 break;
  86         }
  87
  88         ehci->caps = hcd->regs;
  89         ehci->regs = hcd->regs +
  90                 HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
  91
  92         dbg_hcs_params(ehci, "reset");
  93         dbg_hcc_params(ehci, "reset");
  94
  95         /* ehci_init() causes memory for DMA transfers to be
  96          * allocated.  Thus, any vendor-specific workarounds based on
  97          * limiting the type of memory used for DMA transfers must
  98          * happen before ehci_init() is called. */
  99         switch (pdev->vendor) {
 100         case PCI_VENDOR_ID_NVIDIA:
 101                 /* NVidia reports that certain chips don't handle
 102                  * QH, ITD, or SITD addresses above 2GB.  (But TD,
 103                  * data buffer, and periodic schedule are normal.)
 104                  */
 105                 switch (pdev->device) {
 106                 case 0x003c:    /* MCP04 */
 107                 case 0x005b:    /* CK804 */
 108                 case 0x00d8:    /* CK8 */
 109                 case 0x00e8:    /* CK8S */
 110                         if (pci_set_consistent_dma_mask(pdev,
 111                                                 DMA_31BIT_MASK) < 0)
 112                                 ehci_warn(ehci, "can't enable NVidia "
 113                                         "workaround for >2GB RAM\n");
 114                         break;
 115                 }
 116                 break;
 117         }
 118
 119         /* cache this readonly data; minimize chip reads */
 120         ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
 121
 122         retval = ehci_halt(ehci);
 123         if (retval)
 124                 return retval;
 125
 126         /* data structure init */
 127         retval = ehci_init(hcd);
 128         if (retval)
 129                 return retval;
 130
 131         switch (pdev->vendor) {
 132         case PCI_VENDOR_ID_TDI:
 133                 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
 134                         hcd->has_tt = 1;
 135                         tdi_reset(ehci);
 136                 }
 137                 break;
 138         case PCI_VENDOR_ID_AMD:
 139                 /* AMD8111 EHCI doesn't work, according to AMD errata */
 140                 if (pdev->device == 0x7463) {
 141                         ehci_info(ehci, "ignoring AMD8111 (errata)\n");
 142                         retval = -EIO;
 143                         goto done;
 144                 }
 145                 break;
 146         case PCI_VENDOR_ID_NVIDIA:
 147                 switch (pdev->device) {
 148                 /* Some NForce2 chips have problems with selective suspend;
 149                  * fixed in newer silicon.
 150                  */
 151                 case 0x0068:
 152                         if (pdev->revision < 0xa4)
 153                                 ehci->no_selective_suspend = 1;
 154                         break;
 155                 }
 156                 break;
 157         case PCI_VENDOR_ID_VIA:
 158                 if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
 159                         u8 tmp;
 160
 161                         /* The VT6212 defaults to a 1 usec EHCI sleep time which
 162                          * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
 163                          * that sleep time use the conventional 10 usec.
 164                          */
 165                         pci_read_config_byte(pdev, 0x4b, &tmp);
 166                         if (tmp & 0x20)
 167                                 break;
 168                         pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
 169                 }
 170                 break;
 171         case PCI_VENDOR_ID_ATI:
 172                 /* SB700 old version has a bug in EHCI controller,
 173                  * which causes usb devices lose response in some cases.
 174                  */
 175                 if (pdev->device == 0x4396) {
 176                         p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
 177                                                  PCI_DEVICE_ID_ATI_SBX00_SMBUS,
 178                                                  NULL);
 179                         if (!p_smbus)
 180                                 break;
 181                         rev = p_smbus->revision;
 182                         if ((rev == 0x3a) || (rev == 0x3b)) {
 183                                 u8 tmp;
 184                                 pci_read_config_byte(pdev, 0x53, &tmp);
 185                                 pci_write_config_byte(pdev, 0x53, tmp | (1<<3));
 186                         }
 187                         pci_dev_put(p_smbus);
 188                 }
 189                 break;
 190         }
 191
 192         ehci_reset(ehci);
 193
 194         /* at least the Genesys GL880S needs fixup here */
 195         temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
 196         temp &= 0x0f;
 197         if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
 198                 ehci_dbg(ehci, "bogus port configuration: "
 199                         "cc=%d x pcc=%d < ports=%d\n",
 200                         HCS_N_CC(ehci->hcs_params),
 201                         HCS_N_PCC(ehci->hcs_params),
 202                         HCS_N_PORTS(ehci->hcs_params));
 203
 204                 switch (pdev->vendor) {
 205                 case 0x17a0:            /* GENESYS */
 206                         /* GL880S: should be PORTS=2 */
 207                         temp |= (ehci->hcs_params & ~0xf);
 208                         ehci->hcs_params = temp;
 209                         break;
 210                 case PCI_VENDOR_ID_NVIDIA:
 211                         /* NF4: should be PCC=10 */
 212                         break;
 213                 }
 214         }
 215
 216         /* Serial Bus Release Number is at PCI 0x60 offset */
 217         pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
 218
 219         /* Workaround current PCI init glitch:  wakeup bits aren't
 220          * being set from PCI PM capability.
 221          */
 222         if (!device_can_wakeup(&pdev->dev)) {
 223                 u16     port_wake;
 224
 225                 pci_read_config_word(pdev, 0x62, &port_wake);
 226                 if (port_wake & 0x0001)
 227                         device_init_wakeup(&pdev->dev, 1);
 228         }
 229
 230 #ifdef  CONFIG_USB_SUSPEND
 231         /* REVISIT: the controller works fine for wakeup iff the root hub
 232          * itself is "globally" suspended, but usbcore currently doesn't
 233          * understand such things.
 234          *
 235          * System suspend currently expects to be able to suspend the entire
 236          * device tree, device-at-a-time.  If we failed selective suspend
 237          * reports, system suspend would fail; so the root hub code must claim
 238          * success.  That's lying to usbcore, and it matters for for runtime
 239          * PM scenarios with selective suspend and remote wakeup...
 240          */
 241         if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
 242                 ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
 243 #endif
 244
 245         ehci_port_power(ehci, 1);
 246         retval = ehci_pci_reinit(ehci, pdev);
 247 done:
 248         return retval;
 249 }
 250
 251 /*-------------------------------------------------------------------------*/
 252
 253 #ifdef  CONFIG_PM
 254
 255 /* suspend/resume, section 4.3 */
 256
 257 /* These routines rely on the PCI bus glue
 258  * to handle powerdown and wakeup, and currently also on
 259  * transceivers that don't need any software attention to set up
 260  * the right sort of wakeup.
 261  * Also they depend on separate root hub suspend/resume.
 262  */
 263
 264 static int ehci_pci_suspend(struct usb_hcd *hcd, pm_message_t message)
 265 {
 266         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
 267         unsigned long           flags;
 268         int                     rc = 0;
 269
 270         if (time_before(jiffies, ehci->next_statechange))
 271                 msleep(10);
 272
 273         /* Root hub was already suspended. Disable irq emission and
 274          * mark HW unaccessible, bail out if RH has been resumed. Use
 275          * the spinlock to properly synchronize with possible pending
 276          * RH suspend or resume activity.
 277          *
 278          * This is still racy as hcd->state is manipulated outside of
 279          * any locks =P But that will be a different fix.
 280          */
 281         spin_lock_irqsave (&ehci->lock, flags);
 282         if (hcd->state != HC_STATE_SUSPENDED) {
 283                 rc = -EINVAL;
 284                 goto bail;
 285         }
 286         ehci_writel(ehci, 0, &ehci->regs->intr_enable);
 287         (void)ehci_readl(ehci, &ehci->regs->intr_enable);
 288
 289         /* make sure snapshot being resumed re-enumerates everything */
 290         if (message.event == PM_EVENT_PRETHAW) {
 291                 ehci_halt(ehci);
 292                 ehci_reset(ehci);
 293         }
 294
 295         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 296  bail:
 297         spin_unlock_irqrestore (&ehci->lock, flags);
 298
 299         // could save FLADJ in case of Vaux power loss
 300         // ... we'd only use it to handle clock skew
 301
 302         return rc;
 303 }
 304
 305 static int ehci_pci_resume(struct usb_hcd *hcd)
 306 {
 307         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
 308         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 309
 310         // maybe restore FLADJ
 311
 312         if (time_before(jiffies, ehci->next_statechange))
 313                 msleep(100);
 314
 315         /* Mark hardware accessible again as we are out of D3 state by now */
 316         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 317
 318         /* If CF is still set, we maintained PCI Vaux power.
 319          * Just undo the effect of ehci_pci_suspend().
 320          */
 321         if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF) {
 322                 int     mask = INTR_MASK;
 323
 324                 if (!hcd->self.root_hub->do_remote_wakeup)
 325                         mask &= ~STS_PCD;
 326                 ehci_writel(ehci, mask, &ehci->regs->intr_enable);
 327                 ehci_readl(ehci, &ehci->regs->intr_enable);
 328                 return 0;
 329         }
 330
 331         ehci_dbg(ehci, "lost power, restarting\n");
 332         usb_root_hub_lost_power(hcd->self.root_hub);
 333
 334         /* Else reset, to cope with power loss or flush-to-storage
 335          * style "resume" having let BIOS kick in during reboot.
 336          */
 337         (void) ehci_halt(ehci);
 338         (void) ehci_reset(ehci);
 339         (void) ehci_pci_reinit(ehci, pdev);
 340
 341         /* emptying the schedule aborts any urbs */
 342         spin_lock_irq(&ehci->lock);
 343         if (ehci->reclaim)
 344                 end_unlink_async(ehci);
 345         ehci_work(ehci);
 346         spin_unlock_irq(&ehci->lock);
 347
 348         ehci_writel(ehci, ehci->command, &ehci->regs->command);
 349         ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
 350         ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
 351
 352         /* here we "know" root ports should always stay powered */
 353         ehci_port_power(ehci, 1);
 354
 355         hcd->state = HC_STATE_SUSPENDED;
 356         return 0;
 357 }
 358 #endif
 359
 360 static const struct hc_driver ehci_pci_hc_driver = {
 361         .description =          hcd_name,
 362         .product_desc =         "EHCI Host Controller",
 363         .hcd_priv_size =        sizeof(struct ehci_hcd),
 364
 365         /*
 366          * generic hardware linkage
 367          */
 368         .irq =                  ehci_irq,
 369         .flags =                HCD_MEMORY | HCD_USB2,
 370
 371         /*
 372          * basic lifecycle operations
 373          */
 374         .reset =                ehci_pci_setup,
 375         .start =                ehci_run,
 376 #ifdef  CONFIG_PM
 377         .pci_suspend =          ehci_pci_suspend,
 378         .pci_resume =           ehci_pci_resume,
 379 #endif
 380         .stop =                 ehci_stop,
 381         .shutdown =             ehci_shutdown,
 382
 383         /*
 384          * managing i/o requests and associated device resources
 385          */
 386         .urb_enqueue =          ehci_urb_enqueue,
 387         .urb_dequeue =          ehci_urb_dequeue,
 388         .endpoint_disable =     ehci_endpoint_disable,
 389
 390         /*
 391          * scheduling support
 392          */
 393         .get_frame_number =     ehci_get_frame,
 394
 395         /*
 396          * root hub support
 397          */
 398         .hub_status_data =      ehci_hub_status_data,
 399         .hub_control =          ehci_hub_control,
 400         .bus_suspend =          ehci_bus_suspend,
 401         .bus_resume =           ehci_bus_resume,
 402         .relinquish_port =      ehci_relinquish_port,
 403         .port_handed_over =     ehci_port_handed_over,
 404 };
 405
 406 /*-------------------------------------------------------------------------*/
 407
 408 /* PCI driver selection metadata; PCI hotplugging uses this */
 409 static const struct pci_device_id pci_ids [] = { {
 410         /* handle any USB 2.0 EHCI controller */
 411         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
 412         .driver_data =  (unsigned long) &ehci_pci_hc_driver,
 413         },
 414         { /* end: all zeroes */ }
 415 };
 416 MODULE_DEVICE_TABLE(pci, pci_ids);
 417
 418 /* pci driver glue; this is a "new style" PCI driver module */
 419 static struct pci_driver ehci_pci_driver = {
 420         .name =         (char *) hcd_name,
 421         .id_table =     pci_ids,
 422
 423         .probe =        usb_hcd_pci_probe,
 424         .remove =       usb_hcd_pci_remove,
 425
 426 #ifdef  CONFIG_PM
 427         .suspend =      usb_hcd_pci_suspend,
 428         .resume =       usb_hcd_pci_resume,
 429 #endif
 430         .shutdown =     usb_hcd_pci_shutdown,
 431 };