drivers/usb/host/ehci.h

   1 /*
   2  * Copyright (c) 2001-2002 by David Brownell
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the
   6  * Free Software Foundation; either version 2 of the License, or (at your
   7  * option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software Foundation,
  16  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17  */
  18
  19 #ifndef __LINUX_EHCI_HCD_H
  20 #define __LINUX_EHCI_HCD_H
  21
  22 /* definitions used for the EHCI driver */
  23
  24 /*
  25  * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
  26  * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
  27  * the host controller implementation.
  28  *
  29  * To facilitate the strongest possible byte-order checking from "sparse"
  30  * and so on, we use __leXX unless that's not practical.
  31  */
  32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
  33 typedef __u32 __bitwise __hc32;
  34 typedef __u16 __bitwise __hc16;
  35 #else
  36 #define __hc32  __le32
  37 #define __hc16  __le16
  38 #endif
  39
  40 /* statistics can be kept for tuning/monitoring */
  41 #ifdef CONFIG_DYNAMIC_DEBUG
  42 #define EHCI_STATS
  43 #endif
  44
  45 struct ehci_stats {
  46         /* irq usage */
  47         unsigned long           normal;
  48         unsigned long           error;
  49         unsigned long           iaa;
  50         unsigned long           lost_iaa;
  51
  52         /* termination of urbs from core */
  53         unsigned long           complete;
  54         unsigned long           unlink;
  55 };
  56
  57 /*
  58  * Scheduling and budgeting information for periodic transfers, for both
  59  * high-speed devices and full/low-speed devices lying behind a TT.
  60  */
  61 struct ehci_per_sched {
  62         struct usb_device       *udev;          /* access to the TT */
  63         struct usb_host_endpoint *ep;
  64         struct list_head        ps_list;        /* node on ehci_tt's ps_list */
  65         u16                     tt_usecs;       /* time on the FS/LS bus */
  66         u16                     cs_mask;        /* C-mask and S-mask bytes */
  67         u16                     period;         /* actual period in frames */
  68         u16                     phase;          /* actual phase, frame part */
  69         u8                      bw_phase;       /* same, for bandwidth
  70                                                    reservation */
  71         u8                      phase_uf;       /* uframe part of the phase */
  72         u8                      usecs, c_usecs; /* times on the HS bus */
  73         u8                      bw_uperiod;     /* period in microframes, for
  74                                                    bandwidth reservation */
  75         u8                      bw_period;      /* same, in frames */
  76 };
  77 #define NO_FRAME        29999                   /* frame not assigned yet */
  78
  79 /* ehci_hcd->lock guards shared data against other CPUs:
  80  *   ehci_hcd:  async, unlink, periodic (and shadow), ...
  81  *   usb_host_endpoint: hcpriv
  82  *   ehci_qh:   qh_next, qtd_list
  83  *   ehci_qtd:  qtd_list
  84  *
  85  * Also, hold this lock when talking to HC registers or
  86  * when updating hw_* fields in shared qh/qtd/... structures.
  87  */
  88
  89 #define EHCI_MAX_ROOT_PORTS     15              /* see HCS_N_PORTS */
  90
  91 /*
  92  * ehci_rh_state values of EHCI_RH_RUNNING or above mean that the
  93  * controller may be doing DMA.  Lower values mean there's no DMA.
  94  */
  95 enum ehci_rh_state {
  96         EHCI_RH_HALTED,
  97         EHCI_RH_SUSPENDED,
  98         EHCI_RH_RUNNING,
  99         EHCI_RH_STOPPING
 100 };
 101
 102 /*
 103  * Timer events, ordered by increasing delay length.
 104  * Always update event_delays_ns[] and event_handlers[] (defined in
 105  * ehci-timer.c) in parallel with this list.
 106  */
 107 enum ehci_hrtimer_event {
 108         EHCI_HRTIMER_POLL_ASS,          /* Poll for async schedule off */
 109         EHCI_HRTIMER_POLL_PSS,          /* Poll for periodic schedule off */
 110         EHCI_HRTIMER_POLL_DEAD,         /* Wait for dead controller to stop */
 111         EHCI_HRTIMER_UNLINK_INTR,       /* Wait for interrupt QH unlink */
 112         EHCI_HRTIMER_FREE_ITDS,         /* Wait for unused iTDs and siTDs */
 113         EHCI_HRTIMER_ACTIVE_UNLINK,     /* Wait while unlinking an active QH */
 114         EHCI_HRTIMER_START_UNLINK_INTR, /* Unlink empty interrupt QHs */
 115         EHCI_HRTIMER_ASYNC_UNLINKS,     /* Unlink empty async QHs */
 116         EHCI_HRTIMER_IAA_WATCHDOG,      /* Handle lost IAA interrupts */
 117         EHCI_HRTIMER_DISABLE_PERIODIC,  /* Wait to disable periodic sched */
 118         EHCI_HRTIMER_DISABLE_ASYNC,     /* Wait to disable async sched */
 119         EHCI_HRTIMER_IO_WATCHDOG,       /* Check for missing IRQs */
 120         EHCI_HRTIMER_NUM_EVENTS         /* Must come last */
 121 };
 122 #define EHCI_HRTIMER_NO_EVENT   99
 123
 124 struct ehci_hcd {                       /* one per controller */
 125         /* timing support */
 126         enum ehci_hrtimer_event next_hrtimer_event;
 127         unsigned                enabled_hrtimer_events;
 128         ktime_t                 hr_timeouts[EHCI_HRTIMER_NUM_EVENTS];
 129         struct hrtimer          hrtimer;
 130
 131         int                     PSS_poll_count;
 132         int                     ASS_poll_count;
 133         int                     died_poll_count;
 134
 135         /* glue to PCI and HCD framework */
 136         struct ehci_caps __iomem *caps;
 137         struct ehci_regs __iomem *regs;
 138         struct ehci_dbg_port __iomem *debug;
 139
 140         __u32                   hcs_params;     /* cached register copy */
 141         spinlock_t              lock;
 142         enum ehci_rh_state      rh_state;
 143
 144         /* general schedule support */
 145         bool                    scanning:1;
 146         bool                    need_rescan:1;
 147         bool                    intr_unlinking:1;
 148         bool                    iaa_in_progress:1;
 149         bool                    async_unlinking:1;
 150         bool                    shutdown:1;
 151         struct ehci_qh          *qh_scan_next;
 152
 153         /* async schedule support */
 154         struct ehci_qh          *async;
 155         struct ehci_qh          *dummy;         /* For AMD quirk use */
 156         struct list_head        async_unlink;
 157         struct list_head        async_idle;
 158         unsigned                async_unlink_cycle;
 159         unsigned                async_count;    /* async activity count */
 160         __hc32                  old_current;    /* Test for QH becoming */
 161         __hc32                  old_token;      /*  inactive during unlink */
 162
 163         /* periodic schedule support */
 164 #define DEFAULT_I_TDPS          1024            /* some HCs can do less */
 165         unsigned                periodic_size;
 166         __hc32                  *periodic;      /* hw periodic table */
 167         dma_addr_t              periodic_dma;
 168         struct list_head        intr_qh_list;
 169         unsigned                i_thresh;       /* uframes HC might cache */
 170
 171         union ehci_shadow       *pshadow;       /* mirror hw periodic table */
 172         struct list_head        intr_unlink_wait;
 173         struct list_head        intr_unlink;
 174         unsigned                intr_unlink_wait_cycle;
 175         unsigned                intr_unlink_cycle;
 176         unsigned                now_frame;      /* frame from HC hardware */
 177         unsigned                last_iso_frame; /* last frame scanned for iso */
 178         unsigned                intr_count;     /* intr activity count */
 179         unsigned                isoc_count;     /* isoc activity count */
 180         unsigned                periodic_count; /* periodic activity count */
 181         unsigned                uframe_periodic_max; /* max periodic time per uframe */
 182
 183
 184         /* list of itds & sitds completed while now_frame was still active */
 185         struct list_head        cached_itd_list;
 186         struct ehci_itd         *last_itd_to_free;
 187         struct list_head        cached_sitd_list;
 188         struct ehci_sitd        *last_sitd_to_free;
 189
 190         /* per root hub port */
 191         unsigned long           reset_done[EHCI_MAX_ROOT_PORTS];
 192
 193         /* bit vectors (one bit per port) */
 194         unsigned long           bus_suspended;          /* which ports were
 195                         already suspended at the start of a bus suspend */
 196         unsigned long           companion_ports;        /* which ports are
 197                         dedicated to the companion controller */
 198         unsigned long           owned_ports;            /* which ports are
 199                         owned by the companion during a bus suspend */
 200         unsigned long           port_c_suspend;         /* which ports have
 201                         the change-suspend feature turned on */
 202         unsigned long           suspended_ports;        /* which ports are
 203                         suspended */
 204         unsigned long           resuming_ports;         /* which ports have
 205                         started to resume */
 206
 207         /* per-HC memory pools (could be per-bus, but ...) */
 208         struct dma_pool         *qh_pool;       /* qh per active urb */
 209         struct dma_pool         *qtd_pool;      /* one or more per qh */
 210         struct dma_pool         *itd_pool;      /* itd per iso urb */
 211         struct dma_pool         *sitd_pool;     /* sitd per split iso urb */
 212
 213         unsigned                random_frame;
 214         unsigned long           next_statechange;
 215         ktime_t                 last_periodic_enable;
 216         u32                     command;
 217
 218         /* SILICON QUIRKS */
 219         unsigned                no_selective_suspend:1;
 220         unsigned                has_fsl_port_bug:1; /* FreeScale */
 221         unsigned                has_fsl_hs_errata:1;    /* Freescale HS quirk */
 222         unsigned                big_endian_mmio:1;
 223         unsigned                big_endian_desc:1;
 224         unsigned                big_endian_capbase:1;
 225         unsigned                has_amcc_usb23:1;
 226         unsigned                need_io_watchdog:1;
 227         unsigned                amd_pll_fix:1;
 228         unsigned                use_dummy_qh:1; /* AMD Frame List table quirk*/
 229         unsigned                has_synopsys_hc_bug:1; /* Synopsys HC */
 230         unsigned                frame_index_bug:1; /* MosChip (AKA NetMos) */
 231         unsigned                need_oc_pp_cycle:1; /* MPC834X port power */
 232         unsigned                imx28_write_fix:1; /* For Freescale i.MX28 */
 233
 234         /* required for usb32 quirk */
 235         #define OHCI_CTRL_HCFS          (3 << 6)
 236         #define OHCI_USB_OPER           (2 << 6)
 237         #define OHCI_USB_SUSPEND        (3 << 6)
 238
 239         #define OHCI_HCCTRL_OFFSET      0x4
 240         #define OHCI_HCCTRL_LEN         0x4
 241         __hc32                  *ohci_hcctrl_reg;
 242         unsigned                has_hostpc:1;
 243         unsigned                has_tdi_phy_lpm:1;
 244         unsigned                has_ppcd:1; /* support per-port change bits */
 245         u8                      sbrn;           /* packed release number */
 246
 247         /* irq statistics */
 248 #ifdef EHCI_STATS
 249         struct ehci_stats       stats;
 250 #       define COUNT(x) ((x)++)
 251 #else
 252 #       define COUNT(x)
 253 #endif
 254
 255         /* debug files */
 256 #ifdef CONFIG_DYNAMIC_DEBUG
 257         struct dentry           *debug_dir;
 258 #endif
 259
 260         /* bandwidth usage */
 261 #define EHCI_BANDWIDTH_SIZE     64
 262 #define EHCI_BANDWIDTH_FRAMES   (EHCI_BANDWIDTH_SIZE >> 3)
 263         u8                      bandwidth[EHCI_BANDWIDTH_SIZE];
 264                                                 /* us allocated per uframe */
 265         u8                      tt_budget[EHCI_BANDWIDTH_SIZE];
 266                                                 /* us budgeted per uframe */
 267         struct list_head        tt_list;
 268
 269         /* platform-specific data -- must come last */
 270         unsigned long           priv[0] __aligned(sizeof(s64));
 271 };
 272
 273 /* convert between an HCD pointer and the corresponding EHCI_HCD */
 274 static inline struct ehci_hcd *hcd_to_ehci(struct usb_hcd *hcd)
 275 {
 276         return (struct ehci_hcd *) (hcd->hcd_priv);
 277 }
 278 static inline struct usb_hcd *ehci_to_hcd(struct ehci_hcd *ehci)
 279 {
 280         return container_of((void *) ehci, struct usb_hcd, hcd_priv);
 281 }
 282
 283 /*-------------------------------------------------------------------------*/
 284
 285 #include <linux/usb/ehci_def.h>
 286
 287 /*-------------------------------------------------------------------------*/
 288
 289 #define QTD_NEXT(ehci, dma)     cpu_to_hc32(ehci, (u32)dma)
 290
 291 /*
 292  * EHCI Specification 0.95 Section 3.5
 293  * QTD: describe data transfer components (buffer, direction, ...)
 294  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
 295  *
 296  * These are associated only with "QH" (Queue Head) structures,
 297  * used with control, bulk, and interrupt transfers.
 298  */
 299 struct ehci_qtd {
 300         /* first part defined by EHCI spec */
 301         __hc32                  hw_next;        /* see EHCI 3.5.1 */
 302         __hc32                  hw_alt_next;    /* see EHCI 3.5.2 */
 303         __hc32                  hw_token;       /* see EHCI 3.5.3 */
 304 #define QTD_TOGGLE      (1 << 31)       /* data toggle */
 305 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
 306 #define QTD_IOC         (1 << 15)       /* interrupt on complete */
 307 #define QTD_CERR(tok)   (((tok)>>10) & 0x3)
 308 #define QTD_PID(tok)    (((tok)>>8) & 0x3)
 309 #define QTD_STS_ACTIVE  (1 << 7)        /* HC may execute this */
 310 #define QTD_STS_HALT    (1 << 6)        /* halted on error */
 311 #define QTD_STS_DBE     (1 << 5)        /* data buffer error (in HC) */
 312 #define QTD_STS_BABBLE  (1 << 4)        /* device was babbling (qtd halted) */
 313 #define QTD_STS_XACT    (1 << 3)        /* device gave illegal response */
 314 #define QTD_STS_MMF     (1 << 2)        /* incomplete split transaction */
 315 #define QTD_STS_STS     (1 << 1)        /* split transaction state */
 316 #define QTD_STS_PING    (1 << 0)        /* issue PING? */
 317
 318 #define ACTIVE_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_ACTIVE)
 319 #define HALT_BIT(ehci)          cpu_to_hc32(ehci, QTD_STS_HALT)
 320 #define STATUS_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_STS)
 321
 322         __hc32                  hw_buf[5];        /* see EHCI 3.5.4 */
 323         __hc32                  hw_buf_hi[5];        /* Appendix B */
 324
 325         /* the rest is HCD-private */
 326         dma_addr_t              qtd_dma;                /* qtd address */
 327         struct list_head        qtd_list;               /* sw qtd list */
 328         struct urb              *urb;                   /* qtd's urb */
 329         size_t                  length;                 /* length of buffer */
 330 } __aligned(32);
 331
 332 /* mask NakCnt+T in qh->hw_alt_next */
 333 #define QTD_MASK(ehci)  cpu_to_hc32(ehci, ~0x1f)
 334
 335 #define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1)
 336
 337 /*-------------------------------------------------------------------------*/
 338
 339 /* type tag from {qh,itd,sitd,fstn}->hw_next */
 340 #define Q_NEXT_TYPE(ehci, dma)  ((dma) & cpu_to_hc32(ehci, 3 << 1))
 341
 342 /*
 343  * Now the following defines are not converted using the
 344  * cpu_to_le32() macro anymore, since we have to support
 345  * "dynamic" switching between be and le support, so that the driver
 346  * can be used on one system with SoC EHCI controller using big-endian
 347  * descriptors as well as a normal little-endian PCI EHCI controller.
 348  */
 349 /* values for that type tag */
 350 #define Q_TYPE_ITD      (0 << 1)
 351 #define Q_TYPE_QH       (1 << 1)
 352 #define Q_TYPE_SITD     (2 << 1)
 353 #define Q_TYPE_FSTN     (3 << 1)
 354
 355 /* next async queue entry, or pointer to interrupt/periodic QH */
 356 #define QH_NEXT(ehci, dma) \
 357                 (cpu_to_hc32(ehci, (((u32) dma) & ~0x01f) | Q_TYPE_QH))
 358
 359 /* for periodic/async schedules and qtd lists, mark end of list */
 360 #define EHCI_LIST_END(ehci)     cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
 361
 362 /*
 363  * Entries in periodic shadow table are pointers to one of four kinds
 364  * of data structure.  That's dictated by the hardware; a type tag is
 365  * encoded in the low bits of the hardware's periodic schedule.  Use
 366  * Q_NEXT_TYPE to get the tag.
 367  *
 368  * For entries in the async schedule, the type tag always says "qh".
 369  */
 370 union ehci_shadow {
 371         struct ehci_qh          *qh;            /* Q_TYPE_QH */
 372         struct ehci_itd         *itd;           /* Q_TYPE_ITD */
 373         struct ehci_sitd        *sitd;          /* Q_TYPE_SITD */
 374         struct ehci_fstn        *fstn;          /* Q_TYPE_FSTN */
 375         __hc32                  *hw_next;       /* (all types) */
 376         void                    *ptr;
 377 };
 378
 379 /*-------------------------------------------------------------------------*/
 380
 381 /*
 382  * EHCI Specification 0.95 Section 3.6
 383  * QH: describes control/bulk/interrupt endpoints
 384  * See Fig 3-7 "Queue Head Structure Layout".
 385  *
 386  * These appear in both the async and (for interrupt) periodic schedules.
 387  */
 388
 389 /* first part defined by EHCI spec */
 390 struct ehci_qh_hw {
 391         __hc32                  hw_next;        /* see EHCI 3.6.1 */
 392         __hc32                  hw_info1;       /* see EHCI 3.6.2 */
 393 #define QH_CONTROL_EP   (1 << 27)       /* FS/LS control endpoint */
 394 #define QH_HEAD         (1 << 15)       /* Head of async reclamation list */
 395 #define QH_TOGGLE_CTL   (1 << 14)       /* Data toggle control */
 396 #define QH_HIGH_SPEED   (2 << 12)       /* Endpoint speed */
 397 #define QH_LOW_SPEED    (1 << 12)
 398 #define QH_FULL_SPEED   (0 << 12)
 399 #define QH_INACTIVATE   (1 << 7)        /* Inactivate on next transaction */
 400         __hc32                  hw_info2;        /* see EHCI 3.6.2 */
 401 #define QH_SMASK        0x000000ff
 402 #define QH_CMASK        0x0000ff00
 403 #define QH_HUBADDR      0x007f0000
 404 #define QH_HUBPORT      0x3f800000
 405 #define QH_MULT         0xc0000000
 406         __hc32                  hw_current;     /* qtd list - see EHCI 3.6.4 */
 407
 408         /* qtd overlay (hardware parts of a struct ehci_qtd) */
 409         __hc32                  hw_qtd_next;
 410         __hc32                  hw_alt_next;
 411         __hc32                  hw_token;
 412         __hc32                  hw_buf[5];
 413         __hc32                  hw_buf_hi[5];
 414 } __aligned(32);
 415
 416 struct ehci_qh {
 417         struct ehci_qh_hw       *hw;            /* Must come first */
 418         /* the rest is HCD-private */
 419         dma_addr_t              qh_dma;         /* address of qh */
 420         union ehci_shadow       qh_next;        /* ptr to qh; or periodic */
 421         struct list_head        qtd_list;       /* sw qtd list */
 422         struct list_head        intr_node;      /* list of intr QHs */
 423         struct ehci_qtd         *dummy;
 424         struct list_head        unlink_node;
 425         struct ehci_per_sched   ps;             /* scheduling info */
 426
 427         unsigned                unlink_cycle;
 428
 429         u8                      qh_state;
 430 #define QH_STATE_LINKED         1               /* HC sees this */
 431 #define QH_STATE_UNLINK         2               /* HC may still see this */
 432 #define QH_STATE_IDLE           3               /* HC doesn't see this */
 433 #define QH_STATE_UNLINK_WAIT    4               /* LINKED and on unlink q */
 434 #define QH_STATE_COMPLETING     5               /* don't touch token.HALT */
 435
 436         u8                      xacterrs;       /* XactErr retry counter */
 437 #define QH_XACTERR_MAX          32              /* XactErr retry limit */
 438
 439         u8                      unlink_reason;
 440 #define QH_UNLINK_HALTED        0x01            /* Halt flag is set */
 441 #define QH_UNLINK_SHORT_READ    0x02            /* Recover from a short read */
 442 #define QH_UNLINK_DUMMY_OVERLAY 0x04            /* QH overlayed the dummy TD */
 443 #define QH_UNLINK_SHUTDOWN      0x08            /* The HC isn't running */
 444 #define QH_UNLINK_QUEUE_EMPTY   0x10            /* Reached end of the queue */
 445 #define QH_UNLINK_REQUESTED     0x20            /* Disable, reset, or dequeue */
 446
 447         u8                      gap_uf;         /* uframes split/csplit gap */
 448
 449         unsigned                is_out:1;       /* bulk or intr OUT */
 450         unsigned                clearing_tt:1;  /* Clear-TT-Buf in progress */
 451         unsigned                dequeue_during_giveback:1;
 452         unsigned                should_be_inactive:1;
 453 };
 454
 455 /*-------------------------------------------------------------------------*/
 456
 457 /* description of one iso transaction (up to 3 KB data if highspeed) */
 458 struct ehci_iso_packet {
 459         /* These will be copied to iTD when scheduling */
 460         u64                     bufp;           /* itd->hw_bufp{,_hi}[pg] |= */
 461         __hc32                  transaction;    /* itd->hw_transaction[i] |= */
 462         u8                      cross;          /* buf crosses pages */
 463         /* for full speed OUT splits */
 464         u32                     buf1;
 465 };
 466
 467 /* temporary schedule data for packets from iso urbs (both speeds)
 468  * each packet is one logical usb transaction to the device (not TT),
 469  * beginning at stream->next_uframe
 470  */
 471 struct ehci_iso_sched {
 472         struct list_head        td_list;
 473         unsigned                span;
 474         unsigned                first_packet;
 475         struct ehci_iso_packet  packet[0];
 476 };
 477
 478 /*
 479  * ehci_iso_stream - groups all (s)itds for this endpoint.
 480  * acts like a qh would, if EHCI had them for ISO.
 481  */
 482 struct ehci_iso_stream {
 483         /* first field matches ehci_hq, but is NULL */
 484         struct ehci_qh_hw       *hw;
 485
 486         u8                      bEndpointAddress;
 487         u8                      highspeed;
 488         struct list_head        td_list;        /* queued itds/sitds */
 489         struct list_head        free_list;      /* list of unused itds/sitds */
 490
 491         /* output of (re)scheduling */
 492         struct ehci_per_sched   ps;             /* scheduling info */
 493         unsigned                next_uframe;
 494         __hc32                  splits;
 495
 496         /* the rest is derived from the endpoint descriptor,
 497          * including the extra info for hw_bufp[0..2]
 498          */
 499         u16                     uperiod;        /* period in uframes */
 500         u16                     maxp;
 501         unsigned                bandwidth;
 502
 503         /* This is used to initialize iTD's hw_bufp fields */
 504         __hc32                  buf0;
 505         __hc32                  buf1;
 506         __hc32                  buf2;
 507
 508         /* this is used to initialize sITD's tt info */
 509         __hc32                  address;
 510 };
 511
 512 /*-------------------------------------------------------------------------*/
 513
 514 /*
 515  * EHCI Specification 0.95 Section 3.3
 516  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
 517  *
 518  * Schedule records for high speed iso xfers
 519  */
 520 struct ehci_itd {
 521         /* first part defined by EHCI spec */
 522         __hc32                  hw_next;           /* see EHCI 3.3.1 */
 523         __hc32                  hw_transaction[8]; /* see EHCI 3.3.2 */
 524 #define EHCI_ISOC_ACTIVE        (1<<31)        /* activate transfer this slot */
 525 #define EHCI_ISOC_BUF_ERR       (1<<30)        /* Data buffer error */
 526 #define EHCI_ISOC_BABBLE        (1<<29)        /* babble detected */
 527 #define EHCI_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */
 528 #define EHCI_ITD_LENGTH(tok)    (((tok)>>16) & 0x0fff)
 529 #define EHCI_ITD_IOC            (1 << 15)       /* interrupt on complete */
 530
 531 #define ITD_ACTIVE(ehci)        cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
 532
 533         __hc32                  hw_bufp[7];     /* see EHCI 3.3.3 */
 534         __hc32                  hw_bufp_hi[7];  /* Appendix B */
 535
 536         /* the rest is HCD-private */
 537         dma_addr_t              itd_dma;        /* for this itd */
 538         union ehci_shadow       itd_next;       /* ptr to periodic q entry */
 539
 540         struct urb              *urb;
 541         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 542         struct list_head        itd_list;       /* list of stream's itds */
 543
 544         /* any/all hw_transactions here may be used by that urb */
 545         unsigned                frame;          /* where scheduled */
 546         unsigned                pg;
 547         unsigned                index[8];       /* in urb->iso_frame_desc */
 548 } __aligned(32);
 549
 550 /*-------------------------------------------------------------------------*/
 551
 552 /*
 553  * EHCI Specification 0.95 Section 3.4
 554  * siTD, aka split-transaction isochronous Transfer Descriptor
 555  *       ... describe full speed iso xfers through TT in hubs
 556  * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
 557  */
 558 struct ehci_sitd {
 559         /* first part defined by EHCI spec */
 560         __hc32                  hw_next;
 561 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
 562         __hc32                  hw_fullspeed_ep;        /* EHCI table 3-9 */
 563         __hc32                  hw_uframe;              /* EHCI table 3-10 */
 564         __hc32                  hw_results;             /* EHCI table 3-11 */
 565 #define SITD_IOC        (1 << 31)       /* interrupt on completion */
 566 #define SITD_PAGE       (1 << 30)       /* buffer 0/1 */
 567 #define SITD_LENGTH(x)  (((x) >> 16) & 0x3ff)
 568 #define SITD_STS_ACTIVE (1 << 7)        /* HC may execute this */
 569 #define SITD_STS_ERR    (1 << 6)        /* error from TT */
 570 #define SITD_STS_DBE    (1 << 5)        /* data buffer error (in HC) */
 571 #define SITD_STS_BABBLE (1 << 4)        /* device was babbling */
 572 #define SITD_STS_XACT   (1 << 3)        /* illegal IN response */
 573 #define SITD_STS_MMF    (1 << 2)        /* incomplete split transaction */
 574 #define SITD_STS_STS    (1 << 1)        /* split transaction state */
 575
 576 #define SITD_ACTIVE(ehci)       cpu_to_hc32(ehci, SITD_STS_ACTIVE)
 577
 578         __hc32                  hw_buf[2];              /* EHCI table 3-12 */
 579         __hc32                  hw_backpointer;         /* EHCI table 3-13 */
 580         __hc32                  hw_buf_hi[2];           /* Appendix B */
 581
 582         /* the rest is HCD-private */
 583         dma_addr_t              sitd_dma;
 584         union ehci_shadow       sitd_next;      /* ptr to periodic q entry */
 585
 586         struct urb              *urb;
 587         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 588         struct list_head        sitd_list;      /* list of stream's sitds */
 589         unsigned                frame;
 590         unsigned                index;
 591 } __aligned(32);
 592
 593 /*-------------------------------------------------------------------------*/
 594
 595 /*
 596  * EHCI Specification 0.96 Section 3.7
 597  * Periodic Frame Span Traversal Node (FSTN)
 598  *
 599  * Manages split interrupt transactions (using TT) that span frame boundaries
 600  * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN
 601  * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
 602  * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
 603  */
 604 struct ehci_fstn {
 605         __hc32                  hw_next;        /* any periodic q entry */
 606         __hc32                  hw_prev;        /* qh or EHCI_LIST_END */
 607
 608         /* the rest is HCD-private */
 609         dma_addr_t              fstn_dma;
 610         union ehci_shadow       fstn_next;      /* ptr to periodic q entry */
 611 } __aligned(32);
 612
 613 /*-------------------------------------------------------------------------*/
 614
 615 /*
 616  * USB-2.0 Specification Sections 11.14 and 11.18
 617  * Scheduling and budgeting split transactions using TTs
 618  *
 619  * A hub can have a single TT for all its ports, or multiple TTs (one for each
 620  * port).  The bandwidth and budgeting information for the full/low-speed bus
 621  * below each TT is self-contained and independent of the other TTs or the
 622  * high-speed bus.
 623  *
 624  * "Bandwidth" refers to the number of microseconds on the FS/LS bus allocated
 625  * to an interrupt or isochronous endpoint for each frame.  "Budget" refers to
 626  * the best-case estimate of the number of full-speed bytes allocated to an
 627  * endpoint for each microframe within an allocated frame.
 628  *
 629  * Removal of an endpoint invalidates a TT's budget.  Instead of trying to
 630  * keep an up-to-date record, we recompute the budget when it is needed.
 631  */
 632
 633 struct ehci_tt {
 634         u16                     bandwidth[EHCI_BANDWIDTH_FRAMES];
 635
 636         struct list_head        tt_list;        /* List of all ehci_tt's */
 637         struct list_head        ps_list;        /* Items using this TT */
 638         struct usb_tt           *usb_tt;
 639         int                     tt_port;        /* TT port number */
 640 };
 641
 642 /*-------------------------------------------------------------------------*/
 643
 644 /* Prepare the PORTSC wakeup flags during controller suspend/resume */
 645
 646 #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup)      \
 647                 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup)
 648
 649 #define ehci_prepare_ports_for_controller_resume(ehci)                  \
 650                 ehci_adjust_port_wakeup_flags(ehci, false, false)
 651
 652 /*-------------------------------------------------------------------------*/
 653
 654 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
 655
 656 /*
 657  * Some EHCI controllers have a Transaction Translator built into the
 658  * root hub. This is a non-standard feature.  Each controller will need
 659  * to add code to the following inline functions, and call them as
 660  * needed (mostly in root hub code).
 661  */
 662
 663 #define ehci_is_TDI(e)                  (ehci_to_hcd(e)->has_tt)
 664
 665 /* Returns the speed of a device attached to a port on the root hub. */
 666 static inline unsigned int
 667 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
 668 {
 669         if (ehci_is_TDI(ehci)) {
 670                 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
 671                 case 0:
 672                         return 0;
 673                 case 1:
 674                         return USB_PORT_STAT_LOW_SPEED;
 675                 case 2:
 676                 default:
 677                         return USB_PORT_STAT_HIGH_SPEED;
 678                 }
 679         }
 680         return USB_PORT_STAT_HIGH_SPEED;
 681 }
 682
 683 #else
 684
 685 #define ehci_is_TDI(e)                  (0)
 686
 687 #define ehci_port_speed(ehci, portsc)   USB_PORT_STAT_HIGH_SPEED
 688 #endif
 689
 690 /*-------------------------------------------------------------------------*/
 691
 692 #ifdef CONFIG_PPC_83xx
 693 /* Some Freescale processors have an erratum in which the TT
 694  * port number in the queue head was 0..N-1 instead of 1..N.
 695  */
 696 #define ehci_has_fsl_portno_bug(e)              ((e)->has_fsl_port_bug)
 697 #else
 698 #define ehci_has_fsl_portno_bug(e)              (0)
 699 #endif
 700
 701 #define PORTSC_FSL_PFSC 24      /* Port Force Full-Speed Connect */
 702
 703 #if defined(CONFIG_PPC_85xx)
 704 /* Some Freescale processors have an erratum (USB A-005275) in which
 705  * incoming packets get corrupted in HS mode
 706  */
 707 #define ehci_has_fsl_hs_errata(e)       ((e)->has_fsl_hs_errata)
 708 #else
 709 #define ehci_has_fsl_hs_errata(e)       (0)
 710 #endif
 711
 712 /*
 713  * While most USB host controllers implement their registers in
 714  * little-endian format, a minority (celleb companion chip) implement
 715  * them in big endian format.
 716  *
 717  * This attempts to support either format at compile time without a
 718  * runtime penalty, or both formats with the additional overhead
 719  * of checking a flag bit.
 720  *
 721  * ehci_big_endian_capbase is a special quirk for controllers that
 722  * implement the HC capability registers as separate registers and not
 723  * as fields of a 32-bit register.
 724  */
 725
 726 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 727 #define ehci_big_endian_mmio(e)         ((e)->big_endian_mmio)
 728 #define ehci_big_endian_capbase(e)      ((e)->big_endian_capbase)
 729 #else
 730 #define ehci_big_endian_mmio(e)         0
 731 #define ehci_big_endian_capbase(e)      0
 732 #endif
 733
 734 /*
 735  * Big-endian read/write functions are arch-specific.
 736  * Other arches can be added if/when they're needed.
 737  */
 738 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
 739 #define readl_be(addr)          __raw_readl((__force unsigned *)addr)
 740 #define writel_be(val, addr)    __raw_writel(val, (__force unsigned *)addr)
 741 #endif
 742
 743 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
 744                 __u32 __iomem *regs)
 745 {
 746 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 747         return ehci_big_endian_mmio(ehci) ?
 748                 readl_be(regs) :
 749                 readl(regs);
 750 #else
 751         return readl(regs);
 752 #endif
 753 }
 754
 755 #ifdef CONFIG_SOC_IMX28
 756 static inline void imx28_ehci_writel(const unsigned int val,
 757                 volatile __u32 __iomem *addr)
 758 {
 759         __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
 760 }
 761 #else
 762 static inline void imx28_ehci_writel(const unsigned int val,
 763                 volatile __u32 __iomem *addr)
 764 {
 765 }
 766 #endif
 767 static inline void ehci_writel(const struct ehci_hcd *ehci,
 768                 const unsigned int val, __u32 __iomem *regs)
 769 {
 770 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 771         ehci_big_endian_mmio(ehci) ?
 772                 writel_be(val, regs) :
 773                 writel(val, regs);
 774 #else
 775         if (ehci->imx28_write_fix)
 776                 imx28_ehci_writel(val, regs);
 777         else
 778                 writel(val, regs);
 779 #endif
 780 }
 781
 782 /*
 783  * On certain ppc-44x SoC there is a HW issue, that could only worked around with
 784  * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch.
 785  * Other common bits are dependent on has_amcc_usb23 quirk flag.
 786  */
 787 #ifdef CONFIG_44x
 788 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
 789 {
 790         u32 hc_control;
 791
 792         hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
 793         if (operational)
 794                 hc_control |= OHCI_USB_OPER;
 795         else
 796                 hc_control |= OHCI_USB_SUSPEND;
 797
 798         writel_be(hc_control, ehci->ohci_hcctrl_reg);
 799         (void) readl_be(ehci->ohci_hcctrl_reg);
 800 }
 801 #else
 802 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
 803 { }
 804 #endif
 805
 806 /*-------------------------------------------------------------------------*/
 807
 808 /*
 809  * The AMCC 440EPx not only implements its EHCI registers in big-endian
 810  * format, but also its DMA data structures (descriptors).
 811  *
 812  * EHCI controllers accessed through PCI work normally (little-endian
 813  * everywhere), so we won't bother supporting a BE-only mode for now.
 814  */
 815 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
 816 #define ehci_big_endian_desc(e)         ((e)->big_endian_desc)
 817
 818 /* cpu to ehci */
 819 static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x)
 820 {
 821         return ehci_big_endian_desc(ehci)
 822                 ? (__force __hc32)cpu_to_be32(x)
 823                 : (__force __hc32)cpu_to_le32(x);
 824 }
 825
 826 /* ehci to cpu */
 827 static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x)
 828 {
 829         return ehci_big_endian_desc(ehci)
 830                 ? be32_to_cpu((__force __be32)x)
 831                 : le32_to_cpu((__force __le32)x);
 832 }
 833
 834 static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x)
 835 {
 836         return ehci_big_endian_desc(ehci)
 837                 ? be32_to_cpup((__force __be32 *)x)
 838                 : le32_to_cpup((__force __le32 *)x);
 839 }
 840
 841 #else
 842
 843 /* cpu to ehci */
 844 static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x)
 845 {
 846         return cpu_to_le32(x);
 847 }
 848
 849 /* ehci to cpu */
 850 static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x)
 851 {
 852         return le32_to_cpu(x);
 853 }
 854
 855 static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x)
 856 {
 857         return le32_to_cpup(x);
 858 }
 859
 860 #endif
 861
 862 /*-------------------------------------------------------------------------*/
 863
 864 #define ehci_dbg(ehci, fmt, args...) \
 865         dev_dbg(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
 866 #define ehci_err(ehci, fmt, args...) \
 867         dev_err(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
 868 #define ehci_info(ehci, fmt, args...) \
 869         dev_info(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
 870 #define ehci_warn(ehci, fmt, args...) \
 871         dev_warn(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
 872
 873 /*-------------------------------------------------------------------------*/
 874
 875 /* Declarations of things exported for use by ehci platform drivers */
 876
 877 struct ehci_driver_overrides {
 878         size_t          extra_priv_size;
 879         int             (*reset)(struct usb_hcd *hcd);
 880         int             (*port_power)(struct usb_hcd *hcd,
 881                                 int portnum, bool enable);
 882 };
 883
 884 extern void     ehci_init_driver(struct hc_driver *drv,
 885                                 const struct ehci_driver_overrides *over);
 886 extern int      ehci_setup(struct usb_hcd *hcd);
 887 extern int      ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr,
 888                                 u32 mask, u32 done, int usec);
 889 extern int      ehci_reset(struct ehci_hcd *ehci);
 890
 891 extern int      ehci_suspend(struct usb_hcd *hcd, bool do_wakeup);
 892 extern int      ehci_resume(struct usb_hcd *hcd, bool force_reset);
 893 extern void     ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci,
 894                         bool suspending, bool do_wakeup);
 895
 896 extern int      ehci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
 897                                  u16 wIndex, char *buf, u16 wLength);
 898
 899 #endif /* __LINUX_EHCI_HCD_H */