drivers/usb/host/ehci.h

   1 /*
   2  * Copyright (c) 2001-2002 by David Brownell
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the
   6  * Free Software Foundation; either version 2 of the License, or (at your
   7  * option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software Foundation,
  16  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17  */
  18
  19 #ifndef __LINUX_EHCI_HCD_H
  20 #define __LINUX_EHCI_HCD_H
  21
  22 /* definitions used for the EHCI driver */
  23
  24 /*
  25  * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
  26  * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
  27  * the host controller implementation.
  28  *
  29  * To facilitate the strongest possible byte-order checking from "sparse"
  30  * and so on, we use __leXX unless that's not practical.
  31  */
  32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
  33 typedef __u32 __bitwise __hc32;
  34 typedef __u16 __bitwise __hc16;
  35 #else
  36 #define __hc32  __le32
  37 #define __hc16  __le16
  38 #endif
  39
  40 /* statistics can be kept for for tuning/monitoring */
  41 struct ehci_stats {
  42         /* irq usage */
  43         unsigned long           normal;
  44         unsigned long           error;
  45         unsigned long           reclaim;
  46         unsigned long           lost_iaa;
  47
  48         /* termination of urbs from core */
  49         unsigned long           complete;
  50         unsigned long           unlink;
  51 };
  52
  53 /* ehci_hcd->lock guards shared data against other CPUs:
  54  *   ehci_hcd:  async, reclaim, periodic (and shadow), ...
  55  *   usb_host_endpoint: hcpriv
  56  *   ehci_qh:   qh_next, qtd_list
  57  *   ehci_qtd:  qtd_list
  58  *
  59  * Also, hold this lock when talking to HC registers or
  60  * when updating hw_* fields in shared qh/qtd/... structures.
  61  */
  62
  63 #define EHCI_MAX_ROOT_PORTS     15              /* see HCS_N_PORTS */
  64
  65 struct ehci_hcd {                       /* one per controller */
  66         /* glue to PCI and HCD framework */
  67         struct ehci_caps __iomem *caps;
  68         struct ehci_regs __iomem *regs;
  69         struct ehci_dbg_port __iomem *debug;
  70
  71         __u32                   hcs_params;     /* cached register copy */
  72         spinlock_t              lock;
  73
  74         /* async schedule support */
  75         struct ehci_qh          *async;
  76         struct ehci_qh          *reclaim;
  77         unsigned                scanning : 1;
  78
  79         /* periodic schedule support */
  80 #define DEFAULT_I_TDPS          1024            /* some HCs can do less */
  81         unsigned                periodic_size;
  82         __hc32                  *periodic;      /* hw periodic table */
  83         dma_addr_t              periodic_dma;
  84         unsigned                i_thresh;       /* uframes HC might cache */
  85
  86         union ehci_shadow       *pshadow;       /* mirror hw periodic table */
  87         int                     next_uframe;    /* scan periodic, start here */
  88         unsigned                periodic_sched; /* periodic activity count */
  89
  90         /* per root hub port */
  91         unsigned long           reset_done [EHCI_MAX_ROOT_PORTS];
  92
  93         /* bit vectors (one bit per port) */
  94         unsigned long           bus_suspended;          /* which ports were
  95                         already suspended at the start of a bus suspend */
  96         unsigned long           companion_ports;        /* which ports are
  97                         dedicated to the companion controller */
  98         unsigned long           owned_ports;            /* which ports are
  99                         owned by the companion during a bus suspend */
 100         unsigned long           port_c_suspend;         /* which ports have
 101                         the change-suspend feature turned on */
 102         unsigned long           suspended_ports;        /* which ports are
 103                         suspended */
 104
 105         /* per-HC memory pools (could be per-bus, but ...) */
 106         struct dma_pool         *qh_pool;       /* qh per active urb */
 107         struct dma_pool         *qtd_pool;      /* one or more per qh */
 108         struct dma_pool         *itd_pool;      /* itd per iso urb */
 109         struct dma_pool         *sitd_pool;     /* sitd per split iso urb */
 110
 111         struct timer_list       iaa_watchdog;
 112         struct timer_list       watchdog;
 113         unsigned long           actions;
 114         unsigned                stamp;
 115         unsigned long           next_statechange;
 116         u32                     command;
 117
 118         /* SILICON QUIRKS */
 119         unsigned                no_selective_suspend:1;
 120         unsigned                has_fsl_port_bug:1; /* FreeScale */
 121         unsigned                big_endian_mmio:1;
 122         unsigned                big_endian_desc:1;
 123
 124         u8                      sbrn;           /* packed release number */
 125
 126         /* irq statistics */
 127 #ifdef EHCI_STATS
 128         struct ehci_stats       stats;
 129 #       define COUNT(x) do { (x)++; } while (0)
 130 #else
 131 #       define COUNT(x) do {} while (0)
 132 #endif
 133
 134         /* debug files */
 135 #ifdef DEBUG
 136         struct dentry           *debug_dir;
 137         struct dentry           *debug_async;
 138         struct dentry           *debug_periodic;
 139         struct dentry           *debug_registers;
 140 #endif
 141 };
 142
 143 /* convert between an HCD pointer and the corresponding EHCI_HCD */
 144 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
 145 {
 146         return (struct ehci_hcd *) (hcd->hcd_priv);
 147 }
 148 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
 149 {
 150         return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
 151 }
 152
 153
 154 static inline void
 155 iaa_watchdog_start(struct ehci_hcd *ehci)
 156 {
 157         WARN_ON(timer_pending(&ehci->iaa_watchdog));
 158         mod_timer(&ehci->iaa_watchdog,
 159                         jiffies + msecs_to_jiffies(EHCI_IAA_MSECS));
 160 }
 161
 162 static inline void iaa_watchdog_done(struct ehci_hcd *ehci)
 163 {
 164         del_timer(&ehci->iaa_watchdog);
 165 }
 166
 167 enum ehci_timer_action {
 168         TIMER_IO_WATCHDOG,
 169         TIMER_ASYNC_SHRINK,
 170         TIMER_ASYNC_OFF,
 171 };
 172
 173 static inline void
 174 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
 175 {
 176         clear_bit (action, &ehci->actions);
 177 }
 178
 179 static inline void
 180 timer_action (struct ehci_hcd *ehci, enum ehci_timer_action action)
 181 {
 182         /* Don't override timeouts which shrink or (later) disable
 183          * the async ring; just the I/O watchdog.  Note that if a
 184          * SHRINK were pending, OFF would never be requested.
 185          */
 186         if (timer_pending(&ehci->watchdog)
 187                         && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF))
 188                                 & ehci->actions))
 189                 return;
 190
 191         if (!test_and_set_bit (action, &ehci->actions)) {
 192                 unsigned long t;
 193
 194                 switch (action) {
 195                 case TIMER_IO_WATCHDOG:
 196                         t = EHCI_IO_JIFFIES;
 197                         break;
 198                 case TIMER_ASYNC_OFF:
 199                         t = EHCI_ASYNC_JIFFIES;
 200                         break;
 201                 // case TIMER_ASYNC_SHRINK:
 202                 default:
 203                         /* add a jiffie since we synch against the
 204                          * 8 KHz uframe counter.
 205                          */
 206                         t = DIV_ROUND_UP(EHCI_SHRINK_FRAMES * HZ, 1000) + 1;
 207                         break;
 208                 }
 209                 mod_timer(&ehci->watchdog, t + jiffies);
 210         }
 211 }
 212
 213 /*-------------------------------------------------------------------------*/
 214
 215 #include <linux/usb/ehci_def.h>
 216
 217 /*-------------------------------------------------------------------------*/
 218
 219 #define QTD_NEXT(ehci, dma)     cpu_to_hc32(ehci, (u32)dma)
 220
 221 /*
 222  * EHCI Specification 0.95 Section 3.5
 223  * QTD: describe data transfer components (buffer, direction, ...)
 224  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
 225  *
 226  * These are associated only with "QH" (Queue Head) structures,
 227  * used with control, bulk, and interrupt transfers.
 228  */
 229 struct ehci_qtd {
 230         /* first part defined by EHCI spec */
 231         __hc32                  hw_next;        /* see EHCI 3.5.1 */
 232         __hc32                  hw_alt_next;    /* see EHCI 3.5.2 */
 233         __hc32                  hw_token;       /* see EHCI 3.5.3 */
 234 #define QTD_TOGGLE      (1 << 31)       /* data toggle */
 235 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
 236 #define QTD_IOC         (1 << 15)       /* interrupt on complete */
 237 #define QTD_CERR(tok)   (((tok)>>10) & 0x3)
 238 #define QTD_PID(tok)    (((tok)>>8) & 0x3)
 239 #define QTD_STS_ACTIVE  (1 << 7)        /* HC may execute this */
 240 #define QTD_STS_HALT    (1 << 6)        /* halted on error */
 241 #define QTD_STS_DBE     (1 << 5)        /* data buffer error (in HC) */
 242 #define QTD_STS_BABBLE  (1 << 4)        /* device was babbling (qtd halted) */
 243 #define QTD_STS_XACT    (1 << 3)        /* device gave illegal response */
 244 #define QTD_STS_MMF     (1 << 2)        /* incomplete split transaction */
 245 #define QTD_STS_STS     (1 << 1)        /* split transaction state */
 246 #define QTD_STS_PING    (1 << 0)        /* issue PING? */
 247
 248 #define ACTIVE_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_ACTIVE)
 249 #define HALT_BIT(ehci)          cpu_to_hc32(ehci, QTD_STS_HALT)
 250 #define STATUS_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_STS)
 251
 252         __hc32                  hw_buf [5];        /* see EHCI 3.5.4 */
 253         __hc32                  hw_buf_hi [5];        /* Appendix B */
 254
 255         /* the rest is HCD-private */
 256         dma_addr_t              qtd_dma;                /* qtd address */
 257         struct list_head        qtd_list;               /* sw qtd list */
 258         struct urb              *urb;                   /* qtd's urb */
 259         size_t                  length;                 /* length of buffer */
 260 } __attribute__ ((aligned (32)));
 261
 262 /* mask NakCnt+T in qh->hw_alt_next */
 263 #define QTD_MASK(ehci)  cpu_to_hc32 (ehci, ~0x1f)
 264
 265 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
 266
 267 /*-------------------------------------------------------------------------*/
 268
 269 /* type tag from {qh,itd,sitd,fstn}->hw_next */
 270 #define Q_NEXT_TYPE(ehci,dma)   ((dma) & cpu_to_hc32(ehci, 3 << 1))
 271
 272 /*
 273  * Now the following defines are not converted using the
 274  * __constant_cpu_to_le32() macro anymore, since we have to support
 275  * "dynamic" switching between be and le support, so that the driver
 276  * can be used on one system with SoC EHCI controller using big-endian
 277  * descriptors as well as a normal little-endian PCI EHCI controller.
 278  */
 279 /* values for that type tag */
 280 #define Q_TYPE_ITD      (0 << 1)
 281 #define Q_TYPE_QH       (1 << 1)
 282 #define Q_TYPE_SITD     (2 << 1)
 283 #define Q_TYPE_FSTN     (3 << 1)
 284
 285 /* next async queue entry, or pointer to interrupt/periodic QH */
 286 #define QH_NEXT(ehci,dma)       (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
 287
 288 /* for periodic/async schedules and qtd lists, mark end of list */
 289 #define EHCI_LIST_END(ehci)     cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
 290
 291 /*
 292  * Entries in periodic shadow table are pointers to one of four kinds
 293  * of data structure.  That's dictated by the hardware; a type tag is
 294  * encoded in the low bits of the hardware's periodic schedule.  Use
 295  * Q_NEXT_TYPE to get the tag.
 296  *
 297  * For entries in the async schedule, the type tag always says "qh".
 298  */
 299 union ehci_shadow {
 300         struct ehci_qh          *qh;            /* Q_TYPE_QH */
 301         struct ehci_itd         *itd;           /* Q_TYPE_ITD */
 302         struct ehci_sitd        *sitd;          /* Q_TYPE_SITD */
 303         struct ehci_fstn        *fstn;          /* Q_TYPE_FSTN */
 304         __hc32                  *hw_next;       /* (all types) */
 305         void                    *ptr;
 306 };
 307
 308 /*-------------------------------------------------------------------------*/
 309
 310 /*
 311  * EHCI Specification 0.95 Section 3.6
 312  * QH: describes control/bulk/interrupt endpoints
 313  * See Fig 3-7 "Queue Head Structure Layout".
 314  *
 315  * These appear in both the async and (for interrupt) periodic schedules.
 316  */
 317
 318 struct ehci_qh {
 319         /* first part defined by EHCI spec */
 320         __hc32                  hw_next;        /* see EHCI 3.6.1 */
 321         __hc32                  hw_info1;       /* see EHCI 3.6.2 */
 322 #define QH_HEAD         0x00008000
 323         __hc32                  hw_info2;        /* see EHCI 3.6.2 */
 324 #define QH_SMASK        0x000000ff
 325 #define QH_CMASK        0x0000ff00
 326 #define QH_HUBADDR      0x007f0000
 327 #define QH_HUBPORT      0x3f800000
 328 #define QH_MULT         0xc0000000
 329         __hc32                  hw_current;     /* qtd list - see EHCI 3.6.4 */
 330
 331         /* qtd overlay (hardware parts of a struct ehci_qtd) */
 332         __hc32                  hw_qtd_next;
 333         __hc32                  hw_alt_next;
 334         __hc32                  hw_token;
 335         __hc32                  hw_buf [5];
 336         __hc32                  hw_buf_hi [5];
 337
 338         /* the rest is HCD-private */
 339         dma_addr_t              qh_dma;         /* address of qh */
 340         union ehci_shadow       qh_next;        /* ptr to qh; or periodic */
 341         struct list_head        qtd_list;       /* sw qtd list */
 342         struct ehci_qtd         *dummy;
 343         struct ehci_qh          *reclaim;       /* next to reclaim */
 344
 345         struct ehci_hcd         *ehci;
 346
 347         /*
 348          * Do NOT use atomic operations for QH refcounting. On some CPUs
 349          * (PPC7448 for example), atomic operations cannot be performed on
 350          * memory that is cache-inhibited (i.e. being used for DMA).
 351          * Spinlocks are used to protect all QH fields.
 352          */
 353         u32                     refcount;
 354         unsigned                stamp;
 355
 356         u8                      qh_state;
 357 #define QH_STATE_LINKED         1               /* HC sees this */
 358 #define QH_STATE_UNLINK         2               /* HC may still see this */
 359 #define QH_STATE_IDLE           3               /* HC doesn't see this */
 360 #define QH_STATE_UNLINK_WAIT    4               /* LINKED and on reclaim q */
 361 #define QH_STATE_COMPLETING     5               /* don't touch token.HALT */
 362
 363         /* periodic schedule info */
 364         u8                      usecs;          /* intr bandwidth */
 365         u8                      gap_uf;         /* uframes split/csplit gap */
 366         u8                      c_usecs;        /* ... split completion bw */
 367         u16                     tt_usecs;       /* tt downstream bandwidth */
 368         unsigned short          period;         /* polling interval */
 369         unsigned short          start;          /* where polling starts */
 370 #define NO_FRAME ((unsigned short)~0)                   /* pick new start */
 371         struct usb_device       *dev;           /* access to TT */
 372 } __attribute__ ((aligned (32)));
 373
 374 /*-------------------------------------------------------------------------*/
 375
 376 /* description of one iso transaction (up to 3 KB data if highspeed) */
 377 struct ehci_iso_packet {
 378         /* These will be copied to iTD when scheduling */
 379         u64                     bufp;           /* itd->hw_bufp{,_hi}[pg] |= */
 380         __hc32                  transaction;    /* itd->hw_transaction[i] |= */
 381         u8                      cross;          /* buf crosses pages */
 382         /* for full speed OUT splits */
 383         u32                     buf1;
 384 };
 385
 386 /* temporary schedule data for packets from iso urbs (both speeds)
 387  * each packet is one logical usb transaction to the device (not TT),
 388  * beginning at stream->next_uframe
 389  */
 390 struct ehci_iso_sched {
 391         struct list_head        td_list;
 392         unsigned                span;
 393         struct ehci_iso_packet  packet [0];
 394 };
 395
 396 /*
 397  * ehci_iso_stream - groups all (s)itds for this endpoint.
 398  * acts like a qh would, if EHCI had them for ISO.
 399  */
 400 struct ehci_iso_stream {
 401         /* first two fields match QH, but info1 == 0 */
 402         __hc32                  hw_next;
 403         __hc32                  hw_info1;
 404
 405         u32                     refcount;
 406         u8                      bEndpointAddress;
 407         u8                      highspeed;
 408         u16                     depth;          /* depth in uframes */
 409         struct list_head        td_list;        /* queued itds/sitds */
 410         struct list_head        free_list;      /* list of unused itds/sitds */
 411         struct usb_device       *udev;
 412         struct usb_host_endpoint *ep;
 413
 414         /* output of (re)scheduling */
 415         unsigned long           start;          /* jiffies */
 416         unsigned long           rescheduled;
 417         int                     next_uframe;
 418         __hc32                  splits;
 419
 420         /* the rest is derived from the endpoint descriptor,
 421          * trusting urb->interval == f(epdesc->bInterval) and
 422          * including the extra info for hw_bufp[0..2]
 423          */
 424         u8                      usecs, c_usecs;
 425         u16                     interval;
 426         u16                     tt_usecs;
 427         u16                     maxp;
 428         u16                     raw_mask;
 429         unsigned                bandwidth;
 430
 431         /* This is used to initialize iTD's hw_bufp fields */
 432         __hc32                  buf0;
 433         __hc32                  buf1;
 434         __hc32                  buf2;
 435
 436         /* this is used to initialize sITD's tt info */
 437         __hc32                  address;
 438 };
 439
 440 /*-------------------------------------------------------------------------*/
 441
 442 /*
 443  * EHCI Specification 0.95 Section 3.3
 444  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
 445  *
 446  * Schedule records for high speed iso xfers
 447  */
 448 struct ehci_itd {
 449         /* first part defined by EHCI spec */
 450         __hc32                  hw_next;           /* see EHCI 3.3.1 */
 451         __hc32                  hw_transaction [8]; /* see EHCI 3.3.2 */
 452 #define EHCI_ISOC_ACTIVE        (1<<31)        /* activate transfer this slot */
 453 #define EHCI_ISOC_BUF_ERR       (1<<30)        /* Data buffer error */
 454 #define EHCI_ISOC_BABBLE        (1<<29)        /* babble detected */
 455 #define EHCI_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */
 456 #define EHCI_ITD_LENGTH(tok)    (((tok)>>16) & 0x0fff)
 457 #define EHCI_ITD_IOC            (1 << 15)       /* interrupt on complete */
 458
 459 #define ITD_ACTIVE(ehci)        cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
 460
 461         __hc32                  hw_bufp [7];    /* see EHCI 3.3.3 */
 462         __hc32                  hw_bufp_hi [7]; /* Appendix B */
 463
 464         /* the rest is HCD-private */
 465         dma_addr_t              itd_dma;        /* for this itd */
 466         union ehci_shadow       itd_next;       /* ptr to periodic q entry */
 467
 468         struct urb              *urb;
 469         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 470         struct list_head        itd_list;       /* list of stream's itds */
 471
 472         /* any/all hw_transactions here may be used by that urb */
 473         unsigned                frame;          /* where scheduled */
 474         unsigned                pg;
 475         unsigned                index[8];       /* in urb->iso_frame_desc */
 476 } __attribute__ ((aligned (32)));
 477
 478 /*-------------------------------------------------------------------------*/
 479
 480 /*
 481  * EHCI Specification 0.95 Section 3.4
 482  * siTD, aka split-transaction isochronous Transfer Descriptor
 483  *       ... describe full speed iso xfers through TT in hubs
 484  * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
 485  */
 486 struct ehci_sitd {
 487         /* first part defined by EHCI spec */
 488         __hc32                  hw_next;
 489 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
 490         __hc32                  hw_fullspeed_ep;        /* EHCI table 3-9 */
 491         __hc32                  hw_uframe;              /* EHCI table 3-10 */
 492         __hc32                  hw_results;             /* EHCI table 3-11 */
 493 #define SITD_IOC        (1 << 31)       /* interrupt on completion */
 494 #define SITD_PAGE       (1 << 30)       /* buffer 0/1 */
 495 #define SITD_LENGTH(x)  (0x3ff & ((x)>>16))
 496 #define SITD_STS_ACTIVE (1 << 7)        /* HC may execute this */
 497 #define SITD_STS_ERR    (1 << 6)        /* error from TT */
 498 #define SITD_STS_DBE    (1 << 5)        /* data buffer error (in HC) */
 499 #define SITD_STS_BABBLE (1 << 4)        /* device was babbling */
 500 #define SITD_STS_XACT   (1 << 3)        /* illegal IN response */
 501 #define SITD_STS_MMF    (1 << 2)        /* incomplete split transaction */
 502 #define SITD_STS_STS    (1 << 1)        /* split transaction state */
 503
 504 #define SITD_ACTIVE(ehci)       cpu_to_hc32(ehci, SITD_STS_ACTIVE)
 505
 506         __hc32                  hw_buf [2];             /* EHCI table 3-12 */
 507         __hc32                  hw_backpointer;         /* EHCI table 3-13 */
 508         __hc32                  hw_buf_hi [2];          /* Appendix B */
 509
 510         /* the rest is HCD-private */
 511         dma_addr_t              sitd_dma;
 512         union ehci_shadow       sitd_next;      /* ptr to periodic q entry */
 513
 514         struct urb              *urb;
 515         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 516         struct list_head        sitd_list;      /* list of stream's sitds */
 517         unsigned                frame;
 518         unsigned                index;
 519 } __attribute__ ((aligned (32)));
 520
 521 /*-------------------------------------------------------------------------*/
 522
 523 /*
 524  * EHCI Specification 0.96 Section 3.7
 525  * Periodic Frame Span Traversal Node (FSTN)
 526  *
 527  * Manages split interrupt transactions (using TT) that span frame boundaries
 528  * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN
 529  * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
 530  * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
 531  */
 532 struct ehci_fstn {
 533         __hc32                  hw_next;        /* any periodic q entry */
 534         __hc32                  hw_prev;        /* qh or EHCI_LIST_END */
 535
 536         /* the rest is HCD-private */
 537         dma_addr_t              fstn_dma;
 538         union ehci_shadow       fstn_next;      /* ptr to periodic q entry */
 539 } __attribute__ ((aligned (32)));
 540
 541 /*-------------------------------------------------------------------------*/
 542
 543 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
 544
 545 /*
 546  * Some EHCI controllers have a Transaction Translator built into the
 547  * root hub. This is a non-standard feature.  Each controller will need
 548  * to add code to the following inline functions, and call them as
 549  * needed (mostly in root hub code).
 550  */
 551
 552 #define ehci_is_TDI(e)                  (ehci_to_hcd(e)->has_tt)
 553
 554 /* Returns the speed of a device attached to a port on the root hub. */
 555 static inline unsigned int
 556 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
 557 {
 558         if (ehci_is_TDI(ehci)) {
 559                 switch ((portsc>>26)&3) {
 560                 case 0:
 561                         return 0;
 562                 case 1:
 563                         return (1<<USB_PORT_FEAT_LOWSPEED);
 564                 case 2:
 565                 default:
 566                         return (1<<USB_PORT_FEAT_HIGHSPEED);
 567                 }
 568         }
 569         return (1<<USB_PORT_FEAT_HIGHSPEED);
 570 }
 571
 572 #else
 573
 574 #define ehci_is_TDI(e)                  (0)
 575
 576 #define ehci_port_speed(ehci, portsc)   (1<<USB_PORT_FEAT_HIGHSPEED)
 577 #endif
 578
 579 /*-------------------------------------------------------------------------*/
 580
 581 #ifdef CONFIG_PPC_83xx
 582 /* Some Freescale processors have an erratum in which the TT
 583  * port number in the queue head was 0..N-1 instead of 1..N.
 584  */
 585 #define ehci_has_fsl_portno_bug(e)              ((e)->has_fsl_port_bug)
 586 #else
 587 #define ehci_has_fsl_portno_bug(e)              (0)
 588 #endif
 589
 590 /*
 591  * While most USB host controllers implement their registers in
 592  * little-endian format, a minority (celleb companion chip) implement
 593  * them in big endian format.
 594  *
 595  * This attempts to support either format at compile time without a
 596  * runtime penalty, or both formats with the additional overhead
 597  * of checking a flag bit.
 598  */
 599
 600 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 601 #define ehci_big_endian_mmio(e)         ((e)->big_endian_mmio)
 602 #else
 603 #define ehci_big_endian_mmio(e)         0
 604 #endif
 605
 606 /*
 607  * Big-endian read/write functions are arch-specific.
 608  * Other arches can be added if/when they're needed.
 609  */
 610 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
 611 #define readl_be(addr)          __raw_readl((__force unsigned *)addr)
 612 #define writel_be(val, addr)    __raw_writel(val, (__force unsigned *)addr)
 613 #endif
 614
 615 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
 616                 __u32 __iomem * regs)
 617 {
 618 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 619         return ehci_big_endian_mmio(ehci) ?
 620                 readl_be(regs) :
 621                 readl(regs);
 622 #else
 623         return readl(regs);
 624 #endif
 625 }
 626
 627 static inline void ehci_writel(const struct ehci_hcd *ehci,
 628                 const unsigned int val, __u32 __iomem *regs)
 629 {
 630 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 631         ehci_big_endian_mmio(ehci) ?
 632                 writel_be(val, regs) :
 633                 writel(val, regs);
 634 #else
 635         writel(val, regs);
 636 #endif
 637 }
 638
 639 /*-------------------------------------------------------------------------*/
 640
 641 /*
 642  * The AMCC 440EPx not only implements its EHCI registers in big-endian
 643  * format, but also its DMA data structures (descriptors).
 644  *
 645  * EHCI controllers accessed through PCI work normally (little-endian
 646  * everywhere), so we won't bother supporting a BE-only mode for now.
 647  */
 648 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
 649 #define ehci_big_endian_desc(e)         ((e)->big_endian_desc)
 650
 651 /* cpu to ehci */
 652 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
 653 {
 654         return ehci_big_endian_desc(ehci)
 655                 ? (__force __hc32)cpu_to_be32(x)
 656                 : (__force __hc32)cpu_to_le32(x);
 657 }
 658
 659 /* ehci to cpu */
 660 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
 661 {
 662         return ehci_big_endian_desc(ehci)
 663                 ? be32_to_cpu((__force __be32)x)
 664                 : le32_to_cpu((__force __le32)x);
 665 }
 666
 667 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
 668 {
 669         return ehci_big_endian_desc(ehci)
 670                 ? be32_to_cpup((__force __be32 *)x)
 671                 : le32_to_cpup((__force __le32 *)x);
 672 }
 673
 674 #else
 675
 676 /* cpu to ehci */
 677 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
 678 {
 679         return cpu_to_le32(x);
 680 }
 681
 682 /* ehci to cpu */
 683 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
 684 {
 685         return le32_to_cpu(x);
 686 }
 687
 688 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
 689 {
 690         return le32_to_cpup(x);
 691 }
 692
 693 #endif
 694
 695 /*-------------------------------------------------------------------------*/
 696
 697 #ifndef DEBUG
 698 #define STUB_DEBUG_FILES
 699 #endif  /* DEBUG */
 700
 701 /*-------------------------------------------------------------------------*/
 702
 703 #endif /* __LINUX_EHCI_HCD_H */