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1 // SPDX-License-Identifier: GPL-1.0+
3 * Open Host Controller Interface (OHCI) driver for USB.
5 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
7 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
8 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
10 * [ Initialisation is based on Linus' ]
11 * [ uhci code and gregs ohci fragments ]
12 * [ (C) Copyright 1999 Linus Torvalds ]
13 * [ (C) Copyright 1999 Gregory P. Smith]
16 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
17 * interfaces (though some non-x86 Intel chips use it). It supports
18 * smarter hardware than UHCI. A download link for the spec available
19 * through the http://www.usb.org website.
21 * This file is licenced under the GPL.
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/pci.h>
27 #include <linux/kernel.h>
28 #include <linux/delay.h>
29 #include <linux/ioport.h>
30 #include <linux/sched.h>
31 #include <linux/slab.h>
32 #include <linux/errno.h>
33 #include <linux/init.h>
34 #include <linux/timer.h>
35 #include <linux/list.h>
36 #include <linux/usb.h>
37 #include <linux/usb/otg.h>
38 #include <linux/usb/hcd.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/dmapool.h>
41 #include <linux/workqueue.h>
42 #include <linux/debugfs.h>
46 #include <asm/unaligned.h>
47 #include <asm/byteorder.h>
50 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
51 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
53 /*-------------------------------------------------------------------------*/
55 /* For initializing controller (mask in an HCFS mode too) */
56 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
57 #define OHCI_INTR_INIT \
58 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
59 | OHCI_INTR_RD | OHCI_INTR_WDH)
62 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
66 #ifdef CONFIG_ARCH_OMAP
67 /* OMAP doesn't support IR (no SMM; not needed) */
71 /*-------------------------------------------------------------------------*/
73 static const char hcd_name
[] = "ohci_hcd";
75 #define STATECHANGE_DELAY msecs_to_jiffies(300)
76 #define IO_WATCHDOG_DELAY msecs_to_jiffies(275)
77 #define IO_WATCHDOG_OFF 0xffffff00
80 #include "pci-quirks.h"
82 static void ohci_dump(struct ohci_hcd
*ohci
);
83 static void ohci_stop(struct usb_hcd
*hcd
);
84 static void io_watchdog_func(struct timer_list
*t
);
93 * On architectures with edge-triggered interrupts we must never return
96 #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */
97 #define IRQ_NOTMINE IRQ_HANDLED
99 #define IRQ_NOTMINE IRQ_NONE
103 /* Some boards misreport power switching/overcurrent */
104 static bool distrust_firmware
= true;
105 module_param (distrust_firmware
, bool, 0);
106 MODULE_PARM_DESC (distrust_firmware
,
107 "true to distrust firmware power/overcurrent setup");
109 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
110 static bool no_handshake
;
111 module_param (no_handshake
, bool, 0);
112 MODULE_PARM_DESC (no_handshake
, "true (not default) disables BIOS handshake");
114 /*-------------------------------------------------------------------------*/
116 static int number_of_tds(struct urb
*urb
)
118 int len
, i
, num
, this_sg_len
;
119 struct scatterlist
*sg
;
121 len
= urb
->transfer_buffer_length
;
122 i
= urb
->num_mapped_sgs
;
124 if (len
> 0 && i
> 0) { /* Scatter-gather transfer */
128 this_sg_len
= min_t(int, sg_dma_len(sg
), len
);
129 num
+= DIV_ROUND_UP(this_sg_len
, 4096);
131 if (--i
<= 0 || len
<= 0)
136 } else { /* Non-SG transfer */
137 /* one TD for every 4096 Bytes (could be up to 8K) */
138 num
= DIV_ROUND_UP(len
, 4096);
144 * queue up an urb for anything except the root hub
146 static int ohci_urb_enqueue (
151 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
153 urb_priv_t
*urb_priv
;
154 unsigned int pipe
= urb
->pipe
;
159 /* every endpoint has a ed, locate and maybe (re)initialize it */
160 ed
= ed_get(ohci
, urb
->ep
, urb
->dev
, pipe
, urb
->interval
);
164 /* for the private part of the URB we need the number of TDs (size) */
167 /* td_submit_urb() doesn't yet handle these */
168 if (urb
->transfer_buffer_length
> 4096)
171 /* 1 TD for setup, 1 for ACK, plus ... */
174 // case PIPE_INTERRUPT:
177 size
+= number_of_tds(urb
);
178 /* maybe a zero-length packet to wrap it up */
181 else if ((urb
->transfer_flags
& URB_ZERO_PACKET
) != 0
182 && (urb
->transfer_buffer_length
183 % usb_maxpacket (urb
->dev
, pipe
,
184 usb_pipeout (pipe
))) == 0)
187 case PIPE_ISOCHRONOUS
: /* number of packets from URB */
188 size
= urb
->number_of_packets
;
192 /* allocate the private part of the URB */
193 urb_priv
= kzalloc (sizeof (urb_priv_t
) + size
* sizeof (struct td
*),
197 INIT_LIST_HEAD (&urb_priv
->pending
);
198 urb_priv
->length
= size
;
201 /* allocate the TDs (deferring hash chain updates) */
202 for (i
= 0; i
< size
; i
++) {
203 urb_priv
->td
[i
] = td_alloc (ohci
, mem_flags
);
204 if (!urb_priv
->td
[i
]) {
205 urb_priv
->length
= i
;
206 urb_free_priv (ohci
, urb_priv
);
211 spin_lock_irqsave (&ohci
->lock
, flags
);
213 /* don't submit to a dead HC */
214 if (!HCD_HW_ACCESSIBLE(hcd
)) {
218 if (ohci
->rh_state
!= OHCI_RH_RUNNING
) {
222 retval
= usb_hcd_link_urb_to_ep(hcd
, urb
);
226 /* schedule the ed if needed */
227 if (ed
->state
== ED_IDLE
) {
228 retval
= ed_schedule (ohci
, ed
);
230 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
234 /* Start up the I/O watchdog timer, if it's not running */
235 if (ohci
->prev_frame_no
== IO_WATCHDOG_OFF
&&
236 list_empty(&ohci
->eds_in_use
) &&
237 !(ohci
->flags
& OHCI_QUIRK_QEMU
)) {
238 ohci
->prev_frame_no
= ohci_frame_no(ohci
);
239 mod_timer(&ohci
->io_watchdog
,
240 jiffies
+ IO_WATCHDOG_DELAY
);
242 list_add(&ed
->in_use_list
, &ohci
->eds_in_use
);
244 if (ed
->type
== PIPE_ISOCHRONOUS
) {
245 u16 frame
= ohci_frame_no(ohci
);
247 /* delay a few frames before the first TD */
248 frame
+= max_t (u16
, 8, ed
->interval
);
249 frame
&= ~(ed
->interval
- 1);
251 urb
->start_frame
= frame
;
252 ed
->last_iso
= frame
+ ed
->interval
* (size
- 1);
254 } else if (ed
->type
== PIPE_ISOCHRONOUS
) {
255 u16 next
= ohci_frame_no(ohci
) + 1;
256 u16 frame
= ed
->last_iso
+ ed
->interval
;
257 u16 length
= ed
->interval
* (size
- 1);
259 /* Behind the scheduling threshold? */
260 if (unlikely(tick_before(frame
, next
))) {
262 /* URB_ISO_ASAP: Round up to the first available slot */
263 if (urb
->transfer_flags
& URB_ISO_ASAP
) {
264 frame
+= (next
- frame
+ ed
->interval
- 1) &
268 * Not ASAP: Use the next slot in the stream,
273 * Some OHCI hardware doesn't handle late TDs
274 * correctly. After retiring them it proceeds
275 * to the next ED instead of the next TD.
276 * Therefore we have to omit the late TDs
279 urb_priv
->td_cnt
= DIV_ROUND_UP(
280 (u16
) (next
- frame
),
282 if (urb_priv
->td_cnt
>= urb_priv
->length
) {
283 ++urb_priv
->td_cnt
; /* Mark it */
284 ohci_dbg(ohci
, "iso underrun %p (%u+%u < %u)\n",
290 urb
->start_frame
= frame
;
291 ed
->last_iso
= frame
+ length
;
294 /* fill the TDs and link them to the ed; and
295 * enable that part of the schedule, if needed
296 * and update count of queued periodic urbs
298 urb
->hcpriv
= urb_priv
;
299 td_submit_urb (ohci
, urb
);
303 urb_free_priv (ohci
, urb_priv
);
304 spin_unlock_irqrestore (&ohci
->lock
, flags
);
309 * decouple the URB from the HC queues (TDs, urb_priv).
310 * reporting is always done
311 * asynchronously, and we might be dealing with an urb that's
312 * partially transferred, or an ED with other urbs being unlinked.
314 static int ohci_urb_dequeue(struct usb_hcd
*hcd
, struct urb
*urb
, int status
)
316 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
319 urb_priv_t
*urb_priv
;
321 spin_lock_irqsave (&ohci
->lock
, flags
);
322 rc
= usb_hcd_check_unlink_urb(hcd
, urb
, status
);
325 /* Unless an IRQ completed the unlink while it was being
326 * handed to us, flag it for unlink and giveback, and force
327 * some upcoming INTR_SF to call finish_unlinks()
329 urb_priv
= urb
->hcpriv
;
330 if (urb_priv
->ed
->state
== ED_OPER
)
331 start_ed_unlink(ohci
, urb_priv
->ed
);
333 if (ohci
->rh_state
!= OHCI_RH_RUNNING
) {
334 /* With HC dead, we can clean up right away */
338 spin_unlock_irqrestore (&ohci
->lock
, flags
);
342 /*-------------------------------------------------------------------------*/
344 /* frees config/altsetting state for endpoints,
345 * including ED memory, dummy TD, and bulk/intr data toggle
349 ohci_endpoint_disable (struct usb_hcd
*hcd
, struct usb_host_endpoint
*ep
)
351 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
353 struct ed
*ed
= ep
->hcpriv
;
354 unsigned limit
= 1000;
356 /* ASSERT: any requests/urbs are being unlinked */
357 /* ASSERT: nobody can be submitting urbs for this any more */
363 spin_lock_irqsave (&ohci
->lock
, flags
);
365 if (ohci
->rh_state
!= OHCI_RH_RUNNING
) {
372 case ED_UNLINK
: /* wait for hw to finish? */
373 /* major IRQ delivery trouble loses INTR_SF too... */
375 ohci_warn(ohci
, "ED unlink timeout\n");
378 spin_unlock_irqrestore (&ohci
->lock
, flags
);
379 schedule_timeout_uninterruptible(1);
381 case ED_IDLE
: /* fully unlinked */
382 if (list_empty (&ed
->td_list
)) {
383 td_free (ohci
, ed
->dummy
);
389 /* caller was supposed to have unlinked any requests;
390 * that's not our job. can't recover; must leak ed.
392 ohci_err (ohci
, "leak ed %p (#%02x) state %d%s\n",
393 ed
, ep
->desc
.bEndpointAddress
, ed
->state
,
394 list_empty (&ed
->td_list
) ? "" : " (has tds)");
395 td_free (ohci
, ed
->dummy
);
399 spin_unlock_irqrestore (&ohci
->lock
, flags
);
402 static int ohci_get_frame (struct usb_hcd
*hcd
)
404 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
406 return ohci_frame_no(ohci
);
409 static void ohci_usb_reset (struct ohci_hcd
*ohci
)
411 ohci
->hc_control
= ohci_readl (ohci
, &ohci
->regs
->control
);
412 ohci
->hc_control
&= OHCI_CTRL_RWC
;
413 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
414 ohci
->rh_state
= OHCI_RH_HALTED
;
417 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
418 * other cases where the next software may expect clean state from the
419 * "firmware". this is bus-neutral, unlike shutdown() methods.
422 ohci_shutdown (struct usb_hcd
*hcd
)
424 struct ohci_hcd
*ohci
;
426 ohci
= hcd_to_ohci (hcd
);
427 ohci_writel(ohci
, (u32
) ~0, &ohci
->regs
->intrdisable
);
429 /* Software reset, after which the controller goes into SUSPEND */
430 ohci_writel(ohci
, OHCI_HCR
, &ohci
->regs
->cmdstatus
);
431 ohci_readl(ohci
, &ohci
->regs
->cmdstatus
); /* flush the writes */
434 ohci_writel(ohci
, ohci
->fminterval
, &ohci
->regs
->fminterval
);
435 ohci
->rh_state
= OHCI_RH_HALTED
;
438 /*-------------------------------------------------------------------------*
440 *-------------------------------------------------------------------------*/
442 /* init memory, and kick BIOS/SMM off */
444 static int ohci_init (struct ohci_hcd
*ohci
)
447 struct usb_hcd
*hcd
= ohci_to_hcd(ohci
);
449 /* Accept arbitrarily long scatter-gather lists */
450 hcd
->self
.sg_tablesize
= ~0;
452 if (distrust_firmware
)
453 ohci
->flags
|= OHCI_QUIRK_HUB_POWER
;
455 ohci
->rh_state
= OHCI_RH_HALTED
;
456 ohci
->regs
= hcd
->regs
;
458 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
459 * was never needed for most non-PCI systems ... remove the code?
463 /* SMM owns the HC? not for long! */
464 if (!no_handshake
&& ohci_readl (ohci
,
465 &ohci
->regs
->control
) & OHCI_CTRL_IR
) {
468 ohci_dbg (ohci
, "USB HC TakeOver from BIOS/SMM\n");
470 /* this timeout is arbitrary. we make it long, so systems
471 * depending on usb keyboards may be usable even if the
472 * BIOS/SMM code seems pretty broken.
474 temp
= 500; /* arbitrary: five seconds */
476 ohci_writel (ohci
, OHCI_INTR_OC
, &ohci
->regs
->intrenable
);
477 ohci_writel (ohci
, OHCI_OCR
, &ohci
->regs
->cmdstatus
);
478 while (ohci_readl (ohci
, &ohci
->regs
->control
) & OHCI_CTRL_IR
) {
481 ohci_err (ohci
, "USB HC takeover failed!"
482 " (BIOS/SMM bug)\n");
486 ohci_usb_reset (ohci
);
490 /* Disable HC interrupts */
491 ohci_writel (ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrdisable
);
493 /* flush the writes, and save key bits like RWC */
494 if (ohci_readl (ohci
, &ohci
->regs
->control
) & OHCI_CTRL_RWC
)
495 ohci
->hc_control
|= OHCI_CTRL_RWC
;
497 /* Read the number of ports unless overridden */
498 if (ohci
->num_ports
== 0)
499 ohci
->num_ports
= roothub_a(ohci
) & RH_A_NDP
;
504 timer_setup(&ohci
->io_watchdog
, io_watchdog_func
, 0);
505 ohci
->prev_frame_no
= IO_WATCHDOG_OFF
;
507 ohci
->hcca
= dma_alloc_coherent (hcd
->self
.controller
,
508 sizeof(*ohci
->hcca
), &ohci
->hcca_dma
, GFP_KERNEL
);
512 if ((ret
= ohci_mem_init (ohci
)) < 0)
515 create_debug_files (ohci
);
521 /*-------------------------------------------------------------------------*/
523 /* Start an OHCI controller, set the BUS operational
524 * resets USB and controller
527 static int ohci_run (struct ohci_hcd
*ohci
)
530 int first
= ohci
->fminterval
== 0;
531 struct usb_hcd
*hcd
= ohci_to_hcd(ohci
);
533 ohci
->rh_state
= OHCI_RH_HALTED
;
535 /* boot firmware should have set this up (5.1.1.3.1) */
538 val
= ohci_readl (ohci
, &ohci
->regs
->fminterval
);
539 ohci
->fminterval
= val
& 0x3fff;
540 if (ohci
->fminterval
!= FI
)
541 ohci_dbg (ohci
, "fminterval delta %d\n",
542 ohci
->fminterval
- FI
);
543 ohci
->fminterval
|= FSMP (ohci
->fminterval
) << 16;
544 /* also: power/overcurrent flags in roothub.a */
547 /* Reset USB nearly "by the book". RemoteWakeupConnected has
548 * to be checked in case boot firmware (BIOS/SMM/...) has set up
549 * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
550 * If the bus glue detected wakeup capability then it should
551 * already be enabled; if so we'll just enable it again.
553 if ((ohci
->hc_control
& OHCI_CTRL_RWC
) != 0)
554 device_set_wakeup_capable(hcd
->self
.controller
, 1);
556 switch (ohci
->hc_control
& OHCI_CTRL_HCFS
) {
560 case OHCI_USB_SUSPEND
:
561 case OHCI_USB_RESUME
:
562 ohci
->hc_control
&= OHCI_CTRL_RWC
;
563 ohci
->hc_control
|= OHCI_USB_RESUME
;
564 val
= 10 /* msec wait */;
566 // case OHCI_USB_RESET:
568 ohci
->hc_control
&= OHCI_CTRL_RWC
;
569 ohci
->hc_control
|= OHCI_USB_RESET
;
570 val
= 50 /* msec wait */;
573 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
575 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
578 memset (ohci
->hcca
, 0, sizeof (struct ohci_hcca
));
580 /* 2msec timelimit here means no irqs/preempt */
581 spin_lock_irq (&ohci
->lock
);
584 /* HC Reset requires max 10 us delay */
585 ohci_writel (ohci
, OHCI_HCR
, &ohci
->regs
->cmdstatus
);
586 val
= 30; /* ... allow extra time */
587 while ((ohci_readl (ohci
, &ohci
->regs
->cmdstatus
) & OHCI_HCR
) != 0) {
589 spin_unlock_irq (&ohci
->lock
);
590 ohci_err (ohci
, "USB HC reset timed out!\n");
596 /* now we're in the SUSPEND state ... must go OPERATIONAL
597 * within 2msec else HC enters RESUME
599 * ... but some hardware won't init fmInterval "by the book"
600 * (SiS, OPTi ...), so reset again instead. SiS doesn't need
601 * this if we write fmInterval after we're OPERATIONAL.
602 * Unclear about ALi, ServerWorks, and others ... this could
603 * easily be a longstanding bug in chip init on Linux.
605 if (ohci
->flags
& OHCI_QUIRK_INITRESET
) {
606 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
607 // flush those writes
608 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
611 /* Tell the controller where the control and bulk lists are
612 * The lists are empty now. */
613 ohci_writel (ohci
, 0, &ohci
->regs
->ed_controlhead
);
614 ohci_writel (ohci
, 0, &ohci
->regs
->ed_bulkhead
);
616 /* a reset clears this */
617 ohci_writel (ohci
, (u32
) ohci
->hcca_dma
, &ohci
->regs
->hcca
);
619 periodic_reinit (ohci
);
621 /* some OHCI implementations are finicky about how they init.
622 * bogus values here mean not even enumeration could work.
624 if ((ohci_readl (ohci
, &ohci
->regs
->fminterval
) & 0x3fff0000) == 0
625 || !ohci_readl (ohci
, &ohci
->regs
->periodicstart
)) {
626 if (!(ohci
->flags
& OHCI_QUIRK_INITRESET
)) {
627 ohci
->flags
|= OHCI_QUIRK_INITRESET
;
628 ohci_dbg (ohci
, "enabling initreset quirk\n");
631 spin_unlock_irq (&ohci
->lock
);
632 ohci_err (ohci
, "init err (%08x %04x)\n",
633 ohci_readl (ohci
, &ohci
->regs
->fminterval
),
634 ohci_readl (ohci
, &ohci
->regs
->periodicstart
));
638 /* use rhsc irqs after hub_wq is allocated */
639 set_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
640 hcd
->uses_new_polling
= 1;
642 /* start controller operations */
643 ohci
->hc_control
&= OHCI_CTRL_RWC
;
644 ohci
->hc_control
|= OHCI_CONTROL_INIT
| OHCI_USB_OPER
;
645 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
646 ohci
->rh_state
= OHCI_RH_RUNNING
;
648 /* wake on ConnectStatusChange, matching external hubs */
649 ohci_writel (ohci
, RH_HS_DRWE
, &ohci
->regs
->roothub
.status
);
651 /* Choose the interrupts we care about now, others later on demand */
652 mask
= OHCI_INTR_INIT
;
653 ohci_writel (ohci
, ~0, &ohci
->regs
->intrstatus
);
654 ohci_writel (ohci
, mask
, &ohci
->regs
->intrenable
);
656 /* handle root hub init quirks ... */
657 val
= roothub_a (ohci
);
658 val
&= ~(RH_A_PSM
| RH_A_OCPM
);
659 if (ohci
->flags
& OHCI_QUIRK_SUPERIO
) {
660 /* NSC 87560 and maybe others */
662 val
&= ~(RH_A_POTPGT
| RH_A_NPS
);
663 ohci_writel (ohci
, val
, &ohci
->regs
->roothub
.a
);
664 } else if ((ohci
->flags
& OHCI_QUIRK_AMD756
) ||
665 (ohci
->flags
& OHCI_QUIRK_HUB_POWER
)) {
666 /* hub power always on; required for AMD-756 and some
667 * Mac platforms. ganged overcurrent reporting, if any.
670 ohci_writel (ohci
, val
, &ohci
->regs
->roothub
.a
);
672 ohci_writel (ohci
, RH_HS_LPSC
, &ohci
->regs
->roothub
.status
);
673 ohci_writel (ohci
, (val
& RH_A_NPS
) ? 0 : RH_B_PPCM
,
674 &ohci
->regs
->roothub
.b
);
675 // flush those writes
676 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
678 ohci
->next_statechange
= jiffies
+ STATECHANGE_DELAY
;
679 spin_unlock_irq (&ohci
->lock
);
681 // POTPGT delay is bits 24-31, in 2 ms units.
682 mdelay ((val
>> 23) & 0x1fe);
689 /* ohci_setup routine for generic controller initialization */
691 int ohci_setup(struct usb_hcd
*hcd
)
693 struct ohci_hcd
*ohci
= hcd_to_ohci(hcd
);
697 return ohci_init(ohci
);
699 EXPORT_SYMBOL_GPL(ohci_setup
);
701 /* ohci_start routine for generic controller start of all OHCI bus glue */
702 static int ohci_start(struct usb_hcd
*hcd
)
704 struct ohci_hcd
*ohci
= hcd_to_ohci(hcd
);
707 ret
= ohci_run(ohci
);
709 ohci_err(ohci
, "can't start\n");
715 /*-------------------------------------------------------------------------*/
718 * Some OHCI controllers are known to lose track of completed TDs. They
719 * don't add the TDs to the hardware done queue, which means we never see
720 * them as being completed.
722 * This watchdog routine checks for such problems. Without some way to
723 * tell when those TDs have completed, we would never take their EDs off
724 * the unlink list. As a result, URBs could never be dequeued and
725 * endpoints could never be released.
727 static void io_watchdog_func(struct timer_list
*t
)
729 struct ohci_hcd
*ohci
= from_timer(ohci
, t
, io_watchdog
);
730 bool takeback_all_pending
= false;
734 struct td
*td
, *td_start
, *td_next
;
735 unsigned frame_no
, prev_frame_no
= IO_WATCHDOG_OFF
;
738 spin_lock_irqsave(&ohci
->lock
, flags
);
741 * One way to lose track of completed TDs is if the controller
742 * never writes back the done queue head. If it hasn't been
743 * written back since the last time this function ran and if it
744 * was non-empty at that time, something is badly wrong with the
747 status
= ohci_readl(ohci
, &ohci
->regs
->intrstatus
);
748 if (!(status
& OHCI_INTR_WDH
) && ohci
->wdh_cnt
== ohci
->prev_wdh_cnt
) {
749 if (ohci
->prev_donehead
) {
750 ohci_err(ohci
, "HcDoneHead not written back; disabled\n");
752 usb_hc_died(ohci_to_hcd(ohci
));
754 ohci_shutdown(ohci_to_hcd(ohci
));
757 /* No write back because the done queue was empty */
758 takeback_all_pending
= true;
762 /* Check every ED which might have pending TDs */
763 list_for_each_entry(ed
, &ohci
->eds_in_use
, in_use_list
) {
764 if (ed
->pending_td
) {
765 if (takeback_all_pending
||
766 OKAY_TO_TAKEBACK(ohci
, ed
)) {
767 unsigned tmp
= hc32_to_cpu(ohci
, ed
->hwINFO
);
769 ohci_dbg(ohci
, "takeback pending TD for dev %d ep 0x%x\n",
771 (0x000f & (tmp
>> 7)) +
772 ((tmp
& ED_IN
) >> 5));
773 add_to_done_list(ohci
, ed
->pending_td
);
777 /* Starting from the latest pending TD, */
780 /* or the last TD on the done list, */
782 list_for_each_entry(td_next
, &ed
->td_list
, td_list
) {
783 if (!td_next
->next_dl_td
)
789 /* find the last TD processed by the controller. */
790 head
= hc32_to_cpu(ohci
, READ_ONCE(ed
->hwHeadP
)) & TD_MASK
;
792 td_next
= list_prepare_entry(td
, &ed
->td_list
, td_list
);
793 list_for_each_entry_continue(td_next
, &ed
->td_list
, td_list
) {
794 if (head
== (u32
) td_next
->td_dma
)
796 td
= td_next
; /* head pointer has passed this TD */
798 if (td
!= td_start
) {
800 * In case a WDH cycle is in progress, we will wait
801 * for the next two cycles to complete before assuming
802 * this TD will never get on the done queue.
804 ed
->takeback_wdh_cnt
= ohci
->wdh_cnt
+ 2;
811 if (ohci
->rh_state
== OHCI_RH_RUNNING
) {
814 * Sometimes a controller just stops working. We can tell
815 * by checking that the frame counter has advanced since
816 * the last time we ran.
818 * But be careful: Some controllers violate the spec by
819 * stopping their frame counter when no ports are active.
821 frame_no
= ohci_frame_no(ohci
);
822 if (frame_no
== ohci
->prev_frame_no
) {
827 for (i
= 0; i
< ohci
->num_ports
; ++i
) {
828 tmp
= roothub_portstatus(ohci
, i
);
829 /* Enabled and not suspended? */
830 if ((tmp
& RH_PS_PES
) && !(tmp
& RH_PS_PSS
))
834 if (active_cnt
> 0) {
835 ohci_err(ohci
, "frame counter not updating; disabled\n");
839 if (!list_empty(&ohci
->eds_in_use
)) {
840 prev_frame_no
= frame_no
;
841 ohci
->prev_wdh_cnt
= ohci
->wdh_cnt
;
842 ohci
->prev_donehead
= ohci_readl(ohci
,
843 &ohci
->regs
->donehead
);
844 mod_timer(&ohci
->io_watchdog
,
845 jiffies
+ IO_WATCHDOG_DELAY
);
850 ohci
->prev_frame_no
= prev_frame_no
;
851 spin_unlock_irqrestore(&ohci
->lock
, flags
);
854 /* an interrupt happens */
856 static irqreturn_t
ohci_irq (struct usb_hcd
*hcd
)
858 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
859 struct ohci_regs __iomem
*regs
= ohci
->regs
;
862 /* Read interrupt status (and flush pending writes). We ignore the
863 * optimization of checking the LSB of hcca->done_head; it doesn't
864 * work on all systems (edge triggering for OHCI can be a factor).
866 ints
= ohci_readl(ohci
, ®s
->intrstatus
);
868 /* Check for an all 1's result which is a typical consequence
869 * of dead, unclocked, or unplugged (CardBus...) devices
871 if (ints
== ~(u32
)0) {
872 ohci
->rh_state
= OHCI_RH_HALTED
;
873 ohci_dbg (ohci
, "device removed!\n");
878 /* We only care about interrupts that are enabled */
879 ints
&= ohci_readl(ohci
, ®s
->intrenable
);
881 /* interrupt for some other device? */
882 if (ints
== 0 || unlikely(ohci
->rh_state
== OHCI_RH_HALTED
))
885 if (ints
& OHCI_INTR_UE
) {
886 // e.g. due to PCI Master/Target Abort
887 if (quirk_nec(ohci
)) {
888 /* Workaround for a silicon bug in some NEC chips used
889 * in Apple's PowerBooks. Adapted from Darwin code.
891 ohci_err (ohci
, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
893 ohci_writel (ohci
, OHCI_INTR_UE
, ®s
->intrdisable
);
895 schedule_work (&ohci
->nec_work
);
897 ohci_err (ohci
, "OHCI Unrecoverable Error, disabled\n");
898 ohci
->rh_state
= OHCI_RH_HALTED
;
903 ohci_usb_reset (ohci
);
906 if (ints
& OHCI_INTR_RHSC
) {
907 ohci_dbg(ohci
, "rhsc\n");
908 ohci
->next_statechange
= jiffies
+ STATECHANGE_DELAY
;
909 ohci_writel(ohci
, OHCI_INTR_RD
| OHCI_INTR_RHSC
,
912 /* NOTE: Vendors didn't always make the same implementation
913 * choices for RHSC. Many followed the spec; RHSC triggers
914 * on an edge, like setting and maybe clearing a port status
915 * change bit. With others it's level-triggered, active
916 * until hub_wq clears all the port status change bits. We'll
917 * always disable it here and rely on polling until hub_wq
920 ohci_writel(ohci
, OHCI_INTR_RHSC
, ®s
->intrdisable
);
921 usb_hcd_poll_rh_status(hcd
);
924 /* For connect and disconnect events, we expect the controller
925 * to turn on RHSC along with RD. But for remote wakeup events
926 * this might not happen.
928 else if (ints
& OHCI_INTR_RD
) {
929 ohci_dbg(ohci
, "resume detect\n");
930 ohci_writel(ohci
, OHCI_INTR_RD
, ®s
->intrstatus
);
931 set_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
932 if (ohci
->autostop
) {
933 spin_lock (&ohci
->lock
);
934 ohci_rh_resume (ohci
);
935 spin_unlock (&ohci
->lock
);
937 usb_hcd_resume_root_hub(hcd
);
940 spin_lock(&ohci
->lock
);
941 if (ints
& OHCI_INTR_WDH
)
942 update_done_list(ohci
);
944 /* could track INTR_SO to reduce available PCI/... bandwidth */
946 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
947 * when there's still unlinking to be done (next frame).
950 if ((ints
& OHCI_INTR_SF
) != 0 && !ohci
->ed_rm_list
951 && ohci
->rh_state
== OHCI_RH_RUNNING
)
952 ohci_writel (ohci
, OHCI_INTR_SF
, ®s
->intrdisable
);
954 if (ohci
->rh_state
== OHCI_RH_RUNNING
) {
955 ohci_writel (ohci
, ints
, ®s
->intrstatus
);
956 if (ints
& OHCI_INTR_WDH
)
959 ohci_writel (ohci
, OHCI_INTR_MIE
, ®s
->intrenable
);
960 // flush those writes
961 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
963 spin_unlock(&ohci
->lock
);
968 /*-------------------------------------------------------------------------*/
970 static void ohci_stop (struct usb_hcd
*hcd
)
972 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
977 flush_work(&ohci
->nec_work
);
978 del_timer_sync(&ohci
->io_watchdog
);
979 ohci
->prev_frame_no
= IO_WATCHDOG_OFF
;
981 ohci_writel (ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrdisable
);
982 ohci_usb_reset(ohci
);
983 free_irq(hcd
->irq
, hcd
);
986 if (quirk_amdiso(ohci
))
989 remove_debug_files (ohci
);
990 ohci_mem_cleanup (ohci
);
992 dma_free_coherent (hcd
->self
.controller
,
994 ohci
->hcca
, ohci
->hcca_dma
);
1000 /*-------------------------------------------------------------------------*/
1002 #if defined(CONFIG_PM) || defined(CONFIG_USB_PCI)
1004 /* must not be called from interrupt context */
1005 int ohci_restart(struct ohci_hcd
*ohci
)
1009 struct urb_priv
*priv
;
1012 spin_lock_irq(&ohci
->lock
);
1013 ohci
->rh_state
= OHCI_RH_HALTED
;
1015 /* Recycle any "live" eds/tds (and urbs). */
1016 if (!list_empty (&ohci
->pending
))
1017 ohci_dbg(ohci
, "abort schedule...\n");
1018 list_for_each_entry (priv
, &ohci
->pending
, pending
) {
1019 struct urb
*urb
= priv
->td
[0]->urb
;
1020 struct ed
*ed
= priv
->ed
;
1022 switch (ed
->state
) {
1024 ed
->state
= ED_UNLINK
;
1025 ed
->hwINFO
|= cpu_to_hc32(ohci
, ED_DEQUEUE
);
1026 ed_deschedule (ohci
, ed
);
1028 ed
->ed_next
= ohci
->ed_rm_list
;
1030 ohci
->ed_rm_list
= ed
;
1035 ohci_dbg(ohci
, "bogus ed %p state %d\n",
1040 urb
->unlinked
= -ESHUTDOWN
;
1043 spin_unlock_irq(&ohci
->lock
);
1045 /* paranoia, in case that didn't work: */
1047 /* empty the interrupt branches */
1048 for (i
= 0; i
< NUM_INTS
; i
++) ohci
->load
[i
] = 0;
1049 for (i
= 0; i
< NUM_INTS
; i
++) ohci
->hcca
->int_table
[i
] = 0;
1051 /* no EDs to remove */
1052 ohci
->ed_rm_list
= NULL
;
1054 /* empty control and bulk lists */
1055 ohci
->ed_controltail
= NULL
;
1056 ohci
->ed_bulktail
= NULL
;
1058 if ((temp
= ohci_run (ohci
)) < 0) {
1059 ohci_err (ohci
, "can't restart, %d\n", temp
);
1062 ohci_dbg(ohci
, "restart complete\n");
1065 EXPORT_SYMBOL_GPL(ohci_restart
);
1071 int ohci_suspend(struct usb_hcd
*hcd
, bool do_wakeup
)
1073 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
1074 unsigned long flags
;
1077 /* Disable irq emission and mark HW unaccessible. Use
1078 * the spinlock to properly synchronize with possible pending
1079 * RH suspend or resume activity.
1081 spin_lock_irqsave (&ohci
->lock
, flags
);
1082 ohci_writel(ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrdisable
);
1083 (void)ohci_readl(ohci
, &ohci
->regs
->intrdisable
);
1085 clear_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
1086 spin_unlock_irqrestore (&ohci
->lock
, flags
);
1088 synchronize_irq(hcd
->irq
);
1090 if (do_wakeup
&& HCD_WAKEUP_PENDING(hcd
)) {
1091 ohci_resume(hcd
, false);
1096 EXPORT_SYMBOL_GPL(ohci_suspend
);
1099 int ohci_resume(struct usb_hcd
*hcd
, bool hibernated
)
1101 struct ohci_hcd
*ohci
= hcd_to_ohci(hcd
);
1103 bool need_reinit
= false;
1105 set_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
1107 /* Make sure resume from hibernation re-enumerates everything */
1109 ohci_usb_reset(ohci
);
1111 /* See if the controller is already running or has been reset */
1112 ohci
->hc_control
= ohci_readl(ohci
, &ohci
->regs
->control
);
1113 if (ohci
->hc_control
& (OHCI_CTRL_IR
| OHCI_SCHED_ENABLES
)) {
1116 switch (ohci
->hc_control
& OHCI_CTRL_HCFS
) {
1118 case OHCI_USB_RESET
:
1123 /* If needed, reinitialize and suspend the root hub */
1125 spin_lock_irq(&ohci
->lock
);
1126 ohci_rh_resume(ohci
);
1127 ohci_rh_suspend(ohci
, 0);
1128 spin_unlock_irq(&ohci
->lock
);
1131 /* Normally just turn on port power and enable interrupts */
1133 ohci_dbg(ohci
, "powerup ports\n");
1134 for (port
= 0; port
< ohci
->num_ports
; port
++)
1135 ohci_writel(ohci
, RH_PS_PPS
,
1136 &ohci
->regs
->roothub
.portstatus
[port
]);
1138 ohci_writel(ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrenable
);
1139 ohci_readl(ohci
, &ohci
->regs
->intrenable
);
1143 usb_hcd_resume_root_hub(hcd
);
1147 EXPORT_SYMBOL_GPL(ohci_resume
);
1151 /*-------------------------------------------------------------------------*/
1154 * Generic structure: This gets copied for platform drivers so that
1155 * individual entries can be overridden as needed.
1158 static const struct hc_driver ohci_hc_driver
= {
1159 .description
= hcd_name
,
1160 .product_desc
= "OHCI Host Controller",
1161 .hcd_priv_size
= sizeof(struct ohci_hcd
),
1164 * generic hardware linkage
1167 .flags
= HCD_MEMORY
| HCD_USB11
,
1170 * basic lifecycle operations
1172 .reset
= ohci_setup
,
1173 .start
= ohci_start
,
1175 .shutdown
= ohci_shutdown
,
1178 * managing i/o requests and associated device resources
1180 .urb_enqueue
= ohci_urb_enqueue
,
1181 .urb_dequeue
= ohci_urb_dequeue
,
1182 .endpoint_disable
= ohci_endpoint_disable
,
1185 * scheduling support
1187 .get_frame_number
= ohci_get_frame
,
1192 .hub_status_data
= ohci_hub_status_data
,
1193 .hub_control
= ohci_hub_control
,
1195 .bus_suspend
= ohci_bus_suspend
,
1196 .bus_resume
= ohci_bus_resume
,
1198 .start_port_reset
= ohci_start_port_reset
,
1201 void ohci_init_driver(struct hc_driver
*drv
,
1202 const struct ohci_driver_overrides
*over
)
1204 /* Copy the generic table to drv and then apply the overrides */
1205 *drv
= ohci_hc_driver
;
1208 drv
->product_desc
= over
->product_desc
;
1209 drv
->hcd_priv_size
+= over
->extra_priv_size
;
1211 drv
->reset
= over
->reset
;
1214 EXPORT_SYMBOL_GPL(ohci_init_driver
);
1216 /*-------------------------------------------------------------------------*/
1218 MODULE_AUTHOR (DRIVER_AUTHOR
);
1219 MODULE_DESCRIPTION(DRIVER_DESC
);
1220 MODULE_LICENSE ("GPL");
1222 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
1223 #include "ohci-sa1111.c"
1224 #define SA1111_DRIVER ohci_hcd_sa1111_driver
1227 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1228 #include "ohci-ppc-of.c"
1229 #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver
1232 #ifdef CONFIG_PPC_PS3
1233 #include "ohci-ps3.c"
1234 #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver
1237 #ifdef CONFIG_MFD_SM501
1238 #include "ohci-sm501.c"
1239 #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver
1242 #ifdef CONFIG_MFD_TC6393XB
1243 #include "ohci-tmio.c"
1244 #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver
1247 #ifdef CONFIG_TILE_USB
1248 #include "ohci-tilegx.c"
1249 #define PLATFORM_DRIVER ohci_hcd_tilegx_driver
1252 static int __init
ohci_hcd_mod_init(void)
1259 printk(KERN_INFO
"%s: " DRIVER_DESC
"\n", hcd_name
);
1260 pr_debug ("%s: block sizes: ed %zd td %zd\n", hcd_name
,
1261 sizeof (struct ed
), sizeof (struct td
));
1262 set_bit(USB_OHCI_LOADED
, &usb_hcds_loaded
);
1264 ohci_debug_root
= debugfs_create_dir("ohci", usb_debug_root
);
1265 if (!ohci_debug_root
) {
1270 #ifdef PS3_SYSTEM_BUS_DRIVER
1271 retval
= ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER
);
1276 #ifdef PLATFORM_DRIVER
1277 retval
= platform_driver_register(&PLATFORM_DRIVER
);
1279 goto error_platform
;
1282 #ifdef OF_PLATFORM_DRIVER
1283 retval
= platform_driver_register(&OF_PLATFORM_DRIVER
);
1285 goto error_of_platform
;
1288 #ifdef SA1111_DRIVER
1289 retval
= sa1111_driver_register(&SA1111_DRIVER
);
1294 #ifdef SM501_OHCI_DRIVER
1295 retval
= platform_driver_register(&SM501_OHCI_DRIVER
);
1300 #ifdef TMIO_OHCI_DRIVER
1301 retval
= platform_driver_register(&TMIO_OHCI_DRIVER
);
1309 #ifdef TMIO_OHCI_DRIVER
1310 platform_driver_unregister(&TMIO_OHCI_DRIVER
);
1313 #ifdef SM501_OHCI_DRIVER
1314 platform_driver_unregister(&SM501_OHCI_DRIVER
);
1317 #ifdef SA1111_DRIVER
1318 sa1111_driver_unregister(&SA1111_DRIVER
);
1321 #ifdef OF_PLATFORM_DRIVER
1322 platform_driver_unregister(&OF_PLATFORM_DRIVER
);
1325 #ifdef PLATFORM_DRIVER
1326 platform_driver_unregister(&PLATFORM_DRIVER
);
1329 #ifdef PS3_SYSTEM_BUS_DRIVER
1330 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER
);
1333 debugfs_remove(ohci_debug_root
);
1334 ohci_debug_root
= NULL
;
1337 clear_bit(USB_OHCI_LOADED
, &usb_hcds_loaded
);
1340 module_init(ohci_hcd_mod_init
);
1342 static void __exit
ohci_hcd_mod_exit(void)
1344 #ifdef TMIO_OHCI_DRIVER
1345 platform_driver_unregister(&TMIO_OHCI_DRIVER
);
1347 #ifdef SM501_OHCI_DRIVER
1348 platform_driver_unregister(&SM501_OHCI_DRIVER
);
1350 #ifdef SA1111_DRIVER
1351 sa1111_driver_unregister(&SA1111_DRIVER
);
1353 #ifdef OF_PLATFORM_DRIVER
1354 platform_driver_unregister(&OF_PLATFORM_DRIVER
);
1356 #ifdef PLATFORM_DRIVER
1357 platform_driver_unregister(&PLATFORM_DRIVER
);
1359 #ifdef PS3_SYSTEM_BUS_DRIVER
1360 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER
);
1362 debugfs_remove(ohci_debug_root
);
1363 clear_bit(USB_OHCI_LOADED
, &usb_hcds_loaded
);
1365 module_exit(ohci_hcd_mod_exit
);