]>
git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blob - drivers/usb/host/ohci-q.c
2 * OHCI HCD (Host Controller Driver) for USB.
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
7 * This file is licenced under the GPL.
10 #include <linux/irq.h>
11 #include <linux/slab.h>
13 static void urb_free_priv (struct ohci_hcd
*hc
, urb_priv_t
*urb_priv
)
15 int last
= urb_priv
->length
- 1;
21 for (i
= 0; i
<= last
; i
++) {
22 td
= urb_priv
->td
[i
];
28 list_del (&urb_priv
->pending
);
32 /*-------------------------------------------------------------------------*/
35 * URB goes back to driver, and isn't reissued.
36 * It's completely gone from HC data structures.
37 * PRECONDITION: ohci lock held, irqs blocked.
40 finish_urb(struct ohci_hcd
*ohci
, struct urb
*urb
, int status
)
41 __releases(ohci
->lock
)
42 __acquires(ohci
->lock
)
44 // ASSERT (urb->hcpriv != 0);
46 urb_free_priv (ohci
, urb
->hcpriv
);
47 if (likely(status
== -EINPROGRESS
))
50 switch (usb_pipetype (urb
->pipe
)) {
51 case PIPE_ISOCHRONOUS
:
52 ohci_to_hcd(ohci
)->self
.bandwidth_isoc_reqs
--;
53 if (ohci_to_hcd(ohci
)->self
.bandwidth_isoc_reqs
== 0) {
54 if (quirk_amdiso(ohci
))
55 usb_amd_quirk_pll_enable();
56 if (quirk_amdprefetch(ohci
))
57 sb800_prefetch(ohci
, 0);
61 ohci_to_hcd(ohci
)->self
.bandwidth_int_reqs
--;
65 #ifdef OHCI_VERBOSE_DEBUG
66 urb_print(urb
, "RET", usb_pipeout (urb
->pipe
), status
);
69 /* urb->complete() can reenter this HCD */
70 usb_hcd_unlink_urb_from_ep(ohci_to_hcd(ohci
), urb
);
71 spin_unlock (&ohci
->lock
);
72 usb_hcd_giveback_urb(ohci_to_hcd(ohci
), urb
, status
);
73 spin_lock (&ohci
->lock
);
75 /* stop periodic dma if it's not needed */
76 if (ohci_to_hcd(ohci
)->self
.bandwidth_isoc_reqs
== 0
77 && ohci_to_hcd(ohci
)->self
.bandwidth_int_reqs
== 0) {
78 ohci
->hc_control
&= ~(OHCI_CTRL_PLE
|OHCI_CTRL_IE
);
79 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
84 /*-------------------------------------------------------------------------*
85 * ED handling functions
86 *-------------------------------------------------------------------------*/
88 /* search for the right schedule branch to use for a periodic ed.
89 * does some load balancing; returns the branch, or negative errno.
91 static int balance (struct ohci_hcd
*ohci
, int interval
, int load
)
93 int i
, branch
= -ENOSPC
;
95 /* iso periods can be huge; iso tds specify frame numbers */
96 if (interval
> NUM_INTS
)
99 /* search for the least loaded schedule branch of that period
100 * that has enough bandwidth left unreserved.
102 for (i
= 0; i
< interval
; i
++) {
103 if (branch
< 0 || ohci
->load
[branch
] > ohci
->load
[i
]) {
106 /* usb 1.1 says 90% of one frame */
107 for (j
= i
; j
< NUM_INTS
; j
+= interval
) {
108 if ((ohci
->load
[j
] + load
) > 900)
119 /*-------------------------------------------------------------------------*/
121 /* both iso and interrupt requests have periods; this routine puts them
122 * into the schedule tree in the apppropriate place. most iso devices use
123 * 1msec periods, but that's not required.
125 static void periodic_link (struct ohci_hcd
*ohci
, struct ed
*ed
)
129 ohci_vdbg (ohci
, "link %sed %p branch %d [%dus.], interval %d\n",
130 (ed
->hwINFO
& cpu_to_hc32 (ohci
, ED_ISO
)) ? "iso " : "",
131 ed
, ed
->branch
, ed
->load
, ed
->interval
);
133 for (i
= ed
->branch
; i
< NUM_INTS
; i
+= ed
->interval
) {
134 struct ed
**prev
= &ohci
->periodic
[i
];
135 __hc32
*prev_p
= &ohci
->hcca
->int_table
[i
];
136 struct ed
*here
= *prev
;
138 /* sorting each branch by period (slow before fast)
139 * lets us share the faster parts of the tree.
140 * (plus maybe: put interrupt eds before iso)
142 while (here
&& ed
!= here
) {
143 if (ed
->interval
> here
->interval
)
145 prev
= &here
->ed_next
;
146 prev_p
= &here
->hwNextED
;
152 ed
->hwNextED
= *prev_p
;
155 *prev_p
= cpu_to_hc32(ohci
, ed
->dma
);
158 ohci
->load
[i
] += ed
->load
;
160 ohci_to_hcd(ohci
)->self
.bandwidth_allocated
+= ed
->load
/ ed
->interval
;
163 /* link an ed into one of the HC chains */
165 static int ed_schedule (struct ohci_hcd
*ohci
, struct ed
*ed
)
173 if (quirk_zfmicro(ohci
)
174 && (ed
->type
== PIPE_INTERRUPT
)
175 && !(ohci
->eds_scheduled
++))
176 mod_timer(&ohci
->unlink_watchdog
, round_jiffies(jiffies
+ HZ
));
179 /* we care about rm_list when setting CLE/BLE in case the HC was at
180 * work on some TD when CLE/BLE was turned off, and isn't quiesced
181 * yet. finish_unlinks() restarts as needed, some upcoming INTR_SF.
183 * control and bulk EDs are doubly linked (ed_next, ed_prev), but
184 * periodic ones are singly linked (ed_next). that's because the
185 * periodic schedule encodes a tree like figure 3-5 in the ohci
186 * spec: each qh can have several "previous" nodes, and the tree
187 * doesn't have unused/idle descriptors.
191 if (ohci
->ed_controltail
== NULL
) {
192 WARN_ON (ohci
->hc_control
& OHCI_CTRL_CLE
);
193 ohci_writel (ohci
, ed
->dma
,
194 &ohci
->regs
->ed_controlhead
);
196 ohci
->ed_controltail
->ed_next
= ed
;
197 ohci
->ed_controltail
->hwNextED
= cpu_to_hc32 (ohci
,
200 ed
->ed_prev
= ohci
->ed_controltail
;
201 if (!ohci
->ed_controltail
&& !ohci
->ed_rm_list
) {
203 ohci
->hc_control
|= OHCI_CTRL_CLE
;
204 ohci_writel (ohci
, 0, &ohci
->regs
->ed_controlcurrent
);
205 ohci_writel (ohci
, ohci
->hc_control
,
206 &ohci
->regs
->control
);
208 ohci
->ed_controltail
= ed
;
212 if (ohci
->ed_bulktail
== NULL
) {
213 WARN_ON (ohci
->hc_control
& OHCI_CTRL_BLE
);
214 ohci_writel (ohci
, ed
->dma
, &ohci
->regs
->ed_bulkhead
);
216 ohci
->ed_bulktail
->ed_next
= ed
;
217 ohci
->ed_bulktail
->hwNextED
= cpu_to_hc32 (ohci
,
220 ed
->ed_prev
= ohci
->ed_bulktail
;
221 if (!ohci
->ed_bulktail
&& !ohci
->ed_rm_list
) {
223 ohci
->hc_control
|= OHCI_CTRL_BLE
;
224 ohci_writel (ohci
, 0, &ohci
->regs
->ed_bulkcurrent
);
225 ohci_writel (ohci
, ohci
->hc_control
,
226 &ohci
->regs
->control
);
228 ohci
->ed_bulktail
= ed
;
231 // case PIPE_INTERRUPT:
232 // case PIPE_ISOCHRONOUS:
234 branch
= balance (ohci
, ed
->interval
, ed
->load
);
237 "ERR %d, interval %d msecs, load %d\n",
238 branch
, ed
->interval
, ed
->load
);
239 // FIXME if there are TDs queued, fail them!
243 periodic_link (ohci
, ed
);
246 /* the HC may not see the schedule updates yet, but if it does
247 * then they'll be properly ordered.
252 /*-------------------------------------------------------------------------*/
254 /* scan the periodic table to find and unlink this ED */
255 static void periodic_unlink (struct ohci_hcd
*ohci
, struct ed
*ed
)
259 for (i
= ed
->branch
; i
< NUM_INTS
; i
+= ed
->interval
) {
261 struct ed
**prev
= &ohci
->periodic
[i
];
262 __hc32
*prev_p
= &ohci
->hcca
->int_table
[i
];
264 while (*prev
&& (temp
= *prev
) != ed
) {
265 prev_p
= &temp
->hwNextED
;
266 prev
= &temp
->ed_next
;
269 *prev_p
= ed
->hwNextED
;
272 ohci
->load
[i
] -= ed
->load
;
274 ohci_to_hcd(ohci
)->self
.bandwidth_allocated
-= ed
->load
/ ed
->interval
;
276 ohci_vdbg (ohci
, "unlink %sed %p branch %d [%dus.], interval %d\n",
277 (ed
->hwINFO
& cpu_to_hc32 (ohci
, ED_ISO
)) ? "iso " : "",
278 ed
, ed
->branch
, ed
->load
, ed
->interval
);
281 /* unlink an ed from one of the HC chains.
282 * just the link to the ed is unlinked.
283 * the link from the ed still points to another operational ed or 0
284 * so the HC can eventually finish the processing of the unlinked ed
285 * (assuming it already started that, which needn't be true).
287 * ED_UNLINK is a transient state: the HC may still see this ED, but soon
288 * it won't. ED_SKIP means the HC will finish its current transaction,
289 * but won't start anything new. The TD queue may still grow; device
290 * drivers don't know about this HCD-internal state.
292 * When the HC can't see the ED, something changes ED_UNLINK to one of:
294 * - ED_OPER: when there's any request queued, the ED gets rescheduled
295 * immediately. HC should be working on them.
297 * - ED_IDLE: when there's no TD queue. there's no reason for the HC
298 * to care about this ED; safe to disable the endpoint.
300 * When finish_unlinks() runs later, after SOF interrupt, it will often
301 * complete one or more URB unlinks before making that state change.
303 static void ed_deschedule (struct ohci_hcd
*ohci
, struct ed
*ed
)
305 ed
->hwINFO
|= cpu_to_hc32 (ohci
, ED_SKIP
);
307 ed
->state
= ED_UNLINK
;
309 /* To deschedule something from the control or bulk list, just
310 * clear CLE/BLE and wait. There's no safe way to scrub out list
311 * head/current registers until later, and "later" isn't very
312 * tightly specified. Figure 6-5 and Section 6.4.2.2 show how
313 * the HC is reading the ED queues (while we modify them).
315 * For now, ed_schedule() is "later". It might be good paranoia
316 * to scrub those registers in finish_unlinks(), in case of bugs
317 * that make the HC try to use them.
321 /* remove ED from the HC's list: */
322 if (ed
->ed_prev
== NULL
) {
324 ohci
->hc_control
&= ~OHCI_CTRL_CLE
;
325 ohci_writel (ohci
, ohci
->hc_control
,
326 &ohci
->regs
->control
);
327 // a ohci_readl() later syncs CLE with the HC
330 hc32_to_cpup (ohci
, &ed
->hwNextED
),
331 &ohci
->regs
->ed_controlhead
);
333 ed
->ed_prev
->ed_next
= ed
->ed_next
;
334 ed
->ed_prev
->hwNextED
= ed
->hwNextED
;
336 /* remove ED from the HCD's list: */
337 if (ohci
->ed_controltail
== ed
) {
338 ohci
->ed_controltail
= ed
->ed_prev
;
339 if (ohci
->ed_controltail
)
340 ohci
->ed_controltail
->ed_next
= NULL
;
341 } else if (ed
->ed_next
) {
342 ed
->ed_next
->ed_prev
= ed
->ed_prev
;
347 /* remove ED from the HC's list: */
348 if (ed
->ed_prev
== NULL
) {
350 ohci
->hc_control
&= ~OHCI_CTRL_BLE
;
351 ohci_writel (ohci
, ohci
->hc_control
,
352 &ohci
->regs
->control
);
353 // a ohci_readl() later syncs BLE with the HC
356 hc32_to_cpup (ohci
, &ed
->hwNextED
),
357 &ohci
->regs
->ed_bulkhead
);
359 ed
->ed_prev
->ed_next
= ed
->ed_next
;
360 ed
->ed_prev
->hwNextED
= ed
->hwNextED
;
362 /* remove ED from the HCD's list: */
363 if (ohci
->ed_bulktail
== ed
) {
364 ohci
->ed_bulktail
= ed
->ed_prev
;
365 if (ohci
->ed_bulktail
)
366 ohci
->ed_bulktail
->ed_next
= NULL
;
367 } else if (ed
->ed_next
) {
368 ed
->ed_next
->ed_prev
= ed
->ed_prev
;
372 // case PIPE_INTERRUPT:
373 // case PIPE_ISOCHRONOUS:
375 periodic_unlink (ohci
, ed
);
381 /*-------------------------------------------------------------------------*/
383 /* get and maybe (re)init an endpoint. init _should_ be done only as part
384 * of enumeration, usb_set_configuration() or usb_set_interface().
386 static struct ed
*ed_get (
387 struct ohci_hcd
*ohci
,
388 struct usb_host_endpoint
*ep
,
389 struct usb_device
*udev
,
396 spin_lock_irqsave (&ohci
->lock
, flags
);
398 if (!(ed
= ep
->hcpriv
)) {
403 ed
= ed_alloc (ohci
, GFP_ATOMIC
);
409 /* dummy td; end of td list for ed */
410 td
= td_alloc (ohci
, GFP_ATOMIC
);
418 ed
->hwTailP
= cpu_to_hc32 (ohci
, td
->td_dma
);
419 ed
->hwHeadP
= ed
->hwTailP
; /* ED_C, ED_H zeroed */
422 is_out
= !(ep
->desc
.bEndpointAddress
& USB_DIR_IN
);
424 /* FIXME usbcore changes dev->devnum before SET_ADDRESS
425 * succeeds ... otherwise we wouldn't need "pipe".
427 info
= usb_pipedevice (pipe
);
428 ed
->type
= usb_pipetype(pipe
);
430 info
|= (ep
->desc
.bEndpointAddress
& ~USB_DIR_IN
) << 7;
431 info
|= usb_endpoint_maxp(&ep
->desc
) << 16;
432 if (udev
->speed
== USB_SPEED_LOW
)
434 /* only control transfers store pids in tds */
435 if (ed
->type
!= PIPE_CONTROL
) {
436 info
|= is_out
? ED_OUT
: ED_IN
;
437 if (ed
->type
!= PIPE_BULK
) {
438 /* periodic transfers... */
439 if (ed
->type
== PIPE_ISOCHRONOUS
)
441 else if (interval
> 32) /* iso can be bigger */
443 ed
->interval
= interval
;
444 ed
->load
= usb_calc_bus_time (
445 udev
->speed
, !is_out
,
446 ed
->type
== PIPE_ISOCHRONOUS
,
447 usb_endpoint_maxp(&ep
->desc
))
451 ed
->hwINFO
= cpu_to_hc32(ohci
, info
);
457 spin_unlock_irqrestore (&ohci
->lock
, flags
);
461 /*-------------------------------------------------------------------------*/
463 /* request unlinking of an endpoint from an operational HC.
464 * put the ep on the rm_list
465 * real work is done at the next start frame (SF) hardware interrupt
466 * caller guarantees HCD is running, so hardware access is safe,
467 * and that ed->state is ED_OPER
469 static void start_ed_unlink (struct ohci_hcd
*ohci
, struct ed
*ed
)
471 ed
->hwINFO
|= cpu_to_hc32 (ohci
, ED_DEQUEUE
);
472 ed_deschedule (ohci
, ed
);
474 /* rm_list is just singly linked, for simplicity */
475 ed
->ed_next
= ohci
->ed_rm_list
;
477 ohci
->ed_rm_list
= ed
;
479 /* enable SOF interrupt */
480 ohci_writel (ohci
, OHCI_INTR_SF
, &ohci
->regs
->intrstatus
);
481 ohci_writel (ohci
, OHCI_INTR_SF
, &ohci
->regs
->intrenable
);
482 // flush those writes, and get latest HCCA contents
483 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
485 /* SF interrupt might get delayed; record the frame counter value that
486 * indicates when the HC isn't looking at it, so concurrent unlinks
487 * behave. frame_no wraps every 2^16 msec, and changes right before
490 ed
->tick
= ohci_frame_no(ohci
) + 1;
494 /*-------------------------------------------------------------------------*
495 * TD handling functions
496 *-------------------------------------------------------------------------*/
498 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
501 td_fill (struct ohci_hcd
*ohci
, u32 info
,
502 dma_addr_t data
, int len
,
503 struct urb
*urb
, int index
)
505 struct td
*td
, *td_pt
;
506 struct urb_priv
*urb_priv
= urb
->hcpriv
;
507 int is_iso
= info
& TD_ISO
;
510 // ASSERT (index < urb_priv->length);
512 /* aim for only one interrupt per urb. mostly applies to control
513 * and iso; other urbs rarely need more than one TD per urb.
514 * this way, only final tds (or ones with an error) cause IRQs.
515 * at least immediately; use DI=6 in case any control request is
516 * tempted to die part way through. (and to force the hc to flush
517 * its donelist soonish, even on unlink paths.)
519 * NOTE: could delay interrupts even for the last TD, and get fewer
520 * interrupts ... increasing per-urb latency by sharing interrupts.
521 * Drivers that queue bulk urbs may request that behavior.
523 if (index
!= (urb_priv
->length
- 1)
524 || (urb
->transfer_flags
& URB_NO_INTERRUPT
))
525 info
|= TD_DI_SET (6);
527 /* use this td as the next dummy */
528 td_pt
= urb_priv
->td
[index
];
530 /* fill the old dummy TD */
531 td
= urb_priv
->td
[index
] = urb_priv
->ed
->dummy
;
532 urb_priv
->ed
->dummy
= td_pt
;
534 td
->ed
= urb_priv
->ed
;
535 td
->next_dl_td
= NULL
;
542 td
->hwINFO
= cpu_to_hc32 (ohci
, info
);
544 td
->hwCBP
= cpu_to_hc32 (ohci
, data
& 0xFFFFF000);
545 *ohci_hwPSWp(ohci
, td
, 0) = cpu_to_hc16 (ohci
,
546 (data
& 0x0FFF) | 0xE000);
547 td
->ed
->last_iso
= info
& 0xffff;
549 td
->hwCBP
= cpu_to_hc32 (ohci
, data
);
552 td
->hwBE
= cpu_to_hc32 (ohci
, data
+ len
- 1);
555 td
->hwNextTD
= cpu_to_hc32 (ohci
, td_pt
->td_dma
);
557 /* append to queue */
558 list_add_tail (&td
->td_list
, &td
->ed
->td_list
);
560 /* hash it for later reverse mapping */
561 hash
= TD_HASH_FUNC (td
->td_dma
);
562 td
->td_hash
= ohci
->td_hash
[hash
];
563 ohci
->td_hash
[hash
] = td
;
565 /* HC might read the TD (or cachelines) right away ... */
567 td
->ed
->hwTailP
= td
->hwNextTD
;
570 /*-------------------------------------------------------------------------*/
572 /* Prepare all TDs of a transfer, and queue them onto the ED.
573 * Caller guarantees HC is active.
574 * Usually the ED is already on the schedule, so TDs might be
575 * processed as soon as they're queued.
577 static void td_submit_urb (
578 struct ohci_hcd
*ohci
,
581 struct urb_priv
*urb_priv
= urb
->hcpriv
;
583 int data_len
= urb
->transfer_buffer_length
;
586 int is_out
= usb_pipeout (urb
->pipe
);
589 /* OHCI handles the bulk/interrupt data toggles itself. We just
590 * use the device toggle bits for resetting, and rely on the fact
591 * that resetting toggle is meaningless if the endpoint is active.
593 if (!usb_gettoggle (urb
->dev
, usb_pipeendpoint (urb
->pipe
), is_out
)) {
594 usb_settoggle (urb
->dev
, usb_pipeendpoint (urb
->pipe
),
596 urb_priv
->ed
->hwHeadP
&= ~cpu_to_hc32 (ohci
, ED_C
);
599 urb_priv
->td_cnt
= 0;
600 list_add (&urb_priv
->pending
, &ohci
->pending
);
603 data
= urb
->transfer_dma
;
607 /* NOTE: TD_CC is set so we can tell which TDs the HC processed by
608 * using TD_CC_GET, as well as by seeing them on the done list.
609 * (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.)
611 switch (urb_priv
->ed
->type
) {
613 /* Bulk and interrupt are identical except for where in the schedule
617 /* ... and periodic urbs have extra accounting */
618 periodic
= ohci_to_hcd(ohci
)->self
.bandwidth_int_reqs
++ == 0
619 && ohci_to_hcd(ohci
)->self
.bandwidth_isoc_reqs
== 0;
623 ? TD_T_TOGGLE
| TD_CC
| TD_DP_OUT
624 : TD_T_TOGGLE
| TD_CC
| TD_DP_IN
;
625 /* TDs _could_ transfer up to 8K each */
626 while (data_len
> 4096) {
627 td_fill (ohci
, info
, data
, 4096, urb
, cnt
);
632 /* maybe avoid ED halt on final TD short read */
633 if (!(urb
->transfer_flags
& URB_SHORT_NOT_OK
))
635 td_fill (ohci
, info
, data
, data_len
, urb
, cnt
);
637 if ((urb
->transfer_flags
& URB_ZERO_PACKET
)
638 && cnt
< urb_priv
->length
) {
639 td_fill (ohci
, info
, 0, 0, urb
, cnt
);
642 /* maybe kickstart bulk list */
643 if (urb_priv
->ed
->type
== PIPE_BULK
) {
645 ohci_writel (ohci
, OHCI_BLF
, &ohci
->regs
->cmdstatus
);
649 /* control manages DATA0/DATA1 toggle per-request; SETUP resets it,
650 * any DATA phase works normally, and the STATUS ack is special.
653 info
= TD_CC
| TD_DP_SETUP
| TD_T_DATA0
;
654 td_fill (ohci
, info
, urb
->setup_dma
, 8, urb
, cnt
++);
656 info
= TD_CC
| TD_R
| TD_T_DATA1
;
657 info
|= is_out
? TD_DP_OUT
: TD_DP_IN
;
658 /* NOTE: mishandles transfers >8K, some >4K */
659 td_fill (ohci
, info
, data
, data_len
, urb
, cnt
++);
661 info
= (is_out
|| data_len
== 0)
662 ? TD_CC
| TD_DP_IN
| TD_T_DATA1
663 : TD_CC
| TD_DP_OUT
| TD_T_DATA1
;
664 td_fill (ohci
, info
, data
, 0, urb
, cnt
++);
665 /* maybe kickstart control list */
667 ohci_writel (ohci
, OHCI_CLF
, &ohci
->regs
->cmdstatus
);
670 /* ISO has no retransmit, so no toggle; and it uses special TDs.
671 * Each TD could handle multiple consecutive frames (interval 1);
672 * we could often reduce the number of TDs here.
674 case PIPE_ISOCHRONOUS
:
675 for (cnt
= 0; cnt
< urb
->number_of_packets
; cnt
++) {
676 int frame
= urb
->start_frame
;
678 // FIXME scheduling should handle frame counter
679 // roll-around ... exotic case (and OHCI has
680 // a 2^16 iso range, vs other HCs max of 2^10)
681 frame
+= cnt
* urb
->interval
;
683 td_fill (ohci
, TD_CC
| TD_ISO
| frame
,
684 data
+ urb
->iso_frame_desc
[cnt
].offset
,
685 urb
->iso_frame_desc
[cnt
].length
, urb
, cnt
);
687 if (ohci_to_hcd(ohci
)->self
.bandwidth_isoc_reqs
== 0) {
688 if (quirk_amdiso(ohci
))
689 usb_amd_quirk_pll_disable();
690 if (quirk_amdprefetch(ohci
))
691 sb800_prefetch(ohci
, 1);
693 periodic
= ohci_to_hcd(ohci
)->self
.bandwidth_isoc_reqs
++ == 0
694 && ohci_to_hcd(ohci
)->self
.bandwidth_int_reqs
== 0;
698 /* start periodic dma if needed */
701 ohci
->hc_control
|= OHCI_CTRL_PLE
|OHCI_CTRL_IE
;
702 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
705 // ASSERT (urb_priv->length == cnt);
708 /*-------------------------------------------------------------------------*
709 * Done List handling functions
710 *-------------------------------------------------------------------------*/
712 /* calculate transfer length/status and update the urb */
713 static int td_done(struct ohci_hcd
*ohci
, struct urb
*urb
, struct td
*td
)
715 u32 tdINFO
= hc32_to_cpup (ohci
, &td
->hwINFO
);
717 int status
= -EINPROGRESS
;
719 list_del (&td
->td_list
);
721 /* ISO ... drivers see per-TD length/status */
722 if (tdINFO
& TD_ISO
) {
723 u16 tdPSW
= ohci_hwPSW(ohci
, td
, 0);
726 /* NOTE: assumes FC in tdINFO == 0, and that
727 * only the first of 0..MAXPSW psws is used.
730 cc
= (tdPSW
>> 12) & 0xF;
731 if (tdINFO
& TD_CC
) /* hc didn't touch? */
734 if (usb_pipeout (urb
->pipe
))
735 dlen
= urb
->iso_frame_desc
[td
->index
].length
;
737 /* short reads are always OK for ISO */
738 if (cc
== TD_DATAUNDERRUN
)
740 dlen
= tdPSW
& 0x3ff;
742 urb
->actual_length
+= dlen
;
743 urb
->iso_frame_desc
[td
->index
].actual_length
= dlen
;
744 urb
->iso_frame_desc
[td
->index
].status
= cc_to_error
[cc
];
746 if (cc
!= TD_CC_NOERROR
)
748 "urb %p iso td %p (%d) len %d cc %d\n",
749 urb
, td
, 1 + td
->index
, dlen
, cc
);
751 /* BULK, INT, CONTROL ... drivers see aggregate length/status,
752 * except that "setup" bytes aren't counted and "short" transfers
753 * might not be reported as errors.
756 int type
= usb_pipetype (urb
->pipe
);
757 u32 tdBE
= hc32_to_cpup (ohci
, &td
->hwBE
);
759 cc
= TD_CC_GET (tdINFO
);
761 /* update packet status if needed (short is normally ok) */
762 if (cc
== TD_DATAUNDERRUN
763 && !(urb
->transfer_flags
& URB_SHORT_NOT_OK
))
765 if (cc
!= TD_CC_NOERROR
&& cc
< 0x0E)
766 status
= cc_to_error
[cc
];
768 /* count all non-empty packets except control SETUP packet */
769 if ((type
!= PIPE_CONTROL
|| td
->index
!= 0) && tdBE
!= 0) {
771 urb
->actual_length
+= tdBE
- td
->data_dma
+ 1;
773 urb
->actual_length
+=
774 hc32_to_cpup (ohci
, &td
->hwCBP
)
778 if (cc
!= TD_CC_NOERROR
&& cc
< 0x0E)
780 "urb %p td %p (%d) cc %d, len=%d/%d\n",
781 urb
, td
, 1 + td
->index
, cc
,
783 urb
->transfer_buffer_length
);
788 /*-------------------------------------------------------------------------*/
790 static void ed_halted(struct ohci_hcd
*ohci
, struct td
*td
, int cc
)
792 struct urb
*urb
= td
->urb
;
793 urb_priv_t
*urb_priv
= urb
->hcpriv
;
794 struct ed
*ed
= td
->ed
;
795 struct list_head
*tmp
= td
->td_list
.next
;
796 __hc32 toggle
= ed
->hwHeadP
& cpu_to_hc32 (ohci
, ED_C
);
798 /* clear ed halt; this is the td that caused it, but keep it inactive
799 * until its urb->complete() has a chance to clean up.
801 ed
->hwINFO
|= cpu_to_hc32 (ohci
, ED_SKIP
);
803 ed
->hwHeadP
&= ~cpu_to_hc32 (ohci
, ED_H
);
805 /* Get rid of all later tds from this urb. We don't have
806 * to be careful: no errors and nothing was transferred.
807 * Also patch the ed so it looks as if those tds completed normally.
809 while (tmp
!= &ed
->td_list
) {
812 next
= list_entry (tmp
, struct td
, td_list
);
813 tmp
= next
->td_list
.next
;
815 if (next
->urb
!= urb
)
818 /* NOTE: if multi-td control DATA segments get supported,
819 * this urb had one of them, this td wasn't the last td
820 * in that segment (TD_R clear), this ed halted because
821 * of a short read, _and_ URB_SHORT_NOT_OK is clear ...
822 * then we need to leave the control STATUS packet queued
826 list_del(&next
->td_list
);
828 ed
->hwHeadP
= next
->hwNextTD
| toggle
;
831 /* help for troubleshooting: report anything that
832 * looks odd ... that doesn't include protocol stalls
833 * (or maybe some other things)
836 case TD_DATAUNDERRUN
:
837 if ((urb
->transfer_flags
& URB_SHORT_NOT_OK
) == 0)
841 if (usb_pipecontrol (urb
->pipe
))
846 "urb %p path %s ep%d%s %08x cc %d --> status %d\n",
847 urb
, urb
->dev
->devpath
,
848 usb_pipeendpoint (urb
->pipe
),
849 usb_pipein (urb
->pipe
) ? "in" : "out",
850 hc32_to_cpu (ohci
, td
->hwINFO
),
851 cc
, cc_to_error
[cc
]);
855 /* replies to the request have to be on a FIFO basis so
856 * we unreverse the hc-reversed done-list
858 static struct td
*dl_reverse_done_list (struct ohci_hcd
*ohci
)
861 struct td
*td_rev
= NULL
;
862 struct td
*td
= NULL
;
864 td_dma
= hc32_to_cpup (ohci
, &ohci
->hcca
->done_head
);
865 ohci
->hcca
->done_head
= 0;
868 /* get TD from hc's singly linked list, and
869 * prepend to ours. ed->td_list changes later.
874 td
= dma_to_td (ohci
, td_dma
);
876 ohci_err (ohci
, "bad entry %8x\n", td_dma
);
880 td
->hwINFO
|= cpu_to_hc32 (ohci
, TD_DONE
);
881 cc
= TD_CC_GET (hc32_to_cpup (ohci
, &td
->hwINFO
));
883 /* Non-iso endpoints can halt on error; un-halt,
884 * and dequeue any other TDs from this urb.
885 * No other TD could have caused the halt.
887 if (cc
!= TD_CC_NOERROR
888 && (td
->ed
->hwHeadP
& cpu_to_hc32 (ohci
, ED_H
)))
889 ed_halted(ohci
, td
, cc
);
891 td
->next_dl_td
= td_rev
;
893 td_dma
= hc32_to_cpup (ohci
, &td
->hwNextTD
);
898 /*-------------------------------------------------------------------------*/
900 /* there are some urbs/eds to unlink; called in_irq(), with HCD locked */
902 finish_unlinks (struct ohci_hcd
*ohci
, u16 tick
)
904 struct ed
*ed
, **last
;
907 for (last
= &ohci
->ed_rm_list
, ed
= *last
; ed
!= NULL
; ed
= *last
) {
908 struct list_head
*entry
, *tmp
;
909 int completed
, modified
;
912 /* only take off EDs that the HC isn't using, accounting for
913 * frame counter wraps and EDs with partially retired TDs
915 if (likely(ohci
->rh_state
== OHCI_RH_RUNNING
)) {
916 if (tick_before (tick
, ed
->tick
)) {
922 if (!list_empty (&ed
->td_list
)) {
926 td
= list_entry (ed
->td_list
.next
, struct td
,
928 head
= hc32_to_cpu (ohci
, ed
->hwHeadP
) &
931 /* INTR_WDH may need to clean up first */
932 if (td
->td_dma
!= head
) {
933 if (ed
== ohci
->ed_to_check
)
934 ohci
->ed_to_check
= NULL
;
941 /* reentrancy: if we drop the schedule lock, someone might
942 * have modified this list. normally it's just prepending
943 * entries (which we'd ignore), but paranoia won't hurt.
949 /* unlink urbs as requested, but rescan the list after
950 * we call a completion since it might have unlinked
951 * another (earlier) urb
953 * When we get here, the HC doesn't see this ed. But it
954 * must not be rescheduled until all completed URBs have
955 * been given back to the driver.
960 list_for_each_safe (entry
, tmp
, &ed
->td_list
) {
963 urb_priv_t
*urb_priv
;
967 td
= list_entry (entry
, struct td
, td_list
);
969 urb_priv
= td
->urb
->hcpriv
;
971 if (!urb
->unlinked
) {
972 prev
= &td
->hwNextTD
;
976 /* patch pointer hc uses */
977 savebits
= *prev
& ~cpu_to_hc32 (ohci
, TD_MASK
);
978 *prev
= td
->hwNextTD
| savebits
;
980 /* If this was unlinked, the TD may not have been
981 * retired ... so manually save the data toggle.
982 * The controller ignores the value we save for
983 * control and ISO endpoints.
985 tdINFO
= hc32_to_cpup(ohci
, &td
->hwINFO
);
986 if ((tdINFO
& TD_T
) == TD_T_DATA0
)
987 ed
->hwHeadP
&= ~cpu_to_hc32(ohci
, ED_C
);
988 else if ((tdINFO
& TD_T
) == TD_T_DATA1
)
989 ed
->hwHeadP
|= cpu_to_hc32(ohci
, ED_C
);
991 /* HC may have partly processed this TD */
992 td_done (ohci
, urb
, td
);
995 /* if URB is done, clean up */
996 if (urb_priv
->td_cnt
== urb_priv
->length
) {
997 modified
= completed
= 1;
998 finish_urb(ohci
, urb
, 0);
1001 if (completed
&& !list_empty (&ed
->td_list
))
1004 /* ED's now officially unlinked, hc doesn't see */
1005 ed
->state
= ED_IDLE
;
1006 if (quirk_zfmicro(ohci
) && ed
->type
== PIPE_INTERRUPT
)
1007 ohci
->eds_scheduled
--;
1008 ed
->hwHeadP
&= ~cpu_to_hc32(ohci
, ED_H
);
1011 ed
->hwINFO
&= ~cpu_to_hc32 (ohci
, ED_SKIP
| ED_DEQUEUE
);
1013 /* but if there's work queued, reschedule */
1014 if (!list_empty (&ed
->td_list
)) {
1015 if (ohci
->rh_state
== OHCI_RH_RUNNING
)
1016 ed_schedule (ohci
, ed
);
1023 /* maybe reenable control and bulk lists */
1024 if (ohci
->rh_state
== OHCI_RH_RUNNING
&& !ohci
->ed_rm_list
) {
1025 u32 command
= 0, control
= 0;
1027 if (ohci
->ed_controltail
) {
1028 command
|= OHCI_CLF
;
1029 if (quirk_zfmicro(ohci
))
1031 if (!(ohci
->hc_control
& OHCI_CTRL_CLE
)) {
1032 control
|= OHCI_CTRL_CLE
;
1033 ohci_writel (ohci
, 0,
1034 &ohci
->regs
->ed_controlcurrent
);
1037 if (ohci
->ed_bulktail
) {
1038 command
|= OHCI_BLF
;
1039 if (quirk_zfmicro(ohci
))
1041 if (!(ohci
->hc_control
& OHCI_CTRL_BLE
)) {
1042 control
|= OHCI_CTRL_BLE
;
1043 ohci_writel (ohci
, 0,
1044 &ohci
->regs
->ed_bulkcurrent
);
1048 /* CLE/BLE to enable, CLF/BLF to (maybe) kickstart */
1050 ohci
->hc_control
|= control
;
1051 if (quirk_zfmicro(ohci
))
1053 ohci_writel (ohci
, ohci
->hc_control
,
1054 &ohci
->regs
->control
);
1057 if (quirk_zfmicro(ohci
))
1059 ohci_writel (ohci
, command
, &ohci
->regs
->cmdstatus
);
1066 /*-------------------------------------------------------------------------*/
1069 * Used to take back a TD from the host controller. This would normally be
1070 * called from within dl_done_list, however it may be called directly if the
1071 * HC no longer sees the TD and it has not appeared on the donelist (after
1072 * two frames). This bug has been observed on ZF Micro systems.
1074 static void takeback_td(struct ohci_hcd
*ohci
, struct td
*td
)
1076 struct urb
*urb
= td
->urb
;
1077 urb_priv_t
*urb_priv
= urb
->hcpriv
;
1078 struct ed
*ed
= td
->ed
;
1081 /* update URB's length and status from TD */
1082 status
= td_done(ohci
, urb
, td
);
1085 /* If all this urb's TDs are done, call complete() */
1086 if (urb_priv
->td_cnt
== urb_priv
->length
)
1087 finish_urb(ohci
, urb
, status
);
1089 /* clean schedule: unlink EDs that are no longer busy */
1090 if (list_empty(&ed
->td_list
)) {
1091 if (ed
->state
== ED_OPER
)
1092 start_ed_unlink(ohci
, ed
);
1094 /* ... reenabling halted EDs only after fault cleanup */
1095 } else if ((ed
->hwINFO
& cpu_to_hc32(ohci
, ED_SKIP
| ED_DEQUEUE
))
1096 == cpu_to_hc32(ohci
, ED_SKIP
)) {
1097 td
= list_entry(ed
->td_list
.next
, struct td
, td_list
);
1098 if (!(td
->hwINFO
& cpu_to_hc32(ohci
, TD_DONE
))) {
1099 ed
->hwINFO
&= ~cpu_to_hc32(ohci
, ED_SKIP
);
1100 /* ... hc may need waking-up */
1103 ohci_writel(ohci
, OHCI_CLF
,
1104 &ohci
->regs
->cmdstatus
);
1107 ohci_writel(ohci
, OHCI_BLF
,
1108 &ohci
->regs
->cmdstatus
);
1116 * Process normal completions (error or success) and clean the schedules.
1118 * This is the main path for handing urbs back to drivers. The only other
1119 * normal path is finish_unlinks(), which unlinks URBs using ed_rm_list,
1120 * instead of scanning the (re-reversed) donelist as this does. There's
1121 * an abnormal path too, handling a quirk in some Compaq silicon: URBs
1122 * with TDs that appear to be orphaned are directly reclaimed.
1125 dl_done_list (struct ohci_hcd
*ohci
)
1127 struct td
*td
= dl_reverse_done_list (ohci
);
1130 struct td
*td_next
= td
->next_dl_td
;
1131 takeback_td(ohci
, td
);