2 * Universal Host Controller Interface driver for USB.
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
6 * (C) Copyright 1999 Linus Torvalds
7 * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
8 * (C) Copyright 1999 Randy Dunlap
9 * (C) Copyright 1999 Georg Acher, acher@in.tum.de
10 * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
11 * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
12 * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at
13 * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface
14 * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
15 * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
16 * (C) Copyright 2004-2005 Alan Stern, stern@rowland.harvard.edu
18 * Intel documents this fairly well, and as far as I know there
19 * are no royalties or anything like that, but even so there are
20 * people who decided that they want to do the same thing in a
21 * completely different way.
25 #include <linux/config.h>
26 #ifdef CONFIG_USB_DEBUG
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/kernel.h>
34 #include <linux/init.h>
35 #include <linux/delay.h>
36 #include <linux/ioport.h>
37 #include <linux/sched.h>
38 #include <linux/slab.h>
39 #include <linux/smp_lock.h>
40 #include <linux/errno.h>
41 #include <linux/unistd.h>
42 #include <linux/interrupt.h>
43 #include <linux/spinlock.h>
44 #include <linux/debugfs.h>
46 #include <linux/dmapool.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/usb.h>
49 #include <linux/bitops.h>
51 #include <asm/uaccess.h>
54 #include <asm/system.h>
56 #include "../core/hcd.h"
62 #define DRIVER_VERSION "v2.3"
63 #define DRIVER_AUTHOR "Linus 'Frodo Rabbit' Torvalds, Johannes Erdfelt, \
64 Randy Dunlap, Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber, \
66 #define DRIVER_DESC "USB Universal Host Controller Interface driver"
69 * debug = 0, no debugging messages
70 * debug = 1, dump failed URB's except for stalls
71 * debug = 2, dump all failed URB's (including stalls)
72 * show all queues in /debug/uhci/[pci_addr]
73 * debug = 3, show all TD's in URB's when dumping
80 module_param(debug
, int, S_IRUGO
| S_IWUSR
);
81 MODULE_PARM_DESC(debug
, "Debug level");
83 #define ERRBUF_LEN (32 * 1024)
85 static kmem_cache_t
*uhci_up_cachep
; /* urb_priv */
87 static void suspend_rh(struct uhci_hcd
*uhci
, enum uhci_rh_state new_state
);
88 static void wakeup_rh(struct uhci_hcd
*uhci
);
89 static void uhci_get_current_frame_number(struct uhci_hcd
*uhci
);
91 /* If a transfer is still active after this much time, turn off FSBR */
92 #define IDLE_TIMEOUT msecs_to_jiffies(50)
93 #define FSBR_DELAY msecs_to_jiffies(50)
95 /* When we timeout an idle transfer for FSBR, we'll switch it over to */
96 /* depth first traversal. We'll do it in groups of this number of TD's */
97 /* to make sure it doesn't hog all of the bandwidth */
98 #define DEPTH_INTERVAL 5
100 static inline void restart_timer(struct uhci_hcd
*uhci
)
102 mod_timer(&uhci
->stall_timer
, jiffies
+ msecs_to_jiffies(100));
105 #include "uhci-hub.c"
106 #include "uhci-debug.c"
110 * Make sure the controller is completely inactive, unable to
111 * generate interrupts or do DMA.
113 static void reset_hc(struct uhci_hcd
*uhci
)
117 /* Turn off PIRQ enable and SMI enable. (This also turns off the
118 * BIOS's USB Legacy Support.) Turn off all the R/WC bits too.
120 pci_write_config_word(to_pci_dev(uhci_dev(uhci
)), USBLEGSUP
,
123 /* Reset the HC - this will force us to get a
124 * new notification of any already connected
125 * ports due to the virtual disconnect that it
128 outw(USBCMD_HCRESET
, uhci
->io_addr
+ USBCMD
);
131 if (inw(uhci
->io_addr
+ USBCMD
) & USBCMD_HCRESET
)
132 dev_warn(uhci_dev(uhci
), "HCRESET not completed yet!\n");
134 /* Just to be safe, disable interrupt requests and
135 * make sure the controller is stopped.
137 outw(0, uhci
->io_addr
+ USBINTR
);
138 outw(0, uhci
->io_addr
+ USBCMD
);
140 /* HCRESET doesn't affect the Suspend, Reset, and Resume Detect
141 * bits in the port status and control registers.
142 * We have to clear them by hand.
144 for (port
= 0; port
< uhci
->rh_numports
; ++port
)
145 outw(0, uhci
->io_addr
+ USBPORTSC1
+ (port
* 2));
147 uhci
->port_c_suspend
= uhci
->suspended_ports
=
148 uhci
->resuming_ports
= 0;
149 uhci
->rh_state
= UHCI_RH_RESET
;
150 uhci
->is_stopped
= UHCI_IS_STOPPED
;
151 uhci_to_hcd(uhci
)->state
= HC_STATE_HALT
;
152 uhci_to_hcd(uhci
)->poll_rh
= 0;
156 * Last rites for a defunct/nonfunctional controller
158 static void hc_died(struct uhci_hcd
*uhci
)
161 uhci
->hc_inaccessible
= 1;
162 del_timer(&uhci
->stall_timer
);
166 * Initialize a controller that was newly discovered or has just been
167 * resumed. In either case we can't be sure of its previous state.
169 static void check_and_reset_hc(struct uhci_hcd
*uhci
)
172 unsigned int cmd
, intr
;
175 * When restarting a suspended controller, we expect all the
176 * settings to be the same as we left them:
178 * PIRQ and SMI disabled, no R/W bits set in USBLEGSUP;
179 * Controller is stopped and configured with EGSM set;
180 * No interrupts enabled except possibly Resume Detect.
182 * If any of these conditions are violated we do a complete reset.
184 pci_read_config_word(to_pci_dev(uhci_dev(uhci
)), USBLEGSUP
, &legsup
);
185 if (legsup
& ~(USBLEGSUP_RO
| USBLEGSUP_RWC
)) {
186 dev_dbg(uhci_dev(uhci
), "%s: legsup = 0x%04x\n",
187 __FUNCTION__
, legsup
);
191 cmd
= inw(uhci
->io_addr
+ USBCMD
);
192 if ((cmd
& USBCMD_RS
) || !(cmd
& USBCMD_CF
) || !(cmd
& USBCMD_EGSM
)) {
193 dev_dbg(uhci_dev(uhci
), "%s: cmd = 0x%04x\n",
198 intr
= inw(uhci
->io_addr
+ USBINTR
);
199 if (intr
& (~USBINTR_RESUME
)) {
200 dev_dbg(uhci_dev(uhci
), "%s: intr = 0x%04x\n",
207 dev_dbg(uhci_dev(uhci
), "Performing full reset\n");
212 * Store the basic register settings needed by the controller.
214 static void configure_hc(struct uhci_hcd
*uhci
)
216 /* Set the frame length to the default: 1 ms exactly */
217 outb(USBSOF_DEFAULT
, uhci
->io_addr
+ USBSOF
);
219 /* Store the frame list base address */
220 outl(uhci
->fl
->dma_handle
, uhci
->io_addr
+ USBFLBASEADD
);
222 /* Set the current frame number */
223 outw(uhci
->frame_number
, uhci
->io_addr
+ USBFRNUM
);
225 /* Mark controller as running before we enable interrupts */
226 uhci_to_hcd(uhci
)->state
= HC_STATE_RUNNING
;
230 pci_write_config_word(to_pci_dev(uhci_dev(uhci
)), USBLEGSUP
,
235 static int resume_detect_interrupts_are_broken(struct uhci_hcd
*uhci
)
239 switch (to_pci_dev(uhci_dev(uhci
))->vendor
) {
243 case PCI_VENDOR_ID_GENESYS
:
244 /* Genesys Logic's GL880S controllers don't generate
245 * resume-detect interrupts.
249 case PCI_VENDOR_ID_INTEL
:
250 /* Some of Intel's USB controllers have a bug that causes
251 * resume-detect interrupts if any port has an over-current
252 * condition. To make matters worse, some motherboards
253 * hardwire unused USB ports' over-current inputs active!
254 * To prevent problems, we will not enable resume-detect
255 * interrupts if any ports are OC.
257 for (port
= 0; port
< uhci
->rh_numports
; ++port
) {
258 if (inw(uhci
->io_addr
+ USBPORTSC1
+ port
* 2) &
267 static void suspend_rh(struct uhci_hcd
*uhci
, enum uhci_rh_state new_state
)
268 __releases(uhci
->lock
)
269 __acquires(uhci
->lock
)
274 auto_stop
= (new_state
== UHCI_RH_AUTO_STOPPED
);
275 dev_dbg(uhci_dev(uhci
), "%s%s\n", __FUNCTION__
,
276 (auto_stop
? " (auto-stop)" : ""));
278 /* If we get a suspend request when we're already auto-stopped
279 * then there's nothing to do.
281 if (uhci
->rh_state
== UHCI_RH_AUTO_STOPPED
) {
282 uhci
->rh_state
= new_state
;
286 /* Enable resume-detect interrupts if they work.
287 * Then enter Global Suspend mode, still configured.
289 int_enable
= (resume_detect_interrupts_are_broken(uhci
) ?
291 outw(int_enable
, uhci
->io_addr
+ USBINTR
);
292 outw(USBCMD_EGSM
| USBCMD_CF
, uhci
->io_addr
+ USBCMD
);
296 /* If we're auto-stopping then no devices have been attached
297 * for a while, so there shouldn't be any active URBs and the
298 * controller should stop after a few microseconds. Otherwise
299 * we will give the controller one frame to stop.
301 if (!auto_stop
&& !(inw(uhci
->io_addr
+ USBSTS
) & USBSTS_HCH
)) {
302 uhci
->rh_state
= UHCI_RH_SUSPENDING
;
303 spin_unlock_irq(&uhci
->lock
);
305 spin_lock_irq(&uhci
->lock
);
306 if (uhci
->hc_inaccessible
) /* Died */
309 if (!(inw(uhci
->io_addr
+ USBSTS
) & USBSTS_HCH
))
310 dev_warn(uhci_dev(uhci
), "Controller not stopped yet!\n");
312 uhci_get_current_frame_number(uhci
);
315 uhci
->rh_state
= new_state
;
316 uhci
->is_stopped
= UHCI_IS_STOPPED
;
317 del_timer(&uhci
->stall_timer
);
318 uhci_to_hcd(uhci
)->poll_rh
= !int_enable
;
320 uhci_scan_schedule(uhci
, NULL
);
323 static void start_rh(struct uhci_hcd
*uhci
)
325 uhci
->is_stopped
= 0;
328 /* Mark it configured and running with a 64-byte max packet.
329 * All interrupts are enabled, even though RESUME won't do anything.
331 outw(USBCMD_RS
| USBCMD_CF
| USBCMD_MAXP
, uhci
->io_addr
+ USBCMD
);
332 outw(USBINTR_TIMEOUT
| USBINTR_RESUME
| USBINTR_IOC
| USBINTR_SP
,
333 uhci
->io_addr
+ USBINTR
);
335 uhci
->rh_state
= UHCI_RH_RUNNING
;
336 uhci_to_hcd(uhci
)->poll_rh
= 1;
340 static void wakeup_rh(struct uhci_hcd
*uhci
)
341 __releases(uhci
->lock
)
342 __acquires(uhci
->lock
)
344 dev_dbg(uhci_dev(uhci
), "%s%s\n", __FUNCTION__
,
345 uhci
->rh_state
== UHCI_RH_AUTO_STOPPED
?
346 " (auto-start)" : "");
348 /* If we are auto-stopped then no devices are attached so there's
349 * no need for wakeup signals. Otherwise we send Global Resume
352 if (uhci
->rh_state
== UHCI_RH_SUSPENDED
) {
353 uhci
->rh_state
= UHCI_RH_RESUMING
;
354 outw(USBCMD_FGR
| USBCMD_EGSM
| USBCMD_CF
,
355 uhci
->io_addr
+ USBCMD
);
356 spin_unlock_irq(&uhci
->lock
);
358 spin_lock_irq(&uhci
->lock
);
359 if (uhci
->hc_inaccessible
) /* Died */
362 /* End Global Resume and wait for EOP to be sent */
363 outw(USBCMD_CF
, uhci
->io_addr
+ USBCMD
);
366 if (inw(uhci
->io_addr
+ USBCMD
) & USBCMD_FGR
)
367 dev_warn(uhci_dev(uhci
), "FGR not stopped yet!\n");
372 /* Restart root hub polling */
373 mod_timer(&uhci_to_hcd(uhci
)->rh_timer
, jiffies
);
376 static void stall_callback(unsigned long _uhci
)
378 struct uhci_hcd
*uhci
= (struct uhci_hcd
*) _uhci
;
381 spin_lock_irqsave(&uhci
->lock
, flags
);
382 uhci_scan_schedule(uhci
, NULL
);
385 if (!uhci
->is_stopped
)
387 spin_unlock_irqrestore(&uhci
->lock
, flags
);
390 static irqreturn_t
uhci_irq(struct usb_hcd
*hcd
, struct pt_regs
*regs
)
392 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
393 unsigned short status
;
397 * Read the interrupt status, and write it back to clear the
398 * interrupt cause. Contrary to the UHCI specification, the
399 * "HC Halted" status bit is persistent: it is RO, not R/WC.
401 status
= inw(uhci
->io_addr
+ USBSTS
);
402 if (!(status
& ~USBSTS_HCH
)) /* shared interrupt, not mine */
404 outw(status
, uhci
->io_addr
+ USBSTS
); /* Clear it */
406 if (status
& ~(USBSTS_USBINT
| USBSTS_ERROR
| USBSTS_RD
)) {
407 if (status
& USBSTS_HSE
)
408 dev_err(uhci_dev(uhci
), "host system error, "
410 if (status
& USBSTS_HCPE
)
411 dev_err(uhci_dev(uhci
), "host controller process "
412 "error, something bad happened!\n");
413 if (status
& USBSTS_HCH
) {
414 spin_lock_irqsave(&uhci
->lock
, flags
);
415 if (uhci
->rh_state
>= UHCI_RH_RUNNING
) {
416 dev_err(uhci_dev(uhci
),
417 "host controller halted, "
420 spin_unlock_irqrestore(&uhci
->lock
, flags
);
423 spin_unlock_irqrestore(&uhci
->lock
, flags
);
427 if (status
& USBSTS_RD
)
428 usb_hcd_poll_rh_status(hcd
);
430 spin_lock_irqsave(&uhci
->lock
, flags
);
431 uhci_scan_schedule(uhci
, regs
);
432 spin_unlock_irqrestore(&uhci
->lock
, flags
);
438 * Store the current frame number in uhci->frame_number if the controller
441 static void uhci_get_current_frame_number(struct uhci_hcd
*uhci
)
443 if (!uhci
->is_stopped
)
444 uhci
->frame_number
= inw(uhci
->io_addr
+ USBFRNUM
);
448 * De-allocate all resources
450 static void release_uhci(struct uhci_hcd
*uhci
)
454 for (i
= 0; i
< UHCI_NUM_SKELQH
; i
++)
455 if (uhci
->skelqh
[i
]) {
456 uhci_free_qh(uhci
, uhci
->skelqh
[i
]);
457 uhci
->skelqh
[i
] = NULL
;
461 uhci_free_td(uhci
, uhci
->term_td
);
462 uhci
->term_td
= NULL
;
466 dma_pool_destroy(uhci
->qh_pool
);
467 uhci
->qh_pool
= NULL
;
471 dma_pool_destroy(uhci
->td_pool
);
472 uhci
->td_pool
= NULL
;
476 dma_free_coherent(uhci_dev(uhci
), sizeof(*uhci
->fl
),
477 uhci
->fl
, uhci
->fl
->dma_handle
);
482 debugfs_remove(uhci
->dentry
);
487 static int uhci_reset(struct usb_hcd
*hcd
)
489 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
490 unsigned io_size
= (unsigned) hcd
->rsrc_len
;
493 uhci
->io_addr
= (unsigned long) hcd
->rsrc_start
;
495 /* The UHCI spec says devices must have 2 ports, and goes on to say
496 * they may have more but gives no way to determine how many there
497 * are. However, according to the UHCI spec, Bit 7 of the port
498 * status and control register is always set to 1. So we try to
499 * use this to our advantage.
501 for (port
= 0; port
< (io_size
- USBPORTSC1
) / 2; port
++) {
502 unsigned int portstatus
;
504 portstatus
= inw(uhci
->io_addr
+ USBPORTSC1
+ (port
* 2));
505 if (!(portstatus
& 0x0080))
509 dev_info(uhci_dev(uhci
), "detected %d ports\n", port
);
511 /* Anything less than 2 or greater than 7 is weird,
512 * so we'll ignore it.
514 if (port
< 2 || port
> UHCI_RH_MAXCHILD
) {
515 dev_info(uhci_dev(uhci
), "port count misdetected? "
516 "forcing to 2 ports\n");
519 uhci
->rh_numports
= port
;
521 /* Kick BIOS off this hardware and reset if the controller
522 * isn't already safely quiescent.
524 check_and_reset_hc(uhci
);
529 * Allocate a frame list, and then setup the skeleton
531 * The hardware doesn't really know any difference
532 * in the queues, but the order does matter for the
533 * protocols higher up. The order is:
535 * - any isochronous events handled before any
536 * of the queues. We don't do that here, because
537 * we'll create the actual TD entries on demand.
538 * - The first queue is the interrupt queue.
539 * - The second queue is the control queue, split into low- and full-speed
540 * - The third queue is bulk queue.
541 * - The fourth queue is the bandwidth reclamation queue, which loops back
542 * to the full-speed control queue.
544 static int uhci_start(struct usb_hcd
*hcd
)
546 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
549 dma_addr_t dma_handle
;
550 struct usb_device
*udev
;
551 struct dentry
*dentry
;
553 hcd
->uses_new_polling
= 1;
554 if (pci_find_capability(to_pci_dev(uhci_dev(uhci
)), PCI_CAP_ID_PM
))
555 hcd
->can_wakeup
= 1; /* Assume it supports PME# */
557 dentry
= debugfs_create_file(hcd
->self
.bus_name
,
558 S_IFREG
|S_IRUGO
|S_IWUSR
, uhci_debugfs_root
, uhci
,
559 &uhci_debug_operations
);
561 dev_err(uhci_dev(uhci
),
562 "couldn't create uhci debugfs entry\n");
564 goto err_create_debug_entry
;
566 uhci
->dentry
= dentry
;
569 uhci
->fsbrtimeout
= 0;
571 spin_lock_init(&uhci
->lock
);
572 INIT_LIST_HEAD(&uhci
->qh_remove_list
);
574 INIT_LIST_HEAD(&uhci
->td_remove_list
);
576 INIT_LIST_HEAD(&uhci
->urb_remove_list
);
578 INIT_LIST_HEAD(&uhci
->urb_list
);
580 INIT_LIST_HEAD(&uhci
->complete_list
);
582 init_waitqueue_head(&uhci
->waitqh
);
584 init_timer(&uhci
->stall_timer
);
585 uhci
->stall_timer
.function
= stall_callback
;
586 uhci
->stall_timer
.data
= (unsigned long) uhci
;
588 uhci
->fl
= dma_alloc_coherent(uhci_dev(uhci
), sizeof(*uhci
->fl
),
591 dev_err(uhci_dev(uhci
), "unable to allocate "
592 "consistent memory for frame list\n");
596 memset((void *)uhci
->fl
, 0, sizeof(*uhci
->fl
));
598 uhci
->fl
->dma_handle
= dma_handle
;
600 uhci
->td_pool
= dma_pool_create("uhci_td", uhci_dev(uhci
),
601 sizeof(struct uhci_td
), 16, 0);
602 if (!uhci
->td_pool
) {
603 dev_err(uhci_dev(uhci
), "unable to create td dma_pool\n");
604 goto err_create_td_pool
;
607 uhci
->qh_pool
= dma_pool_create("uhci_qh", uhci_dev(uhci
),
608 sizeof(struct uhci_qh
), 16, 0);
609 if (!uhci
->qh_pool
) {
610 dev_err(uhci_dev(uhci
), "unable to create qh dma_pool\n");
611 goto err_create_qh_pool
;
614 /* Initialize the root hub */
616 udev
= usb_alloc_dev(NULL
, &hcd
->self
, 0);
618 dev_err(uhci_dev(uhci
), "unable to allocate root hub\n");
619 goto err_alloc_root_hub
;
622 uhci
->term_td
= uhci_alloc_td(uhci
, udev
);
623 if (!uhci
->term_td
) {
624 dev_err(uhci_dev(uhci
), "unable to allocate terminating TD\n");
625 goto err_alloc_term_td
;
628 for (i
= 0; i
< UHCI_NUM_SKELQH
; i
++) {
629 uhci
->skelqh
[i
] = uhci_alloc_qh(uhci
, udev
);
630 if (!uhci
->skelqh
[i
]) {
631 dev_err(uhci_dev(uhci
), "unable to allocate QH\n");
632 goto err_alloc_skelqh
;
637 * 8 Interrupt queues; link all higher int queues to int1,
638 * then link int1 to control and control to bulk
640 uhci
->skel_int128_qh
->link
=
641 uhci
->skel_int64_qh
->link
=
642 uhci
->skel_int32_qh
->link
=
643 uhci
->skel_int16_qh
->link
=
644 uhci
->skel_int8_qh
->link
=
645 uhci
->skel_int4_qh
->link
=
646 uhci
->skel_int2_qh
->link
=
647 cpu_to_le32(uhci
->skel_int1_qh
->dma_handle
) | UHCI_PTR_QH
;
648 uhci
->skel_int1_qh
->link
= cpu_to_le32(uhci
->skel_ls_control_qh
->dma_handle
) | UHCI_PTR_QH
;
650 uhci
->skel_ls_control_qh
->link
= cpu_to_le32(uhci
->skel_fs_control_qh
->dma_handle
) | UHCI_PTR_QH
;
651 uhci
->skel_fs_control_qh
->link
= cpu_to_le32(uhci
->skel_bulk_qh
->dma_handle
) | UHCI_PTR_QH
;
652 uhci
->skel_bulk_qh
->link
= cpu_to_le32(uhci
->skel_term_qh
->dma_handle
) | UHCI_PTR_QH
;
654 /* This dummy TD is to work around a bug in Intel PIIX controllers */
655 uhci_fill_td(uhci
->term_td
, 0, (UHCI_NULL_DATA_SIZE
<< 21) |
656 (0x7f << TD_TOKEN_DEVADDR_SHIFT
) | USB_PID_IN
, 0);
657 uhci
->term_td
->link
= cpu_to_le32(uhci
->term_td
->dma_handle
);
659 uhci
->skel_term_qh
->link
= UHCI_PTR_TERM
;
660 uhci
->skel_term_qh
->element
= cpu_to_le32(uhci
->term_td
->dma_handle
);
663 * Fill the frame list: make all entries point to the proper
666 * The interrupt queues will be interleaved as evenly as possible.
667 * There's not much to be done about period-1 interrupts; they have
668 * to occur in every frame. But we can schedule period-2 interrupts
669 * in odd-numbered frames, period-4 interrupts in frames congruent
670 * to 2 (mod 4), and so on. This way each frame only has two
671 * interrupt QHs, which will help spread out bandwidth utilization.
673 for (i
= 0; i
< UHCI_NUMFRAMES
; i
++) {
677 * ffs (Find First bit Set) does exactly what we need:
678 * 1,3,5,... => ffs = 0 => use skel_int2_qh = skelqh[6],
679 * 2,6,10,... => ffs = 1 => use skel_int4_qh = skelqh[5], etc.
680 * ffs > 6 => not on any high-period queue, so use
681 * skel_int1_qh = skelqh[7].
682 * Add UHCI_NUMFRAMES to insure at least one bit is set.
684 irq
= 6 - (int) __ffs(i
+ UHCI_NUMFRAMES
);
688 /* Only place we don't use the frame list routines */
689 uhci
->fl
->frame
[i
] = UHCI_PTR_QH
|
690 cpu_to_le32(uhci
->skelqh
[irq
]->dma_handle
);
694 * Some architectures require a full mb() to enforce completion of
695 * the memory writes above before the I/O transfers in configure_hc().
702 udev
->speed
= USB_SPEED_FULL
;
704 if (usb_hcd_register_root_hub(udev
, hcd
) != 0) {
705 dev_err(uhci_dev(uhci
), "unable to start root hub\n");
707 goto err_start_root_hub
;
717 del_timer_sync(&uhci
->stall_timer
);
720 for (i
= 0; i
< UHCI_NUM_SKELQH
; i
++)
721 if (uhci
->skelqh
[i
]) {
722 uhci_free_qh(uhci
, uhci
->skelqh
[i
]);
723 uhci
->skelqh
[i
] = NULL
;
726 uhci_free_td(uhci
, uhci
->term_td
);
727 uhci
->term_td
= NULL
;
733 dma_pool_destroy(uhci
->qh_pool
);
734 uhci
->qh_pool
= NULL
;
737 dma_pool_destroy(uhci
->td_pool
);
738 uhci
->td_pool
= NULL
;
741 dma_free_coherent(uhci_dev(uhci
), sizeof(*uhci
->fl
),
742 uhci
->fl
, uhci
->fl
->dma_handle
);
746 debugfs_remove(uhci
->dentry
);
749 err_create_debug_entry
:
753 static void uhci_stop(struct usb_hcd
*hcd
)
755 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
757 spin_lock_irq(&uhci
->lock
);
759 uhci_scan_schedule(uhci
, NULL
);
760 spin_unlock_irq(&uhci
->lock
);
762 del_timer_sync(&uhci
->stall_timer
);
767 static int uhci_rh_suspend(struct usb_hcd
*hcd
)
769 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
771 spin_lock_irq(&uhci
->lock
);
772 if (!uhci
->hc_inaccessible
) /* Not dead */
773 suspend_rh(uhci
, UHCI_RH_SUSPENDED
);
774 spin_unlock_irq(&uhci
->lock
);
778 static int uhci_rh_resume(struct usb_hcd
*hcd
)
780 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
783 spin_lock_irq(&uhci
->lock
);
784 if (uhci
->hc_inaccessible
) {
785 if (uhci
->rh_state
== UHCI_RH_SUSPENDED
) {
786 dev_warn(uhci_dev(uhci
), "HC isn't running!\n");
789 /* Otherwise the HC is dead */
792 spin_unlock_irq(&uhci
->lock
);
796 static int uhci_suspend(struct usb_hcd
*hcd
, pm_message_t message
)
798 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
801 dev_dbg(uhci_dev(uhci
), "%s\n", __FUNCTION__
);
803 spin_lock_irq(&uhci
->lock
);
804 if (uhci
->hc_inaccessible
) /* Dead or already suspended */
807 #ifndef CONFIG_USB_SUSPEND
808 /* Otherwise this would never happen */
809 suspend_rh(uhci
, UHCI_RH_SUSPENDED
);
812 if (uhci
->rh_state
> UHCI_RH_SUSPENDED
) {
813 dev_warn(uhci_dev(uhci
), "Root hub isn't suspended!\n");
814 hcd
->state
= HC_STATE_RUNNING
;
819 /* All PCI host controllers are required to disable IRQ generation
820 * at the source, so we must turn off PIRQ.
822 pci_write_config_word(to_pci_dev(uhci_dev(uhci
)), USBLEGSUP
, 0);
823 uhci
->hc_inaccessible
= 1;
825 /* FIXME: Enable non-PME# remote wakeup? */
828 spin_unlock_irq(&uhci
->lock
);
830 del_timer_sync(&hcd
->rh_timer
);
834 static int uhci_resume(struct usb_hcd
*hcd
)
836 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
838 dev_dbg(uhci_dev(uhci
), "%s\n", __FUNCTION__
);
840 if (uhci
->rh_state
== UHCI_RH_RESET
) /* Dead */
842 spin_lock_irq(&uhci
->lock
);
844 /* FIXME: Disable non-PME# remote wakeup? */
846 uhci
->hc_inaccessible
= 0;
848 /* The BIOS may have changed the controller settings during a
849 * system wakeup. Check it and reconfigure to avoid problems.
851 check_and_reset_hc(uhci
);
854 #ifndef CONFIG_USB_SUSPEND
855 /* Otherwise this would never happen */
858 if (uhci
->rh_state
== UHCI_RH_RESET
)
859 suspend_rh(uhci
, UHCI_RH_SUSPENDED
);
861 spin_unlock_irq(&uhci
->lock
);
864 usb_hcd_poll_rh_status(hcd
);
869 /* Wait until all the URBs for a particular device/endpoint are gone */
870 static void uhci_hcd_endpoint_disable(struct usb_hcd
*hcd
,
871 struct usb_host_endpoint
*ep
)
873 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
875 wait_event_interruptible(uhci
->waitqh
, list_empty(&ep
->urb_list
));
878 static int uhci_hcd_get_frame_number(struct usb_hcd
*hcd
)
880 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
885 /* Minimize latency by avoiding the spinlock */
886 local_irq_save(flags
);
887 is_stopped
= uhci
->is_stopped
;
889 frame_number
= (is_stopped
? uhci
->frame_number
:
890 inw(uhci
->io_addr
+ USBFRNUM
));
891 local_irq_restore(flags
);
895 static const char hcd_name
[] = "uhci_hcd";
897 static const struct hc_driver uhci_driver
= {
898 .description
= hcd_name
,
899 .product_desc
= "UHCI Host Controller",
900 .hcd_priv_size
= sizeof(struct uhci_hcd
),
902 /* Generic hardware linkage */
906 /* Basic lifecycle operations */
910 .suspend
= uhci_suspend
,
911 .resume
= uhci_resume
,
912 .hub_suspend
= uhci_rh_suspend
,
913 .hub_resume
= uhci_rh_resume
,
917 .urb_enqueue
= uhci_urb_enqueue
,
918 .urb_dequeue
= uhci_urb_dequeue
,
920 .endpoint_disable
= uhci_hcd_endpoint_disable
,
921 .get_frame_number
= uhci_hcd_get_frame_number
,
923 .hub_status_data
= uhci_hub_status_data
,
924 .hub_control
= uhci_hub_control
,
927 static const struct pci_device_id uhci_pci_ids
[] = { {
928 /* handle any USB UHCI controller */
929 PCI_DEVICE_CLASS(((PCI_CLASS_SERIAL_USB
<< 8) | 0x00), ~0),
930 .driver_data
= (unsigned long) &uhci_driver
,
931 }, { /* end: all zeroes */ }
934 MODULE_DEVICE_TABLE(pci
, uhci_pci_ids
);
936 static struct pci_driver uhci_pci_driver
= {
937 .name
= (char *)hcd_name
,
938 .id_table
= uhci_pci_ids
,
940 .probe
= usb_hcd_pci_probe
,
941 .remove
= usb_hcd_pci_remove
,
944 .suspend
= usb_hcd_pci_suspend
,
945 .resume
= usb_hcd_pci_resume
,
949 static int __init
uhci_hcd_init(void)
951 int retval
= -ENOMEM
;
953 printk(KERN_INFO DRIVER_DESC
" " DRIVER_VERSION
"\n");
959 errbuf
= kmalloc(ERRBUF_LEN
, GFP_KERNEL
);
964 uhci_debugfs_root
= debugfs_create_dir("uhci", NULL
);
965 if (!uhci_debugfs_root
)
968 uhci_up_cachep
= kmem_cache_create("uhci_urb_priv",
969 sizeof(struct urb_priv
), 0, 0, NULL
, NULL
);
973 retval
= pci_register_driver(&uhci_pci_driver
);
980 if (kmem_cache_destroy(uhci_up_cachep
))
981 warn("not all urb_priv's were freed!");
984 debugfs_remove(uhci_debugfs_root
);
994 static void __exit
uhci_hcd_cleanup(void)
996 pci_unregister_driver(&uhci_pci_driver
);
998 if (kmem_cache_destroy(uhci_up_cachep
))
999 warn("not all urb_priv's were freed!");
1001 debugfs_remove(uhci_debugfs_root
);
1005 module_init(uhci_hcd_init
);
1006 module_exit(uhci_hcd_cleanup
);
1008 MODULE_AUTHOR(DRIVER_AUTHOR
);
1009 MODULE_DESCRIPTION(DRIVER_DESC
);
1010 MODULE_LICENSE("GPL");