2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/slab.h>
25 #include <asm/unaligned.h>
28 #include "xhci-trace.h"
30 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
31 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
32 PORT_RC | PORT_PLC | PORT_PE)
34 /* USB 3 BOS descriptor and a capability descriptors, combined.
35 * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
37 static u8 usb_bos_descriptor
[] = {
38 USB_DT_BOS_SIZE
, /* __u8 bLength, 5 bytes */
39 USB_DT_BOS
, /* __u8 bDescriptorType */
40 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
41 0x1, /* __u8 bNumDeviceCaps */
42 /* First device capability, SuperSpeed */
43 USB_DT_USB_SS_CAP_SIZE
, /* __u8 bLength, 10 bytes */
44 USB_DT_DEVICE_CAPABILITY
, /* Device Capability */
45 USB_SS_CAP_TYPE
, /* bDevCapabilityType, SUPERSPEED_USB */
46 0x00, /* bmAttributes, LTM off by default */
47 USB_5GBPS_OPERATION
, 0x00, /* wSpeedsSupported, 5Gbps only */
48 0x03, /* bFunctionalitySupport,
50 0x00, /* bU1DevExitLat, set later. */
51 0x00, 0x00, /* __le16 bU2DevExitLat, set later. */
52 /* Second device capability, SuperSpeedPlus */
53 0x1c, /* bLength 28, will be adjusted later */
54 USB_DT_DEVICE_CAPABILITY
, /* Device Capability */
55 USB_SSP_CAP_TYPE
, /* bDevCapabilityType SUPERSPEED_PLUS */
56 0x00, /* bReserved 0 */
57 0x23, 0x00, 0x00, 0x00, /* bmAttributes, SSAC=3 SSIC=1 */
58 0x01, 0x00, /* wFunctionalitySupport */
59 0x00, 0x00, /* wReserved 0 */
60 /* Default Sublink Speed Attributes, overwrite if custom PSI exists */
61 0x34, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, rx, ID = 4 */
62 0xb4, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, tx, ID = 4 */
63 0x35, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, rx, ID = 5 */
64 0xb5, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, tx, ID = 5 */
67 static int xhci_create_usb3_bos_desc(struct xhci_hcd
*xhci
, char *buf
,
72 u16 desc_size
, ssp_cap_size
, ssa_size
= 0;
75 desc_size
= USB_DT_BOS_SIZE
+ USB_DT_USB_SS_CAP_SIZE
;
76 ssp_cap_size
= sizeof(usb_bos_descriptor
) - desc_size
;
78 /* does xhci support USB 3.1 Enhanced SuperSpeed */
79 if (xhci
->usb3_rhub
.min_rev
>= 0x01) {
80 /* does xhci provide a PSI table for SSA speed attributes? */
81 if (xhci
->usb3_rhub
.psi_count
) {
82 /* two SSA entries for each unique PSI ID, RX and TX */
83 ssa_count
= xhci
->usb3_rhub
.psi_uid_count
* 2;
84 ssa_size
= ssa_count
* sizeof(u32
);
85 ssp_cap_size
-= 16; /* skip copying the default SSA */
87 desc_size
+= ssp_cap_size
;
90 memcpy(buf
, &usb_bos_descriptor
, min(desc_size
, wLength
));
93 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
95 put_unaligned_le16(desc_size
+ ssa_size
, &buf
[2]);
98 if (wLength
< USB_DT_BOS_SIZE
+ USB_DT_USB_SS_CAP_SIZE
)
101 /* Indicate whether the host has LTM support. */
102 temp
= readl(&xhci
->cap_regs
->hcc_params
);
104 buf
[8] |= USB_LTM_SUPPORT
;
106 /* Set the U1 and U2 exit latencies. */
107 if ((xhci
->quirks
& XHCI_LPM_SUPPORT
)) {
108 temp
= readl(&xhci
->cap_regs
->hcs_params3
);
109 buf
[12] = HCS_U1_LATENCY(temp
);
110 put_unaligned_le16(HCS_U2_LATENCY(temp
), &buf
[13]);
113 /* If PSI table exists, add the custom speed attributes from it */
114 if (usb3_1
&& xhci
->usb3_rhub
.psi_count
) {
115 u32 ssp_cap_base
, bm_attrib
, psi
;
118 ssp_cap_base
= USB_DT_BOS_SIZE
+ USB_DT_USB_SS_CAP_SIZE
;
120 if (wLength
< desc_size
)
122 buf
[ssp_cap_base
] = ssp_cap_size
+ ssa_size
;
124 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
125 bm_attrib
= (ssa_count
- 1) & 0x1f;
126 bm_attrib
|= (xhci
->usb3_rhub
.psi_uid_count
- 1) << 5;
127 put_unaligned_le32(bm_attrib
, &buf
[ssp_cap_base
+ 4]);
129 if (wLength
< desc_size
+ ssa_size
)
132 * Create the Sublink Speed Attributes (SSA) array.
133 * The xhci PSI field and USB 3.1 SSA fields are very similar,
134 * but link type bits 7:6 differ for values 01b and 10b.
135 * xhci has also only one PSI entry for a symmetric link when
136 * USB 3.1 requires two SSA entries (RX and TX) for every link
139 for (i
= 0; i
< xhci
->usb3_rhub
.psi_count
; i
++) {
140 psi
= xhci
->usb3_rhub
.psi
[i
];
141 psi
&= ~USB_SSP_SUBLINK_SPEED_RSVD
;
142 if ((psi
& PLT_MASK
) == PLT_SYM
) {
143 /* Symmetric, create SSA RX and TX from one PSI entry */
144 put_unaligned_le32(psi
, &buf
[offset
]);
145 psi
|= 1 << 7; /* turn entry to TX */
147 if (offset
>= desc_size
+ ssa_size
)
148 return desc_size
+ ssa_size
;
149 } else if ((psi
& PLT_MASK
) == PLT_ASYM_RX
) {
150 /* Asymetric RX, flip bits 7:6 for SSA */
153 put_unaligned_le32(psi
, &buf
[offset
]);
155 if (offset
>= desc_size
+ ssa_size
)
156 return desc_size
+ ssa_size
;
159 /* ssa_size is 0 for other than usb 3.1 hosts */
160 return desc_size
+ ssa_size
;
163 static void xhci_common_hub_descriptor(struct xhci_hcd
*xhci
,
164 struct usb_hub_descriptor
*desc
, int ports
)
168 desc
->bPwrOn2PwrGood
= 10; /* xhci section 5.4.9 says 20ms max */
169 desc
->bHubContrCurrent
= 0;
171 desc
->bNbrPorts
= ports
;
173 /* Bits 1:0 - support per-port power switching, or power always on */
174 if (HCC_PPC(xhci
->hcc_params
))
175 temp
|= HUB_CHAR_INDV_PORT_LPSM
;
177 temp
|= HUB_CHAR_NO_LPSM
;
178 /* Bit 2 - root hubs are not part of a compound device */
179 /* Bits 4:3 - individual port over current protection */
180 temp
|= HUB_CHAR_INDV_PORT_OCPM
;
181 /* Bits 6:5 - no TTs in root ports */
182 /* Bit 7 - no port indicators */
183 desc
->wHubCharacteristics
= cpu_to_le16(temp
);
186 /* Fill in the USB 2.0 roothub descriptor */
187 static void xhci_usb2_hub_descriptor(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
188 struct usb_hub_descriptor
*desc
)
192 __u8 port_removable
[(USB_MAXCHILDREN
+ 1 + 7) / 8];
196 ports
= xhci
->num_usb2_ports
;
198 xhci_common_hub_descriptor(xhci
, desc
, ports
);
199 desc
->bDescriptorType
= USB_DT_HUB
;
200 temp
= 1 + (ports
/ 8);
201 desc
->bDescLength
= USB_DT_HUB_NONVAR_SIZE
+ 2 * temp
;
203 /* The Device Removable bits are reported on a byte granularity.
204 * If the port doesn't exist within that byte, the bit is set to 0.
206 memset(port_removable
, 0, sizeof(port_removable
));
207 for (i
= 0; i
< ports
; i
++) {
208 portsc
= readl(xhci
->usb2_ports
[i
]);
209 /* If a device is removable, PORTSC reports a 0, same as in the
210 * hub descriptor DeviceRemovable bits.
212 if (portsc
& PORT_DEV_REMOVE
)
213 /* This math is hairy because bit 0 of DeviceRemovable
214 * is reserved, and bit 1 is for port 1, etc.
216 port_removable
[(i
+ 1) / 8] |= 1 << ((i
+ 1) % 8);
219 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
220 * ports on it. The USB 2.0 specification says that there are two
221 * variable length fields at the end of the hub descriptor:
222 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
223 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
224 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
225 * 0xFF, so we initialize the both arrays (DeviceRemovable and
226 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
227 * set of ports that actually exist.
229 memset(desc
->u
.hs
.DeviceRemovable
, 0xff,
230 sizeof(desc
->u
.hs
.DeviceRemovable
));
231 memset(desc
->u
.hs
.PortPwrCtrlMask
, 0xff,
232 sizeof(desc
->u
.hs
.PortPwrCtrlMask
));
234 for (i
= 0; i
< (ports
+ 1 + 7) / 8; i
++)
235 memset(&desc
->u
.hs
.DeviceRemovable
[i
], port_removable
[i
],
239 /* Fill in the USB 3.0 roothub descriptor */
240 static void xhci_usb3_hub_descriptor(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
241 struct usb_hub_descriptor
*desc
)
248 ports
= xhci
->num_usb3_ports
;
249 xhci_common_hub_descriptor(xhci
, desc
, ports
);
250 desc
->bDescriptorType
= USB_DT_SS_HUB
;
251 desc
->bDescLength
= USB_DT_SS_HUB_SIZE
;
253 /* header decode latency should be zero for roothubs,
254 * see section 4.23.5.2.
256 desc
->u
.ss
.bHubHdrDecLat
= 0;
257 desc
->u
.ss
.wHubDelay
= 0;
260 /* bit 0 is reserved, bit 1 is for port 1, etc. */
261 for (i
= 0; i
< ports
; i
++) {
262 portsc
= readl(xhci
->usb3_ports
[i
]);
263 if (portsc
& PORT_DEV_REMOVE
)
264 port_removable
|= 1 << (i
+ 1);
267 desc
->u
.ss
.DeviceRemovable
= cpu_to_le16(port_removable
);
270 static void xhci_hub_descriptor(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
271 struct usb_hub_descriptor
*desc
)
274 if (hcd
->speed
>= HCD_USB3
)
275 xhci_usb3_hub_descriptor(hcd
, xhci
, desc
);
277 xhci_usb2_hub_descriptor(hcd
, xhci
, desc
);
281 static unsigned int xhci_port_speed(unsigned int port_status
)
283 if (DEV_LOWSPEED(port_status
))
284 return USB_PORT_STAT_LOW_SPEED
;
285 if (DEV_HIGHSPEED(port_status
))
286 return USB_PORT_STAT_HIGH_SPEED
;
288 * FIXME: Yes, we should check for full speed, but the core uses that as
289 * a default in portspeed() in usb/core/hub.c (which is the only place
290 * USB_PORT_STAT_*_SPEED is used).
296 * These bits are Read Only (RO) and should be saved and written to the
297 * registers: 0, 3, 10:13, 30
298 * connect status, over-current status, port speed, and device removable.
299 * connect status and port speed are also sticky - meaning they're in
300 * the AUX well and they aren't changed by a hot, warm, or cold reset.
302 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
304 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
305 * bits 5:8, 9, 14:15, 25:27
306 * link state, port power, port indicator state, "wake on" enable state
308 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
310 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
313 #define XHCI_PORT_RW1S ((1<<4))
315 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
316 * bits 1, 17, 18, 19, 20, 21, 22, 23
317 * port enable/disable, and
318 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
319 * over-current, reset, link state, and L1 change
321 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
323 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
326 #define XHCI_PORT_RW ((1<<16))
328 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
331 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
334 * Given a port state, this function returns a value that would result in the
335 * port being in the same state, if the value was written to the port status
337 * Save Read Only (RO) bits and save read/write bits where
338 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
339 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
341 u32
xhci_port_state_to_neutral(u32 state
)
343 /* Save read-only status and port state */
344 return (state
& XHCI_PORT_RO
) | (state
& XHCI_PORT_RWS
);
348 * find slot id based on port number.
349 * @port: The one-based port number from one of the two split roothubs.
351 int xhci_find_slot_id_by_port(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
356 enum usb_device_speed speed
;
359 for (i
= 0; i
< MAX_HC_SLOTS
; i
++) {
362 speed
= xhci
->devs
[i
]->udev
->speed
;
363 if (((speed
>= USB_SPEED_SUPER
) == (hcd
->speed
>= HCD_USB3
))
364 && xhci
->devs
[i
]->fake_port
== port
) {
375 * It issues stop endpoint command for EP 0 to 30. And wait the last command
377 * suspend will set to 1, if suspend bit need to set in command.
379 static int xhci_stop_device(struct xhci_hcd
*xhci
, int slot_id
, int suspend
)
381 struct xhci_virt_device
*virt_dev
;
382 struct xhci_command
*cmd
;
388 virt_dev
= xhci
->devs
[slot_id
];
392 trace_xhci_stop_device(virt_dev
);
394 cmd
= xhci_alloc_command(xhci
, false, true, GFP_NOIO
);
398 spin_lock_irqsave(&xhci
->lock
, flags
);
399 for (i
= LAST_EP_INDEX
; i
> 0; i
--) {
400 if (virt_dev
->eps
[i
].ring
&& virt_dev
->eps
[i
].ring
->dequeue
) {
401 struct xhci_command
*command
;
402 command
= xhci_alloc_command(xhci
, false, false,
405 spin_unlock_irqrestore(&xhci
->lock
, flags
);
406 xhci_free_command(xhci
, cmd
);
410 xhci_queue_stop_endpoint(xhci
, command
, slot_id
, i
,
414 xhci_queue_stop_endpoint(xhci
, cmd
, slot_id
, 0, suspend
);
415 xhci_ring_cmd_db(xhci
);
416 spin_unlock_irqrestore(&xhci
->lock
, flags
);
418 /* Wait for last stop endpoint command to finish */
419 wait_for_completion(cmd
->completion
);
421 if (cmd
->status
== COMP_COMMAND_ABORTED
||
422 cmd
->status
== COMP_COMMAND_RING_STOPPED
) {
423 xhci_warn(xhci
, "Timeout while waiting for stop endpoint command\n");
426 xhci_free_command(xhci
, cmd
);
431 * Ring device, it rings the all doorbells unconditionally.
433 void xhci_ring_device(struct xhci_hcd
*xhci
, int slot_id
)
436 struct xhci_virt_ep
*ep
;
438 for (i
= 0; i
< LAST_EP_INDEX
+ 1; i
++) {
439 ep
= &xhci
->devs
[slot_id
]->eps
[i
];
441 if (ep
->ep_state
& EP_HAS_STREAMS
) {
442 for (s
= 1; s
< ep
->stream_info
->num_streams
; s
++)
443 xhci_ring_ep_doorbell(xhci
, slot_id
, i
, s
);
444 } else if (ep
->ring
&& ep
->ring
->dequeue
) {
445 xhci_ring_ep_doorbell(xhci
, slot_id
, i
, 0);
452 static void xhci_disable_port(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
453 u16 wIndex
, __le32 __iomem
*addr
, u32 port_status
)
455 /* Don't allow the USB core to disable SuperSpeed ports. */
456 if (hcd
->speed
>= HCD_USB3
) {
457 xhci_dbg(xhci
, "Ignoring request to disable "
458 "SuperSpeed port.\n");
462 if (xhci
->quirks
& XHCI_BROKEN_PORT_PED
) {
464 "Broken Port Enabled/Disabled, ignoring port disable request.\n");
468 /* Write 1 to disable the port */
469 writel(port_status
| PORT_PE
, addr
);
470 port_status
= readl(addr
);
471 xhci_dbg(xhci
, "disable port, actual port %d status = 0x%x\n",
472 wIndex
, port_status
);
475 static void xhci_clear_port_change_bit(struct xhci_hcd
*xhci
, u16 wValue
,
476 u16 wIndex
, __le32 __iomem
*addr
, u32 port_status
)
478 char *port_change_bit
;
482 case USB_PORT_FEAT_C_RESET
:
484 port_change_bit
= "reset";
486 case USB_PORT_FEAT_C_BH_PORT_RESET
:
488 port_change_bit
= "warm(BH) reset";
490 case USB_PORT_FEAT_C_CONNECTION
:
492 port_change_bit
= "connect";
494 case USB_PORT_FEAT_C_OVER_CURRENT
:
496 port_change_bit
= "over-current";
498 case USB_PORT_FEAT_C_ENABLE
:
500 port_change_bit
= "enable/disable";
502 case USB_PORT_FEAT_C_SUSPEND
:
504 port_change_bit
= "suspend/resume";
506 case USB_PORT_FEAT_C_PORT_LINK_STATE
:
508 port_change_bit
= "link state";
510 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR
:
512 port_change_bit
= "config error";
515 /* Should never happen */
518 /* Change bits are all write 1 to clear */
519 writel(port_status
| status
, addr
);
520 port_status
= readl(addr
);
521 xhci_dbg(xhci
, "clear port %s change, actual port %d status = 0x%x\n",
522 port_change_bit
, wIndex
, port_status
);
525 static int xhci_get_ports(struct usb_hcd
*hcd
, __le32 __iomem
***port_array
)
528 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
530 if (hcd
->speed
>= HCD_USB3
) {
531 max_ports
= xhci
->num_usb3_ports
;
532 *port_array
= xhci
->usb3_ports
;
534 max_ports
= xhci
->num_usb2_ports
;
535 *port_array
= xhci
->usb2_ports
;
541 static __le32 __iomem
*xhci_get_port_io_addr(struct usb_hcd
*hcd
, int index
)
543 __le32 __iomem
**port_array
;
545 xhci_get_ports(hcd
, &port_array
);
546 return port_array
[index
];
550 * xhci_set_port_power() must be called with xhci->lock held.
551 * It will release and re-aquire the lock while calling ACPI
554 static void xhci_set_port_power(struct xhci_hcd
*xhci
, struct usb_hcd
*hcd
,
555 u16 index
, bool on
, unsigned long *flags
)
557 __le32 __iomem
*addr
;
560 addr
= xhci_get_port_io_addr(hcd
, index
);
562 temp
= xhci_port_state_to_neutral(temp
);
565 writel(temp
| PORT_POWER
, addr
);
567 xhci_dbg(xhci
, "set port power, actual port %d status = 0x%x\n",
571 writel(temp
& ~PORT_POWER
, addr
);
574 spin_unlock_irqrestore(&xhci
->lock
, *flags
);
575 temp
= usb_acpi_power_manageable(hcd
->self
.root_hub
,
578 usb_acpi_set_power_state(hcd
->self
.root_hub
,
580 spin_lock_irqsave(&xhci
->lock
, *flags
);
583 static void xhci_port_set_test_mode(struct xhci_hcd
*xhci
,
584 u16 test_mode
, u16 wIndex
)
587 __le32 __iomem
*addr
;
589 /* xhci only supports test mode for usb2 ports, i.e. xhci->main_hcd */
590 addr
= xhci_get_port_io_addr(xhci
->main_hcd
, wIndex
);
591 temp
= readl(addr
+ PORTPMSC
);
592 temp
|= test_mode
<< PORT_TEST_MODE_SHIFT
;
593 writel(temp
, addr
+ PORTPMSC
);
594 xhci
->test_mode
= test_mode
;
595 if (test_mode
== TEST_FORCE_EN
)
599 static int xhci_enter_test_mode(struct xhci_hcd
*xhci
,
600 u16 test_mode
, u16 wIndex
, unsigned long *flags
)
604 /* Disable all Device Slots */
605 xhci_dbg(xhci
, "Disable all slots\n");
606 for (i
= 1; i
<= HCS_MAX_SLOTS(xhci
->hcs_params1
); i
++) {
607 retval
= xhci_disable_slot(xhci
, NULL
, i
);
609 xhci_err(xhci
, "Failed to disable slot %d, %d. Enter test mode anyway\n",
612 /* Put all ports to the Disable state by clear PP */
613 xhci_dbg(xhci
, "Disable all port (PP = 0)\n");
614 /* Power off USB3 ports*/
615 for (i
= 0; i
< xhci
->num_usb3_ports
; i
++)
616 xhci_set_port_power(xhci
, xhci
->shared_hcd
, i
, false, flags
);
617 /* Power off USB2 ports*/
618 for (i
= 0; i
< xhci
->num_usb2_ports
; i
++)
619 xhci_set_port_power(xhci
, xhci
->main_hcd
, i
, false, flags
);
620 /* Stop the controller */
621 xhci_dbg(xhci
, "Stop controller\n");
622 retval
= xhci_halt(xhci
);
625 /* Disable runtime PM for test mode */
626 pm_runtime_forbid(xhci_to_hcd(xhci
)->self
.controller
);
627 /* Set PORTPMSC.PTC field to enter selected test mode */
628 /* Port is selected by wIndex. port_id = wIndex + 1 */
629 xhci_dbg(xhci
, "Enter Test Mode: %d, Port_id=%d\n",
630 test_mode
, wIndex
+ 1);
631 xhci_port_set_test_mode(xhci
, test_mode
, wIndex
);
635 static int xhci_exit_test_mode(struct xhci_hcd
*xhci
)
639 if (!xhci
->test_mode
) {
640 xhci_err(xhci
, "Not in test mode, do nothing.\n");
643 if (xhci
->test_mode
== TEST_FORCE_EN
&&
644 !(xhci
->xhc_state
& XHCI_STATE_HALTED
)) {
645 retval
= xhci_halt(xhci
);
649 pm_runtime_allow(xhci_to_hcd(xhci
)->self
.controller
);
651 return xhci_reset(xhci
);
654 void xhci_set_link_state(struct xhci_hcd
*xhci
, __le32 __iomem
**port_array
,
655 int port_id
, u32 link_state
)
659 temp
= readl(port_array
[port_id
]);
660 temp
= xhci_port_state_to_neutral(temp
);
661 temp
&= ~PORT_PLS_MASK
;
662 temp
|= PORT_LINK_STROBE
| link_state
;
663 writel(temp
, port_array
[port_id
]);
666 static void xhci_set_remote_wake_mask(struct xhci_hcd
*xhci
,
667 __le32 __iomem
**port_array
, int port_id
, u16 wake_mask
)
671 temp
= readl(port_array
[port_id
]);
672 temp
= xhci_port_state_to_neutral(temp
);
674 if (wake_mask
& USB_PORT_FEAT_REMOTE_WAKE_CONNECT
)
675 temp
|= PORT_WKCONN_E
;
677 temp
&= ~PORT_WKCONN_E
;
679 if (wake_mask
& USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT
)
680 temp
|= PORT_WKDISC_E
;
682 temp
&= ~PORT_WKDISC_E
;
684 if (wake_mask
& USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT
)
687 temp
&= ~PORT_WKOC_E
;
689 writel(temp
, port_array
[port_id
]);
692 /* Test and clear port RWC bit */
693 void xhci_test_and_clear_bit(struct xhci_hcd
*xhci
, __le32 __iomem
**port_array
,
694 int port_id
, u32 port_bit
)
698 temp
= readl(port_array
[port_id
]);
699 if (temp
& port_bit
) {
700 temp
= xhci_port_state_to_neutral(temp
);
702 writel(temp
, port_array
[port_id
]);
706 /* Updates Link Status for USB 2.1 port */
707 static void xhci_hub_report_usb2_link_state(u32
*status
, u32 status_reg
)
709 if ((status_reg
& PORT_PLS_MASK
) == XDEV_U2
)
710 *status
|= USB_PORT_STAT_L1
;
713 /* Updates Link Status for super Speed port */
714 static void xhci_hub_report_usb3_link_state(struct xhci_hcd
*xhci
,
715 u32
*status
, u32 status_reg
)
717 u32 pls
= status_reg
& PORT_PLS_MASK
;
719 /* resume state is a xHCI internal state.
720 * Do not report it to usb core, instead, pretend to be U3,
721 * thus usb core knows it's not ready for transfer
723 if (pls
== XDEV_RESUME
) {
724 *status
|= USB_SS_PORT_LS_U3
;
728 /* When the CAS bit is set then warm reset
729 * should be performed on port
731 if (status_reg
& PORT_CAS
) {
732 /* The CAS bit can be set while the port is
734 * Only roothubs have CAS bit, so we
735 * pretend to be in compliance mode
736 * unless we're already in compliance
737 * or the inactive state.
739 if (pls
!= USB_SS_PORT_LS_COMP_MOD
&&
740 pls
!= USB_SS_PORT_LS_SS_INACTIVE
) {
741 pls
= USB_SS_PORT_LS_COMP_MOD
;
743 /* Return also connection bit -
744 * hub state machine resets port
745 * when this bit is set.
747 pls
|= USB_PORT_STAT_CONNECTION
;
750 * If CAS bit isn't set but the Port is already at
751 * Compliance Mode, fake a connection so the USB core
752 * notices the Compliance state and resets the port.
753 * This resolves an issue generated by the SN65LVPE502CP
754 * in which sometimes the port enters compliance mode
755 * caused by a delay on the host-device negotiation.
757 if ((xhci
->quirks
& XHCI_COMP_MODE_QUIRK
) &&
758 (pls
== USB_SS_PORT_LS_COMP_MOD
))
759 pls
|= USB_PORT_STAT_CONNECTION
;
762 /* update status field */
767 * Function for Compliance Mode Quirk.
769 * This Function verifies if all xhc USB3 ports have entered U0, if so,
770 * the compliance mode timer is deleted. A port won't enter
771 * compliance mode if it has previously entered U0.
773 static void xhci_del_comp_mod_timer(struct xhci_hcd
*xhci
, u32 status
,
776 u32 all_ports_seen_u0
= ((1 << xhci
->num_usb3_ports
)-1);
777 bool port_in_u0
= ((status
& PORT_PLS_MASK
) == XDEV_U0
);
779 if (!(xhci
->quirks
& XHCI_COMP_MODE_QUIRK
))
782 if ((xhci
->port_status_u0
!= all_ports_seen_u0
) && port_in_u0
) {
783 xhci
->port_status_u0
|= 1 << wIndex
;
784 if (xhci
->port_status_u0
== all_ports_seen_u0
) {
785 del_timer_sync(&xhci
->comp_mode_recovery_timer
);
786 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
787 "All USB3 ports have entered U0 already!");
788 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
789 "Compliance Mode Recovery Timer Deleted.");
794 static u32
xhci_get_ext_port_status(u32 raw_port_status
, u32 port_li
)
799 /* only support rx and tx lane counts of 1 in usb3.1 spec */
800 speed_id
= DEV_PORT_SPEED(raw_port_status
);
801 ext_stat
|= speed_id
; /* bits 3:0, RX speed id */
802 ext_stat
|= speed_id
<< 4; /* bits 7:4, TX speed id */
804 ext_stat
|= PORT_RX_LANES(port_li
) << 8; /* bits 11:8 Rx lane count */
805 ext_stat
|= PORT_TX_LANES(port_li
) << 12; /* bits 15:12 Tx lane count */
811 * Converts a raw xHCI port status into the format that external USB 2.0 or USB
814 * Possible side effects:
815 * - Mark a port as being done with device resume,
816 * and ring the endpoint doorbells.
817 * - Stop the Synopsys redriver Compliance Mode polling.
818 * - Drop and reacquire the xHCI lock, in order to wait for port resume.
820 static u32
xhci_get_port_status(struct usb_hcd
*hcd
,
821 struct xhci_bus_state
*bus_state
,
822 __le32 __iomem
**port_array
,
823 u16 wIndex
, u32 raw_port_status
,
825 __releases(&xhci
->lock
)
826 __acquires(&xhci
->lock
)
828 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
832 /* wPortChange bits */
833 if (raw_port_status
& PORT_CSC
)
834 status
|= USB_PORT_STAT_C_CONNECTION
<< 16;
835 if (raw_port_status
& PORT_PEC
)
836 status
|= USB_PORT_STAT_C_ENABLE
<< 16;
837 if ((raw_port_status
& PORT_OCC
))
838 status
|= USB_PORT_STAT_C_OVERCURRENT
<< 16;
839 if ((raw_port_status
& PORT_RC
))
840 status
|= USB_PORT_STAT_C_RESET
<< 16;
842 if (hcd
->speed
>= HCD_USB3
) {
843 /* Port link change with port in resume state should not be
844 * reported to usbcore, as this is an internal state to be
845 * handled by xhci driver. Reporting PLC to usbcore may
846 * cause usbcore clearing PLC first and port change event
847 * irq won't be generated.
849 if ((raw_port_status
& PORT_PLC
) &&
850 (raw_port_status
& PORT_PLS_MASK
) != XDEV_RESUME
)
851 status
|= USB_PORT_STAT_C_LINK_STATE
<< 16;
852 if ((raw_port_status
& PORT_WRC
))
853 status
|= USB_PORT_STAT_C_BH_RESET
<< 16;
854 if ((raw_port_status
& PORT_CEC
))
855 status
|= USB_PORT_STAT_C_CONFIG_ERROR
<< 16;
858 if (hcd
->speed
< HCD_USB3
) {
859 if ((raw_port_status
& PORT_PLS_MASK
) == XDEV_U3
860 && (raw_port_status
& PORT_POWER
))
861 status
|= USB_PORT_STAT_SUSPEND
;
863 if ((raw_port_status
& PORT_PLS_MASK
) == XDEV_RESUME
&&
864 !DEV_SUPERSPEED_ANY(raw_port_status
)) {
865 if ((raw_port_status
& PORT_RESET
) ||
866 !(raw_port_status
& PORT_PE
))
868 /* did port event handler already start resume timing? */
869 if (!bus_state
->resume_done
[wIndex
]) {
870 /* If not, maybe we are in a host initated resume? */
871 if (test_bit(wIndex
, &bus_state
->resuming_ports
)) {
872 /* Host initated resume doesn't time the resume
873 * signalling using resume_done[].
874 * It manually sets RESUME state, sleeps 20ms
875 * and sets U0 state. This should probably be
876 * changed, but not right now.
879 /* port resume was discovered now and here,
880 * start resume timing
882 unsigned long timeout
= jiffies
+
883 msecs_to_jiffies(USB_RESUME_TIMEOUT
);
885 set_bit(wIndex
, &bus_state
->resuming_ports
);
886 bus_state
->resume_done
[wIndex
] = timeout
;
887 mod_timer(&hcd
->rh_timer
, timeout
);
889 /* Has resume been signalled for USB_RESUME_TIME yet? */
890 } else if (time_after_eq(jiffies
,
891 bus_state
->resume_done
[wIndex
])) {
894 xhci_dbg(xhci
, "Resume USB2 port %d\n",
896 bus_state
->resume_done
[wIndex
] = 0;
897 clear_bit(wIndex
, &bus_state
->resuming_ports
);
899 set_bit(wIndex
, &bus_state
->rexit_ports
);
900 xhci_set_link_state(xhci
, port_array
, wIndex
,
903 spin_unlock_irqrestore(&xhci
->lock
, flags
);
904 time_left
= wait_for_completion_timeout(
905 &bus_state
->rexit_done
[wIndex
],
907 XHCI_MAX_REXIT_TIMEOUT
));
908 spin_lock_irqsave(&xhci
->lock
, flags
);
911 slot_id
= xhci_find_slot_id_by_port(hcd
,
914 xhci_dbg(xhci
, "slot_id is zero\n");
917 xhci_ring_device(xhci
, slot_id
);
919 int port_status
= readl(port_array
[wIndex
]);
920 xhci_warn(xhci
, "Port resume took longer than %i msec, port status = 0x%x\n",
921 XHCI_MAX_REXIT_TIMEOUT
,
923 status
|= USB_PORT_STAT_SUSPEND
;
924 clear_bit(wIndex
, &bus_state
->rexit_ports
);
927 bus_state
->port_c_suspend
|= 1 << wIndex
;
928 bus_state
->suspended_ports
&= ~(1 << wIndex
);
931 * The resume has been signaling for less than
932 * USB_RESUME_TIME. Report the port status as SUSPEND,
933 * let the usbcore check port status again and clear
934 * resume signaling later.
936 status
|= USB_PORT_STAT_SUSPEND
;
940 * Clear stale usb2 resume signalling variables in case port changed
941 * state during resume signalling. For example on error
943 if ((bus_state
->resume_done
[wIndex
] ||
944 test_bit(wIndex
, &bus_state
->resuming_ports
)) &&
945 (raw_port_status
& PORT_PLS_MASK
) != XDEV_U3
&&
946 (raw_port_status
& PORT_PLS_MASK
) != XDEV_RESUME
) {
947 bus_state
->resume_done
[wIndex
] = 0;
948 clear_bit(wIndex
, &bus_state
->resuming_ports
);
952 if ((raw_port_status
& PORT_PLS_MASK
) == XDEV_U0
&&
953 (raw_port_status
& PORT_POWER
)) {
954 if (bus_state
->suspended_ports
& (1 << wIndex
)) {
955 bus_state
->suspended_ports
&= ~(1 << wIndex
);
956 if (hcd
->speed
< HCD_USB3
)
957 bus_state
->port_c_suspend
|= 1 << wIndex
;
959 bus_state
->resume_done
[wIndex
] = 0;
960 clear_bit(wIndex
, &bus_state
->resuming_ports
);
962 if (raw_port_status
& PORT_CONNECT
) {
963 status
|= USB_PORT_STAT_CONNECTION
;
964 status
|= xhci_port_speed(raw_port_status
);
966 if (raw_port_status
& PORT_PE
)
967 status
|= USB_PORT_STAT_ENABLE
;
968 if (raw_port_status
& PORT_OC
)
969 status
|= USB_PORT_STAT_OVERCURRENT
;
970 if (raw_port_status
& PORT_RESET
)
971 status
|= USB_PORT_STAT_RESET
;
972 if (raw_port_status
& PORT_POWER
) {
973 if (hcd
->speed
>= HCD_USB3
)
974 status
|= USB_SS_PORT_STAT_POWER
;
976 status
|= USB_PORT_STAT_POWER
;
978 /* Update Port Link State */
979 if (hcd
->speed
>= HCD_USB3
) {
980 xhci_hub_report_usb3_link_state(xhci
, &status
, raw_port_status
);
982 * Verify if all USB3 Ports Have entered U0 already.
983 * Delete Compliance Mode Timer if so.
985 xhci_del_comp_mod_timer(xhci
, raw_port_status
, wIndex
);
987 xhci_hub_report_usb2_link_state(&status
, raw_port_status
);
989 if (bus_state
->port_c_suspend
& (1 << wIndex
))
990 status
|= USB_PORT_STAT_C_SUSPEND
<< 16;
995 int xhci_hub_control(struct usb_hcd
*hcd
, u16 typeReq
, u16 wValue
,
996 u16 wIndex
, char *buf
, u16 wLength
)
998 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
1000 unsigned long flags
;
1003 __le32 __iomem
**port_array
;
1005 struct xhci_bus_state
*bus_state
;
1011 max_ports
= xhci_get_ports(hcd
, &port_array
);
1012 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
1014 spin_lock_irqsave(&xhci
->lock
, flags
);
1017 /* No power source, over-current reported per port */
1020 case GetHubDescriptor
:
1021 /* Check to make sure userspace is asking for the USB 3.0 hub
1022 * descriptor for the USB 3.0 roothub. If not, we stall the
1023 * endpoint, like external hubs do.
1025 if (hcd
->speed
>= HCD_USB3
&&
1026 (wLength
< USB_DT_SS_HUB_SIZE
||
1027 wValue
!= (USB_DT_SS_HUB
<< 8))) {
1028 xhci_dbg(xhci
, "Wrong hub descriptor type for "
1029 "USB 3.0 roothub.\n");
1032 xhci_hub_descriptor(hcd
, xhci
,
1033 (struct usb_hub_descriptor
*) buf
);
1035 case DeviceRequest
| USB_REQ_GET_DESCRIPTOR
:
1036 if ((wValue
& 0xff00) != (USB_DT_BOS
<< 8))
1039 if (hcd
->speed
< HCD_USB3
)
1042 retval
= xhci_create_usb3_bos_desc(xhci
, buf
, wLength
);
1043 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1046 if (!wIndex
|| wIndex
> max_ports
)
1049 temp
= readl(port_array
[wIndex
]);
1050 if (temp
== ~(u32
)0) {
1055 status
= xhci_get_port_status(hcd
, bus_state
, port_array
,
1056 wIndex
, temp
, flags
);
1057 if (status
== 0xffffffff)
1060 xhci_dbg(xhci
, "get port status, actual port %d status = 0x%x\n",
1062 xhci_dbg(xhci
, "Get port status returned 0x%x\n", status
);
1064 put_unaligned(cpu_to_le32(status
), (__le32
*) buf
);
1065 /* if USB 3.1 extended port status return additional 4 bytes */
1066 if (wValue
== 0x02) {
1069 if (hcd
->speed
< HCD_USB31
|| wLength
!= 8) {
1070 xhci_err(xhci
, "get ext port status invalid parameter\n");
1074 port_li
= readl(port_array
[wIndex
] + PORTLI
);
1075 status
= xhci_get_ext_port_status(temp
, port_li
);
1076 put_unaligned_le32(cpu_to_le32(status
), &buf
[4]);
1079 case SetPortFeature
:
1080 if (wValue
== USB_PORT_FEAT_LINK_STATE
)
1081 link_state
= (wIndex
& 0xff00) >> 3;
1082 if (wValue
== USB_PORT_FEAT_REMOTE_WAKE_MASK
)
1083 wake_mask
= wIndex
& 0xff00;
1084 if (wValue
== USB_PORT_FEAT_TEST
)
1085 test_mode
= (wIndex
& 0xff00) >> 8;
1086 /* The MSB of wIndex is the U1/U2 timeout */
1087 timeout
= (wIndex
& 0xff00) >> 8;
1089 if (!wIndex
|| wIndex
> max_ports
)
1092 temp
= readl(port_array
[wIndex
]);
1093 if (temp
== ~(u32
)0) {
1098 temp
= xhci_port_state_to_neutral(temp
);
1099 /* FIXME: What new port features do we need to support? */
1101 case USB_PORT_FEAT_SUSPEND
:
1102 temp
= readl(port_array
[wIndex
]);
1103 if ((temp
& PORT_PLS_MASK
) != XDEV_U0
) {
1104 /* Resume the port to U0 first */
1105 xhci_set_link_state(xhci
, port_array
, wIndex
,
1107 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1109 spin_lock_irqsave(&xhci
->lock
, flags
);
1111 /* In spec software should not attempt to suspend
1112 * a port unless the port reports that it is in the
1113 * enabled (PED = ‘1’,PLS < ‘3’) state.
1115 temp
= readl(port_array
[wIndex
]);
1116 if ((temp
& PORT_PE
) == 0 || (temp
& PORT_RESET
)
1117 || (temp
& PORT_PLS_MASK
) >= XDEV_U3
) {
1118 xhci_warn(xhci
, "USB core suspending device not in U0/U1/U2.\n");
1122 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1125 xhci_warn(xhci
, "slot_id is zero\n");
1128 /* unlock to execute stop endpoint commands */
1129 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1130 xhci_stop_device(xhci
, slot_id
, 1);
1131 spin_lock_irqsave(&xhci
->lock
, flags
);
1133 xhci_set_link_state(xhci
, port_array
, wIndex
, XDEV_U3
);
1135 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1136 msleep(10); /* wait device to enter */
1137 spin_lock_irqsave(&xhci
->lock
, flags
);
1139 temp
= readl(port_array
[wIndex
]);
1140 bus_state
->suspended_ports
|= 1 << wIndex
;
1142 case USB_PORT_FEAT_LINK_STATE
:
1143 temp
= readl(port_array
[wIndex
]);
1146 if (link_state
== USB_SS_PORT_LS_SS_DISABLED
) {
1147 xhci_dbg(xhci
, "Disable port %d\n", wIndex
);
1148 temp
= xhci_port_state_to_neutral(temp
);
1150 * Clear all change bits, so that we get a new
1153 temp
|= PORT_CSC
| PORT_PEC
| PORT_WRC
|
1154 PORT_OCC
| PORT_RC
| PORT_PLC
|
1156 writel(temp
| PORT_PE
, port_array
[wIndex
]);
1157 temp
= readl(port_array
[wIndex
]);
1161 /* Put link in RxDetect (enable port) */
1162 if (link_state
== USB_SS_PORT_LS_RX_DETECT
) {
1163 xhci_dbg(xhci
, "Enable port %d\n", wIndex
);
1164 xhci_set_link_state(xhci
, port_array
, wIndex
,
1166 temp
= readl(port_array
[wIndex
]);
1170 /* Software should not attempt to set
1171 * port link state above '3' (U3) and the port
1174 if ((temp
& PORT_PE
) == 0 ||
1175 (link_state
> USB_SS_PORT_LS_U3
)) {
1176 xhci_warn(xhci
, "Cannot set link state.\n");
1180 if (link_state
== USB_SS_PORT_LS_U3
) {
1181 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1184 /* unlock to execute stop endpoint
1186 spin_unlock_irqrestore(&xhci
->lock
,
1188 xhci_stop_device(xhci
, slot_id
, 1);
1189 spin_lock_irqsave(&xhci
->lock
, flags
);
1193 xhci_set_link_state(xhci
, port_array
, wIndex
,
1196 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1197 msleep(20); /* wait device to enter */
1198 spin_lock_irqsave(&xhci
->lock
, flags
);
1200 temp
= readl(port_array
[wIndex
]);
1201 if (link_state
== USB_SS_PORT_LS_U3
)
1202 bus_state
->suspended_ports
|= 1 << wIndex
;
1204 case USB_PORT_FEAT_POWER
:
1206 * Turn on ports, even if there isn't per-port switching.
1207 * HC will report connect events even before this is set.
1208 * However, hub_wq will ignore the roothub events until
1209 * the roothub is registered.
1211 xhci_set_port_power(xhci
, hcd
, wIndex
, true, &flags
);
1213 case USB_PORT_FEAT_RESET
:
1214 temp
= (temp
| PORT_RESET
);
1215 writel(temp
, port_array
[wIndex
]);
1217 temp
= readl(port_array
[wIndex
]);
1218 xhci_dbg(xhci
, "set port reset, actual port %d status = 0x%x\n", wIndex
, temp
);
1220 case USB_PORT_FEAT_REMOTE_WAKE_MASK
:
1221 xhci_set_remote_wake_mask(xhci
, port_array
,
1223 temp
= readl(port_array
[wIndex
]);
1224 xhci_dbg(xhci
, "set port remote wake mask, "
1225 "actual port %d status = 0x%x\n",
1228 case USB_PORT_FEAT_BH_PORT_RESET
:
1230 writel(temp
, port_array
[wIndex
]);
1232 temp
= readl(port_array
[wIndex
]);
1234 case USB_PORT_FEAT_U1_TIMEOUT
:
1235 if (hcd
->speed
< HCD_USB3
)
1237 temp
= readl(port_array
[wIndex
] + PORTPMSC
);
1238 temp
&= ~PORT_U1_TIMEOUT_MASK
;
1239 temp
|= PORT_U1_TIMEOUT(timeout
);
1240 writel(temp
, port_array
[wIndex
] + PORTPMSC
);
1242 case USB_PORT_FEAT_U2_TIMEOUT
:
1243 if (hcd
->speed
< HCD_USB3
)
1245 temp
= readl(port_array
[wIndex
] + PORTPMSC
);
1246 temp
&= ~PORT_U2_TIMEOUT_MASK
;
1247 temp
|= PORT_U2_TIMEOUT(timeout
);
1248 writel(temp
, port_array
[wIndex
] + PORTPMSC
);
1250 case USB_PORT_FEAT_TEST
:
1251 /* 4.19.6 Port Test Modes (USB2 Test Mode) */
1252 if (hcd
->speed
!= HCD_USB2
)
1254 if (test_mode
> TEST_FORCE_EN
|| test_mode
< TEST_J
)
1256 retval
= xhci_enter_test_mode(xhci
, test_mode
, wIndex
,
1262 /* unblock any posted writes */
1263 temp
= readl(port_array
[wIndex
]);
1265 case ClearPortFeature
:
1266 if (!wIndex
|| wIndex
> max_ports
)
1269 temp
= readl(port_array
[wIndex
]);
1270 if (temp
== ~(u32
)0) {
1275 /* FIXME: What new port features do we need to support? */
1276 temp
= xhci_port_state_to_neutral(temp
);
1278 case USB_PORT_FEAT_SUSPEND
:
1279 temp
= readl(port_array
[wIndex
]);
1280 xhci_dbg(xhci
, "clear USB_PORT_FEAT_SUSPEND\n");
1281 xhci_dbg(xhci
, "PORTSC %04x\n", temp
);
1282 if (temp
& PORT_RESET
)
1284 if ((temp
& PORT_PLS_MASK
) == XDEV_U3
) {
1285 if ((temp
& PORT_PE
) == 0)
1288 set_bit(wIndex
, &bus_state
->resuming_ports
);
1289 xhci_set_link_state(xhci
, port_array
, wIndex
,
1291 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1292 msleep(USB_RESUME_TIMEOUT
);
1293 spin_lock_irqsave(&xhci
->lock
, flags
);
1294 xhci_set_link_state(xhci
, port_array
, wIndex
,
1296 clear_bit(wIndex
, &bus_state
->resuming_ports
);
1298 bus_state
->port_c_suspend
|= 1 << wIndex
;
1300 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1303 xhci_dbg(xhci
, "slot_id is zero\n");
1306 xhci_ring_device(xhci
, slot_id
);
1308 case USB_PORT_FEAT_C_SUSPEND
:
1309 bus_state
->port_c_suspend
&= ~(1 << wIndex
);
1310 case USB_PORT_FEAT_C_RESET
:
1311 case USB_PORT_FEAT_C_BH_PORT_RESET
:
1312 case USB_PORT_FEAT_C_CONNECTION
:
1313 case USB_PORT_FEAT_C_OVER_CURRENT
:
1314 case USB_PORT_FEAT_C_ENABLE
:
1315 case USB_PORT_FEAT_C_PORT_LINK_STATE
:
1316 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR
:
1317 xhci_clear_port_change_bit(xhci
, wValue
, wIndex
,
1318 port_array
[wIndex
], temp
);
1320 case USB_PORT_FEAT_ENABLE
:
1321 xhci_disable_port(hcd
, xhci
, wIndex
,
1322 port_array
[wIndex
], temp
);
1324 case USB_PORT_FEAT_POWER
:
1325 xhci_set_port_power(xhci
, hcd
, wIndex
, false, &flags
);
1327 case USB_PORT_FEAT_TEST
:
1328 retval
= xhci_exit_test_mode(xhci
);
1336 /* "stall" on error */
1339 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1344 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1345 * Ports are 0-indexed from the HCD point of view,
1346 * and 1-indexed from the USB core pointer of view.
1348 * Note that the status change bits will be cleared as soon as a port status
1349 * change event is generated, so we use the saved status from that event.
1351 int xhci_hub_status_data(struct usb_hcd
*hcd
, char *buf
)
1353 unsigned long flags
;
1357 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
1359 __le32 __iomem
**port_array
;
1360 struct xhci_bus_state
*bus_state
;
1361 bool reset_change
= false;
1363 max_ports
= xhci_get_ports(hcd
, &port_array
);
1364 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
1366 /* Initial status is no changes */
1367 retval
= (max_ports
+ 8) / 8;
1368 memset(buf
, 0, retval
);
1371 * Inform the usbcore about resume-in-progress by returning
1372 * a non-zero value even if there are no status changes.
1374 status
= bus_state
->resuming_ports
;
1376 mask
= PORT_CSC
| PORT_PEC
| PORT_OCC
| PORT_PLC
| PORT_WRC
| PORT_CEC
;
1378 spin_lock_irqsave(&xhci
->lock
, flags
);
1379 /* For each port, did anything change? If so, set that bit in buf. */
1380 for (i
= 0; i
< max_ports
; i
++) {
1381 temp
= readl(port_array
[i
]);
1382 if (temp
== ~(u32
)0) {
1387 if ((temp
& mask
) != 0 ||
1388 (bus_state
->port_c_suspend
& 1 << i
) ||
1389 (bus_state
->resume_done
[i
] && time_after_eq(
1390 jiffies
, bus_state
->resume_done
[i
]))) {
1391 buf
[(i
+ 1) / 8] |= 1 << (i
+ 1) % 8;
1394 if ((temp
& PORT_RC
))
1395 reset_change
= true;
1397 if (!status
&& !reset_change
) {
1398 xhci_dbg(xhci
, "%s: stopping port polling.\n", __func__
);
1399 clear_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
1401 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1402 return status
? retval
: 0;
1407 int xhci_bus_suspend(struct usb_hcd
*hcd
)
1409 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
1410 int max_ports
, port_index
;
1411 __le32 __iomem
**port_array
;
1412 struct xhci_bus_state
*bus_state
;
1413 unsigned long flags
;
1415 max_ports
= xhci_get_ports(hcd
, &port_array
);
1416 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
1418 spin_lock_irqsave(&xhci
->lock
, flags
);
1420 if (hcd
->self
.root_hub
->do_remote_wakeup
) {
1421 if (bus_state
->resuming_ports
|| /* USB2 */
1422 bus_state
->port_remote_wakeup
) { /* USB3 */
1423 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1424 xhci_dbg(xhci
, "suspend failed because a port is resuming\n");
1429 port_index
= max_ports
;
1430 bus_state
->bus_suspended
= 0;
1431 while (port_index
--) {
1432 /* suspend the port if the port is not suspended */
1436 t1
= readl(port_array
[port_index
]);
1437 t2
= xhci_port_state_to_neutral(t1
);
1439 if ((t1
& PORT_PE
) && !(t1
& PORT_PLS_MASK
)) {
1440 xhci_dbg(xhci
, "port %d not suspended\n", port_index
);
1441 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1444 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1445 xhci_stop_device(xhci
, slot_id
, 1);
1446 spin_lock_irqsave(&xhci
->lock
, flags
);
1448 t2
&= ~PORT_PLS_MASK
;
1449 t2
|= PORT_LINK_STROBE
| XDEV_U3
;
1450 set_bit(port_index
, &bus_state
->bus_suspended
);
1452 /* USB core sets remote wake mask for USB 3.0 hubs,
1453 * including the USB 3.0 roothub, but only if CONFIG_PM
1454 * is enabled, so also enable remote wake here.
1456 if (hcd
->self
.root_hub
->do_remote_wakeup
) {
1457 if (t1
& PORT_CONNECT
) {
1458 t2
|= PORT_WKOC_E
| PORT_WKDISC_E
;
1459 t2
&= ~PORT_WKCONN_E
;
1461 t2
|= PORT_WKOC_E
| PORT_WKCONN_E
;
1462 t2
&= ~PORT_WKDISC_E
;
1465 t2
&= ~PORT_WAKE_BITS
;
1467 t1
= xhci_port_state_to_neutral(t1
);
1469 writel(t2
, port_array
[port_index
]);
1471 hcd
->state
= HC_STATE_SUSPENDED
;
1472 bus_state
->next_statechange
= jiffies
+ msecs_to_jiffies(10);
1473 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1478 * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1479 * warm reset a USB3 device stuck in polling or compliance mode after resume.
1480 * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1482 static bool xhci_port_missing_cas_quirk(int port_index
,
1483 __le32 __iomem
**port_array
)
1487 portsc
= readl(port_array
[port_index
]);
1489 /* if any of these are set we are not stuck */
1490 if (portsc
& (PORT_CONNECT
| PORT_CAS
))
1493 if (((portsc
& PORT_PLS_MASK
) != XDEV_POLLING
) &&
1494 ((portsc
& PORT_PLS_MASK
) != XDEV_COMP_MODE
))
1497 /* clear wakeup/change bits, and do a warm port reset */
1498 portsc
&= ~(PORT_RWC_BITS
| PORT_CEC
| PORT_WAKE_BITS
);
1500 writel(portsc
, port_array
[port_index
]);
1502 readl(port_array
[port_index
]);
1506 int xhci_bus_resume(struct usb_hcd
*hcd
)
1508 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
1509 int max_ports
, port_index
;
1510 __le32 __iomem
**port_array
;
1511 struct xhci_bus_state
*bus_state
;
1513 unsigned long flags
;
1514 unsigned long port_was_suspended
= 0;
1515 bool need_usb2_u3_exit
= false;
1519 max_ports
= xhci_get_ports(hcd
, &port_array
);
1520 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
1522 if (time_before(jiffies
, bus_state
->next_statechange
))
1525 spin_lock_irqsave(&xhci
->lock
, flags
);
1526 if (!HCD_HW_ACCESSIBLE(hcd
)) {
1527 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1531 /* delay the irqs */
1532 temp
= readl(&xhci
->op_regs
->command
);
1534 writel(temp
, &xhci
->op_regs
->command
);
1536 port_index
= max_ports
;
1537 while (port_index
--) {
1538 /* Check whether need resume ports. If needed
1539 resume port and disable remote wakeup */
1542 temp
= readl(port_array
[port_index
]);
1544 /* warm reset CAS limited ports stuck in polling/compliance */
1545 if ((xhci
->quirks
& XHCI_MISSING_CAS
) &&
1546 (hcd
->speed
>= HCD_USB3
) &&
1547 xhci_port_missing_cas_quirk(port_index
, port_array
)) {
1548 xhci_dbg(xhci
, "reset stuck port %d\n", port_index
);
1551 if (DEV_SUPERSPEED_ANY(temp
))
1552 temp
&= ~(PORT_RWC_BITS
| PORT_CEC
| PORT_WAKE_BITS
);
1554 temp
&= ~(PORT_RWC_BITS
| PORT_WAKE_BITS
);
1555 if (test_bit(port_index
, &bus_state
->bus_suspended
) &&
1556 (temp
& PORT_PLS_MASK
)) {
1557 set_bit(port_index
, &port_was_suspended
);
1558 if (!DEV_SUPERSPEED_ANY(temp
)) {
1559 xhci_set_link_state(xhci
, port_array
,
1560 port_index
, XDEV_RESUME
);
1561 need_usb2_u3_exit
= true;
1564 writel(temp
, port_array
[port_index
]);
1567 if (need_usb2_u3_exit
) {
1568 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1569 msleep(USB_RESUME_TIMEOUT
);
1570 spin_lock_irqsave(&xhci
->lock
, flags
);
1573 port_index
= max_ports
;
1574 while (port_index
--) {
1575 if (!(port_was_suspended
& BIT(port_index
)))
1577 /* Clear PLC to poll it later after XDEV_U0 */
1578 xhci_test_and_clear_bit(xhci
, port_array
, port_index
, PORT_PLC
);
1579 xhci_set_link_state(xhci
, port_array
, port_index
, XDEV_U0
);
1582 port_index
= max_ports
;
1583 while (port_index
--) {
1584 if (!(port_was_suspended
& BIT(port_index
)))
1586 /* Poll and Clear PLC */
1587 sret
= xhci_handshake(port_array
[port_index
], PORT_PLC
,
1588 PORT_PLC
, 10 * 1000);
1590 xhci_warn(xhci
, "port %d resume PLC timeout\n",
1592 xhci_test_and_clear_bit(xhci
, port_array
, port_index
, PORT_PLC
);
1593 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
, port_index
+ 1);
1595 xhci_ring_device(xhci
, slot_id
);
1598 (void) readl(&xhci
->op_regs
->command
);
1600 bus_state
->next_statechange
= jiffies
+ msecs_to_jiffies(5);
1601 /* re-enable irqs */
1602 temp
= readl(&xhci
->op_regs
->command
);
1604 writel(temp
, &xhci
->op_regs
->command
);
1605 temp
= readl(&xhci
->op_regs
->command
);
1607 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1611 #endif /* CONFIG_PM */