2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/slab.h>
25 #include <asm/unaligned.h>
28 #include "xhci-trace.h"
30 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
31 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
32 PORT_RC | PORT_PLC | PORT_PE)
34 /* USB 3 BOS descriptor and a capability descriptors, combined.
35 * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
37 static u8 usb_bos_descriptor
[] = {
38 USB_DT_BOS_SIZE
, /* __u8 bLength, 5 bytes */
39 USB_DT_BOS
, /* __u8 bDescriptorType */
40 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
41 0x1, /* __u8 bNumDeviceCaps */
42 /* First device capability, SuperSpeed */
43 USB_DT_USB_SS_CAP_SIZE
, /* __u8 bLength, 10 bytes */
44 USB_DT_DEVICE_CAPABILITY
, /* Device Capability */
45 USB_SS_CAP_TYPE
, /* bDevCapabilityType, SUPERSPEED_USB */
46 0x00, /* bmAttributes, LTM off by default */
47 USB_5GBPS_OPERATION
, 0x00, /* wSpeedsSupported, 5Gbps only */
48 0x03, /* bFunctionalitySupport,
50 0x00, /* bU1DevExitLat, set later. */
51 0x00, 0x00, /* __le16 bU2DevExitLat, set later. */
52 /* Second device capability, SuperSpeedPlus */
53 0x1c, /* bLength 28, will be adjusted later */
54 USB_DT_DEVICE_CAPABILITY
, /* Device Capability */
55 USB_SSP_CAP_TYPE
, /* bDevCapabilityType SUPERSPEED_PLUS */
56 0x00, /* bReserved 0 */
57 0x23, 0x00, 0x00, 0x00, /* bmAttributes, SSAC=3 SSIC=1 */
58 0x01, 0x00, /* wFunctionalitySupport */
59 0x00, 0x00, /* wReserved 0 */
60 /* Default Sublink Speed Attributes, overwrite if custom PSI exists */
61 0x34, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, rx, ID = 4 */
62 0xb4, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, tx, ID = 4 */
63 0x35, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, rx, ID = 5 */
64 0xb5, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, tx, ID = 5 */
67 static int xhci_create_usb3_bos_desc(struct xhci_hcd
*xhci
, char *buf
,
72 u16 desc_size
, ssp_cap_size
, ssa_size
= 0;
75 desc_size
= USB_DT_BOS_SIZE
+ USB_DT_USB_SS_CAP_SIZE
;
76 ssp_cap_size
= sizeof(usb_bos_descriptor
) - desc_size
;
78 /* does xhci support USB 3.1 Enhanced SuperSpeed */
79 if (xhci
->usb3_rhub
.min_rev
>= 0x01) {
80 /* does xhci provide a PSI table for SSA speed attributes? */
81 if (xhci
->usb3_rhub
.psi_count
) {
82 /* two SSA entries for each unique PSI ID, RX and TX */
83 ssa_count
= xhci
->usb3_rhub
.psi_uid_count
* 2;
84 ssa_size
= ssa_count
* sizeof(u32
);
85 ssp_cap_size
-= 16; /* skip copying the default SSA */
87 desc_size
+= ssp_cap_size
;
90 memcpy(buf
, &usb_bos_descriptor
, min(desc_size
, wLength
));
93 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
95 put_unaligned_le16(desc_size
+ ssa_size
, &buf
[2]);
98 if (wLength
< USB_DT_BOS_SIZE
+ USB_DT_USB_SS_CAP_SIZE
)
101 /* Indicate whether the host has LTM support. */
102 temp
= readl(&xhci
->cap_regs
->hcc_params
);
104 buf
[8] |= USB_LTM_SUPPORT
;
106 /* Set the U1 and U2 exit latencies. */
107 if ((xhci
->quirks
& XHCI_LPM_SUPPORT
)) {
108 temp
= readl(&xhci
->cap_regs
->hcs_params3
);
109 buf
[12] = HCS_U1_LATENCY(temp
);
110 put_unaligned_le16(HCS_U2_LATENCY(temp
), &buf
[13]);
113 /* If PSI table exists, add the custom speed attributes from it */
114 if (usb3_1
&& xhci
->usb3_rhub
.psi_count
) {
115 u32 ssp_cap_base
, bm_attrib
, psi
, psi_mant
, psi_exp
;
118 ssp_cap_base
= USB_DT_BOS_SIZE
+ USB_DT_USB_SS_CAP_SIZE
;
120 if (wLength
< desc_size
)
122 buf
[ssp_cap_base
] = ssp_cap_size
+ ssa_size
;
124 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
125 bm_attrib
= (ssa_count
- 1) & 0x1f;
126 bm_attrib
|= (xhci
->usb3_rhub
.psi_uid_count
- 1) << 5;
127 put_unaligned_le32(bm_attrib
, &buf
[ssp_cap_base
+ 4]);
129 if (wLength
< desc_size
+ ssa_size
)
132 * Create the Sublink Speed Attributes (SSA) array.
133 * The xhci PSI field and USB 3.1 SSA fields are very similar,
134 * but link type bits 7:6 differ for values 01b and 10b.
135 * xhci has also only one PSI entry for a symmetric link when
136 * USB 3.1 requires two SSA entries (RX and TX) for every link
139 for (i
= 0; i
< xhci
->usb3_rhub
.psi_count
; i
++) {
140 psi
= xhci
->usb3_rhub
.psi
[i
];
141 psi
&= ~USB_SSP_SUBLINK_SPEED_RSVD
;
142 psi_exp
= XHCI_EXT_PORT_PSIE(psi
);
143 psi_mant
= XHCI_EXT_PORT_PSIM(psi
);
145 /* Shift to Gbps and set SSP Link BIT(14) if 10Gpbs */
146 for (; psi_exp
< 3; psi_exp
++)
151 if ((psi
& PLT_MASK
) == PLT_SYM
) {
152 /* Symmetric, create SSA RX and TX from one PSI entry */
153 put_unaligned_le32(psi
, &buf
[offset
]);
154 psi
|= 1 << 7; /* turn entry to TX */
156 if (offset
>= desc_size
+ ssa_size
)
157 return desc_size
+ ssa_size
;
158 } else if ((psi
& PLT_MASK
) == PLT_ASYM_RX
) {
159 /* Asymetric RX, flip bits 7:6 for SSA */
162 put_unaligned_le32(psi
, &buf
[offset
]);
164 if (offset
>= desc_size
+ ssa_size
)
165 return desc_size
+ ssa_size
;
168 /* ssa_size is 0 for other than usb 3.1 hosts */
169 return desc_size
+ ssa_size
;
172 static void xhci_common_hub_descriptor(struct xhci_hcd
*xhci
,
173 struct usb_hub_descriptor
*desc
, int ports
)
177 desc
->bPwrOn2PwrGood
= 10; /* xhci section 5.4.9 says 20ms max */
178 desc
->bHubContrCurrent
= 0;
180 desc
->bNbrPorts
= ports
;
182 /* Bits 1:0 - support per-port power switching, or power always on */
183 if (HCC_PPC(xhci
->hcc_params
))
184 temp
|= HUB_CHAR_INDV_PORT_LPSM
;
186 temp
|= HUB_CHAR_NO_LPSM
;
187 /* Bit 2 - root hubs are not part of a compound device */
188 /* Bits 4:3 - individual port over current protection */
189 temp
|= HUB_CHAR_INDV_PORT_OCPM
;
190 /* Bits 6:5 - no TTs in root ports */
191 /* Bit 7 - no port indicators */
192 desc
->wHubCharacteristics
= cpu_to_le16(temp
);
195 /* Fill in the USB 2.0 roothub descriptor */
196 static void xhci_usb2_hub_descriptor(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
197 struct usb_hub_descriptor
*desc
)
201 __u8 port_removable
[(USB_MAXCHILDREN
+ 1 + 7) / 8];
205 ports
= xhci
->num_usb2_ports
;
207 xhci_common_hub_descriptor(xhci
, desc
, ports
);
208 desc
->bDescriptorType
= USB_DT_HUB
;
209 temp
= 1 + (ports
/ 8);
210 desc
->bDescLength
= USB_DT_HUB_NONVAR_SIZE
+ 2 * temp
;
212 /* The Device Removable bits are reported on a byte granularity.
213 * If the port doesn't exist within that byte, the bit is set to 0.
215 memset(port_removable
, 0, sizeof(port_removable
));
216 for (i
= 0; i
< ports
; i
++) {
217 portsc
= readl(xhci
->usb2_ports
[i
]);
218 /* If a device is removable, PORTSC reports a 0, same as in the
219 * hub descriptor DeviceRemovable bits.
221 if (portsc
& PORT_DEV_REMOVE
)
222 /* This math is hairy because bit 0 of DeviceRemovable
223 * is reserved, and bit 1 is for port 1, etc.
225 port_removable
[(i
+ 1) / 8] |= 1 << ((i
+ 1) % 8);
228 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
229 * ports on it. The USB 2.0 specification says that there are two
230 * variable length fields at the end of the hub descriptor:
231 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
232 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
233 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
234 * 0xFF, so we initialize the both arrays (DeviceRemovable and
235 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
236 * set of ports that actually exist.
238 memset(desc
->u
.hs
.DeviceRemovable
, 0xff,
239 sizeof(desc
->u
.hs
.DeviceRemovable
));
240 memset(desc
->u
.hs
.PortPwrCtrlMask
, 0xff,
241 sizeof(desc
->u
.hs
.PortPwrCtrlMask
));
243 for (i
= 0; i
< (ports
+ 1 + 7) / 8; i
++)
244 memset(&desc
->u
.hs
.DeviceRemovable
[i
], port_removable
[i
],
248 /* Fill in the USB 3.0 roothub descriptor */
249 static void xhci_usb3_hub_descriptor(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
250 struct usb_hub_descriptor
*desc
)
257 ports
= xhci
->num_usb3_ports
;
258 xhci_common_hub_descriptor(xhci
, desc
, ports
);
259 desc
->bDescriptorType
= USB_DT_SS_HUB
;
260 desc
->bDescLength
= USB_DT_SS_HUB_SIZE
;
262 /* header decode latency should be zero for roothubs,
263 * see section 4.23.5.2.
265 desc
->u
.ss
.bHubHdrDecLat
= 0;
266 desc
->u
.ss
.wHubDelay
= 0;
269 /* bit 0 is reserved, bit 1 is for port 1, etc. */
270 for (i
= 0; i
< ports
; i
++) {
271 portsc
= readl(xhci
->usb3_ports
[i
]);
272 if (portsc
& PORT_DEV_REMOVE
)
273 port_removable
|= 1 << (i
+ 1);
276 desc
->u
.ss
.DeviceRemovable
= cpu_to_le16(port_removable
);
279 static void xhci_hub_descriptor(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
280 struct usb_hub_descriptor
*desc
)
283 if (hcd
->speed
>= HCD_USB3
)
284 xhci_usb3_hub_descriptor(hcd
, xhci
, desc
);
286 xhci_usb2_hub_descriptor(hcd
, xhci
, desc
);
290 static unsigned int xhci_port_speed(unsigned int port_status
)
292 if (DEV_LOWSPEED(port_status
))
293 return USB_PORT_STAT_LOW_SPEED
;
294 if (DEV_HIGHSPEED(port_status
))
295 return USB_PORT_STAT_HIGH_SPEED
;
297 * FIXME: Yes, we should check for full speed, but the core uses that as
298 * a default in portspeed() in usb/core/hub.c (which is the only place
299 * USB_PORT_STAT_*_SPEED is used).
305 * These bits are Read Only (RO) and should be saved and written to the
306 * registers: 0, 3, 10:13, 30
307 * connect status, over-current status, port speed, and device removable.
308 * connect status and port speed are also sticky - meaning they're in
309 * the AUX well and they aren't changed by a hot, warm, or cold reset.
311 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
313 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
314 * bits 5:8, 9, 14:15, 25:27
315 * link state, port power, port indicator state, "wake on" enable state
317 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
319 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
322 #define XHCI_PORT_RW1S ((1<<4))
324 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
325 * bits 1, 17, 18, 19, 20, 21, 22, 23
326 * port enable/disable, and
327 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
328 * over-current, reset, link state, and L1 change
330 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
332 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
335 #define XHCI_PORT_RW ((1<<16))
337 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
340 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
343 * Given a port state, this function returns a value that would result in the
344 * port being in the same state, if the value was written to the port status
346 * Save Read Only (RO) bits and save read/write bits where
347 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
348 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
350 u32
xhci_port_state_to_neutral(u32 state
)
352 /* Save read-only status and port state */
353 return (state
& XHCI_PORT_RO
) | (state
& XHCI_PORT_RWS
);
357 * find slot id based on port number.
358 * @port: The one-based port number from one of the two split roothubs.
360 int xhci_find_slot_id_by_port(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
365 enum usb_device_speed speed
;
368 for (i
= 0; i
< MAX_HC_SLOTS
; i
++) {
371 speed
= xhci
->devs
[i
]->udev
->speed
;
372 if (((speed
>= USB_SPEED_SUPER
) == (hcd
->speed
>= HCD_USB3
))
373 && xhci
->devs
[i
]->fake_port
== port
) {
384 * It issues stop endpoint command for EP 0 to 30. And wait the last command
386 * suspend will set to 1, if suspend bit need to set in command.
388 static int xhci_stop_device(struct xhci_hcd
*xhci
, int slot_id
, int suspend
)
390 struct xhci_virt_device
*virt_dev
;
391 struct xhci_command
*cmd
;
397 virt_dev
= xhci
->devs
[slot_id
];
401 trace_xhci_stop_device(virt_dev
);
403 cmd
= xhci_alloc_command(xhci
, false, true, GFP_NOIO
);
407 spin_lock_irqsave(&xhci
->lock
, flags
);
408 for (i
= LAST_EP_INDEX
; i
> 0; i
--) {
409 if (virt_dev
->eps
[i
].ring
&& virt_dev
->eps
[i
].ring
->dequeue
) {
410 struct xhci_ep_ctx
*ep_ctx
;
411 struct xhci_command
*command
;
413 ep_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->out_ctx
, i
);
415 /* Check ep is running, required by AMD SNPS 3.1 xHC */
416 if (GET_EP_CTX_STATE(ep_ctx
) != EP_STATE_RUNNING
)
419 command
= xhci_alloc_command(xhci
, false, false,
422 spin_unlock_irqrestore(&xhci
->lock
, flags
);
427 ret
= xhci_queue_stop_endpoint(xhci
, command
, slot_id
,
430 spin_unlock_irqrestore(&xhci
->lock
, flags
);
431 xhci_free_command(xhci
, command
);
436 ret
= xhci_queue_stop_endpoint(xhci
, cmd
, slot_id
, 0, suspend
);
438 spin_unlock_irqrestore(&xhci
->lock
, flags
);
442 xhci_ring_cmd_db(xhci
);
443 spin_unlock_irqrestore(&xhci
->lock
, flags
);
445 /* Wait for last stop endpoint command to finish */
446 wait_for_completion(cmd
->completion
);
448 if (cmd
->status
== COMP_COMMAND_ABORTED
||
449 cmd
->status
== COMP_COMMAND_RING_STOPPED
) {
450 xhci_warn(xhci
, "Timeout while waiting for stop endpoint command\n");
455 xhci_free_command(xhci
, cmd
);
460 * Ring device, it rings the all doorbells unconditionally.
462 void xhci_ring_device(struct xhci_hcd
*xhci
, int slot_id
)
465 struct xhci_virt_ep
*ep
;
467 for (i
= 0; i
< LAST_EP_INDEX
+ 1; i
++) {
468 ep
= &xhci
->devs
[slot_id
]->eps
[i
];
470 if (ep
->ep_state
& EP_HAS_STREAMS
) {
471 for (s
= 1; s
< ep
->stream_info
->num_streams
; s
++)
472 xhci_ring_ep_doorbell(xhci
, slot_id
, i
, s
);
473 } else if (ep
->ring
&& ep
->ring
->dequeue
) {
474 xhci_ring_ep_doorbell(xhci
, slot_id
, i
, 0);
481 static void xhci_disable_port(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
482 u16 wIndex
, __le32 __iomem
*addr
, u32 port_status
)
484 /* Don't allow the USB core to disable SuperSpeed ports. */
485 if (hcd
->speed
>= HCD_USB3
) {
486 xhci_dbg(xhci
, "Ignoring request to disable "
487 "SuperSpeed port.\n");
491 if (xhci
->quirks
& XHCI_BROKEN_PORT_PED
) {
493 "Broken Port Enabled/Disabled, ignoring port disable request.\n");
497 /* Write 1 to disable the port */
498 writel(port_status
| PORT_PE
, addr
);
499 port_status
= readl(addr
);
500 xhci_dbg(xhci
, "disable port, actual port %d status = 0x%x\n",
501 wIndex
, port_status
);
504 static void xhci_clear_port_change_bit(struct xhci_hcd
*xhci
, u16 wValue
,
505 u16 wIndex
, __le32 __iomem
*addr
, u32 port_status
)
507 char *port_change_bit
;
511 case USB_PORT_FEAT_C_RESET
:
513 port_change_bit
= "reset";
515 case USB_PORT_FEAT_C_BH_PORT_RESET
:
517 port_change_bit
= "warm(BH) reset";
519 case USB_PORT_FEAT_C_CONNECTION
:
521 port_change_bit
= "connect";
523 case USB_PORT_FEAT_C_OVER_CURRENT
:
525 port_change_bit
= "over-current";
527 case USB_PORT_FEAT_C_ENABLE
:
529 port_change_bit
= "enable/disable";
531 case USB_PORT_FEAT_C_SUSPEND
:
533 port_change_bit
= "suspend/resume";
535 case USB_PORT_FEAT_C_PORT_LINK_STATE
:
537 port_change_bit
= "link state";
539 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR
:
541 port_change_bit
= "config error";
544 /* Should never happen */
547 /* Change bits are all write 1 to clear */
548 writel(port_status
| status
, addr
);
549 port_status
= readl(addr
);
550 xhci_dbg(xhci
, "clear port %s change, actual port %d status = 0x%x\n",
551 port_change_bit
, wIndex
, port_status
);
554 static int xhci_get_ports(struct usb_hcd
*hcd
, __le32 __iomem
***port_array
)
557 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
559 if (hcd
->speed
>= HCD_USB3
) {
560 max_ports
= xhci
->num_usb3_ports
;
561 *port_array
= xhci
->usb3_ports
;
563 max_ports
= xhci
->num_usb2_ports
;
564 *port_array
= xhci
->usb2_ports
;
570 static __le32 __iomem
*xhci_get_port_io_addr(struct usb_hcd
*hcd
, int index
)
572 __le32 __iomem
**port_array
;
574 xhci_get_ports(hcd
, &port_array
);
575 return port_array
[index
];
579 * xhci_set_port_power() must be called with xhci->lock held.
580 * It will release and re-aquire the lock while calling ACPI
583 static void xhci_set_port_power(struct xhci_hcd
*xhci
, struct usb_hcd
*hcd
,
584 u16 index
, bool on
, unsigned long *flags
)
586 __le32 __iomem
*addr
;
589 addr
= xhci_get_port_io_addr(hcd
, index
);
591 temp
= xhci_port_state_to_neutral(temp
);
594 writel(temp
| PORT_POWER
, addr
);
596 xhci_dbg(xhci
, "set port power, actual port %d status = 0x%x\n",
600 writel(temp
& ~PORT_POWER
, addr
);
603 spin_unlock_irqrestore(&xhci
->lock
, *flags
);
604 temp
= usb_acpi_power_manageable(hcd
->self
.root_hub
,
607 usb_acpi_set_power_state(hcd
->self
.root_hub
,
609 spin_lock_irqsave(&xhci
->lock
, *flags
);
612 static void xhci_port_set_test_mode(struct xhci_hcd
*xhci
,
613 u16 test_mode
, u16 wIndex
)
616 __le32 __iomem
*addr
;
618 /* xhci only supports test mode for usb2 ports, i.e. xhci->main_hcd */
619 addr
= xhci_get_port_io_addr(xhci
->main_hcd
, wIndex
);
620 temp
= readl(addr
+ PORTPMSC
);
621 temp
|= test_mode
<< PORT_TEST_MODE_SHIFT
;
622 writel(temp
, addr
+ PORTPMSC
);
623 xhci
->test_mode
= test_mode
;
624 if (test_mode
== TEST_FORCE_EN
)
628 static int xhci_enter_test_mode(struct xhci_hcd
*xhci
,
629 u16 test_mode
, u16 wIndex
, unsigned long *flags
)
633 /* Disable all Device Slots */
634 xhci_dbg(xhci
, "Disable all slots\n");
635 spin_unlock_irqrestore(&xhci
->lock
, *flags
);
636 for (i
= 1; i
<= HCS_MAX_SLOTS(xhci
->hcs_params1
); i
++) {
640 retval
= xhci_disable_slot(xhci
, i
);
642 xhci_err(xhci
, "Failed to disable slot %d, %d. Enter test mode anyway\n",
645 spin_lock_irqsave(&xhci
->lock
, *flags
);
646 /* Put all ports to the Disable state by clear PP */
647 xhci_dbg(xhci
, "Disable all port (PP = 0)\n");
648 /* Power off USB3 ports*/
649 for (i
= 0; i
< xhci
->num_usb3_ports
; i
++)
650 xhci_set_port_power(xhci
, xhci
->shared_hcd
, i
, false, flags
);
651 /* Power off USB2 ports*/
652 for (i
= 0; i
< xhci
->num_usb2_ports
; i
++)
653 xhci_set_port_power(xhci
, xhci
->main_hcd
, i
, false, flags
);
654 /* Stop the controller */
655 xhci_dbg(xhci
, "Stop controller\n");
656 retval
= xhci_halt(xhci
);
659 /* Disable runtime PM for test mode */
660 pm_runtime_forbid(xhci_to_hcd(xhci
)->self
.controller
);
661 /* Set PORTPMSC.PTC field to enter selected test mode */
662 /* Port is selected by wIndex. port_id = wIndex + 1 */
663 xhci_dbg(xhci
, "Enter Test Mode: %d, Port_id=%d\n",
664 test_mode
, wIndex
+ 1);
665 xhci_port_set_test_mode(xhci
, test_mode
, wIndex
);
669 static int xhci_exit_test_mode(struct xhci_hcd
*xhci
)
673 if (!xhci
->test_mode
) {
674 xhci_err(xhci
, "Not in test mode, do nothing.\n");
677 if (xhci
->test_mode
== TEST_FORCE_EN
&&
678 !(xhci
->xhc_state
& XHCI_STATE_HALTED
)) {
679 retval
= xhci_halt(xhci
);
683 pm_runtime_allow(xhci_to_hcd(xhci
)->self
.controller
);
685 return xhci_reset(xhci
);
688 void xhci_set_link_state(struct xhci_hcd
*xhci
, __le32 __iomem
**port_array
,
689 int port_id
, u32 link_state
)
693 temp
= readl(port_array
[port_id
]);
694 temp
= xhci_port_state_to_neutral(temp
);
695 temp
&= ~PORT_PLS_MASK
;
696 temp
|= PORT_LINK_STROBE
| link_state
;
697 writel(temp
, port_array
[port_id
]);
700 static void xhci_set_remote_wake_mask(struct xhci_hcd
*xhci
,
701 __le32 __iomem
**port_array
, int port_id
, u16 wake_mask
)
705 temp
= readl(port_array
[port_id
]);
706 temp
= xhci_port_state_to_neutral(temp
);
708 if (wake_mask
& USB_PORT_FEAT_REMOTE_WAKE_CONNECT
)
709 temp
|= PORT_WKCONN_E
;
711 temp
&= ~PORT_WKCONN_E
;
713 if (wake_mask
& USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT
)
714 temp
|= PORT_WKDISC_E
;
716 temp
&= ~PORT_WKDISC_E
;
718 if (wake_mask
& USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT
)
721 temp
&= ~PORT_WKOC_E
;
723 writel(temp
, port_array
[port_id
]);
726 /* Test and clear port RWC bit */
727 void xhci_test_and_clear_bit(struct xhci_hcd
*xhci
, __le32 __iomem
**port_array
,
728 int port_id
, u32 port_bit
)
732 temp
= readl(port_array
[port_id
]);
733 if (temp
& port_bit
) {
734 temp
= xhci_port_state_to_neutral(temp
);
736 writel(temp
, port_array
[port_id
]);
740 /* Updates Link Status for USB 2.1 port */
741 static void xhci_hub_report_usb2_link_state(u32
*status
, u32 status_reg
)
743 if ((status_reg
& PORT_PLS_MASK
) == XDEV_U2
)
744 *status
|= USB_PORT_STAT_L1
;
747 /* Updates Link Status for super Speed port */
748 static void xhci_hub_report_usb3_link_state(struct xhci_hcd
*xhci
,
749 u32
*status
, u32 status_reg
)
751 u32 pls
= status_reg
& PORT_PLS_MASK
;
753 /* resume state is a xHCI internal state.
754 * Do not report it to usb core, instead, pretend to be U3,
755 * thus usb core knows it's not ready for transfer
757 if (pls
== XDEV_RESUME
) {
758 *status
|= USB_SS_PORT_LS_U3
;
762 /* When the CAS bit is set then warm reset
763 * should be performed on port
765 if (status_reg
& PORT_CAS
) {
766 /* The CAS bit can be set while the port is
768 * Only roothubs have CAS bit, so we
769 * pretend to be in compliance mode
770 * unless we're already in compliance
771 * or the inactive state.
773 if (pls
!= USB_SS_PORT_LS_COMP_MOD
&&
774 pls
!= USB_SS_PORT_LS_SS_INACTIVE
) {
775 pls
= USB_SS_PORT_LS_COMP_MOD
;
777 /* Return also connection bit -
778 * hub state machine resets port
779 * when this bit is set.
781 pls
|= USB_PORT_STAT_CONNECTION
;
784 * If CAS bit isn't set but the Port is already at
785 * Compliance Mode, fake a connection so the USB core
786 * notices the Compliance state and resets the port.
787 * This resolves an issue generated by the SN65LVPE502CP
788 * in which sometimes the port enters compliance mode
789 * caused by a delay on the host-device negotiation.
791 if ((xhci
->quirks
& XHCI_COMP_MODE_QUIRK
) &&
792 (pls
== USB_SS_PORT_LS_COMP_MOD
))
793 pls
|= USB_PORT_STAT_CONNECTION
;
796 /* update status field */
801 * Function for Compliance Mode Quirk.
803 * This Function verifies if all xhc USB3 ports have entered U0, if so,
804 * the compliance mode timer is deleted. A port won't enter
805 * compliance mode if it has previously entered U0.
807 static void xhci_del_comp_mod_timer(struct xhci_hcd
*xhci
, u32 status
,
810 u32 all_ports_seen_u0
= ((1 << xhci
->num_usb3_ports
)-1);
811 bool port_in_u0
= ((status
& PORT_PLS_MASK
) == XDEV_U0
);
813 if (!(xhci
->quirks
& XHCI_COMP_MODE_QUIRK
))
816 if ((xhci
->port_status_u0
!= all_ports_seen_u0
) && port_in_u0
) {
817 xhci
->port_status_u0
|= 1 << wIndex
;
818 if (xhci
->port_status_u0
== all_ports_seen_u0
) {
819 del_timer_sync(&xhci
->comp_mode_recovery_timer
);
820 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
821 "All USB3 ports have entered U0 already!");
822 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
823 "Compliance Mode Recovery Timer Deleted.");
828 static u32
xhci_get_ext_port_status(u32 raw_port_status
, u32 port_li
)
833 /* only support rx and tx lane counts of 1 in usb3.1 spec */
834 speed_id
= DEV_PORT_SPEED(raw_port_status
);
835 ext_stat
|= speed_id
; /* bits 3:0, RX speed id */
836 ext_stat
|= speed_id
<< 4; /* bits 7:4, TX speed id */
838 ext_stat
|= PORT_RX_LANES(port_li
) << 8; /* bits 11:8 Rx lane count */
839 ext_stat
|= PORT_TX_LANES(port_li
) << 12; /* bits 15:12 Tx lane count */
845 * Converts a raw xHCI port status into the format that external USB 2.0 or USB
848 * Possible side effects:
849 * - Mark a port as being done with device resume,
850 * and ring the endpoint doorbells.
851 * - Stop the Synopsys redriver Compliance Mode polling.
852 * - Drop and reacquire the xHCI lock, in order to wait for port resume.
854 static u32
xhci_get_port_status(struct usb_hcd
*hcd
,
855 struct xhci_bus_state
*bus_state
,
856 __le32 __iomem
**port_array
,
857 u16 wIndex
, u32 raw_port_status
,
859 __releases(&xhci
->lock
)
860 __acquires(&xhci
->lock
)
862 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
866 /* wPortChange bits */
867 if (raw_port_status
& PORT_CSC
)
868 status
|= USB_PORT_STAT_C_CONNECTION
<< 16;
869 if (raw_port_status
& PORT_PEC
)
870 status
|= USB_PORT_STAT_C_ENABLE
<< 16;
871 if ((raw_port_status
& PORT_OCC
))
872 status
|= USB_PORT_STAT_C_OVERCURRENT
<< 16;
873 if ((raw_port_status
& PORT_RC
))
874 status
|= USB_PORT_STAT_C_RESET
<< 16;
876 if (hcd
->speed
>= HCD_USB3
) {
877 /* Port link change with port in resume state should not be
878 * reported to usbcore, as this is an internal state to be
879 * handled by xhci driver. Reporting PLC to usbcore may
880 * cause usbcore clearing PLC first and port change event
881 * irq won't be generated.
883 if ((raw_port_status
& PORT_PLC
) &&
884 (raw_port_status
& PORT_PLS_MASK
) != XDEV_RESUME
)
885 status
|= USB_PORT_STAT_C_LINK_STATE
<< 16;
886 if ((raw_port_status
& PORT_WRC
))
887 status
|= USB_PORT_STAT_C_BH_RESET
<< 16;
888 if ((raw_port_status
& PORT_CEC
))
889 status
|= USB_PORT_STAT_C_CONFIG_ERROR
<< 16;
892 if (hcd
->speed
< HCD_USB3
) {
893 if ((raw_port_status
& PORT_PLS_MASK
) == XDEV_U3
894 && (raw_port_status
& PORT_POWER
))
895 status
|= USB_PORT_STAT_SUSPEND
;
897 if ((raw_port_status
& PORT_PLS_MASK
) == XDEV_RESUME
&&
898 !DEV_SUPERSPEED_ANY(raw_port_status
)) {
899 if ((raw_port_status
& PORT_RESET
) ||
900 !(raw_port_status
& PORT_PE
))
902 /* did port event handler already start resume timing? */
903 if (!bus_state
->resume_done
[wIndex
]) {
904 /* If not, maybe we are in a host initated resume? */
905 if (test_bit(wIndex
, &bus_state
->resuming_ports
)) {
906 /* Host initated resume doesn't time the resume
907 * signalling using resume_done[].
908 * It manually sets RESUME state, sleeps 20ms
909 * and sets U0 state. This should probably be
910 * changed, but not right now.
913 /* port resume was discovered now and here,
914 * start resume timing
916 unsigned long timeout
= jiffies
+
917 msecs_to_jiffies(USB_RESUME_TIMEOUT
);
919 set_bit(wIndex
, &bus_state
->resuming_ports
);
920 bus_state
->resume_done
[wIndex
] = timeout
;
921 mod_timer(&hcd
->rh_timer
, timeout
);
923 /* Has resume been signalled for USB_RESUME_TIME yet? */
924 } else if (time_after_eq(jiffies
,
925 bus_state
->resume_done
[wIndex
])) {
928 xhci_dbg(xhci
, "Resume USB2 port %d\n",
930 bus_state
->resume_done
[wIndex
] = 0;
931 clear_bit(wIndex
, &bus_state
->resuming_ports
);
933 set_bit(wIndex
, &bus_state
->rexit_ports
);
935 xhci_test_and_clear_bit(xhci
, port_array
, wIndex
,
937 xhci_set_link_state(xhci
, port_array
, wIndex
,
940 spin_unlock_irqrestore(&xhci
->lock
, flags
);
941 time_left
= wait_for_completion_timeout(
942 &bus_state
->rexit_done
[wIndex
],
944 XHCI_MAX_REXIT_TIMEOUT
));
945 spin_lock_irqsave(&xhci
->lock
, flags
);
948 slot_id
= xhci_find_slot_id_by_port(hcd
,
951 xhci_dbg(xhci
, "slot_id is zero\n");
954 xhci_ring_device(xhci
, slot_id
);
956 int port_status
= readl(port_array
[wIndex
]);
957 xhci_warn(xhci
, "Port resume took longer than %i msec, port status = 0x%x\n",
958 XHCI_MAX_REXIT_TIMEOUT
,
960 status
|= USB_PORT_STAT_SUSPEND
;
961 clear_bit(wIndex
, &bus_state
->rexit_ports
);
964 bus_state
->port_c_suspend
|= 1 << wIndex
;
965 bus_state
->suspended_ports
&= ~(1 << wIndex
);
968 * The resume has been signaling for less than
969 * USB_RESUME_TIME. Report the port status as SUSPEND,
970 * let the usbcore check port status again and clear
971 * resume signaling later.
973 status
|= USB_PORT_STAT_SUSPEND
;
977 * Clear stale usb2 resume signalling variables in case port changed
978 * state during resume signalling. For example on error
980 if ((bus_state
->resume_done
[wIndex
] ||
981 test_bit(wIndex
, &bus_state
->resuming_ports
)) &&
982 (raw_port_status
& PORT_PLS_MASK
) != XDEV_U3
&&
983 (raw_port_status
& PORT_PLS_MASK
) != XDEV_RESUME
) {
984 bus_state
->resume_done
[wIndex
] = 0;
985 clear_bit(wIndex
, &bus_state
->resuming_ports
);
989 if ((raw_port_status
& PORT_PLS_MASK
) == XDEV_U0
&&
990 (raw_port_status
& PORT_POWER
)) {
991 if (bus_state
->suspended_ports
& (1 << wIndex
)) {
992 bus_state
->suspended_ports
&= ~(1 << wIndex
);
993 if (hcd
->speed
< HCD_USB3
)
994 bus_state
->port_c_suspend
|= 1 << wIndex
;
996 bus_state
->resume_done
[wIndex
] = 0;
997 clear_bit(wIndex
, &bus_state
->resuming_ports
);
999 if (raw_port_status
& PORT_CONNECT
) {
1000 status
|= USB_PORT_STAT_CONNECTION
;
1001 status
|= xhci_port_speed(raw_port_status
);
1003 if (raw_port_status
& PORT_PE
)
1004 status
|= USB_PORT_STAT_ENABLE
;
1005 if (raw_port_status
& PORT_OC
)
1006 status
|= USB_PORT_STAT_OVERCURRENT
;
1007 if (raw_port_status
& PORT_RESET
)
1008 status
|= USB_PORT_STAT_RESET
;
1009 if (raw_port_status
& PORT_POWER
) {
1010 if (hcd
->speed
>= HCD_USB3
)
1011 status
|= USB_SS_PORT_STAT_POWER
;
1013 status
|= USB_PORT_STAT_POWER
;
1015 /* Update Port Link State */
1016 if (hcd
->speed
>= HCD_USB3
) {
1017 xhci_hub_report_usb3_link_state(xhci
, &status
, raw_port_status
);
1019 * Verify if all USB3 Ports Have entered U0 already.
1020 * Delete Compliance Mode Timer if so.
1022 xhci_del_comp_mod_timer(xhci
, raw_port_status
, wIndex
);
1024 xhci_hub_report_usb2_link_state(&status
, raw_port_status
);
1026 if (bus_state
->port_c_suspend
& (1 << wIndex
))
1027 status
|= USB_PORT_STAT_C_SUSPEND
<< 16;
1032 int xhci_hub_control(struct usb_hcd
*hcd
, u16 typeReq
, u16 wValue
,
1033 u16 wIndex
, char *buf
, u16 wLength
)
1035 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
1037 unsigned long flags
;
1040 __le32 __iomem
**port_array
;
1042 struct xhci_bus_state
*bus_state
;
1048 max_ports
= xhci_get_ports(hcd
, &port_array
);
1049 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
1051 spin_lock_irqsave(&xhci
->lock
, flags
);
1054 /* No power source, over-current reported per port */
1057 case GetHubDescriptor
:
1058 /* Check to make sure userspace is asking for the USB 3.0 hub
1059 * descriptor for the USB 3.0 roothub. If not, we stall the
1060 * endpoint, like external hubs do.
1062 if (hcd
->speed
>= HCD_USB3
&&
1063 (wLength
< USB_DT_SS_HUB_SIZE
||
1064 wValue
!= (USB_DT_SS_HUB
<< 8))) {
1065 xhci_dbg(xhci
, "Wrong hub descriptor type for "
1066 "USB 3.0 roothub.\n");
1069 xhci_hub_descriptor(hcd
, xhci
,
1070 (struct usb_hub_descriptor
*) buf
);
1072 case DeviceRequest
| USB_REQ_GET_DESCRIPTOR
:
1073 if ((wValue
& 0xff00) != (USB_DT_BOS
<< 8))
1076 if (hcd
->speed
< HCD_USB3
)
1079 retval
= xhci_create_usb3_bos_desc(xhci
, buf
, wLength
);
1080 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1083 if (!wIndex
|| wIndex
> max_ports
)
1086 temp
= readl(port_array
[wIndex
]);
1087 if (temp
== ~(u32
)0) {
1092 status
= xhci_get_port_status(hcd
, bus_state
, port_array
,
1093 wIndex
, temp
, flags
);
1094 if (status
== 0xffffffff)
1097 xhci_dbg(xhci
, "get port status, actual port %d status = 0x%x\n",
1099 xhci_dbg(xhci
, "Get port status returned 0x%x\n", status
);
1101 put_unaligned(cpu_to_le32(status
), (__le32
*) buf
);
1102 /* if USB 3.1 extended port status return additional 4 bytes */
1103 if (wValue
== 0x02) {
1106 if (hcd
->speed
< HCD_USB31
|| wLength
!= 8) {
1107 xhci_err(xhci
, "get ext port status invalid parameter\n");
1111 port_li
= readl(port_array
[wIndex
] + PORTLI
);
1112 status
= xhci_get_ext_port_status(temp
, port_li
);
1113 put_unaligned_le32(cpu_to_le32(status
), &buf
[4]);
1116 case SetPortFeature
:
1117 if (wValue
== USB_PORT_FEAT_LINK_STATE
)
1118 link_state
= (wIndex
& 0xff00) >> 3;
1119 if (wValue
== USB_PORT_FEAT_REMOTE_WAKE_MASK
)
1120 wake_mask
= wIndex
& 0xff00;
1121 if (wValue
== USB_PORT_FEAT_TEST
)
1122 test_mode
= (wIndex
& 0xff00) >> 8;
1123 /* The MSB of wIndex is the U1/U2 timeout */
1124 timeout
= (wIndex
& 0xff00) >> 8;
1126 if (!wIndex
|| wIndex
> max_ports
)
1129 temp
= readl(port_array
[wIndex
]);
1130 if (temp
== ~(u32
)0) {
1135 temp
= xhci_port_state_to_neutral(temp
);
1136 /* FIXME: What new port features do we need to support? */
1138 case USB_PORT_FEAT_SUSPEND
:
1139 temp
= readl(port_array
[wIndex
]);
1140 if ((temp
& PORT_PLS_MASK
) != XDEV_U0
) {
1141 /* Resume the port to U0 first */
1142 xhci_set_link_state(xhci
, port_array
, wIndex
,
1144 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1146 spin_lock_irqsave(&xhci
->lock
, flags
);
1148 /* In spec software should not attempt to suspend
1149 * a port unless the port reports that it is in the
1150 * enabled (PED = ‘1’,PLS < ‘3’) state.
1152 temp
= readl(port_array
[wIndex
]);
1153 if ((temp
& PORT_PE
) == 0 || (temp
& PORT_RESET
)
1154 || (temp
& PORT_PLS_MASK
) >= XDEV_U3
) {
1155 xhci_warn(xhci
, "USB core suspending device not in U0/U1/U2.\n");
1159 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1162 xhci_warn(xhci
, "slot_id is zero\n");
1165 /* unlock to execute stop endpoint commands */
1166 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1167 xhci_stop_device(xhci
, slot_id
, 1);
1168 spin_lock_irqsave(&xhci
->lock
, flags
);
1170 xhci_set_link_state(xhci
, port_array
, wIndex
, XDEV_U3
);
1172 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1173 msleep(10); /* wait device to enter */
1174 spin_lock_irqsave(&xhci
->lock
, flags
);
1176 temp
= readl(port_array
[wIndex
]);
1177 bus_state
->suspended_ports
|= 1 << wIndex
;
1179 case USB_PORT_FEAT_LINK_STATE
:
1180 temp
= readl(port_array
[wIndex
]);
1183 if (link_state
== USB_SS_PORT_LS_SS_DISABLED
) {
1184 xhci_dbg(xhci
, "Disable port %d\n", wIndex
);
1185 temp
= xhci_port_state_to_neutral(temp
);
1187 * Clear all change bits, so that we get a new
1190 temp
|= PORT_CSC
| PORT_PEC
| PORT_WRC
|
1191 PORT_OCC
| PORT_RC
| PORT_PLC
|
1193 writel(temp
| PORT_PE
, port_array
[wIndex
]);
1194 temp
= readl(port_array
[wIndex
]);
1198 /* Put link in RxDetect (enable port) */
1199 if (link_state
== USB_SS_PORT_LS_RX_DETECT
) {
1200 xhci_dbg(xhci
, "Enable port %d\n", wIndex
);
1201 xhci_set_link_state(xhci
, port_array
, wIndex
,
1203 temp
= readl(port_array
[wIndex
]);
1208 * For xHCI 1.1 according to section 4.19.1.2.4.1 a
1209 * root hub port's transition to compliance mode upon
1210 * detecting LFPS timeout may be controlled by an
1211 * Compliance Transition Enabled (CTE) flag (not
1212 * software visible). This flag is set by writing 0xA
1213 * to PORTSC PLS field which will allow transition to
1214 * compliance mode the next time LFPS timeout is
1215 * encountered. A warm reset will clear it.
1217 * The CTE flag is only supported if the HCCPARAMS2 CTC
1218 * flag is set, otherwise, the compliance substate is
1219 * automatically entered as on 1.0 and prior.
1221 if (link_state
== USB_SS_PORT_LS_COMP_MOD
) {
1222 if (!HCC2_CTC(xhci
->hcc_params2
)) {
1223 xhci_dbg(xhci
, "CTC flag is 0, port already supports entering compliance mode\n");
1227 if ((temp
& PORT_CONNECT
)) {
1228 xhci_warn(xhci
, "Can't set compliance mode when port is connected\n");
1232 xhci_dbg(xhci
, "Enable compliance mode transition for port %d\n",
1234 xhci_set_link_state(xhci
, port_array
, wIndex
,
1236 temp
= readl(port_array
[wIndex
]);
1240 /* Software should not attempt to set
1241 * port link state above '3' (U3) and the port
1244 if ((temp
& PORT_PE
) == 0 ||
1245 (link_state
> USB_SS_PORT_LS_U3
)) {
1246 xhci_warn(xhci
, "Cannot set link state.\n");
1250 if (link_state
== USB_SS_PORT_LS_U3
) {
1251 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1254 /* unlock to execute stop endpoint
1256 spin_unlock_irqrestore(&xhci
->lock
,
1258 xhci_stop_device(xhci
, slot_id
, 1);
1259 spin_lock_irqsave(&xhci
->lock
, flags
);
1263 xhci_set_link_state(xhci
, port_array
, wIndex
,
1266 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1267 msleep(20); /* wait device to enter */
1268 spin_lock_irqsave(&xhci
->lock
, flags
);
1270 temp
= readl(port_array
[wIndex
]);
1271 if (link_state
== USB_SS_PORT_LS_U3
)
1272 bus_state
->suspended_ports
|= 1 << wIndex
;
1274 case USB_PORT_FEAT_POWER
:
1276 * Turn on ports, even if there isn't per-port switching.
1277 * HC will report connect events even before this is set.
1278 * However, hub_wq will ignore the roothub events until
1279 * the roothub is registered.
1281 xhci_set_port_power(xhci
, hcd
, wIndex
, true, &flags
);
1283 case USB_PORT_FEAT_RESET
:
1284 temp
= (temp
| PORT_RESET
);
1285 writel(temp
, port_array
[wIndex
]);
1287 temp
= readl(port_array
[wIndex
]);
1288 xhci_dbg(xhci
, "set port reset, actual port %d status = 0x%x\n", wIndex
, temp
);
1290 case USB_PORT_FEAT_REMOTE_WAKE_MASK
:
1291 xhci_set_remote_wake_mask(xhci
, port_array
,
1293 temp
= readl(port_array
[wIndex
]);
1294 xhci_dbg(xhci
, "set port remote wake mask, "
1295 "actual port %d status = 0x%x\n",
1298 case USB_PORT_FEAT_BH_PORT_RESET
:
1300 writel(temp
, port_array
[wIndex
]);
1302 temp
= readl(port_array
[wIndex
]);
1304 case USB_PORT_FEAT_U1_TIMEOUT
:
1305 if (hcd
->speed
< HCD_USB3
)
1307 temp
= readl(port_array
[wIndex
] + PORTPMSC
);
1308 temp
&= ~PORT_U1_TIMEOUT_MASK
;
1309 temp
|= PORT_U1_TIMEOUT(timeout
);
1310 writel(temp
, port_array
[wIndex
] + PORTPMSC
);
1312 case USB_PORT_FEAT_U2_TIMEOUT
:
1313 if (hcd
->speed
< HCD_USB3
)
1315 temp
= readl(port_array
[wIndex
] + PORTPMSC
);
1316 temp
&= ~PORT_U2_TIMEOUT_MASK
;
1317 temp
|= PORT_U2_TIMEOUT(timeout
);
1318 writel(temp
, port_array
[wIndex
] + PORTPMSC
);
1320 case USB_PORT_FEAT_TEST
:
1321 /* 4.19.6 Port Test Modes (USB2 Test Mode) */
1322 if (hcd
->speed
!= HCD_USB2
)
1324 if (test_mode
> TEST_FORCE_EN
|| test_mode
< TEST_J
)
1326 retval
= xhci_enter_test_mode(xhci
, test_mode
, wIndex
,
1332 /* unblock any posted writes */
1333 temp
= readl(port_array
[wIndex
]);
1335 case ClearPortFeature
:
1336 if (!wIndex
|| wIndex
> max_ports
)
1339 temp
= readl(port_array
[wIndex
]);
1340 if (temp
== ~(u32
)0) {
1345 /* FIXME: What new port features do we need to support? */
1346 temp
= xhci_port_state_to_neutral(temp
);
1348 case USB_PORT_FEAT_SUSPEND
:
1349 temp
= readl(port_array
[wIndex
]);
1350 xhci_dbg(xhci
, "clear USB_PORT_FEAT_SUSPEND\n");
1351 xhci_dbg(xhci
, "PORTSC %04x\n", temp
);
1352 if (temp
& PORT_RESET
)
1354 if ((temp
& PORT_PLS_MASK
) == XDEV_U3
) {
1355 if ((temp
& PORT_PE
) == 0)
1358 set_bit(wIndex
, &bus_state
->resuming_ports
);
1359 xhci_set_link_state(xhci
, port_array
, wIndex
,
1361 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1362 msleep(USB_RESUME_TIMEOUT
);
1363 spin_lock_irqsave(&xhci
->lock
, flags
);
1364 xhci_set_link_state(xhci
, port_array
, wIndex
,
1366 clear_bit(wIndex
, &bus_state
->resuming_ports
);
1368 bus_state
->port_c_suspend
|= 1 << wIndex
;
1370 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1373 xhci_dbg(xhci
, "slot_id is zero\n");
1376 xhci_ring_device(xhci
, slot_id
);
1378 case USB_PORT_FEAT_C_SUSPEND
:
1379 bus_state
->port_c_suspend
&= ~(1 << wIndex
);
1380 case USB_PORT_FEAT_C_RESET
:
1381 case USB_PORT_FEAT_C_BH_PORT_RESET
:
1382 case USB_PORT_FEAT_C_CONNECTION
:
1383 case USB_PORT_FEAT_C_OVER_CURRENT
:
1384 case USB_PORT_FEAT_C_ENABLE
:
1385 case USB_PORT_FEAT_C_PORT_LINK_STATE
:
1386 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR
:
1387 xhci_clear_port_change_bit(xhci
, wValue
, wIndex
,
1388 port_array
[wIndex
], temp
);
1390 case USB_PORT_FEAT_ENABLE
:
1391 xhci_disable_port(hcd
, xhci
, wIndex
,
1392 port_array
[wIndex
], temp
);
1394 case USB_PORT_FEAT_POWER
:
1395 xhci_set_port_power(xhci
, hcd
, wIndex
, false, &flags
);
1397 case USB_PORT_FEAT_TEST
:
1398 retval
= xhci_exit_test_mode(xhci
);
1406 /* "stall" on error */
1409 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1414 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1415 * Ports are 0-indexed from the HCD point of view,
1416 * and 1-indexed from the USB core pointer of view.
1418 * Note that the status change bits will be cleared as soon as a port status
1419 * change event is generated, so we use the saved status from that event.
1421 int xhci_hub_status_data(struct usb_hcd
*hcd
, char *buf
)
1423 unsigned long flags
;
1427 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
1429 __le32 __iomem
**port_array
;
1430 struct xhci_bus_state
*bus_state
;
1431 bool reset_change
= false;
1433 max_ports
= xhci_get_ports(hcd
, &port_array
);
1434 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
1436 /* Initial status is no changes */
1437 retval
= (max_ports
+ 8) / 8;
1438 memset(buf
, 0, retval
);
1441 * Inform the usbcore about resume-in-progress by returning
1442 * a non-zero value even if there are no status changes.
1444 status
= bus_state
->resuming_ports
;
1446 mask
= PORT_CSC
| PORT_PEC
| PORT_OCC
| PORT_PLC
| PORT_WRC
| PORT_CEC
;
1448 spin_lock_irqsave(&xhci
->lock
, flags
);
1449 /* For each port, did anything change? If so, set that bit in buf. */
1450 for (i
= 0; i
< max_ports
; i
++) {
1451 temp
= readl(port_array
[i
]);
1452 if (temp
== ~(u32
)0) {
1457 if ((temp
& mask
) != 0 ||
1458 (bus_state
->port_c_suspend
& 1 << i
) ||
1459 (bus_state
->resume_done
[i
] && time_after_eq(
1460 jiffies
, bus_state
->resume_done
[i
]))) {
1461 buf
[(i
+ 1) / 8] |= 1 << (i
+ 1) % 8;
1464 if ((temp
& PORT_RC
))
1465 reset_change
= true;
1467 if (!status
&& !reset_change
) {
1468 xhci_dbg(xhci
, "%s: stopping port polling.\n", __func__
);
1469 clear_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
1471 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1472 return status
? retval
: 0;
1477 int xhci_bus_suspend(struct usb_hcd
*hcd
)
1479 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
1480 int max_ports
, port_index
;
1481 __le32 __iomem
**port_array
;
1482 struct xhci_bus_state
*bus_state
;
1483 unsigned long flags
;
1485 max_ports
= xhci_get_ports(hcd
, &port_array
);
1486 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
1488 spin_lock_irqsave(&xhci
->lock
, flags
);
1490 if (hcd
->self
.root_hub
->do_remote_wakeup
) {
1491 if (bus_state
->resuming_ports
|| /* USB2 */
1492 bus_state
->port_remote_wakeup
) { /* USB3 */
1493 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1494 xhci_dbg(xhci
, "suspend failed because a port is resuming\n");
1499 port_index
= max_ports
;
1500 bus_state
->bus_suspended
= 0;
1501 while (port_index
--) {
1502 /* suspend the port if the port is not suspended */
1506 t1
= readl(port_array
[port_index
]);
1507 t2
= xhci_port_state_to_neutral(t1
);
1509 if ((t1
& PORT_PE
) && !(t1
& PORT_PLS_MASK
)) {
1510 xhci_dbg(xhci
, "port %d not suspended\n", port_index
);
1511 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1514 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1515 xhci_stop_device(xhci
, slot_id
, 1);
1516 spin_lock_irqsave(&xhci
->lock
, flags
);
1518 t2
&= ~PORT_PLS_MASK
;
1519 t2
|= PORT_LINK_STROBE
| XDEV_U3
;
1520 set_bit(port_index
, &bus_state
->bus_suspended
);
1522 /* USB core sets remote wake mask for USB 3.0 hubs,
1523 * including the USB 3.0 roothub, but only if CONFIG_PM
1524 * is enabled, so also enable remote wake here.
1526 if (hcd
->self
.root_hub
->do_remote_wakeup
) {
1527 if (t1
& PORT_CONNECT
) {
1528 t2
|= PORT_WKOC_E
| PORT_WKDISC_E
;
1529 t2
&= ~PORT_WKCONN_E
;
1531 t2
|= PORT_WKOC_E
| PORT_WKCONN_E
;
1532 t2
&= ~PORT_WKDISC_E
;
1535 t2
&= ~PORT_WAKE_BITS
;
1537 t1
= xhci_port_state_to_neutral(t1
);
1539 writel(t2
, port_array
[port_index
]);
1541 hcd
->state
= HC_STATE_SUSPENDED
;
1542 bus_state
->next_statechange
= jiffies
+ msecs_to_jiffies(10);
1543 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1548 * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1549 * warm reset a USB3 device stuck in polling or compliance mode after resume.
1550 * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1552 static bool xhci_port_missing_cas_quirk(int port_index
,
1553 __le32 __iomem
**port_array
)
1557 portsc
= readl(port_array
[port_index
]);
1559 /* if any of these are set we are not stuck */
1560 if (portsc
& (PORT_CONNECT
| PORT_CAS
))
1563 if (((portsc
& PORT_PLS_MASK
) != XDEV_POLLING
) &&
1564 ((portsc
& PORT_PLS_MASK
) != XDEV_COMP_MODE
))
1567 /* clear wakeup/change bits, and do a warm port reset */
1568 portsc
&= ~(PORT_RWC_BITS
| PORT_CEC
| PORT_WAKE_BITS
);
1570 writel(portsc
, port_array
[port_index
]);
1572 readl(port_array
[port_index
]);
1576 int xhci_bus_resume(struct usb_hcd
*hcd
)
1578 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
1579 struct xhci_bus_state
*bus_state
;
1580 __le32 __iomem
**port_array
;
1581 unsigned long flags
;
1582 int max_ports
, port_index
;
1588 max_ports
= xhci_get_ports(hcd
, &port_array
);
1589 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
1591 if (time_before(jiffies
, bus_state
->next_statechange
))
1594 spin_lock_irqsave(&xhci
->lock
, flags
);
1595 if (!HCD_HW_ACCESSIBLE(hcd
)) {
1596 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1600 /* delay the irqs */
1601 temp
= readl(&xhci
->op_regs
->command
);
1603 writel(temp
, &xhci
->op_regs
->command
);
1605 /* bus specific resume for ports we suspended at bus_suspend */
1606 if (hcd
->speed
>= HCD_USB3
)
1607 next_state
= XDEV_U0
;
1609 next_state
= XDEV_RESUME
;
1611 port_index
= max_ports
;
1612 while (port_index
--) {
1613 portsc
= readl(port_array
[port_index
]);
1615 /* warm reset CAS limited ports stuck in polling/compliance */
1616 if ((xhci
->quirks
& XHCI_MISSING_CAS
) &&
1617 (hcd
->speed
>= HCD_USB3
) &&
1618 xhci_port_missing_cas_quirk(port_index
, port_array
)) {
1619 xhci_dbg(xhci
, "reset stuck port %d\n", port_index
);
1620 clear_bit(port_index
, &bus_state
->bus_suspended
);
1623 /* resume if we suspended the link, and it is still suspended */
1624 if (test_bit(port_index
, &bus_state
->bus_suspended
))
1625 switch (portsc
& PORT_PLS_MASK
) {
1627 portsc
= xhci_port_state_to_neutral(portsc
);
1628 portsc
&= ~PORT_PLS_MASK
;
1629 portsc
|= PORT_LINK_STROBE
| next_state
;
1632 /* resume already initiated */
1635 /* not in a resumeable state, ignore it */
1636 clear_bit(port_index
,
1637 &bus_state
->bus_suspended
);
1640 /* disable wake for all ports, write new link state if needed */
1641 portsc
&= ~(PORT_RWC_BITS
| PORT_CEC
| PORT_WAKE_BITS
);
1642 writel(portsc
, port_array
[port_index
]);
1645 /* USB2 specific resume signaling delay and U0 link state transition */
1646 if (hcd
->speed
< HCD_USB3
) {
1647 if (bus_state
->bus_suspended
) {
1648 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1649 msleep(USB_RESUME_TIMEOUT
);
1650 spin_lock_irqsave(&xhci
->lock
, flags
);
1652 for_each_set_bit(port_index
, &bus_state
->bus_suspended
,
1654 /* Clear PLC to poll it later for U0 transition */
1655 xhci_test_and_clear_bit(xhci
, port_array
, port_index
,
1657 xhci_set_link_state(xhci
, port_array
, port_index
,
1662 /* poll for U0 link state complete, both USB2 and USB3 */
1663 for_each_set_bit(port_index
, &bus_state
->bus_suspended
, BITS_PER_LONG
) {
1664 sret
= xhci_handshake(port_array
[port_index
], PORT_PLC
,
1665 PORT_PLC
, 10 * 1000);
1667 xhci_warn(xhci
, "port %d resume PLC timeout\n",
1671 xhci_test_and_clear_bit(xhci
, port_array
, port_index
, PORT_PLC
);
1672 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
, port_index
+ 1);
1674 xhci_ring_device(xhci
, slot_id
);
1676 (void) readl(&xhci
->op_regs
->command
);
1678 bus_state
->next_statechange
= jiffies
+ msecs_to_jiffies(5);
1679 /* re-enable irqs */
1680 temp
= readl(&xhci
->op_regs
->command
);
1682 writel(temp
, &xhci
->op_regs
->command
);
1683 temp
= readl(&xhci
->op_regs
->command
);
1685 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1689 #endif /* CONFIG_PM */