2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/slab.h>
25 #include <asm/unaligned.h>
28 #include "xhci-trace.h"
30 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
31 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
32 PORT_RC | PORT_PLC | PORT_PE)
34 /* USB 3 BOS descriptor and a capability descriptors, combined.
35 * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
37 static u8 usb_bos_descriptor
[] = {
38 USB_DT_BOS_SIZE
, /* __u8 bLength, 5 bytes */
39 USB_DT_BOS
, /* __u8 bDescriptorType */
40 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
41 0x1, /* __u8 bNumDeviceCaps */
42 /* First device capability, SuperSpeed */
43 USB_DT_USB_SS_CAP_SIZE
, /* __u8 bLength, 10 bytes */
44 USB_DT_DEVICE_CAPABILITY
, /* Device Capability */
45 USB_SS_CAP_TYPE
, /* bDevCapabilityType, SUPERSPEED_USB */
46 0x00, /* bmAttributes, LTM off by default */
47 USB_5GBPS_OPERATION
, 0x00, /* wSpeedsSupported, 5Gbps only */
48 0x03, /* bFunctionalitySupport,
50 0x00, /* bU1DevExitLat, set later. */
51 0x00, 0x00, /* __le16 bU2DevExitLat, set later. */
52 /* Second device capability, SuperSpeedPlus */
53 0x1c, /* bLength 28, will be adjusted later */
54 USB_DT_DEVICE_CAPABILITY
, /* Device Capability */
55 USB_SSP_CAP_TYPE
, /* bDevCapabilityType SUPERSPEED_PLUS */
56 0x00, /* bReserved 0 */
57 0x23, 0x00, 0x00, 0x00, /* bmAttributes, SSAC=3 SSIC=1 */
58 0x01, 0x00, /* wFunctionalitySupport */
59 0x00, 0x00, /* wReserved 0 */
60 /* Default Sublink Speed Attributes, overwrite if custom PSI exists */
61 0x34, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, rx, ID = 4 */
62 0xb4, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, tx, ID = 4 */
63 0x35, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, rx, ID = 5 */
64 0xb5, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, tx, ID = 5 */
67 static int xhci_create_usb3_bos_desc(struct xhci_hcd
*xhci
, char *buf
,
72 u16 desc_size
, ssp_cap_size
, ssa_size
= 0;
75 desc_size
= USB_DT_BOS_SIZE
+ USB_DT_USB_SS_CAP_SIZE
;
76 ssp_cap_size
= sizeof(usb_bos_descriptor
) - desc_size
;
78 /* does xhci support USB 3.1 Enhanced SuperSpeed */
79 if (xhci
->usb3_rhub
.min_rev
>= 0x01) {
80 /* does xhci provide a PSI table for SSA speed attributes? */
81 if (xhci
->usb3_rhub
.psi_count
) {
82 /* two SSA entries for each unique PSI ID, RX and TX */
83 ssa_count
= xhci
->usb3_rhub
.psi_uid_count
* 2;
84 ssa_size
= ssa_count
* sizeof(u32
);
85 ssp_cap_size
-= 16; /* skip copying the default SSA */
87 desc_size
+= ssp_cap_size
;
90 memcpy(buf
, &usb_bos_descriptor
, min(desc_size
, wLength
));
93 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
95 put_unaligned_le16(desc_size
+ ssa_size
, &buf
[2]);
98 if (wLength
< USB_DT_BOS_SIZE
+ USB_DT_USB_SS_CAP_SIZE
)
101 /* Indicate whether the host has LTM support. */
102 temp
= readl(&xhci
->cap_regs
->hcc_params
);
104 buf
[8] |= USB_LTM_SUPPORT
;
106 /* Set the U1 and U2 exit latencies. */
107 if ((xhci
->quirks
& XHCI_LPM_SUPPORT
)) {
108 temp
= readl(&xhci
->cap_regs
->hcs_params3
);
109 buf
[12] = HCS_U1_LATENCY(temp
);
110 put_unaligned_le16(HCS_U2_LATENCY(temp
), &buf
[13]);
113 /* If PSI table exists, add the custom speed attributes from it */
114 if (usb3_1
&& xhci
->usb3_rhub
.psi_count
) {
115 u32 ssp_cap_base
, bm_attrib
, psi
, psi_mant
, psi_exp
;
118 ssp_cap_base
= USB_DT_BOS_SIZE
+ USB_DT_USB_SS_CAP_SIZE
;
120 if (wLength
< desc_size
)
122 buf
[ssp_cap_base
] = ssp_cap_size
+ ssa_size
;
124 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
125 bm_attrib
= (ssa_count
- 1) & 0x1f;
126 bm_attrib
|= (xhci
->usb3_rhub
.psi_uid_count
- 1) << 5;
127 put_unaligned_le32(bm_attrib
, &buf
[ssp_cap_base
+ 4]);
129 if (wLength
< desc_size
+ ssa_size
)
132 * Create the Sublink Speed Attributes (SSA) array.
133 * The xhci PSI field and USB 3.1 SSA fields are very similar,
134 * but link type bits 7:6 differ for values 01b and 10b.
135 * xhci has also only one PSI entry for a symmetric link when
136 * USB 3.1 requires two SSA entries (RX and TX) for every link
139 for (i
= 0; i
< xhci
->usb3_rhub
.psi_count
; i
++) {
140 psi
= xhci
->usb3_rhub
.psi
[i
];
141 psi
&= ~USB_SSP_SUBLINK_SPEED_RSVD
;
142 psi_exp
= XHCI_EXT_PORT_PSIE(psi
);
143 psi_mant
= XHCI_EXT_PORT_PSIM(psi
);
145 /* Shift to Gbps and set SSP Link BIT(14) if 10Gpbs */
146 for (; psi_exp
< 3; psi_exp
++)
151 if ((psi
& PLT_MASK
) == PLT_SYM
) {
152 /* Symmetric, create SSA RX and TX from one PSI entry */
153 put_unaligned_le32(psi
, &buf
[offset
]);
154 psi
|= 1 << 7; /* turn entry to TX */
156 if (offset
>= desc_size
+ ssa_size
)
157 return desc_size
+ ssa_size
;
158 } else if ((psi
& PLT_MASK
) == PLT_ASYM_RX
) {
159 /* Asymetric RX, flip bits 7:6 for SSA */
162 put_unaligned_le32(psi
, &buf
[offset
]);
164 if (offset
>= desc_size
+ ssa_size
)
165 return desc_size
+ ssa_size
;
168 /* ssa_size is 0 for other than usb 3.1 hosts */
169 return desc_size
+ ssa_size
;
172 static void xhci_common_hub_descriptor(struct xhci_hcd
*xhci
,
173 struct usb_hub_descriptor
*desc
, int ports
)
177 desc
->bPwrOn2PwrGood
= 10; /* xhci section 5.4.9 says 20ms max */
178 desc
->bHubContrCurrent
= 0;
180 desc
->bNbrPorts
= ports
;
182 /* Bits 1:0 - support per-port power switching, or power always on */
183 if (HCC_PPC(xhci
->hcc_params
))
184 temp
|= HUB_CHAR_INDV_PORT_LPSM
;
186 temp
|= HUB_CHAR_NO_LPSM
;
187 /* Bit 2 - root hubs are not part of a compound device */
188 /* Bits 4:3 - individual port over current protection */
189 temp
|= HUB_CHAR_INDV_PORT_OCPM
;
190 /* Bits 6:5 - no TTs in root ports */
191 /* Bit 7 - no port indicators */
192 desc
->wHubCharacteristics
= cpu_to_le16(temp
);
195 /* Fill in the USB 2.0 roothub descriptor */
196 static void xhci_usb2_hub_descriptor(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
197 struct usb_hub_descriptor
*desc
)
201 __u8 port_removable
[(USB_MAXCHILDREN
+ 1 + 7) / 8];
205 ports
= xhci
->num_usb2_ports
;
207 xhci_common_hub_descriptor(xhci
, desc
, ports
);
208 desc
->bDescriptorType
= USB_DT_HUB
;
209 temp
= 1 + (ports
/ 8);
210 desc
->bDescLength
= USB_DT_HUB_NONVAR_SIZE
+ 2 * temp
;
212 /* The Device Removable bits are reported on a byte granularity.
213 * If the port doesn't exist within that byte, the bit is set to 0.
215 memset(port_removable
, 0, sizeof(port_removable
));
216 for (i
= 0; i
< ports
; i
++) {
217 portsc
= readl(xhci
->usb2_ports
[i
]);
218 /* If a device is removable, PORTSC reports a 0, same as in the
219 * hub descriptor DeviceRemovable bits.
221 if (portsc
& PORT_DEV_REMOVE
)
222 /* This math is hairy because bit 0 of DeviceRemovable
223 * is reserved, and bit 1 is for port 1, etc.
225 port_removable
[(i
+ 1) / 8] |= 1 << ((i
+ 1) % 8);
228 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
229 * ports on it. The USB 2.0 specification says that there are two
230 * variable length fields at the end of the hub descriptor:
231 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
232 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
233 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
234 * 0xFF, so we initialize the both arrays (DeviceRemovable and
235 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
236 * set of ports that actually exist.
238 memset(desc
->u
.hs
.DeviceRemovable
, 0xff,
239 sizeof(desc
->u
.hs
.DeviceRemovable
));
240 memset(desc
->u
.hs
.PortPwrCtrlMask
, 0xff,
241 sizeof(desc
->u
.hs
.PortPwrCtrlMask
));
243 for (i
= 0; i
< (ports
+ 1 + 7) / 8; i
++)
244 memset(&desc
->u
.hs
.DeviceRemovable
[i
], port_removable
[i
],
248 /* Fill in the USB 3.0 roothub descriptor */
249 static void xhci_usb3_hub_descriptor(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
250 struct usb_hub_descriptor
*desc
)
257 ports
= xhci
->num_usb3_ports
;
258 xhci_common_hub_descriptor(xhci
, desc
, ports
);
259 desc
->bDescriptorType
= USB_DT_SS_HUB
;
260 desc
->bDescLength
= USB_DT_SS_HUB_SIZE
;
262 /* header decode latency should be zero for roothubs,
263 * see section 4.23.5.2.
265 desc
->u
.ss
.bHubHdrDecLat
= 0;
266 desc
->u
.ss
.wHubDelay
= 0;
269 /* bit 0 is reserved, bit 1 is for port 1, etc. */
270 for (i
= 0; i
< ports
; i
++) {
271 portsc
= readl(xhci
->usb3_ports
[i
]);
272 if (portsc
& PORT_DEV_REMOVE
)
273 port_removable
|= 1 << (i
+ 1);
276 desc
->u
.ss
.DeviceRemovable
= cpu_to_le16(port_removable
);
279 static void xhci_hub_descriptor(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
280 struct usb_hub_descriptor
*desc
)
283 if (hcd
->speed
>= HCD_USB3
)
284 xhci_usb3_hub_descriptor(hcd
, xhci
, desc
);
286 xhci_usb2_hub_descriptor(hcd
, xhci
, desc
);
290 static unsigned int xhci_port_speed(unsigned int port_status
)
292 if (DEV_LOWSPEED(port_status
))
293 return USB_PORT_STAT_LOW_SPEED
;
294 if (DEV_HIGHSPEED(port_status
))
295 return USB_PORT_STAT_HIGH_SPEED
;
297 * FIXME: Yes, we should check for full speed, but the core uses that as
298 * a default in portspeed() in usb/core/hub.c (which is the only place
299 * USB_PORT_STAT_*_SPEED is used).
305 * These bits are Read Only (RO) and should be saved and written to the
306 * registers: 0, 3, 10:13, 30
307 * connect status, over-current status, port speed, and device removable.
308 * connect status and port speed are also sticky - meaning they're in
309 * the AUX well and they aren't changed by a hot, warm, or cold reset.
311 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
313 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
314 * bits 5:8, 9, 14:15, 25:27
315 * link state, port power, port indicator state, "wake on" enable state
317 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
319 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
322 #define XHCI_PORT_RW1S ((1<<4))
324 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
325 * bits 1, 17, 18, 19, 20, 21, 22, 23
326 * port enable/disable, and
327 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
328 * over-current, reset, link state, and L1 change
330 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
332 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
335 #define XHCI_PORT_RW ((1<<16))
337 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
340 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
343 * Given a port state, this function returns a value that would result in the
344 * port being in the same state, if the value was written to the port status
346 * Save Read Only (RO) bits and save read/write bits where
347 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
348 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
350 u32
xhci_port_state_to_neutral(u32 state
)
352 /* Save read-only status and port state */
353 return (state
& XHCI_PORT_RO
) | (state
& XHCI_PORT_RWS
);
357 * find slot id based on port number.
358 * @port: The one-based port number from one of the two split roothubs.
360 int xhci_find_slot_id_by_port(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
365 enum usb_device_speed speed
;
368 for (i
= 0; i
< MAX_HC_SLOTS
; i
++) {
371 speed
= xhci
->devs
[i
]->udev
->speed
;
372 if (((speed
>= USB_SPEED_SUPER
) == (hcd
->speed
>= HCD_USB3
))
373 && xhci
->devs
[i
]->fake_port
== port
) {
384 * It issues stop endpoint command for EP 0 to 30. And wait the last command
386 * suspend will set to 1, if suspend bit need to set in command.
388 static int xhci_stop_device(struct xhci_hcd
*xhci
, int slot_id
, int suspend
)
390 struct xhci_virt_device
*virt_dev
;
391 struct xhci_command
*cmd
;
397 virt_dev
= xhci
->devs
[slot_id
];
401 trace_xhci_stop_device(virt_dev
);
403 cmd
= xhci_alloc_command(xhci
, false, true, GFP_NOIO
);
407 spin_lock_irqsave(&xhci
->lock
, flags
);
408 for (i
= LAST_EP_INDEX
; i
> 0; i
--) {
409 if (virt_dev
->eps
[i
].ring
&& virt_dev
->eps
[i
].ring
->dequeue
) {
410 struct xhci_ep_ctx
*ep_ctx
;
411 struct xhci_command
*command
;
413 ep_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->out_ctx
, i
);
415 /* Check ep is running, required by AMD SNPS 3.1 xHC */
416 if (GET_EP_CTX_STATE(ep_ctx
) != EP_STATE_RUNNING
)
419 command
= xhci_alloc_command(xhci
, false, false,
422 spin_unlock_irqrestore(&xhci
->lock
, flags
);
427 ret
= xhci_queue_stop_endpoint(xhci
, command
, slot_id
,
430 spin_unlock_irqrestore(&xhci
->lock
, flags
);
431 xhci_free_command(xhci
, command
);
436 ret
= xhci_queue_stop_endpoint(xhci
, cmd
, slot_id
, 0, suspend
);
438 spin_unlock_irqrestore(&xhci
->lock
, flags
);
442 xhci_ring_cmd_db(xhci
);
443 spin_unlock_irqrestore(&xhci
->lock
, flags
);
445 /* Wait for last stop endpoint command to finish */
446 wait_for_completion(cmd
->completion
);
448 if (cmd
->status
== COMP_COMMAND_ABORTED
||
449 cmd
->status
== COMP_COMMAND_RING_STOPPED
) {
450 xhci_warn(xhci
, "Timeout while waiting for stop endpoint command\n");
455 xhci_free_command(xhci
, cmd
);
460 * Ring device, it rings the all doorbells unconditionally.
462 void xhci_ring_device(struct xhci_hcd
*xhci
, int slot_id
)
465 struct xhci_virt_ep
*ep
;
467 for (i
= 0; i
< LAST_EP_INDEX
+ 1; i
++) {
468 ep
= &xhci
->devs
[slot_id
]->eps
[i
];
470 if (ep
->ep_state
& EP_HAS_STREAMS
) {
471 for (s
= 1; s
< ep
->stream_info
->num_streams
; s
++)
472 xhci_ring_ep_doorbell(xhci
, slot_id
, i
, s
);
473 } else if (ep
->ring
&& ep
->ring
->dequeue
) {
474 xhci_ring_ep_doorbell(xhci
, slot_id
, i
, 0);
481 static void xhci_disable_port(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
482 u16 wIndex
, __le32 __iomem
*addr
, u32 port_status
)
484 /* Don't allow the USB core to disable SuperSpeed ports. */
485 if (hcd
->speed
>= HCD_USB3
) {
486 xhci_dbg(xhci
, "Ignoring request to disable "
487 "SuperSpeed port.\n");
491 if (xhci
->quirks
& XHCI_BROKEN_PORT_PED
) {
493 "Broken Port Enabled/Disabled, ignoring port disable request.\n");
497 /* Write 1 to disable the port */
498 writel(port_status
| PORT_PE
, addr
);
499 port_status
= readl(addr
);
500 xhci_dbg(xhci
, "disable port, actual port %d status = 0x%x\n",
501 wIndex
, port_status
);
504 static void xhci_clear_port_change_bit(struct xhci_hcd
*xhci
, u16 wValue
,
505 u16 wIndex
, __le32 __iomem
*addr
, u32 port_status
)
507 char *port_change_bit
;
511 case USB_PORT_FEAT_C_RESET
:
513 port_change_bit
= "reset";
515 case USB_PORT_FEAT_C_BH_PORT_RESET
:
517 port_change_bit
= "warm(BH) reset";
519 case USB_PORT_FEAT_C_CONNECTION
:
521 port_change_bit
= "connect";
523 case USB_PORT_FEAT_C_OVER_CURRENT
:
525 port_change_bit
= "over-current";
527 case USB_PORT_FEAT_C_ENABLE
:
529 port_change_bit
= "enable/disable";
531 case USB_PORT_FEAT_C_SUSPEND
:
533 port_change_bit
= "suspend/resume";
535 case USB_PORT_FEAT_C_PORT_LINK_STATE
:
537 port_change_bit
= "link state";
539 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR
:
541 port_change_bit
= "config error";
544 /* Should never happen */
547 /* Change bits are all write 1 to clear */
548 writel(port_status
| status
, addr
);
549 port_status
= readl(addr
);
550 xhci_dbg(xhci
, "clear port %s change, actual port %d status = 0x%x\n",
551 port_change_bit
, wIndex
, port_status
);
554 static int xhci_get_ports(struct usb_hcd
*hcd
, __le32 __iomem
***port_array
)
557 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
559 if (hcd
->speed
>= HCD_USB3
) {
560 max_ports
= xhci
->num_usb3_ports
;
561 *port_array
= xhci
->usb3_ports
;
563 max_ports
= xhci
->num_usb2_ports
;
564 *port_array
= xhci
->usb2_ports
;
570 static __le32 __iomem
*xhci_get_port_io_addr(struct usb_hcd
*hcd
, int index
)
572 __le32 __iomem
**port_array
;
574 xhci_get_ports(hcd
, &port_array
);
575 return port_array
[index
];
579 * xhci_set_port_power() must be called with xhci->lock held.
580 * It will release and re-aquire the lock while calling ACPI
583 static void xhci_set_port_power(struct xhci_hcd
*xhci
, struct usb_hcd
*hcd
,
584 u16 index
, bool on
, unsigned long *flags
)
586 __le32 __iomem
*addr
;
589 addr
= xhci_get_port_io_addr(hcd
, index
);
591 temp
= xhci_port_state_to_neutral(temp
);
594 writel(temp
| PORT_POWER
, addr
);
596 xhci_dbg(xhci
, "set port power, actual port %d status = 0x%x\n",
600 writel(temp
& ~PORT_POWER
, addr
);
603 spin_unlock_irqrestore(&xhci
->lock
, *flags
);
604 temp
= usb_acpi_power_manageable(hcd
->self
.root_hub
,
607 usb_acpi_set_power_state(hcd
->self
.root_hub
,
609 spin_lock_irqsave(&xhci
->lock
, *flags
);
612 static void xhci_port_set_test_mode(struct xhci_hcd
*xhci
,
613 u16 test_mode
, u16 wIndex
)
616 __le32 __iomem
*addr
;
618 /* xhci only supports test mode for usb2 ports, i.e. xhci->main_hcd */
619 addr
= xhci_get_port_io_addr(xhci
->main_hcd
, wIndex
);
620 temp
= readl(addr
+ PORTPMSC
);
621 temp
|= test_mode
<< PORT_TEST_MODE_SHIFT
;
622 writel(temp
, addr
+ PORTPMSC
);
623 xhci
->test_mode
= test_mode
;
624 if (test_mode
== TEST_FORCE_EN
)
628 static int xhci_enter_test_mode(struct xhci_hcd
*xhci
,
629 u16 test_mode
, u16 wIndex
, unsigned long *flags
)
633 /* Disable all Device Slots */
634 xhci_dbg(xhci
, "Disable all slots\n");
635 spin_unlock_irqrestore(&xhci
->lock
, *flags
);
636 for (i
= 1; i
<= HCS_MAX_SLOTS(xhci
->hcs_params1
); i
++) {
637 retval
= xhci_disable_slot(xhci
, NULL
, i
);
639 xhci_err(xhci
, "Failed to disable slot %d, %d. Enter test mode anyway\n",
642 spin_lock_irqsave(&xhci
->lock
, *flags
);
643 /* Put all ports to the Disable state by clear PP */
644 xhci_dbg(xhci
, "Disable all port (PP = 0)\n");
645 /* Power off USB3 ports*/
646 for (i
= 0; i
< xhci
->num_usb3_ports
; i
++)
647 xhci_set_port_power(xhci
, xhci
->shared_hcd
, i
, false, flags
);
648 /* Power off USB2 ports*/
649 for (i
= 0; i
< xhci
->num_usb2_ports
; i
++)
650 xhci_set_port_power(xhci
, xhci
->main_hcd
, i
, false, flags
);
651 /* Stop the controller */
652 xhci_dbg(xhci
, "Stop controller\n");
653 retval
= xhci_halt(xhci
);
656 /* Disable runtime PM for test mode */
657 pm_runtime_forbid(xhci_to_hcd(xhci
)->self
.controller
);
658 /* Set PORTPMSC.PTC field to enter selected test mode */
659 /* Port is selected by wIndex. port_id = wIndex + 1 */
660 xhci_dbg(xhci
, "Enter Test Mode: %d, Port_id=%d\n",
661 test_mode
, wIndex
+ 1);
662 xhci_port_set_test_mode(xhci
, test_mode
, wIndex
);
666 static int xhci_exit_test_mode(struct xhci_hcd
*xhci
)
670 if (!xhci
->test_mode
) {
671 xhci_err(xhci
, "Not in test mode, do nothing.\n");
674 if (xhci
->test_mode
== TEST_FORCE_EN
&&
675 !(xhci
->xhc_state
& XHCI_STATE_HALTED
)) {
676 retval
= xhci_halt(xhci
);
680 pm_runtime_allow(xhci_to_hcd(xhci
)->self
.controller
);
682 return xhci_reset(xhci
);
685 void xhci_set_link_state(struct xhci_hcd
*xhci
, __le32 __iomem
**port_array
,
686 int port_id
, u32 link_state
)
690 temp
= readl(port_array
[port_id
]);
691 temp
= xhci_port_state_to_neutral(temp
);
692 temp
&= ~PORT_PLS_MASK
;
693 temp
|= PORT_LINK_STROBE
| link_state
;
694 writel(temp
, port_array
[port_id
]);
697 static void xhci_set_remote_wake_mask(struct xhci_hcd
*xhci
,
698 __le32 __iomem
**port_array
, int port_id
, u16 wake_mask
)
702 temp
= readl(port_array
[port_id
]);
703 temp
= xhci_port_state_to_neutral(temp
);
705 if (wake_mask
& USB_PORT_FEAT_REMOTE_WAKE_CONNECT
)
706 temp
|= PORT_WKCONN_E
;
708 temp
&= ~PORT_WKCONN_E
;
710 if (wake_mask
& USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT
)
711 temp
|= PORT_WKDISC_E
;
713 temp
&= ~PORT_WKDISC_E
;
715 if (wake_mask
& USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT
)
718 temp
&= ~PORT_WKOC_E
;
720 writel(temp
, port_array
[port_id
]);
723 /* Test and clear port RWC bit */
724 void xhci_test_and_clear_bit(struct xhci_hcd
*xhci
, __le32 __iomem
**port_array
,
725 int port_id
, u32 port_bit
)
729 temp
= readl(port_array
[port_id
]);
730 if (temp
& port_bit
) {
731 temp
= xhci_port_state_to_neutral(temp
);
733 writel(temp
, port_array
[port_id
]);
737 /* Updates Link Status for USB 2.1 port */
738 static void xhci_hub_report_usb2_link_state(u32
*status
, u32 status_reg
)
740 if ((status_reg
& PORT_PLS_MASK
) == XDEV_U2
)
741 *status
|= USB_PORT_STAT_L1
;
744 /* Updates Link Status for super Speed port */
745 static void xhci_hub_report_usb3_link_state(struct xhci_hcd
*xhci
,
746 u32
*status
, u32 status_reg
)
748 u32 pls
= status_reg
& PORT_PLS_MASK
;
750 /* resume state is a xHCI internal state.
751 * Do not report it to usb core, instead, pretend to be U3,
752 * thus usb core knows it's not ready for transfer
754 if (pls
== XDEV_RESUME
) {
755 *status
|= USB_SS_PORT_LS_U3
;
759 /* When the CAS bit is set then warm reset
760 * should be performed on port
762 if (status_reg
& PORT_CAS
) {
763 /* The CAS bit can be set while the port is
765 * Only roothubs have CAS bit, so we
766 * pretend to be in compliance mode
767 * unless we're already in compliance
768 * or the inactive state.
770 if (pls
!= USB_SS_PORT_LS_COMP_MOD
&&
771 pls
!= USB_SS_PORT_LS_SS_INACTIVE
) {
772 pls
= USB_SS_PORT_LS_COMP_MOD
;
774 /* Return also connection bit -
775 * hub state machine resets port
776 * when this bit is set.
778 pls
|= USB_PORT_STAT_CONNECTION
;
781 * If CAS bit isn't set but the Port is already at
782 * Compliance Mode, fake a connection so the USB core
783 * notices the Compliance state and resets the port.
784 * This resolves an issue generated by the SN65LVPE502CP
785 * in which sometimes the port enters compliance mode
786 * caused by a delay on the host-device negotiation.
788 if ((xhci
->quirks
& XHCI_COMP_MODE_QUIRK
) &&
789 (pls
== USB_SS_PORT_LS_COMP_MOD
))
790 pls
|= USB_PORT_STAT_CONNECTION
;
793 /* update status field */
798 * Function for Compliance Mode Quirk.
800 * This Function verifies if all xhc USB3 ports have entered U0, if so,
801 * the compliance mode timer is deleted. A port won't enter
802 * compliance mode if it has previously entered U0.
804 static void xhci_del_comp_mod_timer(struct xhci_hcd
*xhci
, u32 status
,
807 u32 all_ports_seen_u0
= ((1 << xhci
->num_usb3_ports
)-1);
808 bool port_in_u0
= ((status
& PORT_PLS_MASK
) == XDEV_U0
);
810 if (!(xhci
->quirks
& XHCI_COMP_MODE_QUIRK
))
813 if ((xhci
->port_status_u0
!= all_ports_seen_u0
) && port_in_u0
) {
814 xhci
->port_status_u0
|= 1 << wIndex
;
815 if (xhci
->port_status_u0
== all_ports_seen_u0
) {
816 del_timer_sync(&xhci
->comp_mode_recovery_timer
);
817 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
818 "All USB3 ports have entered U0 already!");
819 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
820 "Compliance Mode Recovery Timer Deleted.");
825 static u32
xhci_get_ext_port_status(u32 raw_port_status
, u32 port_li
)
830 /* only support rx and tx lane counts of 1 in usb3.1 spec */
831 speed_id
= DEV_PORT_SPEED(raw_port_status
);
832 ext_stat
|= speed_id
; /* bits 3:0, RX speed id */
833 ext_stat
|= speed_id
<< 4; /* bits 7:4, TX speed id */
835 ext_stat
|= PORT_RX_LANES(port_li
) << 8; /* bits 11:8 Rx lane count */
836 ext_stat
|= PORT_TX_LANES(port_li
) << 12; /* bits 15:12 Tx lane count */
842 * Converts a raw xHCI port status into the format that external USB 2.0 or USB
845 * Possible side effects:
846 * - Mark a port as being done with device resume,
847 * and ring the endpoint doorbells.
848 * - Stop the Synopsys redriver Compliance Mode polling.
849 * - Drop and reacquire the xHCI lock, in order to wait for port resume.
851 static u32
xhci_get_port_status(struct usb_hcd
*hcd
,
852 struct xhci_bus_state
*bus_state
,
853 __le32 __iomem
**port_array
,
854 u16 wIndex
, u32 raw_port_status
,
856 __releases(&xhci
->lock
)
857 __acquires(&xhci
->lock
)
859 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
863 /* wPortChange bits */
864 if (raw_port_status
& PORT_CSC
)
865 status
|= USB_PORT_STAT_C_CONNECTION
<< 16;
866 if (raw_port_status
& PORT_PEC
)
867 status
|= USB_PORT_STAT_C_ENABLE
<< 16;
868 if ((raw_port_status
& PORT_OCC
))
869 status
|= USB_PORT_STAT_C_OVERCURRENT
<< 16;
870 if ((raw_port_status
& PORT_RC
))
871 status
|= USB_PORT_STAT_C_RESET
<< 16;
873 if (hcd
->speed
>= HCD_USB3
) {
874 /* Port link change with port in resume state should not be
875 * reported to usbcore, as this is an internal state to be
876 * handled by xhci driver. Reporting PLC to usbcore may
877 * cause usbcore clearing PLC first and port change event
878 * irq won't be generated.
880 if ((raw_port_status
& PORT_PLC
) &&
881 (raw_port_status
& PORT_PLS_MASK
) != XDEV_RESUME
)
882 status
|= USB_PORT_STAT_C_LINK_STATE
<< 16;
883 if ((raw_port_status
& PORT_WRC
))
884 status
|= USB_PORT_STAT_C_BH_RESET
<< 16;
885 if ((raw_port_status
& PORT_CEC
))
886 status
|= USB_PORT_STAT_C_CONFIG_ERROR
<< 16;
889 if (hcd
->speed
< HCD_USB3
) {
890 if ((raw_port_status
& PORT_PLS_MASK
) == XDEV_U3
891 && (raw_port_status
& PORT_POWER
))
892 status
|= USB_PORT_STAT_SUSPEND
;
894 if ((raw_port_status
& PORT_PLS_MASK
) == XDEV_RESUME
&&
895 !DEV_SUPERSPEED_ANY(raw_port_status
)) {
896 if ((raw_port_status
& PORT_RESET
) ||
897 !(raw_port_status
& PORT_PE
))
899 /* did port event handler already start resume timing? */
900 if (!bus_state
->resume_done
[wIndex
]) {
901 /* If not, maybe we are in a host initated resume? */
902 if (test_bit(wIndex
, &bus_state
->resuming_ports
)) {
903 /* Host initated resume doesn't time the resume
904 * signalling using resume_done[].
905 * It manually sets RESUME state, sleeps 20ms
906 * and sets U0 state. This should probably be
907 * changed, but not right now.
910 /* port resume was discovered now and here,
911 * start resume timing
913 unsigned long timeout
= jiffies
+
914 msecs_to_jiffies(USB_RESUME_TIMEOUT
);
916 set_bit(wIndex
, &bus_state
->resuming_ports
);
917 bus_state
->resume_done
[wIndex
] = timeout
;
918 mod_timer(&hcd
->rh_timer
, timeout
);
920 /* Has resume been signalled for USB_RESUME_TIME yet? */
921 } else if (time_after_eq(jiffies
,
922 bus_state
->resume_done
[wIndex
])) {
925 xhci_dbg(xhci
, "Resume USB2 port %d\n",
927 bus_state
->resume_done
[wIndex
] = 0;
928 clear_bit(wIndex
, &bus_state
->resuming_ports
);
930 set_bit(wIndex
, &bus_state
->rexit_ports
);
932 xhci_test_and_clear_bit(xhci
, port_array
, wIndex
,
934 xhci_set_link_state(xhci
, port_array
, wIndex
,
937 spin_unlock_irqrestore(&xhci
->lock
, flags
);
938 time_left
= wait_for_completion_timeout(
939 &bus_state
->rexit_done
[wIndex
],
941 XHCI_MAX_REXIT_TIMEOUT
));
942 spin_lock_irqsave(&xhci
->lock
, flags
);
945 slot_id
= xhci_find_slot_id_by_port(hcd
,
948 xhci_dbg(xhci
, "slot_id is zero\n");
951 xhci_ring_device(xhci
, slot_id
);
953 int port_status
= readl(port_array
[wIndex
]);
954 xhci_warn(xhci
, "Port resume took longer than %i msec, port status = 0x%x\n",
955 XHCI_MAX_REXIT_TIMEOUT
,
957 status
|= USB_PORT_STAT_SUSPEND
;
958 clear_bit(wIndex
, &bus_state
->rexit_ports
);
961 bus_state
->port_c_suspend
|= 1 << wIndex
;
962 bus_state
->suspended_ports
&= ~(1 << wIndex
);
965 * The resume has been signaling for less than
966 * USB_RESUME_TIME. Report the port status as SUSPEND,
967 * let the usbcore check port status again and clear
968 * resume signaling later.
970 status
|= USB_PORT_STAT_SUSPEND
;
974 * Clear stale usb2 resume signalling variables in case port changed
975 * state during resume signalling. For example on error
977 if ((bus_state
->resume_done
[wIndex
] ||
978 test_bit(wIndex
, &bus_state
->resuming_ports
)) &&
979 (raw_port_status
& PORT_PLS_MASK
) != XDEV_U3
&&
980 (raw_port_status
& PORT_PLS_MASK
) != XDEV_RESUME
) {
981 bus_state
->resume_done
[wIndex
] = 0;
982 clear_bit(wIndex
, &bus_state
->resuming_ports
);
986 if ((raw_port_status
& PORT_PLS_MASK
) == XDEV_U0
&&
987 (raw_port_status
& PORT_POWER
)) {
988 if (bus_state
->suspended_ports
& (1 << wIndex
)) {
989 bus_state
->suspended_ports
&= ~(1 << wIndex
);
990 if (hcd
->speed
< HCD_USB3
)
991 bus_state
->port_c_suspend
|= 1 << wIndex
;
993 bus_state
->resume_done
[wIndex
] = 0;
994 clear_bit(wIndex
, &bus_state
->resuming_ports
);
996 if (raw_port_status
& PORT_CONNECT
) {
997 status
|= USB_PORT_STAT_CONNECTION
;
998 status
|= xhci_port_speed(raw_port_status
);
1000 if (raw_port_status
& PORT_PE
)
1001 status
|= USB_PORT_STAT_ENABLE
;
1002 if (raw_port_status
& PORT_OC
)
1003 status
|= USB_PORT_STAT_OVERCURRENT
;
1004 if (raw_port_status
& PORT_RESET
)
1005 status
|= USB_PORT_STAT_RESET
;
1006 if (raw_port_status
& PORT_POWER
) {
1007 if (hcd
->speed
>= HCD_USB3
)
1008 status
|= USB_SS_PORT_STAT_POWER
;
1010 status
|= USB_PORT_STAT_POWER
;
1012 /* Update Port Link State */
1013 if (hcd
->speed
>= HCD_USB3
) {
1014 xhci_hub_report_usb3_link_state(xhci
, &status
, raw_port_status
);
1016 * Verify if all USB3 Ports Have entered U0 already.
1017 * Delete Compliance Mode Timer if so.
1019 xhci_del_comp_mod_timer(xhci
, raw_port_status
, wIndex
);
1021 xhci_hub_report_usb2_link_state(&status
, raw_port_status
);
1023 if (bus_state
->port_c_suspend
& (1 << wIndex
))
1024 status
|= USB_PORT_STAT_C_SUSPEND
<< 16;
1029 int xhci_hub_control(struct usb_hcd
*hcd
, u16 typeReq
, u16 wValue
,
1030 u16 wIndex
, char *buf
, u16 wLength
)
1032 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
1034 unsigned long flags
;
1037 __le32 __iomem
**port_array
;
1039 struct xhci_bus_state
*bus_state
;
1045 max_ports
= xhci_get_ports(hcd
, &port_array
);
1046 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
1048 spin_lock_irqsave(&xhci
->lock
, flags
);
1051 /* No power source, over-current reported per port */
1054 case GetHubDescriptor
:
1055 /* Check to make sure userspace is asking for the USB 3.0 hub
1056 * descriptor for the USB 3.0 roothub. If not, we stall the
1057 * endpoint, like external hubs do.
1059 if (hcd
->speed
>= HCD_USB3
&&
1060 (wLength
< USB_DT_SS_HUB_SIZE
||
1061 wValue
!= (USB_DT_SS_HUB
<< 8))) {
1062 xhci_dbg(xhci
, "Wrong hub descriptor type for "
1063 "USB 3.0 roothub.\n");
1066 xhci_hub_descriptor(hcd
, xhci
,
1067 (struct usb_hub_descriptor
*) buf
);
1069 case DeviceRequest
| USB_REQ_GET_DESCRIPTOR
:
1070 if ((wValue
& 0xff00) != (USB_DT_BOS
<< 8))
1073 if (hcd
->speed
< HCD_USB3
)
1076 retval
= xhci_create_usb3_bos_desc(xhci
, buf
, wLength
);
1077 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1080 if (!wIndex
|| wIndex
> max_ports
)
1083 temp
= readl(port_array
[wIndex
]);
1084 if (temp
== ~(u32
)0) {
1089 status
= xhci_get_port_status(hcd
, bus_state
, port_array
,
1090 wIndex
, temp
, flags
);
1091 if (status
== 0xffffffff)
1094 xhci_dbg(xhci
, "get port status, actual port %d status = 0x%x\n",
1096 xhci_dbg(xhci
, "Get port status returned 0x%x\n", status
);
1098 put_unaligned(cpu_to_le32(status
), (__le32
*) buf
);
1099 /* if USB 3.1 extended port status return additional 4 bytes */
1100 if (wValue
== 0x02) {
1103 if (hcd
->speed
< HCD_USB31
|| wLength
!= 8) {
1104 xhci_err(xhci
, "get ext port status invalid parameter\n");
1108 port_li
= readl(port_array
[wIndex
] + PORTLI
);
1109 status
= xhci_get_ext_port_status(temp
, port_li
);
1110 put_unaligned_le32(cpu_to_le32(status
), &buf
[4]);
1113 case SetPortFeature
:
1114 if (wValue
== USB_PORT_FEAT_LINK_STATE
)
1115 link_state
= (wIndex
& 0xff00) >> 3;
1116 if (wValue
== USB_PORT_FEAT_REMOTE_WAKE_MASK
)
1117 wake_mask
= wIndex
& 0xff00;
1118 if (wValue
== USB_PORT_FEAT_TEST
)
1119 test_mode
= (wIndex
& 0xff00) >> 8;
1120 /* The MSB of wIndex is the U1/U2 timeout */
1121 timeout
= (wIndex
& 0xff00) >> 8;
1123 if (!wIndex
|| wIndex
> max_ports
)
1126 temp
= readl(port_array
[wIndex
]);
1127 if (temp
== ~(u32
)0) {
1132 temp
= xhci_port_state_to_neutral(temp
);
1133 /* FIXME: What new port features do we need to support? */
1135 case USB_PORT_FEAT_SUSPEND
:
1136 temp
= readl(port_array
[wIndex
]);
1137 if ((temp
& PORT_PLS_MASK
) != XDEV_U0
) {
1138 /* Resume the port to U0 first */
1139 xhci_set_link_state(xhci
, port_array
, wIndex
,
1141 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1143 spin_lock_irqsave(&xhci
->lock
, flags
);
1145 /* In spec software should not attempt to suspend
1146 * a port unless the port reports that it is in the
1147 * enabled (PED = ‘1’,PLS < ‘3’) state.
1149 temp
= readl(port_array
[wIndex
]);
1150 if ((temp
& PORT_PE
) == 0 || (temp
& PORT_RESET
)
1151 || (temp
& PORT_PLS_MASK
) >= XDEV_U3
) {
1152 xhci_warn(xhci
, "USB core suspending device not in U0/U1/U2.\n");
1156 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1159 xhci_warn(xhci
, "slot_id is zero\n");
1162 /* unlock to execute stop endpoint commands */
1163 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1164 xhci_stop_device(xhci
, slot_id
, 1);
1165 spin_lock_irqsave(&xhci
->lock
, flags
);
1167 xhci_set_link_state(xhci
, port_array
, wIndex
, XDEV_U3
);
1169 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1170 msleep(10); /* wait device to enter */
1171 spin_lock_irqsave(&xhci
->lock
, flags
);
1173 temp
= readl(port_array
[wIndex
]);
1174 bus_state
->suspended_ports
|= 1 << wIndex
;
1176 case USB_PORT_FEAT_LINK_STATE
:
1177 temp
= readl(port_array
[wIndex
]);
1180 if (link_state
== USB_SS_PORT_LS_SS_DISABLED
) {
1181 xhci_dbg(xhci
, "Disable port %d\n", wIndex
);
1182 temp
= xhci_port_state_to_neutral(temp
);
1184 * Clear all change bits, so that we get a new
1187 temp
|= PORT_CSC
| PORT_PEC
| PORT_WRC
|
1188 PORT_OCC
| PORT_RC
| PORT_PLC
|
1190 writel(temp
| PORT_PE
, port_array
[wIndex
]);
1191 temp
= readl(port_array
[wIndex
]);
1195 /* Put link in RxDetect (enable port) */
1196 if (link_state
== USB_SS_PORT_LS_RX_DETECT
) {
1197 xhci_dbg(xhci
, "Enable port %d\n", wIndex
);
1198 xhci_set_link_state(xhci
, port_array
, wIndex
,
1200 temp
= readl(port_array
[wIndex
]);
1204 /* Software should not attempt to set
1205 * port link state above '3' (U3) and the port
1208 if ((temp
& PORT_PE
) == 0 ||
1209 (link_state
> USB_SS_PORT_LS_U3
)) {
1210 xhci_warn(xhci
, "Cannot set link state.\n");
1214 if (link_state
== USB_SS_PORT_LS_U3
) {
1215 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1218 /* unlock to execute stop endpoint
1220 spin_unlock_irqrestore(&xhci
->lock
,
1222 xhci_stop_device(xhci
, slot_id
, 1);
1223 spin_lock_irqsave(&xhci
->lock
, flags
);
1227 xhci_set_link_state(xhci
, port_array
, wIndex
,
1230 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1231 msleep(20); /* wait device to enter */
1232 spin_lock_irqsave(&xhci
->lock
, flags
);
1234 temp
= readl(port_array
[wIndex
]);
1235 if (link_state
== USB_SS_PORT_LS_U3
)
1236 bus_state
->suspended_ports
|= 1 << wIndex
;
1238 case USB_PORT_FEAT_POWER
:
1240 * Turn on ports, even if there isn't per-port switching.
1241 * HC will report connect events even before this is set.
1242 * However, hub_wq will ignore the roothub events until
1243 * the roothub is registered.
1245 xhci_set_port_power(xhci
, hcd
, wIndex
, true, &flags
);
1247 case USB_PORT_FEAT_RESET
:
1248 temp
= (temp
| PORT_RESET
);
1249 writel(temp
, port_array
[wIndex
]);
1251 temp
= readl(port_array
[wIndex
]);
1252 xhci_dbg(xhci
, "set port reset, actual port %d status = 0x%x\n", wIndex
, temp
);
1254 case USB_PORT_FEAT_REMOTE_WAKE_MASK
:
1255 xhci_set_remote_wake_mask(xhci
, port_array
,
1257 temp
= readl(port_array
[wIndex
]);
1258 xhci_dbg(xhci
, "set port remote wake mask, "
1259 "actual port %d status = 0x%x\n",
1262 case USB_PORT_FEAT_BH_PORT_RESET
:
1264 writel(temp
, port_array
[wIndex
]);
1266 temp
= readl(port_array
[wIndex
]);
1268 case USB_PORT_FEAT_U1_TIMEOUT
:
1269 if (hcd
->speed
< HCD_USB3
)
1271 temp
= readl(port_array
[wIndex
] + PORTPMSC
);
1272 temp
&= ~PORT_U1_TIMEOUT_MASK
;
1273 temp
|= PORT_U1_TIMEOUT(timeout
);
1274 writel(temp
, port_array
[wIndex
] + PORTPMSC
);
1276 case USB_PORT_FEAT_U2_TIMEOUT
:
1277 if (hcd
->speed
< HCD_USB3
)
1279 temp
= readl(port_array
[wIndex
] + PORTPMSC
);
1280 temp
&= ~PORT_U2_TIMEOUT_MASK
;
1281 temp
|= PORT_U2_TIMEOUT(timeout
);
1282 writel(temp
, port_array
[wIndex
] + PORTPMSC
);
1284 case USB_PORT_FEAT_TEST
:
1285 /* 4.19.6 Port Test Modes (USB2 Test Mode) */
1286 if (hcd
->speed
!= HCD_USB2
)
1288 if (test_mode
> TEST_FORCE_EN
|| test_mode
< TEST_J
)
1290 retval
= xhci_enter_test_mode(xhci
, test_mode
, wIndex
,
1296 /* unblock any posted writes */
1297 temp
= readl(port_array
[wIndex
]);
1299 case ClearPortFeature
:
1300 if (!wIndex
|| wIndex
> max_ports
)
1303 temp
= readl(port_array
[wIndex
]);
1304 if (temp
== ~(u32
)0) {
1309 /* FIXME: What new port features do we need to support? */
1310 temp
= xhci_port_state_to_neutral(temp
);
1312 case USB_PORT_FEAT_SUSPEND
:
1313 temp
= readl(port_array
[wIndex
]);
1314 xhci_dbg(xhci
, "clear USB_PORT_FEAT_SUSPEND\n");
1315 xhci_dbg(xhci
, "PORTSC %04x\n", temp
);
1316 if (temp
& PORT_RESET
)
1318 if ((temp
& PORT_PLS_MASK
) == XDEV_U3
) {
1319 if ((temp
& PORT_PE
) == 0)
1322 set_bit(wIndex
, &bus_state
->resuming_ports
);
1323 xhci_set_link_state(xhci
, port_array
, wIndex
,
1325 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1326 msleep(USB_RESUME_TIMEOUT
);
1327 spin_lock_irqsave(&xhci
->lock
, flags
);
1328 xhci_set_link_state(xhci
, port_array
, wIndex
,
1330 clear_bit(wIndex
, &bus_state
->resuming_ports
);
1332 bus_state
->port_c_suspend
|= 1 << wIndex
;
1334 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1337 xhci_dbg(xhci
, "slot_id is zero\n");
1340 xhci_ring_device(xhci
, slot_id
);
1342 case USB_PORT_FEAT_C_SUSPEND
:
1343 bus_state
->port_c_suspend
&= ~(1 << wIndex
);
1344 case USB_PORT_FEAT_C_RESET
:
1345 case USB_PORT_FEAT_C_BH_PORT_RESET
:
1346 case USB_PORT_FEAT_C_CONNECTION
:
1347 case USB_PORT_FEAT_C_OVER_CURRENT
:
1348 case USB_PORT_FEAT_C_ENABLE
:
1349 case USB_PORT_FEAT_C_PORT_LINK_STATE
:
1350 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR
:
1351 xhci_clear_port_change_bit(xhci
, wValue
, wIndex
,
1352 port_array
[wIndex
], temp
);
1354 case USB_PORT_FEAT_ENABLE
:
1355 xhci_disable_port(hcd
, xhci
, wIndex
,
1356 port_array
[wIndex
], temp
);
1358 case USB_PORT_FEAT_POWER
:
1359 xhci_set_port_power(xhci
, hcd
, wIndex
, false, &flags
);
1361 case USB_PORT_FEAT_TEST
:
1362 retval
= xhci_exit_test_mode(xhci
);
1370 /* "stall" on error */
1373 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1378 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1379 * Ports are 0-indexed from the HCD point of view,
1380 * and 1-indexed from the USB core pointer of view.
1382 * Note that the status change bits will be cleared as soon as a port status
1383 * change event is generated, so we use the saved status from that event.
1385 int xhci_hub_status_data(struct usb_hcd
*hcd
, char *buf
)
1387 unsigned long flags
;
1391 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
1393 __le32 __iomem
**port_array
;
1394 struct xhci_bus_state
*bus_state
;
1395 bool reset_change
= false;
1397 max_ports
= xhci_get_ports(hcd
, &port_array
);
1398 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
1400 /* Initial status is no changes */
1401 retval
= (max_ports
+ 8) / 8;
1402 memset(buf
, 0, retval
);
1405 * Inform the usbcore about resume-in-progress by returning
1406 * a non-zero value even if there are no status changes.
1408 status
= bus_state
->resuming_ports
;
1410 mask
= PORT_CSC
| PORT_PEC
| PORT_OCC
| PORT_PLC
| PORT_WRC
| PORT_CEC
;
1412 spin_lock_irqsave(&xhci
->lock
, flags
);
1413 /* For each port, did anything change? If so, set that bit in buf. */
1414 for (i
= 0; i
< max_ports
; i
++) {
1415 temp
= readl(port_array
[i
]);
1416 if (temp
== ~(u32
)0) {
1421 if ((temp
& mask
) != 0 ||
1422 (bus_state
->port_c_suspend
& 1 << i
) ||
1423 (bus_state
->resume_done
[i
] && time_after_eq(
1424 jiffies
, bus_state
->resume_done
[i
]))) {
1425 buf
[(i
+ 1) / 8] |= 1 << (i
+ 1) % 8;
1428 if ((temp
& PORT_RC
))
1429 reset_change
= true;
1431 if (!status
&& !reset_change
) {
1432 xhci_dbg(xhci
, "%s: stopping port polling.\n", __func__
);
1433 clear_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
1435 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1436 return status
? retval
: 0;
1441 int xhci_bus_suspend(struct usb_hcd
*hcd
)
1443 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
1444 int max_ports
, port_index
;
1445 __le32 __iomem
**port_array
;
1446 struct xhci_bus_state
*bus_state
;
1447 unsigned long flags
;
1449 max_ports
= xhci_get_ports(hcd
, &port_array
);
1450 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
1452 spin_lock_irqsave(&xhci
->lock
, flags
);
1454 if (hcd
->self
.root_hub
->do_remote_wakeup
) {
1455 if (bus_state
->resuming_ports
|| /* USB2 */
1456 bus_state
->port_remote_wakeup
) { /* USB3 */
1457 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1458 xhci_dbg(xhci
, "suspend failed because a port is resuming\n");
1463 port_index
= max_ports
;
1464 bus_state
->bus_suspended
= 0;
1465 while (port_index
--) {
1466 /* suspend the port if the port is not suspended */
1470 t1
= readl(port_array
[port_index
]);
1471 t2
= xhci_port_state_to_neutral(t1
);
1473 if ((t1
& PORT_PE
) && !(t1
& PORT_PLS_MASK
)) {
1474 xhci_dbg(xhci
, "port %d not suspended\n", port_index
);
1475 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1478 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1479 xhci_stop_device(xhci
, slot_id
, 1);
1480 spin_lock_irqsave(&xhci
->lock
, flags
);
1482 t2
&= ~PORT_PLS_MASK
;
1483 t2
|= PORT_LINK_STROBE
| XDEV_U3
;
1484 set_bit(port_index
, &bus_state
->bus_suspended
);
1486 /* USB core sets remote wake mask for USB 3.0 hubs,
1487 * including the USB 3.0 roothub, but only if CONFIG_PM
1488 * is enabled, so also enable remote wake here.
1490 if (hcd
->self
.root_hub
->do_remote_wakeup
) {
1491 if (t1
& PORT_CONNECT
) {
1492 t2
|= PORT_WKOC_E
| PORT_WKDISC_E
;
1493 t2
&= ~PORT_WKCONN_E
;
1495 t2
|= PORT_WKOC_E
| PORT_WKCONN_E
;
1496 t2
&= ~PORT_WKDISC_E
;
1499 t2
&= ~PORT_WAKE_BITS
;
1501 t1
= xhci_port_state_to_neutral(t1
);
1503 writel(t2
, port_array
[port_index
]);
1505 hcd
->state
= HC_STATE_SUSPENDED
;
1506 bus_state
->next_statechange
= jiffies
+ msecs_to_jiffies(10);
1507 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1512 * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1513 * warm reset a USB3 device stuck in polling or compliance mode after resume.
1514 * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1516 static bool xhci_port_missing_cas_quirk(int port_index
,
1517 __le32 __iomem
**port_array
)
1521 portsc
= readl(port_array
[port_index
]);
1523 /* if any of these are set we are not stuck */
1524 if (portsc
& (PORT_CONNECT
| PORT_CAS
))
1527 if (((portsc
& PORT_PLS_MASK
) != XDEV_POLLING
) &&
1528 ((portsc
& PORT_PLS_MASK
) != XDEV_COMP_MODE
))
1531 /* clear wakeup/change bits, and do a warm port reset */
1532 portsc
&= ~(PORT_RWC_BITS
| PORT_CEC
| PORT_WAKE_BITS
);
1534 writel(portsc
, port_array
[port_index
]);
1536 readl(port_array
[port_index
]);
1540 int xhci_bus_resume(struct usb_hcd
*hcd
)
1542 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
1543 int max_ports
, port_index
;
1544 __le32 __iomem
**port_array
;
1545 struct xhci_bus_state
*bus_state
;
1547 unsigned long flags
;
1548 unsigned long port_was_suspended
= 0;
1549 bool need_usb2_u3_exit
= false;
1553 max_ports
= xhci_get_ports(hcd
, &port_array
);
1554 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
1556 if (time_before(jiffies
, bus_state
->next_statechange
))
1559 spin_lock_irqsave(&xhci
->lock
, flags
);
1560 if (!HCD_HW_ACCESSIBLE(hcd
)) {
1561 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1565 /* delay the irqs */
1566 temp
= readl(&xhci
->op_regs
->command
);
1568 writel(temp
, &xhci
->op_regs
->command
);
1570 port_index
= max_ports
;
1571 while (port_index
--) {
1572 /* Check whether need resume ports. If needed
1573 resume port and disable remote wakeup */
1576 temp
= readl(port_array
[port_index
]);
1578 /* warm reset CAS limited ports stuck in polling/compliance */
1579 if ((xhci
->quirks
& XHCI_MISSING_CAS
) &&
1580 (hcd
->speed
>= HCD_USB3
) &&
1581 xhci_port_missing_cas_quirk(port_index
, port_array
)) {
1582 xhci_dbg(xhci
, "reset stuck port %d\n", port_index
);
1585 if (DEV_SUPERSPEED_ANY(temp
))
1586 temp
&= ~(PORT_RWC_BITS
| PORT_CEC
| PORT_WAKE_BITS
);
1588 temp
&= ~(PORT_RWC_BITS
| PORT_WAKE_BITS
);
1589 if (test_bit(port_index
, &bus_state
->bus_suspended
) &&
1590 (temp
& PORT_PLS_MASK
)) {
1591 set_bit(port_index
, &port_was_suspended
);
1592 if (!DEV_SUPERSPEED_ANY(temp
)) {
1593 xhci_set_link_state(xhci
, port_array
,
1594 port_index
, XDEV_RESUME
);
1595 need_usb2_u3_exit
= true;
1598 writel(temp
, port_array
[port_index
]);
1601 if (need_usb2_u3_exit
) {
1602 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1603 msleep(USB_RESUME_TIMEOUT
);
1604 spin_lock_irqsave(&xhci
->lock
, flags
);
1607 port_index
= max_ports
;
1608 while (port_index
--) {
1609 if (!(port_was_suspended
& BIT(port_index
)))
1611 /* Clear PLC to poll it later after XDEV_U0 */
1612 xhci_test_and_clear_bit(xhci
, port_array
, port_index
, PORT_PLC
);
1613 xhci_set_link_state(xhci
, port_array
, port_index
, XDEV_U0
);
1616 port_index
= max_ports
;
1617 while (port_index
--) {
1618 if (!(port_was_suspended
& BIT(port_index
)))
1620 /* Poll and Clear PLC */
1621 sret
= xhci_handshake(port_array
[port_index
], PORT_PLC
,
1622 PORT_PLC
, 10 * 1000);
1624 xhci_warn(xhci
, "port %d resume PLC timeout\n",
1626 xhci_test_and_clear_bit(xhci
, port_array
, port_index
, PORT_PLC
);
1627 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
, port_index
+ 1);
1629 xhci_ring_device(xhci
, slot_id
);
1632 (void) readl(&xhci
->op_regs
->command
);
1634 bus_state
->next_statechange
= jiffies
+ msecs_to_jiffies(5);
1635 /* re-enable irqs */
1636 temp
= readl(&xhci
->op_regs
->command
);
1638 writel(temp
, &xhci
->op_regs
->command
);
1639 temp
= readl(&xhci
->op_regs
->command
);
1641 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1645 #endif /* CONFIG_PM */