1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
12 #include <linux/slab.h>
13 #include <asm/unaligned.h>
14 #include <linux/bitfield.h>
17 #include "xhci-trace.h"
19 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
20 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
21 PORT_RC | PORT_PLC | PORT_PE)
23 /* Default sublink speed attribute of each lane */
24 static u32 ssp_cap_default_ssa
[] = {
25 0x00050034, /* USB 3.0 SS Gen1x1 id:4 symmetric rx 5Gbps */
26 0x000500b4, /* USB 3.0 SS Gen1x1 id:4 symmetric tx 5Gbps */
27 0x000a4035, /* USB 3.1 SSP Gen2x1 id:5 symmetric rx 10Gbps */
28 0x000a40b5, /* USB 3.1 SSP Gen2x1 id:5 symmetric tx 10Gbps */
29 0x00054036, /* USB 3.2 SSP Gen1x2 id:6 symmetric rx 5Gbps */
30 0x000540b6, /* USB 3.2 SSP Gen1x2 id:6 symmetric tx 5Gbps */
31 0x000a4037, /* USB 3.2 SSP Gen2x2 id:7 symmetric rx 10Gbps */
32 0x000a40b7, /* USB 3.2 SSP Gen2x2 id:7 symmetric tx 10Gbps */
35 static int xhci_create_usb3x_bos_desc(struct xhci_hcd
*xhci
, char *buf
,
38 struct usb_bos_descriptor
*bos
;
39 struct usb_ss_cap_descriptor
*ss_cap
;
40 struct usb_ssp_cap_descriptor
*ssp_cap
;
41 struct xhci_port_cap
*port_cap
= NULL
;
52 bos
= (struct usb_bos_descriptor
*)buf
;
53 bos
->bLength
= USB_DT_BOS_SIZE
;
54 bos
->bDescriptorType
= USB_DT_BOS
;
55 bos
->wTotalLength
= cpu_to_le16(USB_DT_BOS_SIZE
+
56 USB_DT_USB_SS_CAP_SIZE
);
57 bos
->bNumDeviceCaps
= 1;
59 /* Create the descriptor for port with the highest revision */
60 for (i
= 0; i
< xhci
->num_port_caps
; i
++) {
61 u8 major
= xhci
->port_caps
[i
].maj_rev
;
62 u8 minor
= xhci
->port_caps
[i
].min_rev
;
63 u16 rev
= (major
<< 8) | minor
;
65 if (i
== 0 || bcdUSB
< rev
) {
67 port_cap
= &xhci
->port_caps
[i
];
71 if (bcdUSB
>= 0x0310) {
72 if (port_cap
->psi_count
) {
75 for (i
= 0; i
< port_cap
->psi_count
; i
++) {
76 if ((port_cap
->psi
[i
] & PLT_MASK
) == PLT_SYM
)
80 ssac
= port_cap
->psi_count
+ num_sym_ssa
- 1;
81 ssic
= port_cap
->psi_uid_count
- 1;
88 ssic
= (ssac
+ 1) / 2 - 1;
91 bos
->bNumDeviceCaps
++;
92 bos
->wTotalLength
= cpu_to_le16(USB_DT_BOS_SIZE
+
93 USB_DT_USB_SS_CAP_SIZE
+
94 USB_DT_USB_SSP_CAP_SIZE(ssac
));
97 if (wLength
< USB_DT_BOS_SIZE
+ USB_DT_USB_SS_CAP_SIZE
)
100 /* SuperSpeed USB Device Capability */
101 ss_cap
= (struct usb_ss_cap_descriptor
*)&buf
[USB_DT_BOS_SIZE
];
102 ss_cap
->bLength
= USB_DT_USB_SS_CAP_SIZE
;
103 ss_cap
->bDescriptorType
= USB_DT_DEVICE_CAPABILITY
;
104 ss_cap
->bDevCapabilityType
= USB_SS_CAP_TYPE
;
105 ss_cap
->bmAttributes
= 0; /* set later */
106 ss_cap
->wSpeedSupported
= cpu_to_le16(USB_5GBPS_OPERATION
);
107 ss_cap
->bFunctionalitySupport
= USB_LOW_SPEED_OPERATION
;
108 ss_cap
->bU1devExitLat
= 0; /* set later */
109 ss_cap
->bU2DevExitLat
= 0; /* set later */
111 reg
= readl(&xhci
->cap_regs
->hcc_params
);
113 ss_cap
->bmAttributes
|= USB_LTM_SUPPORT
;
115 if ((xhci
->quirks
& XHCI_LPM_SUPPORT
)) {
116 reg
= readl(&xhci
->cap_regs
->hcs_params3
);
117 ss_cap
->bU1devExitLat
= HCS_U1_LATENCY(reg
);
118 ss_cap
->bU2DevExitLat
= cpu_to_le16(HCS_U2_LATENCY(reg
));
121 if (wLength
< le16_to_cpu(bos
->wTotalLength
))
125 return le16_to_cpu(bos
->wTotalLength
);
127 ssp_cap
= (struct usb_ssp_cap_descriptor
*)&buf
[USB_DT_BOS_SIZE
+
128 USB_DT_USB_SS_CAP_SIZE
];
129 ssp_cap
->bLength
= USB_DT_USB_SSP_CAP_SIZE(ssac
);
130 ssp_cap
->bDescriptorType
= USB_DT_DEVICE_CAPABILITY
;
131 ssp_cap
->bDevCapabilityType
= USB_SSP_CAP_TYPE
;
132 ssp_cap
->bReserved
= 0;
133 ssp_cap
->wReserved
= 0;
134 ssp_cap
->bmAttributes
=
135 cpu_to_le32(FIELD_PREP(USB_SSP_SUBLINK_SPEED_ATTRIBS
, ssac
) |
136 FIELD_PREP(USB_SSP_SUBLINK_SPEED_IDS
, ssic
));
138 if (!port_cap
->psi_count
) {
139 for (i
= 0; i
< ssac
+ 1; i
++)
140 ssp_cap
->bmSublinkSpeedAttr
[i
] =
141 cpu_to_le32(ssp_cap_default_ssa
[i
]);
148 for (i
= 0; i
< port_cap
->psi_count
; i
++) {
159 psi
= port_cap
->psi
[i
];
160 ssid
= XHCI_EXT_PORT_PSIV(psi
);
161 lp
= XHCI_EXT_PORT_LP(psi
);
162 psie
= XHCI_EXT_PORT_PSIE(psi
);
163 psim
= XHCI_EXT_PORT_PSIM(psi
);
164 plt
= psi
& PLT_MASK
;
167 lane_mantissa
= psim
;
169 /* Shift to Gbps and set SSP Link Protocol if 10Gpbs */
170 for (; psie
< USB_SSP_SUBLINK_SPEED_LSE_GBPS
; psie
++)
173 if (!min_rate
|| psim
< min_rate
) {
178 /* Some host controllers don't set the link protocol for SSP */
180 lp
= USB_SSP_SUBLINK_SPEED_LP_SSP
;
183 * PSIM and PSIE represent the total speed of PSI. The BOS
184 * descriptor SSP sublink speed attribute lane mantissa
185 * describes the lane speed. E.g. PSIM and PSIE for gen2x2
186 * is 20Gbps, but the BOS descriptor lane speed mantissa is
187 * 10Gbps. Check and modify the mantissa value to match the
190 if (bcdUSB
== 0x0320 && plt
== PLT_SYM
) {
192 * The PSI dword for gen1x2 and gen2x1 share the same
193 * values. But the lane speed for gen1x2 is 5Gbps while
194 * gen2x1 is 10Gbps. If the previous PSI dword SSID is
195 * 5 and the PSIE and PSIM match with SSID 6, let's
196 * assume that the controller follows the default speed
197 * id with SSID 6 for gen1x2.
199 if (ssid
== 6 && psie
== 3 && psim
== 10 && i
) {
200 u32 prev
= port_cap
->psi
[i
- 1];
202 if ((prev
& PLT_MASK
) == PLT_SYM
&&
203 XHCI_EXT_PORT_PSIV(prev
) == 5 &&
204 XHCI_EXT_PORT_PSIE(prev
) == 3 &&
205 XHCI_EXT_PORT_PSIM(prev
) == 10) {
206 lse
= USB_SSP_SUBLINK_SPEED_LSE_GBPS
;
211 if (psie
== 3 && psim
> 10) {
212 lse
= USB_SSP_SUBLINK_SPEED_LSE_GBPS
;
217 attr
= (FIELD_PREP(USB_SSP_SUBLINK_SPEED_SSID
, ssid
) |
218 FIELD_PREP(USB_SSP_SUBLINK_SPEED_LP
, lp
) |
219 FIELD_PREP(USB_SSP_SUBLINK_SPEED_LSE
, lse
) |
220 FIELD_PREP(USB_SSP_SUBLINK_SPEED_LSM
, lane_mantissa
));
224 attr
|= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST
,
225 USB_SSP_SUBLINK_SPEED_ST_SYM_RX
);
226 ssp_cap
->bmSublinkSpeedAttr
[offset
++] = cpu_to_le32(attr
);
228 attr
&= ~USB_SSP_SUBLINK_SPEED_ST
;
229 attr
|= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST
,
230 USB_SSP_SUBLINK_SPEED_ST_SYM_TX
);
231 ssp_cap
->bmSublinkSpeedAttr
[offset
++] = cpu_to_le32(attr
);
234 attr
|= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST
,
235 USB_SSP_SUBLINK_SPEED_ST_ASYM_RX
);
236 ssp_cap
->bmSublinkSpeedAttr
[offset
++] = cpu_to_le32(attr
);
239 attr
|= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST
,
240 USB_SSP_SUBLINK_SPEED_ST_ASYM_TX
);
241 ssp_cap
->bmSublinkSpeedAttr
[offset
++] = cpu_to_le32(attr
);
246 ssp_cap
->wFunctionalitySupport
=
247 cpu_to_le16(FIELD_PREP(USB_SSP_MIN_SUBLINK_SPEED_ATTRIBUTE_ID
,
249 FIELD_PREP(USB_SSP_MIN_RX_LANE_COUNT
, 1) |
250 FIELD_PREP(USB_SSP_MIN_TX_LANE_COUNT
, 1));
252 return le16_to_cpu(bos
->wTotalLength
);
255 static void xhci_common_hub_descriptor(struct xhci_hcd
*xhci
,
256 struct usb_hub_descriptor
*desc
, int ports
)
260 desc
->bPwrOn2PwrGood
= 10; /* xhci section 5.4.9 says 20ms max */
261 desc
->bHubContrCurrent
= 0;
263 desc
->bNbrPorts
= ports
;
265 /* Bits 1:0 - support per-port power switching, or power always on */
266 if (HCC_PPC(xhci
->hcc_params
))
267 temp
|= HUB_CHAR_INDV_PORT_LPSM
;
269 temp
|= HUB_CHAR_NO_LPSM
;
270 /* Bit 2 - root hubs are not part of a compound device */
271 /* Bits 4:3 - individual port over current protection */
272 temp
|= HUB_CHAR_INDV_PORT_OCPM
;
273 /* Bits 6:5 - no TTs in root ports */
274 /* Bit 7 - no port indicators */
275 desc
->wHubCharacteristics
= cpu_to_le16(temp
);
278 /* Fill in the USB 2.0 roothub descriptor */
279 static void xhci_usb2_hub_descriptor(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
280 struct usb_hub_descriptor
*desc
)
284 __u8 port_removable
[(USB_MAXCHILDREN
+ 1 + 7) / 8];
287 struct xhci_hub
*rhub
;
289 rhub
= &xhci
->usb2_rhub
;
290 ports
= rhub
->num_ports
;
291 xhci_common_hub_descriptor(xhci
, desc
, ports
);
292 desc
->bDescriptorType
= USB_DT_HUB
;
293 temp
= 1 + (ports
/ 8);
294 desc
->bDescLength
= USB_DT_HUB_NONVAR_SIZE
+ 2 * temp
;
296 /* The Device Removable bits are reported on a byte granularity.
297 * If the port doesn't exist within that byte, the bit is set to 0.
299 memset(port_removable
, 0, sizeof(port_removable
));
300 for (i
= 0; i
< ports
; i
++) {
301 portsc
= readl(rhub
->ports
[i
]->addr
);
302 /* If a device is removable, PORTSC reports a 0, same as in the
303 * hub descriptor DeviceRemovable bits.
305 if (portsc
& PORT_DEV_REMOVE
)
306 /* This math is hairy because bit 0 of DeviceRemovable
307 * is reserved, and bit 1 is for port 1, etc.
309 port_removable
[(i
+ 1) / 8] |= 1 << ((i
+ 1) % 8);
312 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
313 * ports on it. The USB 2.0 specification says that there are two
314 * variable length fields at the end of the hub descriptor:
315 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
316 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
317 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
318 * 0xFF, so we initialize the both arrays (DeviceRemovable and
319 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
320 * set of ports that actually exist.
322 memset(desc
->u
.hs
.DeviceRemovable
, 0xff,
323 sizeof(desc
->u
.hs
.DeviceRemovable
));
324 memset(desc
->u
.hs
.PortPwrCtrlMask
, 0xff,
325 sizeof(desc
->u
.hs
.PortPwrCtrlMask
));
327 for (i
= 0; i
< (ports
+ 1 + 7) / 8; i
++)
328 memset(&desc
->u
.hs
.DeviceRemovable
[i
], port_removable
[i
],
332 /* Fill in the USB 3.0 roothub descriptor */
333 static void xhci_usb3_hub_descriptor(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
334 struct usb_hub_descriptor
*desc
)
340 struct xhci_hub
*rhub
;
342 rhub
= &xhci
->usb3_rhub
;
343 ports
= rhub
->num_ports
;
344 xhci_common_hub_descriptor(xhci
, desc
, ports
);
345 desc
->bDescriptorType
= USB_DT_SS_HUB
;
346 desc
->bDescLength
= USB_DT_SS_HUB_SIZE
;
348 /* header decode latency should be zero for roothubs,
349 * see section 4.23.5.2.
351 desc
->u
.ss
.bHubHdrDecLat
= 0;
352 desc
->u
.ss
.wHubDelay
= 0;
355 /* bit 0 is reserved, bit 1 is for port 1, etc. */
356 for (i
= 0; i
< ports
; i
++) {
357 portsc
= readl(rhub
->ports
[i
]->addr
);
358 if (portsc
& PORT_DEV_REMOVE
)
359 port_removable
|= 1 << (i
+ 1);
362 desc
->u
.ss
.DeviceRemovable
= cpu_to_le16(port_removable
);
365 static void xhci_hub_descriptor(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
366 struct usb_hub_descriptor
*desc
)
369 if (hcd
->speed
>= HCD_USB3
)
370 xhci_usb3_hub_descriptor(hcd
, xhci
, desc
);
372 xhci_usb2_hub_descriptor(hcd
, xhci
, desc
);
376 static unsigned int xhci_port_speed(unsigned int port_status
)
378 if (DEV_LOWSPEED(port_status
))
379 return USB_PORT_STAT_LOW_SPEED
;
380 if (DEV_HIGHSPEED(port_status
))
381 return USB_PORT_STAT_HIGH_SPEED
;
383 * FIXME: Yes, we should check for full speed, but the core uses that as
384 * a default in portspeed() in usb/core/hub.c (which is the only place
385 * USB_PORT_STAT_*_SPEED is used).
391 * These bits are Read Only (RO) and should be saved and written to the
392 * registers: 0, 3, 10:13, 30
393 * connect status, over-current status, port speed, and device removable.
394 * connect status and port speed are also sticky - meaning they're in
395 * the AUX well and they aren't changed by a hot, warm, or cold reset.
397 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
399 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
400 * bits 5:8, 9, 14:15, 25:27
401 * link state, port power, port indicator state, "wake on" enable state
403 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
405 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
408 #define XHCI_PORT_RW1S ((1<<4))
410 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
411 * bits 1, 17, 18, 19, 20, 21, 22, 23
412 * port enable/disable, and
413 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
414 * over-current, reset, link state, and L1 change
416 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
418 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
421 #define XHCI_PORT_RW ((1<<16))
423 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
426 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
429 * Given a port state, this function returns a value that would result in the
430 * port being in the same state, if the value was written to the port status
432 * Save Read Only (RO) bits and save read/write bits where
433 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
434 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
436 u32
xhci_port_state_to_neutral(u32 state
)
438 /* Save read-only status and port state */
439 return (state
& XHCI_PORT_RO
) | (state
& XHCI_PORT_RWS
);
443 * find slot id based on port number.
444 * @port: The one-based port number from one of the two split roothubs.
446 int xhci_find_slot_id_by_port(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
451 enum usb_device_speed speed
;
454 for (i
= 0; i
< MAX_HC_SLOTS
; i
++) {
455 if (!xhci
->devs
[i
] || !xhci
->devs
[i
]->udev
)
457 speed
= xhci
->devs
[i
]->udev
->speed
;
458 if (((speed
>= USB_SPEED_SUPER
) == (hcd
->speed
>= HCD_USB3
))
459 && xhci
->devs
[i
]->fake_port
== port
) {
470 * It issues stop endpoint command for EP 0 to 30. And wait the last command
472 * suspend will set to 1, if suspend bit need to set in command.
474 static int xhci_stop_device(struct xhci_hcd
*xhci
, int slot_id
, int suspend
)
476 struct xhci_virt_device
*virt_dev
;
477 struct xhci_command
*cmd
;
483 virt_dev
= xhci
->devs
[slot_id
];
487 trace_xhci_stop_device(virt_dev
);
489 cmd
= xhci_alloc_command(xhci
, true, GFP_NOIO
);
493 spin_lock_irqsave(&xhci
->lock
, flags
);
494 for (i
= LAST_EP_INDEX
; i
> 0; i
--) {
495 if (virt_dev
->eps
[i
].ring
&& virt_dev
->eps
[i
].ring
->dequeue
) {
496 struct xhci_ep_ctx
*ep_ctx
;
497 struct xhci_command
*command
;
499 ep_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->out_ctx
, i
);
501 /* Check ep is running, required by AMD SNPS 3.1 xHC */
502 if (GET_EP_CTX_STATE(ep_ctx
) != EP_STATE_RUNNING
)
505 command
= xhci_alloc_command(xhci
, false, GFP_NOWAIT
);
507 spin_unlock_irqrestore(&xhci
->lock
, flags
);
512 ret
= xhci_queue_stop_endpoint(xhci
, command
, slot_id
,
515 spin_unlock_irqrestore(&xhci
->lock
, flags
);
516 xhci_free_command(xhci
, command
);
521 ret
= xhci_queue_stop_endpoint(xhci
, cmd
, slot_id
, 0, suspend
);
523 spin_unlock_irqrestore(&xhci
->lock
, flags
);
527 xhci_ring_cmd_db(xhci
);
528 spin_unlock_irqrestore(&xhci
->lock
, flags
);
530 /* Wait for last stop endpoint command to finish */
531 wait_for_completion(cmd
->completion
);
533 if (cmd
->status
== COMP_COMMAND_ABORTED
||
534 cmd
->status
== COMP_COMMAND_RING_STOPPED
) {
535 xhci_warn(xhci
, "Timeout while waiting for stop endpoint command\n");
540 xhci_free_command(xhci
, cmd
);
545 * Ring device, it rings the all doorbells unconditionally.
547 void xhci_ring_device(struct xhci_hcd
*xhci
, int slot_id
)
550 struct xhci_virt_ep
*ep
;
552 for (i
= 0; i
< LAST_EP_INDEX
+ 1; i
++) {
553 ep
= &xhci
->devs
[slot_id
]->eps
[i
];
555 if (ep
->ep_state
& EP_HAS_STREAMS
) {
556 for (s
= 1; s
< ep
->stream_info
->num_streams
; s
++)
557 xhci_ring_ep_doorbell(xhci
, slot_id
, i
, s
);
558 } else if (ep
->ring
&& ep
->ring
->dequeue
) {
559 xhci_ring_ep_doorbell(xhci
, slot_id
, i
, 0);
566 static void xhci_disable_port(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
567 u16 wIndex
, __le32 __iomem
*addr
, u32 port_status
)
569 /* Don't allow the USB core to disable SuperSpeed ports. */
570 if (hcd
->speed
>= HCD_USB3
) {
571 xhci_dbg(xhci
, "Ignoring request to disable "
572 "SuperSpeed port.\n");
576 if (xhci
->quirks
& XHCI_BROKEN_PORT_PED
) {
578 "Broken Port Enabled/Disabled, ignoring port disable request.\n");
582 /* Write 1 to disable the port */
583 writel(port_status
| PORT_PE
, addr
);
584 port_status
= readl(addr
);
585 xhci_dbg(xhci
, "disable port %d-%d, portsc: 0x%x\n",
586 hcd
->self
.busnum
, wIndex
+ 1, port_status
);
589 static void xhci_clear_port_change_bit(struct xhci_hcd
*xhci
, u16 wValue
,
590 u16 wIndex
, __le32 __iomem
*addr
, u32 port_status
)
592 char *port_change_bit
;
596 case USB_PORT_FEAT_C_RESET
:
598 port_change_bit
= "reset";
600 case USB_PORT_FEAT_C_BH_PORT_RESET
:
602 port_change_bit
= "warm(BH) reset";
604 case USB_PORT_FEAT_C_CONNECTION
:
606 port_change_bit
= "connect";
608 case USB_PORT_FEAT_C_OVER_CURRENT
:
610 port_change_bit
= "over-current";
612 case USB_PORT_FEAT_C_ENABLE
:
614 port_change_bit
= "enable/disable";
616 case USB_PORT_FEAT_C_SUSPEND
:
618 port_change_bit
= "suspend/resume";
620 case USB_PORT_FEAT_C_PORT_LINK_STATE
:
622 port_change_bit
= "link state";
624 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR
:
626 port_change_bit
= "config error";
629 /* Should never happen */
632 /* Change bits are all write 1 to clear */
633 writel(port_status
| status
, addr
);
634 port_status
= readl(addr
);
636 xhci_dbg(xhci
, "clear port%d %s change, portsc: 0x%x\n",
637 wIndex
+ 1, port_change_bit
, port_status
);
640 struct xhci_hub
*xhci_get_rhub(struct usb_hcd
*hcd
)
642 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
644 if (hcd
->speed
>= HCD_USB3
)
645 return &xhci
->usb3_rhub
;
646 return &xhci
->usb2_rhub
;
650 * xhci_set_port_power() must be called with xhci->lock held.
651 * It will release and re-aquire the lock while calling ACPI
654 static void xhci_set_port_power(struct xhci_hcd
*xhci
, struct usb_hcd
*hcd
,
655 u16 index
, bool on
, unsigned long *flags
)
656 __must_hold(&xhci
->lock
)
658 struct xhci_hub
*rhub
;
659 struct xhci_port
*port
;
662 rhub
= xhci_get_rhub(hcd
);
663 port
= rhub
->ports
[index
];
664 temp
= readl(port
->addr
);
666 xhci_dbg(xhci
, "set port power %d-%d %s, portsc: 0x%x\n",
667 hcd
->self
.busnum
, index
+ 1, on
? "ON" : "OFF", temp
);
669 temp
= xhci_port_state_to_neutral(temp
);
673 writel(temp
| PORT_POWER
, port
->addr
);
677 writel(temp
& ~PORT_POWER
, port
->addr
);
680 spin_unlock_irqrestore(&xhci
->lock
, *flags
);
681 temp
= usb_acpi_power_manageable(hcd
->self
.root_hub
,
684 usb_acpi_set_power_state(hcd
->self
.root_hub
,
686 spin_lock_irqsave(&xhci
->lock
, *flags
);
689 static void xhci_port_set_test_mode(struct xhci_hcd
*xhci
,
690 u16 test_mode
, u16 wIndex
)
693 struct xhci_port
*port
;
695 /* xhci only supports test mode for usb2 ports */
696 port
= xhci
->usb2_rhub
.ports
[wIndex
];
697 temp
= readl(port
->addr
+ PORTPMSC
);
698 temp
|= test_mode
<< PORT_TEST_MODE_SHIFT
;
699 writel(temp
, port
->addr
+ PORTPMSC
);
700 xhci
->test_mode
= test_mode
;
701 if (test_mode
== USB_TEST_FORCE_ENABLE
)
705 static int xhci_enter_test_mode(struct xhci_hcd
*xhci
,
706 u16 test_mode
, u16 wIndex
, unsigned long *flags
)
707 __must_hold(&xhci
->lock
)
711 /* Disable all Device Slots */
712 xhci_dbg(xhci
, "Disable all slots\n");
713 spin_unlock_irqrestore(&xhci
->lock
, *flags
);
714 for (i
= 1; i
<= HCS_MAX_SLOTS(xhci
->hcs_params1
); i
++) {
718 retval
= xhci_disable_slot(xhci
, i
);
720 xhci_err(xhci
, "Failed to disable slot %d, %d. Enter test mode anyway\n",
723 spin_lock_irqsave(&xhci
->lock
, *flags
);
724 /* Put all ports to the Disable state by clear PP */
725 xhci_dbg(xhci
, "Disable all port (PP = 0)\n");
726 /* Power off USB3 ports*/
727 for (i
= 0; i
< xhci
->usb3_rhub
.num_ports
; i
++)
728 xhci_set_port_power(xhci
, xhci
->shared_hcd
, i
, false, flags
);
729 /* Power off USB2 ports*/
730 for (i
= 0; i
< xhci
->usb2_rhub
.num_ports
; i
++)
731 xhci_set_port_power(xhci
, xhci
->main_hcd
, i
, false, flags
);
732 /* Stop the controller */
733 xhci_dbg(xhci
, "Stop controller\n");
734 retval
= xhci_halt(xhci
);
737 /* Disable runtime PM for test mode */
738 pm_runtime_forbid(xhci_to_hcd(xhci
)->self
.controller
);
739 /* Set PORTPMSC.PTC field to enter selected test mode */
740 /* Port is selected by wIndex. port_id = wIndex + 1 */
741 xhci_dbg(xhci
, "Enter Test Mode: %d, Port_id=%d\n",
742 test_mode
, wIndex
+ 1);
743 xhci_port_set_test_mode(xhci
, test_mode
, wIndex
);
747 static int xhci_exit_test_mode(struct xhci_hcd
*xhci
)
751 if (!xhci
->test_mode
) {
752 xhci_err(xhci
, "Not in test mode, do nothing.\n");
755 if (xhci
->test_mode
== USB_TEST_FORCE_ENABLE
&&
756 !(xhci
->xhc_state
& XHCI_STATE_HALTED
)) {
757 retval
= xhci_halt(xhci
);
761 pm_runtime_allow(xhci_to_hcd(xhci
)->self
.controller
);
763 return xhci_reset(xhci
);
766 void xhci_set_link_state(struct xhci_hcd
*xhci
, struct xhci_port
*port
,
772 portsc
= readl(port
->addr
);
773 temp
= xhci_port_state_to_neutral(portsc
);
774 temp
&= ~PORT_PLS_MASK
;
775 temp
|= PORT_LINK_STROBE
| link_state
;
776 writel(temp
, port
->addr
);
778 xhci_dbg(xhci
, "Set port %d-%d link state, portsc: 0x%x, write 0x%x",
779 port
->rhub
->hcd
->self
.busnum
, port
->hcd_portnum
+ 1,
783 static void xhci_set_remote_wake_mask(struct xhci_hcd
*xhci
,
784 struct xhci_port
*port
, u16 wake_mask
)
788 temp
= readl(port
->addr
);
789 temp
= xhci_port_state_to_neutral(temp
);
791 if (wake_mask
& USB_PORT_FEAT_REMOTE_WAKE_CONNECT
)
792 temp
|= PORT_WKCONN_E
;
794 temp
&= ~PORT_WKCONN_E
;
796 if (wake_mask
& USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT
)
797 temp
|= PORT_WKDISC_E
;
799 temp
&= ~PORT_WKDISC_E
;
801 if (wake_mask
& USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT
)
804 temp
&= ~PORT_WKOC_E
;
806 writel(temp
, port
->addr
);
809 /* Test and clear port RWC bit */
810 void xhci_test_and_clear_bit(struct xhci_hcd
*xhci
, struct xhci_port
*port
,
815 temp
= readl(port
->addr
);
816 if (temp
& port_bit
) {
817 temp
= xhci_port_state_to_neutral(temp
);
819 writel(temp
, port
->addr
);
823 /* Updates Link Status for super Speed port */
824 static void xhci_hub_report_usb3_link_state(struct xhci_hcd
*xhci
,
825 u32
*status
, u32 status_reg
)
827 u32 pls
= status_reg
& PORT_PLS_MASK
;
829 /* When the CAS bit is set then warm reset
830 * should be performed on port
832 if (status_reg
& PORT_CAS
) {
833 /* The CAS bit can be set while the port is
835 * Only roothubs have CAS bit, so we
836 * pretend to be in compliance mode
837 * unless we're already in compliance
838 * or the inactive state.
840 if (pls
!= USB_SS_PORT_LS_COMP_MOD
&&
841 pls
!= USB_SS_PORT_LS_SS_INACTIVE
) {
842 pls
= USB_SS_PORT_LS_COMP_MOD
;
844 /* Return also connection bit -
845 * hub state machine resets port
846 * when this bit is set.
848 pls
|= USB_PORT_STAT_CONNECTION
;
851 * Resume state is an xHCI internal state. Do not report it to
852 * usb core, instead, pretend to be U3, thus usb core knows
853 * it's not ready for transfer.
855 if (pls
== XDEV_RESUME
) {
856 *status
|= USB_SS_PORT_LS_U3
;
861 * If CAS bit isn't set but the Port is already at
862 * Compliance Mode, fake a connection so the USB core
863 * notices the Compliance state and resets the port.
864 * This resolves an issue generated by the SN65LVPE502CP
865 * in which sometimes the port enters compliance mode
866 * caused by a delay on the host-device negotiation.
868 if ((xhci
->quirks
& XHCI_COMP_MODE_QUIRK
) &&
869 (pls
== USB_SS_PORT_LS_COMP_MOD
))
870 pls
|= USB_PORT_STAT_CONNECTION
;
873 /* update status field */
878 * Function for Compliance Mode Quirk.
880 * This Function verifies if all xhc USB3 ports have entered U0, if so,
881 * the compliance mode timer is deleted. A port won't enter
882 * compliance mode if it has previously entered U0.
884 static void xhci_del_comp_mod_timer(struct xhci_hcd
*xhci
, u32 status
,
887 u32 all_ports_seen_u0
= ((1 << xhci
->usb3_rhub
.num_ports
) - 1);
888 bool port_in_u0
= ((status
& PORT_PLS_MASK
) == XDEV_U0
);
890 if (!(xhci
->quirks
& XHCI_COMP_MODE_QUIRK
))
893 if ((xhci
->port_status_u0
!= all_ports_seen_u0
) && port_in_u0
) {
894 xhci
->port_status_u0
|= 1 << wIndex
;
895 if (xhci
->port_status_u0
== all_ports_seen_u0
) {
896 del_timer_sync(&xhci
->comp_mode_recovery_timer
);
897 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
898 "All USB3 ports have entered U0 already!");
899 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
900 "Compliance Mode Recovery Timer Deleted.");
905 static int xhci_handle_usb2_port_link_resume(struct xhci_port
*port
,
906 u32
*status
, u32 portsc
,
907 unsigned long *flags
)
909 struct xhci_bus_state
*bus_state
;
910 struct xhci_hcd
*xhci
;
915 hcd
= port
->rhub
->hcd
;
916 bus_state
= &port
->rhub
->bus_state
;
917 xhci
= hcd_to_xhci(hcd
);
918 wIndex
= port
->hcd_portnum
;
920 if ((portsc
& PORT_RESET
) || !(portsc
& PORT_PE
)) {
921 *status
= 0xffffffff;
924 /* did port event handler already start resume timing? */
925 if (!bus_state
->resume_done
[wIndex
]) {
926 /* If not, maybe we are in a host initated resume? */
927 if (test_bit(wIndex
, &bus_state
->resuming_ports
)) {
928 /* Host initated resume doesn't time the resume
929 * signalling using resume_done[].
930 * It manually sets RESUME state, sleeps 20ms
931 * and sets U0 state. This should probably be
932 * changed, but not right now.
935 /* port resume was discovered now and here,
936 * start resume timing
938 unsigned long timeout
= jiffies
+
939 msecs_to_jiffies(USB_RESUME_TIMEOUT
);
941 set_bit(wIndex
, &bus_state
->resuming_ports
);
942 bus_state
->resume_done
[wIndex
] = timeout
;
943 mod_timer(&hcd
->rh_timer
, timeout
);
944 usb_hcd_start_port_resume(&hcd
->self
, wIndex
);
946 /* Has resume been signalled for USB_RESUME_TIME yet? */
947 } else if (time_after_eq(jiffies
, bus_state
->resume_done
[wIndex
])) {
950 xhci_dbg(xhci
, "resume USB2 port %d-%d\n",
951 hcd
->self
.busnum
, wIndex
+ 1);
953 bus_state
->resume_done
[wIndex
] = 0;
954 clear_bit(wIndex
, &bus_state
->resuming_ports
);
956 set_bit(wIndex
, &bus_state
->rexit_ports
);
958 xhci_test_and_clear_bit(xhci
, port
, PORT_PLC
);
959 xhci_set_link_state(xhci
, port
, XDEV_U0
);
961 spin_unlock_irqrestore(&xhci
->lock
, *flags
);
962 time_left
= wait_for_completion_timeout(
963 &bus_state
->rexit_done
[wIndex
],
964 msecs_to_jiffies(XHCI_MAX_REXIT_TIMEOUT_MS
));
965 spin_lock_irqsave(&xhci
->lock
, *flags
);
968 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
971 xhci_dbg(xhci
, "slot_id is zero\n");
972 *status
= 0xffffffff;
975 xhci_ring_device(xhci
, slot_id
);
977 int port_status
= readl(port
->addr
);
979 xhci_warn(xhci
, "Port resume timed out, port %d-%d: 0x%x\n",
980 hcd
->self
.busnum
, wIndex
+ 1, port_status
);
981 *status
|= USB_PORT_STAT_SUSPEND
;
982 clear_bit(wIndex
, &bus_state
->rexit_ports
);
985 usb_hcd_end_port_resume(&hcd
->self
, wIndex
);
986 bus_state
->port_c_suspend
|= 1 << wIndex
;
987 bus_state
->suspended_ports
&= ~(1 << wIndex
);
990 * The resume has been signaling for less than
991 * USB_RESUME_TIME. Report the port status as SUSPEND,
992 * let the usbcore check port status again and clear
993 * resume signaling later.
995 *status
|= USB_PORT_STAT_SUSPEND
;
1000 static u32
xhci_get_ext_port_status(u32 raw_port_status
, u32 port_li
)
1005 /* only support rx and tx lane counts of 1 in usb3.1 spec */
1006 speed_id
= DEV_PORT_SPEED(raw_port_status
);
1007 ext_stat
|= speed_id
; /* bits 3:0, RX speed id */
1008 ext_stat
|= speed_id
<< 4; /* bits 7:4, TX speed id */
1010 ext_stat
|= PORT_RX_LANES(port_li
) << 8; /* bits 11:8 Rx lane count */
1011 ext_stat
|= PORT_TX_LANES(port_li
) << 12; /* bits 15:12 Tx lane count */
1016 static void xhci_get_usb3_port_status(struct xhci_port
*port
, u32
*status
,
1019 struct xhci_bus_state
*bus_state
;
1020 struct xhci_hcd
*xhci
;
1021 struct usb_hcd
*hcd
;
1025 bus_state
= &port
->rhub
->bus_state
;
1026 xhci
= hcd_to_xhci(port
->rhub
->hcd
);
1027 hcd
= port
->rhub
->hcd
;
1028 link_state
= portsc
& PORT_PLS_MASK
;
1029 portnum
= port
->hcd_portnum
;
1031 /* USB3 specific wPortChange bits
1033 * Port link change with port in resume state should not be
1034 * reported to usbcore, as this is an internal state to be
1035 * handled by xhci driver. Reporting PLC to usbcore may
1036 * cause usbcore clearing PLC first and port change event
1037 * irq won't be generated.
1040 if (portsc
& PORT_PLC
&& (link_state
!= XDEV_RESUME
))
1041 *status
|= USB_PORT_STAT_C_LINK_STATE
<< 16;
1042 if (portsc
& PORT_WRC
)
1043 *status
|= USB_PORT_STAT_C_BH_RESET
<< 16;
1044 if (portsc
& PORT_CEC
)
1045 *status
|= USB_PORT_STAT_C_CONFIG_ERROR
<< 16;
1047 /* USB3 specific wPortStatus bits */
1048 if (portsc
& PORT_POWER
) {
1049 *status
|= USB_SS_PORT_STAT_POWER
;
1050 /* link state handling */
1051 if (link_state
== XDEV_U0
)
1052 bus_state
->suspended_ports
&= ~(1 << portnum
);
1055 /* remote wake resume signaling complete */
1056 if (bus_state
->port_remote_wakeup
& (1 << portnum
) &&
1057 link_state
!= XDEV_RESUME
&&
1058 link_state
!= XDEV_RECOVERY
) {
1059 bus_state
->port_remote_wakeup
&= ~(1 << portnum
);
1060 usb_hcd_end_port_resume(&hcd
->self
, portnum
);
1063 xhci_hub_report_usb3_link_state(xhci
, status
, portsc
);
1064 xhci_del_comp_mod_timer(xhci
, portsc
, portnum
);
1067 static void xhci_get_usb2_port_status(struct xhci_port
*port
, u32
*status
,
1068 u32 portsc
, unsigned long *flags
)
1070 struct xhci_bus_state
*bus_state
;
1075 bus_state
= &port
->rhub
->bus_state
;
1076 link_state
= portsc
& PORT_PLS_MASK
;
1077 portnum
= port
->hcd_portnum
;
1079 /* USB2 wPortStatus bits */
1080 if (portsc
& PORT_POWER
) {
1081 *status
|= USB_PORT_STAT_POWER
;
1083 /* link state is only valid if port is powered */
1084 if (link_state
== XDEV_U3
)
1085 *status
|= USB_PORT_STAT_SUSPEND
;
1086 if (link_state
== XDEV_U2
)
1087 *status
|= USB_PORT_STAT_L1
;
1088 if (link_state
== XDEV_U0
) {
1089 bus_state
->resume_done
[portnum
] = 0;
1090 clear_bit(portnum
, &bus_state
->resuming_ports
);
1091 if (bus_state
->suspended_ports
& (1 << portnum
)) {
1092 bus_state
->suspended_ports
&= ~(1 << portnum
);
1093 bus_state
->port_c_suspend
|= 1 << portnum
;
1096 if (link_state
== XDEV_RESUME
) {
1097 ret
= xhci_handle_usb2_port_link_resume(port
, status
,
1106 * Converts a raw xHCI port status into the format that external USB 2.0 or USB
1109 * Possible side effects:
1110 * - Mark a port as being done with device resume,
1111 * and ring the endpoint doorbells.
1112 * - Stop the Synopsys redriver Compliance Mode polling.
1113 * - Drop and reacquire the xHCI lock, in order to wait for port resume.
1115 static u32
xhci_get_port_status(struct usb_hcd
*hcd
,
1116 struct xhci_bus_state
*bus_state
,
1117 u16 wIndex
, u32 raw_port_status
,
1118 unsigned long *flags
)
1119 __releases(&xhci
->lock
)
1120 __acquires(&xhci
->lock
)
1123 struct xhci_hub
*rhub
;
1124 struct xhci_port
*port
;
1126 rhub
= xhci_get_rhub(hcd
);
1127 port
= rhub
->ports
[wIndex
];
1129 /* common wPortChange bits */
1130 if (raw_port_status
& PORT_CSC
)
1131 status
|= USB_PORT_STAT_C_CONNECTION
<< 16;
1132 if (raw_port_status
& PORT_PEC
)
1133 status
|= USB_PORT_STAT_C_ENABLE
<< 16;
1134 if ((raw_port_status
& PORT_OCC
))
1135 status
|= USB_PORT_STAT_C_OVERCURRENT
<< 16;
1136 if ((raw_port_status
& PORT_RC
))
1137 status
|= USB_PORT_STAT_C_RESET
<< 16;
1139 /* common wPortStatus bits */
1140 if (raw_port_status
& PORT_CONNECT
) {
1141 status
|= USB_PORT_STAT_CONNECTION
;
1142 status
|= xhci_port_speed(raw_port_status
);
1144 if (raw_port_status
& PORT_PE
)
1145 status
|= USB_PORT_STAT_ENABLE
;
1146 if (raw_port_status
& PORT_OC
)
1147 status
|= USB_PORT_STAT_OVERCURRENT
;
1148 if (raw_port_status
& PORT_RESET
)
1149 status
|= USB_PORT_STAT_RESET
;
1151 /* USB2 and USB3 specific bits, including Port Link State */
1152 if (hcd
->speed
>= HCD_USB3
)
1153 xhci_get_usb3_port_status(port
, &status
, raw_port_status
);
1155 xhci_get_usb2_port_status(port
, &status
, raw_port_status
,
1158 * Clear stale usb2 resume signalling variables in case port changed
1159 * state during resume signalling. For example on error
1161 if ((bus_state
->resume_done
[wIndex
] ||
1162 test_bit(wIndex
, &bus_state
->resuming_ports
)) &&
1163 (raw_port_status
& PORT_PLS_MASK
) != XDEV_U3
&&
1164 (raw_port_status
& PORT_PLS_MASK
) != XDEV_RESUME
) {
1165 bus_state
->resume_done
[wIndex
] = 0;
1166 clear_bit(wIndex
, &bus_state
->resuming_ports
);
1167 usb_hcd_end_port_resume(&hcd
->self
, wIndex
);
1170 if (bus_state
->port_c_suspend
& (1 << wIndex
))
1171 status
|= USB_PORT_STAT_C_SUSPEND
<< 16;
1176 int xhci_hub_control(struct usb_hcd
*hcd
, u16 typeReq
, u16 wValue
,
1177 u16 wIndex
, char *buf
, u16 wLength
)
1179 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
1181 unsigned long flags
;
1185 struct xhci_bus_state
*bus_state
;
1190 struct xhci_hub
*rhub
;
1191 struct xhci_port
**ports
;
1193 rhub
= xhci_get_rhub(hcd
);
1194 ports
= rhub
->ports
;
1195 max_ports
= rhub
->num_ports
;
1196 bus_state
= &rhub
->bus_state
;
1198 spin_lock_irqsave(&xhci
->lock
, flags
);
1201 /* No power source, over-current reported per port */
1204 case GetHubDescriptor
:
1205 /* Check to make sure userspace is asking for the USB 3.0 hub
1206 * descriptor for the USB 3.0 roothub. If not, we stall the
1207 * endpoint, like external hubs do.
1209 if (hcd
->speed
>= HCD_USB3
&&
1210 (wLength
< USB_DT_SS_HUB_SIZE
||
1211 wValue
!= (USB_DT_SS_HUB
<< 8))) {
1212 xhci_dbg(xhci
, "Wrong hub descriptor type for "
1213 "USB 3.0 roothub.\n");
1216 xhci_hub_descriptor(hcd
, xhci
,
1217 (struct usb_hub_descriptor
*) buf
);
1219 case DeviceRequest
| USB_REQ_GET_DESCRIPTOR
:
1220 if ((wValue
& 0xff00) != (USB_DT_BOS
<< 8))
1223 if (hcd
->speed
< HCD_USB3
)
1226 retval
= xhci_create_usb3x_bos_desc(xhci
, buf
, wLength
);
1227 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1230 if (!wIndex
|| wIndex
> max_ports
)
1233 temp
= readl(ports
[wIndex
]->addr
);
1234 if (temp
== ~(u32
)0) {
1239 trace_xhci_get_port_status(wIndex
, temp
);
1240 status
= xhci_get_port_status(hcd
, bus_state
, wIndex
, temp
,
1242 if (status
== 0xffffffff)
1245 xhci_dbg(xhci
, "Get port status %d-%d read: 0x%x, return 0x%x",
1246 hcd
->self
.busnum
, wIndex
+ 1, temp
, status
);
1248 put_unaligned(cpu_to_le32(status
), (__le32
*) buf
);
1249 /* if USB 3.1 extended port status return additional 4 bytes */
1250 if (wValue
== 0x02) {
1253 if (hcd
->speed
< HCD_USB31
|| wLength
!= 8) {
1254 xhci_err(xhci
, "get ext port status invalid parameter\n");
1258 port_li
= readl(ports
[wIndex
]->addr
+ PORTLI
);
1259 status
= xhci_get_ext_port_status(temp
, port_li
);
1260 put_unaligned_le32(status
, &buf
[4]);
1263 case SetPortFeature
:
1264 if (wValue
== USB_PORT_FEAT_LINK_STATE
)
1265 link_state
= (wIndex
& 0xff00) >> 3;
1266 if (wValue
== USB_PORT_FEAT_REMOTE_WAKE_MASK
)
1267 wake_mask
= wIndex
& 0xff00;
1268 if (wValue
== USB_PORT_FEAT_TEST
)
1269 test_mode
= (wIndex
& 0xff00) >> 8;
1270 /* The MSB of wIndex is the U1/U2 timeout */
1271 timeout
= (wIndex
& 0xff00) >> 8;
1273 if (!wIndex
|| wIndex
> max_ports
)
1276 temp
= readl(ports
[wIndex
]->addr
);
1277 if (temp
== ~(u32
)0) {
1282 temp
= xhci_port_state_to_neutral(temp
);
1283 /* FIXME: What new port features do we need to support? */
1285 case USB_PORT_FEAT_SUSPEND
:
1286 temp
= readl(ports
[wIndex
]->addr
);
1287 if ((temp
& PORT_PLS_MASK
) != XDEV_U0
) {
1288 /* Resume the port to U0 first */
1289 xhci_set_link_state(xhci
, ports
[wIndex
],
1291 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1293 spin_lock_irqsave(&xhci
->lock
, flags
);
1295 /* In spec software should not attempt to suspend
1296 * a port unless the port reports that it is in the
1297 * enabled (PED = ‘1’,PLS < ‘3’) state.
1299 temp
= readl(ports
[wIndex
]->addr
);
1300 if ((temp
& PORT_PE
) == 0 || (temp
& PORT_RESET
)
1301 || (temp
& PORT_PLS_MASK
) >= XDEV_U3
) {
1302 xhci_warn(xhci
, "USB core suspending port %d-%d not in U0/U1/U2\n",
1303 hcd
->self
.busnum
, wIndex
+ 1);
1307 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1310 xhci_warn(xhci
, "slot_id is zero\n");
1313 /* unlock to execute stop endpoint commands */
1314 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1315 xhci_stop_device(xhci
, slot_id
, 1);
1316 spin_lock_irqsave(&xhci
->lock
, flags
);
1318 xhci_set_link_state(xhci
, ports
[wIndex
], XDEV_U3
);
1320 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1321 msleep(10); /* wait device to enter */
1322 spin_lock_irqsave(&xhci
->lock
, flags
);
1324 temp
= readl(ports
[wIndex
]->addr
);
1325 bus_state
->suspended_ports
|= 1 << wIndex
;
1327 case USB_PORT_FEAT_LINK_STATE
:
1328 temp
= readl(ports
[wIndex
]->addr
);
1330 if (link_state
== USB_SS_PORT_LS_SS_DISABLED
) {
1331 xhci_dbg(xhci
, "Disable port %d-%d\n",
1332 hcd
->self
.busnum
, wIndex
+ 1);
1333 temp
= xhci_port_state_to_neutral(temp
);
1335 * Clear all change bits, so that we get a new
1338 temp
|= PORT_CSC
| PORT_PEC
| PORT_WRC
|
1339 PORT_OCC
| PORT_RC
| PORT_PLC
|
1341 writel(temp
| PORT_PE
, ports
[wIndex
]->addr
);
1342 temp
= readl(ports
[wIndex
]->addr
);
1346 /* Put link in RxDetect (enable port) */
1347 if (link_state
== USB_SS_PORT_LS_RX_DETECT
) {
1348 xhci_dbg(xhci
, "Enable port %d-%d\n",
1349 hcd
->self
.busnum
, wIndex
+ 1);
1350 xhci_set_link_state(xhci
, ports
[wIndex
],
1352 temp
= readl(ports
[wIndex
]->addr
);
1357 * For xHCI 1.1 according to section 4.19.1.2.4.1 a
1358 * root hub port's transition to compliance mode upon
1359 * detecting LFPS timeout may be controlled by an
1360 * Compliance Transition Enabled (CTE) flag (not
1361 * software visible). This flag is set by writing 0xA
1362 * to PORTSC PLS field which will allow transition to
1363 * compliance mode the next time LFPS timeout is
1364 * encountered. A warm reset will clear it.
1366 * The CTE flag is only supported if the HCCPARAMS2 CTC
1367 * flag is set, otherwise, the compliance substate is
1368 * automatically entered as on 1.0 and prior.
1370 if (link_state
== USB_SS_PORT_LS_COMP_MOD
) {
1371 if (!HCC2_CTC(xhci
->hcc_params2
)) {
1372 xhci_dbg(xhci
, "CTC flag is 0, port already supports entering compliance mode\n");
1376 if ((temp
& PORT_CONNECT
)) {
1377 xhci_warn(xhci
, "Can't set compliance mode when port is connected\n");
1381 xhci_dbg(xhci
, "Enable compliance mode transition for port %d-%d\n",
1382 hcd
->self
.busnum
, wIndex
+ 1);
1383 xhci_set_link_state(xhci
, ports
[wIndex
],
1386 temp
= readl(ports
[wIndex
]->addr
);
1389 /* Port must be enabled */
1390 if (!(temp
& PORT_PE
)) {
1394 /* Can't set port link state above '3' (U3) */
1395 if (link_state
> USB_SS_PORT_LS_U3
) {
1396 xhci_warn(xhci
, "Cannot set port %d-%d link state %d\n",
1397 hcd
->self
.busnum
, wIndex
+ 1,
1403 * set link to U0, steps depend on current link state.
1404 * U3: set link to U0 and wait for u3exit completion.
1405 * U1/U2: no PLC complete event, only set link to U0.
1406 * Resume/Recovery: device initiated U0, only wait for
1409 if (link_state
== USB_SS_PORT_LS_U0
) {
1410 u32 pls
= temp
& PORT_PLS_MASK
;
1411 bool wait_u0
= false;
1416 if (pls
== XDEV_U3
||
1417 pls
== XDEV_RESUME
||
1418 pls
== XDEV_RECOVERY
) {
1420 reinit_completion(&bus_state
->u3exit_done
[wIndex
]);
1422 if (pls
<= XDEV_U3
) /* U1, U2, U3 */
1423 xhci_set_link_state(xhci
, ports
[wIndex
],
1430 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1431 if (!wait_for_completion_timeout(&bus_state
->u3exit_done
[wIndex
],
1432 msecs_to_jiffies(100)))
1433 xhci_dbg(xhci
, "missing U0 port change event for port %d-%d\n",
1434 hcd
->self
.busnum
, wIndex
+ 1);
1435 spin_lock_irqsave(&xhci
->lock
, flags
);
1436 temp
= readl(ports
[wIndex
]->addr
);
1440 if (link_state
== USB_SS_PORT_LS_U3
) {
1442 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1445 /* unlock to execute stop endpoint
1447 spin_unlock_irqrestore(&xhci
->lock
,
1449 xhci_stop_device(xhci
, slot_id
, 1);
1450 spin_lock_irqsave(&xhci
->lock
, flags
);
1452 xhci_set_link_state(xhci
, ports
[wIndex
], USB_SS_PORT_LS_U3
);
1453 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1455 usleep_range(4000, 8000);
1456 temp
= readl(ports
[wIndex
]->addr
);
1457 if ((temp
& PORT_PLS_MASK
) == XDEV_U3
)
1460 spin_lock_irqsave(&xhci
->lock
, flags
);
1461 temp
= readl(ports
[wIndex
]->addr
);
1462 bus_state
->suspended_ports
|= 1 << wIndex
;
1465 case USB_PORT_FEAT_POWER
:
1467 * Turn on ports, even if there isn't per-port switching.
1468 * HC will report connect events even before this is set.
1469 * However, hub_wq will ignore the roothub events until
1470 * the roothub is registered.
1472 xhci_set_port_power(xhci
, hcd
, wIndex
, true, &flags
);
1474 case USB_PORT_FEAT_RESET
:
1475 temp
= (temp
| PORT_RESET
);
1476 writel(temp
, ports
[wIndex
]->addr
);
1478 temp
= readl(ports
[wIndex
]->addr
);
1479 xhci_dbg(xhci
, "set port reset, actual port %d-%d status = 0x%x\n",
1480 hcd
->self
.busnum
, wIndex
+ 1, temp
);
1482 case USB_PORT_FEAT_REMOTE_WAKE_MASK
:
1483 xhci_set_remote_wake_mask(xhci
, ports
[wIndex
],
1485 temp
= readl(ports
[wIndex
]->addr
);
1486 xhci_dbg(xhci
, "set port remote wake mask, actual port %d-%d status = 0x%x\n",
1487 hcd
->self
.busnum
, wIndex
+ 1, temp
);
1489 case USB_PORT_FEAT_BH_PORT_RESET
:
1491 writel(temp
, ports
[wIndex
]->addr
);
1492 temp
= readl(ports
[wIndex
]->addr
);
1494 case USB_PORT_FEAT_U1_TIMEOUT
:
1495 if (hcd
->speed
< HCD_USB3
)
1497 temp
= readl(ports
[wIndex
]->addr
+ PORTPMSC
);
1498 temp
&= ~PORT_U1_TIMEOUT_MASK
;
1499 temp
|= PORT_U1_TIMEOUT(timeout
);
1500 writel(temp
, ports
[wIndex
]->addr
+ PORTPMSC
);
1502 case USB_PORT_FEAT_U2_TIMEOUT
:
1503 if (hcd
->speed
< HCD_USB3
)
1505 temp
= readl(ports
[wIndex
]->addr
+ PORTPMSC
);
1506 temp
&= ~PORT_U2_TIMEOUT_MASK
;
1507 temp
|= PORT_U2_TIMEOUT(timeout
);
1508 writel(temp
, ports
[wIndex
]->addr
+ PORTPMSC
);
1510 case USB_PORT_FEAT_TEST
:
1511 /* 4.19.6 Port Test Modes (USB2 Test Mode) */
1512 if (hcd
->speed
!= HCD_USB2
)
1514 if (test_mode
> USB_TEST_FORCE_ENABLE
||
1515 test_mode
< USB_TEST_J
)
1517 retval
= xhci_enter_test_mode(xhci
, test_mode
, wIndex
,
1523 /* unblock any posted writes */
1524 temp
= readl(ports
[wIndex
]->addr
);
1526 case ClearPortFeature
:
1527 if (!wIndex
|| wIndex
> max_ports
)
1530 temp
= readl(ports
[wIndex
]->addr
);
1531 if (temp
== ~(u32
)0) {
1536 /* FIXME: What new port features do we need to support? */
1537 temp
= xhci_port_state_to_neutral(temp
);
1539 case USB_PORT_FEAT_SUSPEND
:
1540 temp
= readl(ports
[wIndex
]->addr
);
1541 xhci_dbg(xhci
, "clear USB_PORT_FEAT_SUSPEND\n");
1542 xhci_dbg(xhci
, "PORTSC %04x\n", temp
);
1543 if (temp
& PORT_RESET
)
1545 if ((temp
& PORT_PLS_MASK
) == XDEV_U3
) {
1546 if ((temp
& PORT_PE
) == 0)
1549 set_bit(wIndex
, &bus_state
->resuming_ports
);
1550 usb_hcd_start_port_resume(&hcd
->self
, wIndex
);
1551 xhci_set_link_state(xhci
, ports
[wIndex
],
1553 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1554 msleep(USB_RESUME_TIMEOUT
);
1555 spin_lock_irqsave(&xhci
->lock
, flags
);
1556 xhci_set_link_state(xhci
, ports
[wIndex
],
1558 clear_bit(wIndex
, &bus_state
->resuming_ports
);
1559 usb_hcd_end_port_resume(&hcd
->self
, wIndex
);
1561 bus_state
->port_c_suspend
|= 1 << wIndex
;
1563 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1566 xhci_dbg(xhci
, "slot_id is zero\n");
1569 xhci_ring_device(xhci
, slot_id
);
1571 case USB_PORT_FEAT_C_SUSPEND
:
1572 bus_state
->port_c_suspend
&= ~(1 << wIndex
);
1574 case USB_PORT_FEAT_C_RESET
:
1575 case USB_PORT_FEAT_C_BH_PORT_RESET
:
1576 case USB_PORT_FEAT_C_CONNECTION
:
1577 case USB_PORT_FEAT_C_OVER_CURRENT
:
1578 case USB_PORT_FEAT_C_ENABLE
:
1579 case USB_PORT_FEAT_C_PORT_LINK_STATE
:
1580 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR
:
1581 xhci_clear_port_change_bit(xhci
, wValue
, wIndex
,
1582 ports
[wIndex
]->addr
, temp
);
1584 case USB_PORT_FEAT_ENABLE
:
1585 xhci_disable_port(hcd
, xhci
, wIndex
,
1586 ports
[wIndex
]->addr
, temp
);
1588 case USB_PORT_FEAT_POWER
:
1589 xhci_set_port_power(xhci
, hcd
, wIndex
, false, &flags
);
1591 case USB_PORT_FEAT_TEST
:
1592 retval
= xhci_exit_test_mode(xhci
);
1600 /* "stall" on error */
1603 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1608 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1609 * Ports are 0-indexed from the HCD point of view,
1610 * and 1-indexed from the USB core pointer of view.
1612 * Note that the status change bits will be cleared as soon as a port status
1613 * change event is generated, so we use the saved status from that event.
1615 int xhci_hub_status_data(struct usb_hcd
*hcd
, char *buf
)
1617 unsigned long flags
;
1621 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
1623 struct xhci_bus_state
*bus_state
;
1624 bool reset_change
= false;
1625 struct xhci_hub
*rhub
;
1626 struct xhci_port
**ports
;
1628 rhub
= xhci_get_rhub(hcd
);
1629 ports
= rhub
->ports
;
1630 max_ports
= rhub
->num_ports
;
1631 bus_state
= &rhub
->bus_state
;
1633 /* Initial status is no changes */
1634 retval
= (max_ports
+ 8) / 8;
1635 memset(buf
, 0, retval
);
1638 * Inform the usbcore about resume-in-progress by returning
1639 * a non-zero value even if there are no status changes.
1641 status
= bus_state
->resuming_ports
;
1643 mask
= PORT_CSC
| PORT_PEC
| PORT_OCC
| PORT_PLC
| PORT_WRC
| PORT_CEC
;
1645 spin_lock_irqsave(&xhci
->lock
, flags
);
1646 /* For each port, did anything change? If so, set that bit in buf. */
1647 for (i
= 0; i
< max_ports
; i
++) {
1648 temp
= readl(ports
[i
]->addr
);
1649 if (temp
== ~(u32
)0) {
1654 trace_xhci_hub_status_data(i
, temp
);
1656 if ((temp
& mask
) != 0 ||
1657 (bus_state
->port_c_suspend
& 1 << i
) ||
1658 (bus_state
->resume_done
[i
] && time_after_eq(
1659 jiffies
, bus_state
->resume_done
[i
]))) {
1660 buf
[(i
+ 1) / 8] |= 1 << (i
+ 1) % 8;
1663 if ((temp
& PORT_RC
))
1664 reset_change
= true;
1668 if (!status
&& !reset_change
) {
1669 xhci_dbg(xhci
, "%s: stopping port polling.\n", __func__
);
1670 clear_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
1672 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1673 return status
? retval
: 0;
1678 int xhci_bus_suspend(struct usb_hcd
*hcd
)
1680 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
1681 int max_ports
, port_index
;
1682 struct xhci_bus_state
*bus_state
;
1683 unsigned long flags
;
1684 struct xhci_hub
*rhub
;
1685 struct xhci_port
**ports
;
1686 u32 portsc_buf
[USB_MAXCHILDREN
];
1689 rhub
= xhci_get_rhub(hcd
);
1690 ports
= rhub
->ports
;
1691 max_ports
= rhub
->num_ports
;
1692 bus_state
= &rhub
->bus_state
;
1693 wake_enabled
= hcd
->self
.root_hub
->do_remote_wakeup
;
1695 spin_lock_irqsave(&xhci
->lock
, flags
);
1698 if (bus_state
->resuming_ports
|| /* USB2 */
1699 bus_state
->port_remote_wakeup
) { /* USB3 */
1700 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1701 xhci_dbg(xhci
, "suspend failed because a port is resuming\n");
1706 * Prepare ports for suspend, but don't write anything before all ports
1707 * are checked and we know bus suspend can proceed
1709 bus_state
->bus_suspended
= 0;
1710 port_index
= max_ports
;
1711 while (port_index
--) {
1715 t1
= readl(ports
[port_index
]->addr
);
1716 t2
= xhci_port_state_to_neutral(t1
);
1717 portsc_buf
[port_index
] = 0;
1720 * Give a USB3 port in link training time to finish, but don't
1721 * prevent suspend as port might be stuck
1723 if ((hcd
->speed
>= HCD_USB3
) && retries
-- &&
1724 (t1
& PORT_PLS_MASK
) == XDEV_POLLING
) {
1725 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1726 msleep(XHCI_PORT_POLLING_LFPS_TIME
);
1727 spin_lock_irqsave(&xhci
->lock
, flags
);
1728 xhci_dbg(xhci
, "port %d-%d polling in bus suspend, waiting\n",
1729 hcd
->self
.busnum
, port_index
+ 1);
1732 /* bail out if port detected a over-current condition */
1734 bus_state
->bus_suspended
= 0;
1735 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1736 xhci_dbg(xhci
, "Bus suspend bailout, port over-current detected\n");
1739 /* suspend ports in U0, or bail out for new connect changes */
1740 if ((t1
& PORT_PE
) && (t1
& PORT_PLS_MASK
) == XDEV_U0
) {
1741 if ((t1
& PORT_CSC
) && wake_enabled
) {
1742 bus_state
->bus_suspended
= 0;
1743 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1744 xhci_dbg(xhci
, "Bus suspend bailout, port connect change\n");
1747 xhci_dbg(xhci
, "port %d-%d not suspended\n",
1748 hcd
->self
.busnum
, port_index
+ 1);
1749 t2
&= ~PORT_PLS_MASK
;
1750 t2
|= PORT_LINK_STROBE
| XDEV_U3
;
1751 set_bit(port_index
, &bus_state
->bus_suspended
);
1753 /* USB core sets remote wake mask for USB 3.0 hubs,
1754 * including the USB 3.0 roothub, but only if CONFIG_PM
1755 * is enabled, so also enable remote wake here.
1758 if (t1
& PORT_CONNECT
) {
1759 t2
|= PORT_WKOC_E
| PORT_WKDISC_E
;
1760 t2
&= ~PORT_WKCONN_E
;
1762 t2
|= PORT_WKOC_E
| PORT_WKCONN_E
;
1763 t2
&= ~PORT_WKDISC_E
;
1766 if ((xhci
->quirks
& XHCI_U2_DISABLE_WAKE
) &&
1767 (hcd
->speed
< HCD_USB3
)) {
1768 if (usb_amd_pt_check_port(hcd
->self
.controller
,
1770 t2
&= ~PORT_WAKE_BITS
;
1773 t2
&= ~PORT_WAKE_BITS
;
1775 t1
= xhci_port_state_to_neutral(t1
);
1777 portsc_buf
[port_index
] = t2
;
1780 /* write port settings, stopping and suspending ports if needed */
1781 port_index
= max_ports
;
1782 while (port_index
--) {
1783 if (!portsc_buf
[port_index
])
1785 if (test_bit(port_index
, &bus_state
->bus_suspended
)) {
1788 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1791 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1792 xhci_stop_device(xhci
, slot_id
, 1);
1793 spin_lock_irqsave(&xhci
->lock
, flags
);
1796 writel(portsc_buf
[port_index
], ports
[port_index
]->addr
);
1798 hcd
->state
= HC_STATE_SUSPENDED
;
1799 bus_state
->next_statechange
= jiffies
+ msecs_to_jiffies(10);
1800 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1802 if (bus_state
->bus_suspended
)
1803 usleep_range(5000, 10000);
1809 * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1810 * warm reset a USB3 device stuck in polling or compliance mode after resume.
1811 * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1813 static bool xhci_port_missing_cas_quirk(struct xhci_port
*port
)
1817 portsc
= readl(port
->addr
);
1819 /* if any of these are set we are not stuck */
1820 if (portsc
& (PORT_CONNECT
| PORT_CAS
))
1823 if (((portsc
& PORT_PLS_MASK
) != XDEV_POLLING
) &&
1824 ((portsc
& PORT_PLS_MASK
) != XDEV_COMP_MODE
))
1827 /* clear wakeup/change bits, and do a warm port reset */
1828 portsc
&= ~(PORT_RWC_BITS
| PORT_CEC
| PORT_WAKE_BITS
);
1830 writel(portsc
, port
->addr
);
1836 int xhci_bus_resume(struct usb_hcd
*hcd
)
1838 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
1839 struct xhci_bus_state
*bus_state
;
1840 unsigned long flags
;
1841 int max_ports
, port_index
;
1846 struct xhci_hub
*rhub
;
1847 struct xhci_port
**ports
;
1849 rhub
= xhci_get_rhub(hcd
);
1850 ports
= rhub
->ports
;
1851 max_ports
= rhub
->num_ports
;
1852 bus_state
= &rhub
->bus_state
;
1854 if (time_before(jiffies
, bus_state
->next_statechange
))
1857 spin_lock_irqsave(&xhci
->lock
, flags
);
1858 if (!HCD_HW_ACCESSIBLE(hcd
)) {
1859 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1863 /* delay the irqs */
1864 temp
= readl(&xhci
->op_regs
->command
);
1866 writel(temp
, &xhci
->op_regs
->command
);
1868 /* bus specific resume for ports we suspended at bus_suspend */
1869 if (hcd
->speed
>= HCD_USB3
)
1870 next_state
= XDEV_U0
;
1872 next_state
= XDEV_RESUME
;
1874 port_index
= max_ports
;
1875 while (port_index
--) {
1876 portsc
= readl(ports
[port_index
]->addr
);
1878 /* warm reset CAS limited ports stuck in polling/compliance */
1879 if ((xhci
->quirks
& XHCI_MISSING_CAS
) &&
1880 (hcd
->speed
>= HCD_USB3
) &&
1881 xhci_port_missing_cas_quirk(ports
[port_index
])) {
1882 xhci_dbg(xhci
, "reset stuck port %d-%d\n",
1883 hcd
->self
.busnum
, port_index
+ 1);
1884 clear_bit(port_index
, &bus_state
->bus_suspended
);
1887 /* resume if we suspended the link, and it is still suspended */
1888 if (test_bit(port_index
, &bus_state
->bus_suspended
))
1889 switch (portsc
& PORT_PLS_MASK
) {
1891 portsc
= xhci_port_state_to_neutral(portsc
);
1892 portsc
&= ~PORT_PLS_MASK
;
1893 portsc
|= PORT_LINK_STROBE
| next_state
;
1896 /* resume already initiated */
1899 /* not in a resumeable state, ignore it */
1900 clear_bit(port_index
,
1901 &bus_state
->bus_suspended
);
1904 /* disable wake for all ports, write new link state if needed */
1905 portsc
&= ~(PORT_RWC_BITS
| PORT_CEC
| PORT_WAKE_BITS
);
1906 writel(portsc
, ports
[port_index
]->addr
);
1909 /* USB2 specific resume signaling delay and U0 link state transition */
1910 if (hcd
->speed
< HCD_USB3
) {
1911 if (bus_state
->bus_suspended
) {
1912 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1913 msleep(USB_RESUME_TIMEOUT
);
1914 spin_lock_irqsave(&xhci
->lock
, flags
);
1916 for_each_set_bit(port_index
, &bus_state
->bus_suspended
,
1918 /* Clear PLC to poll it later for U0 transition */
1919 xhci_test_and_clear_bit(xhci
, ports
[port_index
],
1921 xhci_set_link_state(xhci
, ports
[port_index
], XDEV_U0
);
1925 /* poll for U0 link state complete, both USB2 and USB3 */
1926 for_each_set_bit(port_index
, &bus_state
->bus_suspended
, BITS_PER_LONG
) {
1927 sret
= xhci_handshake(ports
[port_index
]->addr
, PORT_PLC
,
1928 PORT_PLC
, 10 * 1000);
1930 xhci_warn(xhci
, "port %d-%d resume PLC timeout\n",
1931 hcd
->self
.busnum
, port_index
+ 1);
1934 xhci_test_and_clear_bit(xhci
, ports
[port_index
], PORT_PLC
);
1935 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
, port_index
+ 1);
1937 xhci_ring_device(xhci
, slot_id
);
1939 (void) readl(&xhci
->op_regs
->command
);
1941 bus_state
->next_statechange
= jiffies
+ msecs_to_jiffies(5);
1942 /* re-enable irqs */
1943 temp
= readl(&xhci
->op_regs
->command
);
1945 writel(temp
, &xhci
->op_regs
->command
);
1946 temp
= readl(&xhci
->op_regs
->command
);
1948 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1952 unsigned long xhci_get_resuming_ports(struct usb_hcd
*hcd
)
1954 struct xhci_hub
*rhub
= xhci_get_rhub(hcd
);
1956 /* USB3 port wakeups are reported via usb_wakeup_notification() */
1957 return rhub
->bus_state
.resuming_ports
; /* USB2 ports only */
1960 #endif /* CONFIG_PM */