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Merge tag 'usb-5.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
[mirror_ubuntu-jammy-kernel.git] / drivers / usb / host / xhci-hub.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * xHCI host controller driver
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11
12 #include <linux/slab.h>
13 #include <asm/unaligned.h>
14 #include <linux/bitfield.h>
15
16 #include "xhci.h"
17 #include "xhci-trace.h"
18
19 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
20 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
21 PORT_RC | PORT_PLC | PORT_PE)
22
23 /* Default sublink speed attribute of each lane */
24 static u32 ssp_cap_default_ssa[] = {
25 0x00050034, /* USB 3.0 SS Gen1x1 id:4 symmetric rx 5Gbps */
26 0x000500b4, /* USB 3.0 SS Gen1x1 id:4 symmetric tx 5Gbps */
27 0x000a4035, /* USB 3.1 SSP Gen2x1 id:5 symmetric rx 10Gbps */
28 0x000a40b5, /* USB 3.1 SSP Gen2x1 id:5 symmetric tx 10Gbps */
29 0x00054036, /* USB 3.2 SSP Gen1x2 id:6 symmetric rx 5Gbps */
30 0x000540b6, /* USB 3.2 SSP Gen1x2 id:6 symmetric tx 5Gbps */
31 0x000a4037, /* USB 3.2 SSP Gen2x2 id:7 symmetric rx 10Gbps */
32 0x000a40b7, /* USB 3.2 SSP Gen2x2 id:7 symmetric tx 10Gbps */
33 };
34
35 static int xhci_create_usb3x_bos_desc(struct xhci_hcd *xhci, char *buf,
36 u16 wLength)
37 {
38 struct usb_bos_descriptor *bos;
39 struct usb_ss_cap_descriptor *ss_cap;
40 struct usb_ssp_cap_descriptor *ssp_cap;
41 struct xhci_port_cap *port_cap = NULL;
42 u16 bcdUSB;
43 u32 reg;
44 u32 min_rate = 0;
45 u8 min_ssid;
46 u8 ssac;
47 u8 ssic;
48 int offset;
49 int i;
50
51 /* BOS descriptor */
52 bos = (struct usb_bos_descriptor *)buf;
53 bos->bLength = USB_DT_BOS_SIZE;
54 bos->bDescriptorType = USB_DT_BOS;
55 bos->wTotalLength = cpu_to_le16(USB_DT_BOS_SIZE +
56 USB_DT_USB_SS_CAP_SIZE);
57 bos->bNumDeviceCaps = 1;
58
59 /* Create the descriptor for port with the highest revision */
60 for (i = 0; i < xhci->num_port_caps; i++) {
61 u8 major = xhci->port_caps[i].maj_rev;
62 u8 minor = xhci->port_caps[i].min_rev;
63 u16 rev = (major << 8) | minor;
64
65 if (i == 0 || bcdUSB < rev) {
66 bcdUSB = rev;
67 port_cap = &xhci->port_caps[i];
68 }
69 }
70
71 if (bcdUSB >= 0x0310) {
72 if (port_cap->psi_count) {
73 u8 num_sym_ssa = 0;
74
75 for (i = 0; i < port_cap->psi_count; i++) {
76 if ((port_cap->psi[i] & PLT_MASK) == PLT_SYM)
77 num_sym_ssa++;
78 }
79
80 ssac = port_cap->psi_count + num_sym_ssa - 1;
81 ssic = port_cap->psi_uid_count - 1;
82 } else {
83 if (bcdUSB >= 0x0320)
84 ssac = 7;
85 else
86 ssac = 3;
87
88 ssic = (ssac + 1) / 2 - 1;
89 }
90
91 bos->bNumDeviceCaps++;
92 bos->wTotalLength = cpu_to_le16(USB_DT_BOS_SIZE +
93 USB_DT_USB_SS_CAP_SIZE +
94 USB_DT_USB_SSP_CAP_SIZE(ssac));
95 }
96
97 if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
98 return wLength;
99
100 /* SuperSpeed USB Device Capability */
101 ss_cap = (struct usb_ss_cap_descriptor *)&buf[USB_DT_BOS_SIZE];
102 ss_cap->bLength = USB_DT_USB_SS_CAP_SIZE;
103 ss_cap->bDescriptorType = USB_DT_DEVICE_CAPABILITY;
104 ss_cap->bDevCapabilityType = USB_SS_CAP_TYPE;
105 ss_cap->bmAttributes = 0; /* set later */
106 ss_cap->wSpeedSupported = cpu_to_le16(USB_5GBPS_OPERATION);
107 ss_cap->bFunctionalitySupport = USB_LOW_SPEED_OPERATION;
108 ss_cap->bU1devExitLat = 0; /* set later */
109 ss_cap->bU2DevExitLat = 0; /* set later */
110
111 reg = readl(&xhci->cap_regs->hcc_params);
112 if (HCC_LTC(reg))
113 ss_cap->bmAttributes |= USB_LTM_SUPPORT;
114
115 if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
116 reg = readl(&xhci->cap_regs->hcs_params3);
117 ss_cap->bU1devExitLat = HCS_U1_LATENCY(reg);
118 ss_cap->bU2DevExitLat = cpu_to_le16(HCS_U2_LATENCY(reg));
119 }
120
121 if (wLength < le16_to_cpu(bos->wTotalLength))
122 return wLength;
123
124 if (bcdUSB < 0x0310)
125 return le16_to_cpu(bos->wTotalLength);
126
127 ssp_cap = (struct usb_ssp_cap_descriptor *)&buf[USB_DT_BOS_SIZE +
128 USB_DT_USB_SS_CAP_SIZE];
129 ssp_cap->bLength = USB_DT_USB_SSP_CAP_SIZE(ssac);
130 ssp_cap->bDescriptorType = USB_DT_DEVICE_CAPABILITY;
131 ssp_cap->bDevCapabilityType = USB_SSP_CAP_TYPE;
132 ssp_cap->bReserved = 0;
133 ssp_cap->wReserved = 0;
134 ssp_cap->bmAttributes =
135 cpu_to_le32(FIELD_PREP(USB_SSP_SUBLINK_SPEED_ATTRIBS, ssac) |
136 FIELD_PREP(USB_SSP_SUBLINK_SPEED_IDS, ssic));
137
138 if (!port_cap->psi_count) {
139 for (i = 0; i < ssac + 1; i++)
140 ssp_cap->bmSublinkSpeedAttr[i] =
141 cpu_to_le32(ssp_cap_default_ssa[i]);
142
143 min_ssid = 4;
144 goto out;
145 }
146
147 offset = 0;
148 for (i = 0; i < port_cap->psi_count; i++) {
149 u32 psi;
150 u32 attr;
151 u8 ssid;
152 u8 lp;
153 u8 lse;
154 u8 psie;
155 u16 lane_mantissa;
156 u16 psim;
157 u16 plt;
158
159 psi = port_cap->psi[i];
160 ssid = XHCI_EXT_PORT_PSIV(psi);
161 lp = XHCI_EXT_PORT_LP(psi);
162 psie = XHCI_EXT_PORT_PSIE(psi);
163 psim = XHCI_EXT_PORT_PSIM(psi);
164 plt = psi & PLT_MASK;
165
166 lse = psie;
167 lane_mantissa = psim;
168
169 /* Shift to Gbps and set SSP Link Protocol if 10Gpbs */
170 for (; psie < USB_SSP_SUBLINK_SPEED_LSE_GBPS; psie++)
171 psim /= 1000;
172
173 if (!min_rate || psim < min_rate) {
174 min_ssid = ssid;
175 min_rate = psim;
176 }
177
178 /* Some host controllers don't set the link protocol for SSP */
179 if (psim >= 10)
180 lp = USB_SSP_SUBLINK_SPEED_LP_SSP;
181
182 /*
183 * PSIM and PSIE represent the total speed of PSI. The BOS
184 * descriptor SSP sublink speed attribute lane mantissa
185 * describes the lane speed. E.g. PSIM and PSIE for gen2x2
186 * is 20Gbps, but the BOS descriptor lane speed mantissa is
187 * 10Gbps. Check and modify the mantissa value to match the
188 * lane speed.
189 */
190 if (bcdUSB == 0x0320 && plt == PLT_SYM) {
191 /*
192 * The PSI dword for gen1x2 and gen2x1 share the same
193 * values. But the lane speed for gen1x2 is 5Gbps while
194 * gen2x1 is 10Gbps. If the previous PSI dword SSID is
195 * 5 and the PSIE and PSIM match with SSID 6, let's
196 * assume that the controller follows the default speed
197 * id with SSID 6 for gen1x2.
198 */
199 if (ssid == 6 && psie == 3 && psim == 10 && i) {
200 u32 prev = port_cap->psi[i - 1];
201
202 if ((prev & PLT_MASK) == PLT_SYM &&
203 XHCI_EXT_PORT_PSIV(prev) == 5 &&
204 XHCI_EXT_PORT_PSIE(prev) == 3 &&
205 XHCI_EXT_PORT_PSIM(prev) == 10) {
206 lse = USB_SSP_SUBLINK_SPEED_LSE_GBPS;
207 lane_mantissa = 5;
208 }
209 }
210
211 if (psie == 3 && psim > 10) {
212 lse = USB_SSP_SUBLINK_SPEED_LSE_GBPS;
213 lane_mantissa = 10;
214 }
215 }
216
217 attr = (FIELD_PREP(USB_SSP_SUBLINK_SPEED_SSID, ssid) |
218 FIELD_PREP(USB_SSP_SUBLINK_SPEED_LP, lp) |
219 FIELD_PREP(USB_SSP_SUBLINK_SPEED_LSE, lse) |
220 FIELD_PREP(USB_SSP_SUBLINK_SPEED_LSM, lane_mantissa));
221
222 switch (plt) {
223 case PLT_SYM:
224 attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST,
225 USB_SSP_SUBLINK_SPEED_ST_SYM_RX);
226 ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr);
227
228 attr &= ~USB_SSP_SUBLINK_SPEED_ST;
229 attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST,
230 USB_SSP_SUBLINK_SPEED_ST_SYM_TX);
231 ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr);
232 break;
233 case PLT_ASYM_RX:
234 attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST,
235 USB_SSP_SUBLINK_SPEED_ST_ASYM_RX);
236 ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr);
237 break;
238 case PLT_ASYM_TX:
239 attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST,
240 USB_SSP_SUBLINK_SPEED_ST_ASYM_TX);
241 ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr);
242 break;
243 }
244 }
245 out:
246 ssp_cap->wFunctionalitySupport =
247 cpu_to_le16(FIELD_PREP(USB_SSP_MIN_SUBLINK_SPEED_ATTRIBUTE_ID,
248 min_ssid) |
249 FIELD_PREP(USB_SSP_MIN_RX_LANE_COUNT, 1) |
250 FIELD_PREP(USB_SSP_MIN_TX_LANE_COUNT, 1));
251
252 return le16_to_cpu(bos->wTotalLength);
253 }
254
255 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
256 struct usb_hub_descriptor *desc, int ports)
257 {
258 u16 temp;
259
260 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */
261 desc->bHubContrCurrent = 0;
262
263 desc->bNbrPorts = ports;
264 temp = 0;
265 /* Bits 1:0 - support per-port power switching, or power always on */
266 if (HCC_PPC(xhci->hcc_params))
267 temp |= HUB_CHAR_INDV_PORT_LPSM;
268 else
269 temp |= HUB_CHAR_NO_LPSM;
270 /* Bit 2 - root hubs are not part of a compound device */
271 /* Bits 4:3 - individual port over current protection */
272 temp |= HUB_CHAR_INDV_PORT_OCPM;
273 /* Bits 6:5 - no TTs in root ports */
274 /* Bit 7 - no port indicators */
275 desc->wHubCharacteristics = cpu_to_le16(temp);
276 }
277
278 /* Fill in the USB 2.0 roothub descriptor */
279 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
280 struct usb_hub_descriptor *desc)
281 {
282 int ports;
283 u16 temp;
284 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
285 u32 portsc;
286 unsigned int i;
287 struct xhci_hub *rhub;
288
289 rhub = &xhci->usb2_rhub;
290 ports = rhub->num_ports;
291 xhci_common_hub_descriptor(xhci, desc, ports);
292 desc->bDescriptorType = USB_DT_HUB;
293 temp = 1 + (ports / 8);
294 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
295
296 /* The Device Removable bits are reported on a byte granularity.
297 * If the port doesn't exist within that byte, the bit is set to 0.
298 */
299 memset(port_removable, 0, sizeof(port_removable));
300 for (i = 0; i < ports; i++) {
301 portsc = readl(rhub->ports[i]->addr);
302 /* If a device is removable, PORTSC reports a 0, same as in the
303 * hub descriptor DeviceRemovable bits.
304 */
305 if (portsc & PORT_DEV_REMOVE)
306 /* This math is hairy because bit 0 of DeviceRemovable
307 * is reserved, and bit 1 is for port 1, etc.
308 */
309 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
310 }
311
312 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
313 * ports on it. The USB 2.0 specification says that there are two
314 * variable length fields at the end of the hub descriptor:
315 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
316 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
317 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
318 * 0xFF, so we initialize the both arrays (DeviceRemovable and
319 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
320 * set of ports that actually exist.
321 */
322 memset(desc->u.hs.DeviceRemovable, 0xff,
323 sizeof(desc->u.hs.DeviceRemovable));
324 memset(desc->u.hs.PortPwrCtrlMask, 0xff,
325 sizeof(desc->u.hs.PortPwrCtrlMask));
326
327 for (i = 0; i < (ports + 1 + 7) / 8; i++)
328 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
329 sizeof(__u8));
330 }
331
332 /* Fill in the USB 3.0 roothub descriptor */
333 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
334 struct usb_hub_descriptor *desc)
335 {
336 int ports;
337 u16 port_removable;
338 u32 portsc;
339 unsigned int i;
340 struct xhci_hub *rhub;
341
342 rhub = &xhci->usb3_rhub;
343 ports = rhub->num_ports;
344 xhci_common_hub_descriptor(xhci, desc, ports);
345 desc->bDescriptorType = USB_DT_SS_HUB;
346 desc->bDescLength = USB_DT_SS_HUB_SIZE;
347
348 /* header decode latency should be zero for roothubs,
349 * see section 4.23.5.2.
350 */
351 desc->u.ss.bHubHdrDecLat = 0;
352 desc->u.ss.wHubDelay = 0;
353
354 port_removable = 0;
355 /* bit 0 is reserved, bit 1 is for port 1, etc. */
356 for (i = 0; i < ports; i++) {
357 portsc = readl(rhub->ports[i]->addr);
358 if (portsc & PORT_DEV_REMOVE)
359 port_removable |= 1 << (i + 1);
360 }
361
362 desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
363 }
364
365 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
366 struct usb_hub_descriptor *desc)
367 {
368
369 if (hcd->speed >= HCD_USB3)
370 xhci_usb3_hub_descriptor(hcd, xhci, desc);
371 else
372 xhci_usb2_hub_descriptor(hcd, xhci, desc);
373
374 }
375
376 static unsigned int xhci_port_speed(unsigned int port_status)
377 {
378 if (DEV_LOWSPEED(port_status))
379 return USB_PORT_STAT_LOW_SPEED;
380 if (DEV_HIGHSPEED(port_status))
381 return USB_PORT_STAT_HIGH_SPEED;
382 /*
383 * FIXME: Yes, we should check for full speed, but the core uses that as
384 * a default in portspeed() in usb/core/hub.c (which is the only place
385 * USB_PORT_STAT_*_SPEED is used).
386 */
387 return 0;
388 }
389
390 /*
391 * These bits are Read Only (RO) and should be saved and written to the
392 * registers: 0, 3, 10:13, 30
393 * connect status, over-current status, port speed, and device removable.
394 * connect status and port speed are also sticky - meaning they're in
395 * the AUX well and they aren't changed by a hot, warm, or cold reset.
396 */
397 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
398 /*
399 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
400 * bits 5:8, 9, 14:15, 25:27
401 * link state, port power, port indicator state, "wake on" enable state
402 */
403 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
404 /*
405 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
406 * bit 4 (port reset)
407 */
408 #define XHCI_PORT_RW1S ((1<<4))
409 /*
410 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
411 * bits 1, 17, 18, 19, 20, 21, 22, 23
412 * port enable/disable, and
413 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
414 * over-current, reset, link state, and L1 change
415 */
416 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
417 /*
418 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
419 * latched in
420 */
421 #define XHCI_PORT_RW ((1<<16))
422 /*
423 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
424 * bits 2, 24, 28:31
425 */
426 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
427
428 /*
429 * Given a port state, this function returns a value that would result in the
430 * port being in the same state, if the value was written to the port status
431 * control register.
432 * Save Read Only (RO) bits and save read/write bits where
433 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
434 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
435 */
436 u32 xhci_port_state_to_neutral(u32 state)
437 {
438 /* Save read-only status and port state */
439 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
440 }
441
442 /*
443 * find slot id based on port number.
444 * @port: The one-based port number from one of the two split roothubs.
445 */
446 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
447 u16 port)
448 {
449 int slot_id;
450 int i;
451 enum usb_device_speed speed;
452
453 slot_id = 0;
454 for (i = 0; i < MAX_HC_SLOTS; i++) {
455 if (!xhci->devs[i] || !xhci->devs[i]->udev)
456 continue;
457 speed = xhci->devs[i]->udev->speed;
458 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
459 && xhci->devs[i]->fake_port == port) {
460 slot_id = i;
461 break;
462 }
463 }
464
465 return slot_id;
466 }
467
468 /*
469 * Stop device
470 * It issues stop endpoint command for EP 0 to 30. And wait the last command
471 * to complete.
472 * suspend will set to 1, if suspend bit need to set in command.
473 */
474 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
475 {
476 struct xhci_virt_device *virt_dev;
477 struct xhci_command *cmd;
478 unsigned long flags;
479 int ret;
480 int i;
481
482 ret = 0;
483 virt_dev = xhci->devs[slot_id];
484 if (!virt_dev)
485 return -ENODEV;
486
487 trace_xhci_stop_device(virt_dev);
488
489 cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
490 if (!cmd)
491 return -ENOMEM;
492
493 spin_lock_irqsave(&xhci->lock, flags);
494 for (i = LAST_EP_INDEX; i > 0; i--) {
495 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
496 struct xhci_ep_ctx *ep_ctx;
497 struct xhci_command *command;
498
499 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i);
500
501 /* Check ep is running, required by AMD SNPS 3.1 xHC */
502 if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING)
503 continue;
504
505 command = xhci_alloc_command(xhci, false, GFP_NOWAIT);
506 if (!command) {
507 spin_unlock_irqrestore(&xhci->lock, flags);
508 ret = -ENOMEM;
509 goto cmd_cleanup;
510 }
511
512 ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
513 i, suspend);
514 if (ret) {
515 spin_unlock_irqrestore(&xhci->lock, flags);
516 xhci_free_command(xhci, command);
517 goto cmd_cleanup;
518 }
519 }
520 }
521 ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
522 if (ret) {
523 spin_unlock_irqrestore(&xhci->lock, flags);
524 goto cmd_cleanup;
525 }
526
527 xhci_ring_cmd_db(xhci);
528 spin_unlock_irqrestore(&xhci->lock, flags);
529
530 /* Wait for last stop endpoint command to finish */
531 wait_for_completion(cmd->completion);
532
533 if (cmd->status == COMP_COMMAND_ABORTED ||
534 cmd->status == COMP_COMMAND_RING_STOPPED) {
535 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
536 ret = -ETIME;
537 }
538
539 cmd_cleanup:
540 xhci_free_command(xhci, cmd);
541 return ret;
542 }
543
544 /*
545 * Ring device, it rings the all doorbells unconditionally.
546 */
547 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
548 {
549 int i, s;
550 struct xhci_virt_ep *ep;
551
552 for (i = 0; i < LAST_EP_INDEX + 1; i++) {
553 ep = &xhci->devs[slot_id]->eps[i];
554
555 if (ep->ep_state & EP_HAS_STREAMS) {
556 for (s = 1; s < ep->stream_info->num_streams; s++)
557 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
558 } else if (ep->ring && ep->ring->dequeue) {
559 xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
560 }
561 }
562
563 return;
564 }
565
566 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
567 u16 wIndex, __le32 __iomem *addr, u32 port_status)
568 {
569 /* Don't allow the USB core to disable SuperSpeed ports. */
570 if (hcd->speed >= HCD_USB3) {
571 xhci_dbg(xhci, "Ignoring request to disable "
572 "SuperSpeed port.\n");
573 return;
574 }
575
576 if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
577 xhci_dbg(xhci,
578 "Broken Port Enabled/Disabled, ignoring port disable request.\n");
579 return;
580 }
581
582 /* Write 1 to disable the port */
583 writel(port_status | PORT_PE, addr);
584 port_status = readl(addr);
585 xhci_dbg(xhci, "disable port %d-%d, portsc: 0x%x\n",
586 hcd->self.busnum, wIndex + 1, port_status);
587 }
588
589 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
590 u16 wIndex, __le32 __iomem *addr, u32 port_status)
591 {
592 char *port_change_bit;
593 u32 status;
594
595 switch (wValue) {
596 case USB_PORT_FEAT_C_RESET:
597 status = PORT_RC;
598 port_change_bit = "reset";
599 break;
600 case USB_PORT_FEAT_C_BH_PORT_RESET:
601 status = PORT_WRC;
602 port_change_bit = "warm(BH) reset";
603 break;
604 case USB_PORT_FEAT_C_CONNECTION:
605 status = PORT_CSC;
606 port_change_bit = "connect";
607 break;
608 case USB_PORT_FEAT_C_OVER_CURRENT:
609 status = PORT_OCC;
610 port_change_bit = "over-current";
611 break;
612 case USB_PORT_FEAT_C_ENABLE:
613 status = PORT_PEC;
614 port_change_bit = "enable/disable";
615 break;
616 case USB_PORT_FEAT_C_SUSPEND:
617 status = PORT_PLC;
618 port_change_bit = "suspend/resume";
619 break;
620 case USB_PORT_FEAT_C_PORT_LINK_STATE:
621 status = PORT_PLC;
622 port_change_bit = "link state";
623 break;
624 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
625 status = PORT_CEC;
626 port_change_bit = "config error";
627 break;
628 default:
629 /* Should never happen */
630 return;
631 }
632 /* Change bits are all write 1 to clear */
633 writel(port_status | status, addr);
634 port_status = readl(addr);
635
636 xhci_dbg(xhci, "clear port%d %s change, portsc: 0x%x\n",
637 wIndex + 1, port_change_bit, port_status);
638 }
639
640 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd)
641 {
642 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
643
644 if (hcd->speed >= HCD_USB3)
645 return &xhci->usb3_rhub;
646 return &xhci->usb2_rhub;
647 }
648
649 /*
650 * xhci_set_port_power() must be called with xhci->lock held.
651 * It will release and re-aquire the lock while calling ACPI
652 * method.
653 */
654 static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd,
655 u16 index, bool on, unsigned long *flags)
656 __must_hold(&xhci->lock)
657 {
658 struct xhci_hub *rhub;
659 struct xhci_port *port;
660 u32 temp;
661
662 rhub = xhci_get_rhub(hcd);
663 port = rhub->ports[index];
664 temp = readl(port->addr);
665
666 xhci_dbg(xhci, "set port power %d-%d %s, portsc: 0x%x\n",
667 hcd->self.busnum, index + 1, on ? "ON" : "OFF", temp);
668
669 temp = xhci_port_state_to_neutral(temp);
670
671 if (on) {
672 /* Power on */
673 writel(temp | PORT_POWER, port->addr);
674 readl(port->addr);
675 } else {
676 /* Power off */
677 writel(temp & ~PORT_POWER, port->addr);
678 }
679
680 spin_unlock_irqrestore(&xhci->lock, *flags);
681 temp = usb_acpi_power_manageable(hcd->self.root_hub,
682 index);
683 if (temp)
684 usb_acpi_set_power_state(hcd->self.root_hub,
685 index, on);
686 spin_lock_irqsave(&xhci->lock, *flags);
687 }
688
689 static void xhci_port_set_test_mode(struct xhci_hcd *xhci,
690 u16 test_mode, u16 wIndex)
691 {
692 u32 temp;
693 struct xhci_port *port;
694
695 /* xhci only supports test mode for usb2 ports */
696 port = xhci->usb2_rhub.ports[wIndex];
697 temp = readl(port->addr + PORTPMSC);
698 temp |= test_mode << PORT_TEST_MODE_SHIFT;
699 writel(temp, port->addr + PORTPMSC);
700 xhci->test_mode = test_mode;
701 if (test_mode == USB_TEST_FORCE_ENABLE)
702 xhci_start(xhci);
703 }
704
705 static int xhci_enter_test_mode(struct xhci_hcd *xhci,
706 u16 test_mode, u16 wIndex, unsigned long *flags)
707 __must_hold(&xhci->lock)
708 {
709 int i, retval;
710
711 /* Disable all Device Slots */
712 xhci_dbg(xhci, "Disable all slots\n");
713 spin_unlock_irqrestore(&xhci->lock, *flags);
714 for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
715 if (!xhci->devs[i])
716 continue;
717
718 retval = xhci_disable_slot(xhci, i);
719 if (retval)
720 xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n",
721 i, retval);
722 }
723 spin_lock_irqsave(&xhci->lock, *flags);
724 /* Put all ports to the Disable state by clear PP */
725 xhci_dbg(xhci, "Disable all port (PP = 0)\n");
726 /* Power off USB3 ports*/
727 for (i = 0; i < xhci->usb3_rhub.num_ports; i++)
728 xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags);
729 /* Power off USB2 ports*/
730 for (i = 0; i < xhci->usb2_rhub.num_ports; i++)
731 xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags);
732 /* Stop the controller */
733 xhci_dbg(xhci, "Stop controller\n");
734 retval = xhci_halt(xhci);
735 if (retval)
736 return retval;
737 /* Disable runtime PM for test mode */
738 pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller);
739 /* Set PORTPMSC.PTC field to enter selected test mode */
740 /* Port is selected by wIndex. port_id = wIndex + 1 */
741 xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n",
742 test_mode, wIndex + 1);
743 xhci_port_set_test_mode(xhci, test_mode, wIndex);
744 return retval;
745 }
746
747 static int xhci_exit_test_mode(struct xhci_hcd *xhci)
748 {
749 int retval;
750
751 if (!xhci->test_mode) {
752 xhci_err(xhci, "Not in test mode, do nothing.\n");
753 return 0;
754 }
755 if (xhci->test_mode == USB_TEST_FORCE_ENABLE &&
756 !(xhci->xhc_state & XHCI_STATE_HALTED)) {
757 retval = xhci_halt(xhci);
758 if (retval)
759 return retval;
760 }
761 pm_runtime_allow(xhci_to_hcd(xhci)->self.controller);
762 xhci->test_mode = 0;
763 return xhci_reset(xhci);
764 }
765
766 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
767 u32 link_state)
768 {
769 u32 temp;
770 u32 portsc;
771
772 portsc = readl(port->addr);
773 temp = xhci_port_state_to_neutral(portsc);
774 temp &= ~PORT_PLS_MASK;
775 temp |= PORT_LINK_STROBE | link_state;
776 writel(temp, port->addr);
777
778 xhci_dbg(xhci, "Set port %d-%d link state, portsc: 0x%x, write 0x%x",
779 port->rhub->hcd->self.busnum, port->hcd_portnum + 1,
780 portsc, temp);
781 }
782
783 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
784 struct xhci_port *port, u16 wake_mask)
785 {
786 u32 temp;
787
788 temp = readl(port->addr);
789 temp = xhci_port_state_to_neutral(temp);
790
791 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
792 temp |= PORT_WKCONN_E;
793 else
794 temp &= ~PORT_WKCONN_E;
795
796 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
797 temp |= PORT_WKDISC_E;
798 else
799 temp &= ~PORT_WKDISC_E;
800
801 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
802 temp |= PORT_WKOC_E;
803 else
804 temp &= ~PORT_WKOC_E;
805
806 writel(temp, port->addr);
807 }
808
809 /* Test and clear port RWC bit */
810 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
811 u32 port_bit)
812 {
813 u32 temp;
814
815 temp = readl(port->addr);
816 if (temp & port_bit) {
817 temp = xhci_port_state_to_neutral(temp);
818 temp |= port_bit;
819 writel(temp, port->addr);
820 }
821 }
822
823 /* Updates Link Status for super Speed port */
824 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
825 u32 *status, u32 status_reg)
826 {
827 u32 pls = status_reg & PORT_PLS_MASK;
828
829 /* When the CAS bit is set then warm reset
830 * should be performed on port
831 */
832 if (status_reg & PORT_CAS) {
833 /* The CAS bit can be set while the port is
834 * in any link state.
835 * Only roothubs have CAS bit, so we
836 * pretend to be in compliance mode
837 * unless we're already in compliance
838 * or the inactive state.
839 */
840 if (pls != USB_SS_PORT_LS_COMP_MOD &&
841 pls != USB_SS_PORT_LS_SS_INACTIVE) {
842 pls = USB_SS_PORT_LS_COMP_MOD;
843 }
844 /* Return also connection bit -
845 * hub state machine resets port
846 * when this bit is set.
847 */
848 pls |= USB_PORT_STAT_CONNECTION;
849 } else {
850 /*
851 * Resume state is an xHCI internal state. Do not report it to
852 * usb core, instead, pretend to be U3, thus usb core knows
853 * it's not ready for transfer.
854 */
855 if (pls == XDEV_RESUME) {
856 *status |= USB_SS_PORT_LS_U3;
857 return;
858 }
859
860 /*
861 * If CAS bit isn't set but the Port is already at
862 * Compliance Mode, fake a connection so the USB core
863 * notices the Compliance state and resets the port.
864 * This resolves an issue generated by the SN65LVPE502CP
865 * in which sometimes the port enters compliance mode
866 * caused by a delay on the host-device negotiation.
867 */
868 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
869 (pls == USB_SS_PORT_LS_COMP_MOD))
870 pls |= USB_PORT_STAT_CONNECTION;
871 }
872
873 /* update status field */
874 *status |= pls;
875 }
876
877 /*
878 * Function for Compliance Mode Quirk.
879 *
880 * This Function verifies if all xhc USB3 ports have entered U0, if so,
881 * the compliance mode timer is deleted. A port won't enter
882 * compliance mode if it has previously entered U0.
883 */
884 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
885 u16 wIndex)
886 {
887 u32 all_ports_seen_u0 = ((1 << xhci->usb3_rhub.num_ports) - 1);
888 bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
889
890 if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
891 return;
892
893 if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
894 xhci->port_status_u0 |= 1 << wIndex;
895 if (xhci->port_status_u0 == all_ports_seen_u0) {
896 del_timer_sync(&xhci->comp_mode_recovery_timer);
897 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
898 "All USB3 ports have entered U0 already!");
899 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
900 "Compliance Mode Recovery Timer Deleted.");
901 }
902 }
903 }
904
905 static int xhci_handle_usb2_port_link_resume(struct xhci_port *port,
906 u32 *status, u32 portsc,
907 unsigned long *flags)
908 {
909 struct xhci_bus_state *bus_state;
910 struct xhci_hcd *xhci;
911 struct usb_hcd *hcd;
912 int slot_id;
913 u32 wIndex;
914
915 hcd = port->rhub->hcd;
916 bus_state = &port->rhub->bus_state;
917 xhci = hcd_to_xhci(hcd);
918 wIndex = port->hcd_portnum;
919
920 if ((portsc & PORT_RESET) || !(portsc & PORT_PE)) {
921 *status = 0xffffffff;
922 return -EINVAL;
923 }
924 /* did port event handler already start resume timing? */
925 if (!bus_state->resume_done[wIndex]) {
926 /* If not, maybe we are in a host initated resume? */
927 if (test_bit(wIndex, &bus_state->resuming_ports)) {
928 /* Host initated resume doesn't time the resume
929 * signalling using resume_done[].
930 * It manually sets RESUME state, sleeps 20ms
931 * and sets U0 state. This should probably be
932 * changed, but not right now.
933 */
934 } else {
935 /* port resume was discovered now and here,
936 * start resume timing
937 */
938 unsigned long timeout = jiffies +
939 msecs_to_jiffies(USB_RESUME_TIMEOUT);
940
941 set_bit(wIndex, &bus_state->resuming_ports);
942 bus_state->resume_done[wIndex] = timeout;
943 mod_timer(&hcd->rh_timer, timeout);
944 usb_hcd_start_port_resume(&hcd->self, wIndex);
945 }
946 /* Has resume been signalled for USB_RESUME_TIME yet? */
947 } else if (time_after_eq(jiffies, bus_state->resume_done[wIndex])) {
948 int time_left;
949
950 xhci_dbg(xhci, "resume USB2 port %d-%d\n",
951 hcd->self.busnum, wIndex + 1);
952
953 bus_state->resume_done[wIndex] = 0;
954 clear_bit(wIndex, &bus_state->resuming_ports);
955
956 set_bit(wIndex, &bus_state->rexit_ports);
957
958 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
959 xhci_set_link_state(xhci, port, XDEV_U0);
960
961 spin_unlock_irqrestore(&xhci->lock, *flags);
962 time_left = wait_for_completion_timeout(
963 &bus_state->rexit_done[wIndex],
964 msecs_to_jiffies(XHCI_MAX_REXIT_TIMEOUT_MS));
965 spin_lock_irqsave(&xhci->lock, *flags);
966
967 if (time_left) {
968 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
969 wIndex + 1);
970 if (!slot_id) {
971 xhci_dbg(xhci, "slot_id is zero\n");
972 *status = 0xffffffff;
973 return -ENODEV;
974 }
975 xhci_ring_device(xhci, slot_id);
976 } else {
977 int port_status = readl(port->addr);
978
979 xhci_warn(xhci, "Port resume timed out, port %d-%d: 0x%x\n",
980 hcd->self.busnum, wIndex + 1, port_status);
981 *status |= USB_PORT_STAT_SUSPEND;
982 clear_bit(wIndex, &bus_state->rexit_ports);
983 }
984
985 usb_hcd_end_port_resume(&hcd->self, wIndex);
986 bus_state->port_c_suspend |= 1 << wIndex;
987 bus_state->suspended_ports &= ~(1 << wIndex);
988 } else {
989 /*
990 * The resume has been signaling for less than
991 * USB_RESUME_TIME. Report the port status as SUSPEND,
992 * let the usbcore check port status again and clear
993 * resume signaling later.
994 */
995 *status |= USB_PORT_STAT_SUSPEND;
996 }
997 return 0;
998 }
999
1000 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
1001 {
1002 u32 ext_stat = 0;
1003 int speed_id;
1004
1005 /* only support rx and tx lane counts of 1 in usb3.1 spec */
1006 speed_id = DEV_PORT_SPEED(raw_port_status);
1007 ext_stat |= speed_id; /* bits 3:0, RX speed id */
1008 ext_stat |= speed_id << 4; /* bits 7:4, TX speed id */
1009
1010 ext_stat |= PORT_RX_LANES(port_li) << 8; /* bits 11:8 Rx lane count */
1011 ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
1012
1013 return ext_stat;
1014 }
1015
1016 static void xhci_get_usb3_port_status(struct xhci_port *port, u32 *status,
1017 u32 portsc)
1018 {
1019 struct xhci_bus_state *bus_state;
1020 struct xhci_hcd *xhci;
1021 struct usb_hcd *hcd;
1022 u32 link_state;
1023 u32 portnum;
1024
1025 bus_state = &port->rhub->bus_state;
1026 xhci = hcd_to_xhci(port->rhub->hcd);
1027 hcd = port->rhub->hcd;
1028 link_state = portsc & PORT_PLS_MASK;
1029 portnum = port->hcd_portnum;
1030
1031 /* USB3 specific wPortChange bits
1032 *
1033 * Port link change with port in resume state should not be
1034 * reported to usbcore, as this is an internal state to be
1035 * handled by xhci driver. Reporting PLC to usbcore may
1036 * cause usbcore clearing PLC first and port change event
1037 * irq won't be generated.
1038 */
1039
1040 if (portsc & PORT_PLC && (link_state != XDEV_RESUME))
1041 *status |= USB_PORT_STAT_C_LINK_STATE << 16;
1042 if (portsc & PORT_WRC)
1043 *status |= USB_PORT_STAT_C_BH_RESET << 16;
1044 if (portsc & PORT_CEC)
1045 *status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
1046
1047 /* USB3 specific wPortStatus bits */
1048 if (portsc & PORT_POWER) {
1049 *status |= USB_SS_PORT_STAT_POWER;
1050 /* link state handling */
1051 if (link_state == XDEV_U0)
1052 bus_state->suspended_ports &= ~(1 << portnum);
1053 }
1054
1055 /* remote wake resume signaling complete */
1056 if (bus_state->port_remote_wakeup & (1 << portnum) &&
1057 link_state != XDEV_RESUME &&
1058 link_state != XDEV_RECOVERY) {
1059 bus_state->port_remote_wakeup &= ~(1 << portnum);
1060 usb_hcd_end_port_resume(&hcd->self, portnum);
1061 }
1062
1063 xhci_hub_report_usb3_link_state(xhci, status, portsc);
1064 xhci_del_comp_mod_timer(xhci, portsc, portnum);
1065 }
1066
1067 static void xhci_get_usb2_port_status(struct xhci_port *port, u32 *status,
1068 u32 portsc, unsigned long *flags)
1069 {
1070 struct xhci_bus_state *bus_state;
1071 u32 link_state;
1072 u32 portnum;
1073 int ret;
1074
1075 bus_state = &port->rhub->bus_state;
1076 link_state = portsc & PORT_PLS_MASK;
1077 portnum = port->hcd_portnum;
1078
1079 /* USB2 wPortStatus bits */
1080 if (portsc & PORT_POWER) {
1081 *status |= USB_PORT_STAT_POWER;
1082
1083 /* link state is only valid if port is powered */
1084 if (link_state == XDEV_U3)
1085 *status |= USB_PORT_STAT_SUSPEND;
1086 if (link_state == XDEV_U2)
1087 *status |= USB_PORT_STAT_L1;
1088 if (link_state == XDEV_U0) {
1089 bus_state->resume_done[portnum] = 0;
1090 clear_bit(portnum, &bus_state->resuming_ports);
1091 if (bus_state->suspended_ports & (1 << portnum)) {
1092 bus_state->suspended_ports &= ~(1 << portnum);
1093 bus_state->port_c_suspend |= 1 << portnum;
1094 }
1095 }
1096 if (link_state == XDEV_RESUME) {
1097 ret = xhci_handle_usb2_port_link_resume(port, status,
1098 portsc, flags);
1099 if (ret)
1100 return;
1101 }
1102 }
1103 }
1104
1105 /*
1106 * Converts a raw xHCI port status into the format that external USB 2.0 or USB
1107 * 3.0 hubs use.
1108 *
1109 * Possible side effects:
1110 * - Mark a port as being done with device resume,
1111 * and ring the endpoint doorbells.
1112 * - Stop the Synopsys redriver Compliance Mode polling.
1113 * - Drop and reacquire the xHCI lock, in order to wait for port resume.
1114 */
1115 static u32 xhci_get_port_status(struct usb_hcd *hcd,
1116 struct xhci_bus_state *bus_state,
1117 u16 wIndex, u32 raw_port_status,
1118 unsigned long *flags)
1119 __releases(&xhci->lock)
1120 __acquires(&xhci->lock)
1121 {
1122 u32 status = 0;
1123 struct xhci_hub *rhub;
1124 struct xhci_port *port;
1125
1126 rhub = xhci_get_rhub(hcd);
1127 port = rhub->ports[wIndex];
1128
1129 /* common wPortChange bits */
1130 if (raw_port_status & PORT_CSC)
1131 status |= USB_PORT_STAT_C_CONNECTION << 16;
1132 if (raw_port_status & PORT_PEC)
1133 status |= USB_PORT_STAT_C_ENABLE << 16;
1134 if ((raw_port_status & PORT_OCC))
1135 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
1136 if ((raw_port_status & PORT_RC))
1137 status |= USB_PORT_STAT_C_RESET << 16;
1138
1139 /* common wPortStatus bits */
1140 if (raw_port_status & PORT_CONNECT) {
1141 status |= USB_PORT_STAT_CONNECTION;
1142 status |= xhci_port_speed(raw_port_status);
1143 }
1144 if (raw_port_status & PORT_PE)
1145 status |= USB_PORT_STAT_ENABLE;
1146 if (raw_port_status & PORT_OC)
1147 status |= USB_PORT_STAT_OVERCURRENT;
1148 if (raw_port_status & PORT_RESET)
1149 status |= USB_PORT_STAT_RESET;
1150
1151 /* USB2 and USB3 specific bits, including Port Link State */
1152 if (hcd->speed >= HCD_USB3)
1153 xhci_get_usb3_port_status(port, &status, raw_port_status);
1154 else
1155 xhci_get_usb2_port_status(port, &status, raw_port_status,
1156 flags);
1157 /*
1158 * Clear stale usb2 resume signalling variables in case port changed
1159 * state during resume signalling. For example on error
1160 */
1161 if ((bus_state->resume_done[wIndex] ||
1162 test_bit(wIndex, &bus_state->resuming_ports)) &&
1163 (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
1164 (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
1165 bus_state->resume_done[wIndex] = 0;
1166 clear_bit(wIndex, &bus_state->resuming_ports);
1167 usb_hcd_end_port_resume(&hcd->self, wIndex);
1168 }
1169
1170 if (bus_state->port_c_suspend & (1 << wIndex))
1171 status |= USB_PORT_STAT_C_SUSPEND << 16;
1172
1173 return status;
1174 }
1175
1176 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1177 u16 wIndex, char *buf, u16 wLength)
1178 {
1179 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1180 int max_ports;
1181 unsigned long flags;
1182 u32 temp, status;
1183 int retval = 0;
1184 int slot_id;
1185 struct xhci_bus_state *bus_state;
1186 u16 link_state = 0;
1187 u16 wake_mask = 0;
1188 u16 timeout = 0;
1189 u16 test_mode = 0;
1190 struct xhci_hub *rhub;
1191 struct xhci_port **ports;
1192
1193 rhub = xhci_get_rhub(hcd);
1194 ports = rhub->ports;
1195 max_ports = rhub->num_ports;
1196 bus_state = &rhub->bus_state;
1197
1198 spin_lock_irqsave(&xhci->lock, flags);
1199 switch (typeReq) {
1200 case GetHubStatus:
1201 /* No power source, over-current reported per port */
1202 memset(buf, 0, 4);
1203 break;
1204 case GetHubDescriptor:
1205 /* Check to make sure userspace is asking for the USB 3.0 hub
1206 * descriptor for the USB 3.0 roothub. If not, we stall the
1207 * endpoint, like external hubs do.
1208 */
1209 if (hcd->speed >= HCD_USB3 &&
1210 (wLength < USB_DT_SS_HUB_SIZE ||
1211 wValue != (USB_DT_SS_HUB << 8))) {
1212 xhci_dbg(xhci, "Wrong hub descriptor type for "
1213 "USB 3.0 roothub.\n");
1214 goto error;
1215 }
1216 xhci_hub_descriptor(hcd, xhci,
1217 (struct usb_hub_descriptor *) buf);
1218 break;
1219 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
1220 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
1221 goto error;
1222
1223 if (hcd->speed < HCD_USB3)
1224 goto error;
1225
1226 retval = xhci_create_usb3x_bos_desc(xhci, buf, wLength);
1227 spin_unlock_irqrestore(&xhci->lock, flags);
1228 return retval;
1229 case GetPortStatus:
1230 if (!wIndex || wIndex > max_ports)
1231 goto error;
1232 wIndex--;
1233 temp = readl(ports[wIndex]->addr);
1234 if (temp == ~(u32)0) {
1235 xhci_hc_died(xhci);
1236 retval = -ENODEV;
1237 break;
1238 }
1239 trace_xhci_get_port_status(wIndex, temp);
1240 status = xhci_get_port_status(hcd, bus_state, wIndex, temp,
1241 &flags);
1242 if (status == 0xffffffff)
1243 goto error;
1244
1245 xhci_dbg(xhci, "Get port status %d-%d read: 0x%x, return 0x%x",
1246 hcd->self.busnum, wIndex + 1, temp, status);
1247
1248 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1249 /* if USB 3.1 extended port status return additional 4 bytes */
1250 if (wValue == 0x02) {
1251 u32 port_li;
1252
1253 if (hcd->speed < HCD_USB31 || wLength != 8) {
1254 xhci_err(xhci, "get ext port status invalid parameter\n");
1255 retval = -EINVAL;
1256 break;
1257 }
1258 port_li = readl(ports[wIndex]->addr + PORTLI);
1259 status = xhci_get_ext_port_status(temp, port_li);
1260 put_unaligned_le32(status, &buf[4]);
1261 }
1262 break;
1263 case SetPortFeature:
1264 if (wValue == USB_PORT_FEAT_LINK_STATE)
1265 link_state = (wIndex & 0xff00) >> 3;
1266 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
1267 wake_mask = wIndex & 0xff00;
1268 if (wValue == USB_PORT_FEAT_TEST)
1269 test_mode = (wIndex & 0xff00) >> 8;
1270 /* The MSB of wIndex is the U1/U2 timeout */
1271 timeout = (wIndex & 0xff00) >> 8;
1272 wIndex &= 0xff;
1273 if (!wIndex || wIndex > max_ports)
1274 goto error;
1275 wIndex--;
1276 temp = readl(ports[wIndex]->addr);
1277 if (temp == ~(u32)0) {
1278 xhci_hc_died(xhci);
1279 retval = -ENODEV;
1280 break;
1281 }
1282 temp = xhci_port_state_to_neutral(temp);
1283 /* FIXME: What new port features do we need to support? */
1284 switch (wValue) {
1285 case USB_PORT_FEAT_SUSPEND:
1286 temp = readl(ports[wIndex]->addr);
1287 if ((temp & PORT_PLS_MASK) != XDEV_U0) {
1288 /* Resume the port to U0 first */
1289 xhci_set_link_state(xhci, ports[wIndex],
1290 XDEV_U0);
1291 spin_unlock_irqrestore(&xhci->lock, flags);
1292 msleep(10);
1293 spin_lock_irqsave(&xhci->lock, flags);
1294 }
1295 /* In spec software should not attempt to suspend
1296 * a port unless the port reports that it is in the
1297 * enabled (PED = ‘1’,PLS < ‘3’) state.
1298 */
1299 temp = readl(ports[wIndex]->addr);
1300 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1301 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
1302 xhci_warn(xhci, "USB core suspending port %d-%d not in U0/U1/U2\n",
1303 hcd->self.busnum, wIndex + 1);
1304 goto error;
1305 }
1306
1307 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1308 wIndex + 1);
1309 if (!slot_id) {
1310 xhci_warn(xhci, "slot_id is zero\n");
1311 goto error;
1312 }
1313 /* unlock to execute stop endpoint commands */
1314 spin_unlock_irqrestore(&xhci->lock, flags);
1315 xhci_stop_device(xhci, slot_id, 1);
1316 spin_lock_irqsave(&xhci->lock, flags);
1317
1318 xhci_set_link_state(xhci, ports[wIndex], XDEV_U3);
1319
1320 spin_unlock_irqrestore(&xhci->lock, flags);
1321 msleep(10); /* wait device to enter */
1322 spin_lock_irqsave(&xhci->lock, flags);
1323
1324 temp = readl(ports[wIndex]->addr);
1325 bus_state->suspended_ports |= 1 << wIndex;
1326 break;
1327 case USB_PORT_FEAT_LINK_STATE:
1328 temp = readl(ports[wIndex]->addr);
1329 /* Disable port */
1330 if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1331 xhci_dbg(xhci, "Disable port %d-%d\n",
1332 hcd->self.busnum, wIndex + 1);
1333 temp = xhci_port_state_to_neutral(temp);
1334 /*
1335 * Clear all change bits, so that we get a new
1336 * connection event.
1337 */
1338 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1339 PORT_OCC | PORT_RC | PORT_PLC |
1340 PORT_CEC;
1341 writel(temp | PORT_PE, ports[wIndex]->addr);
1342 temp = readl(ports[wIndex]->addr);
1343 break;
1344 }
1345
1346 /* Put link in RxDetect (enable port) */
1347 if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1348 xhci_dbg(xhci, "Enable port %d-%d\n",
1349 hcd->self.busnum, wIndex + 1);
1350 xhci_set_link_state(xhci, ports[wIndex],
1351 link_state);
1352 temp = readl(ports[wIndex]->addr);
1353 break;
1354 }
1355
1356 /*
1357 * For xHCI 1.1 according to section 4.19.1.2.4.1 a
1358 * root hub port's transition to compliance mode upon
1359 * detecting LFPS timeout may be controlled by an
1360 * Compliance Transition Enabled (CTE) flag (not
1361 * software visible). This flag is set by writing 0xA
1362 * to PORTSC PLS field which will allow transition to
1363 * compliance mode the next time LFPS timeout is
1364 * encountered. A warm reset will clear it.
1365 *
1366 * The CTE flag is only supported if the HCCPARAMS2 CTC
1367 * flag is set, otherwise, the compliance substate is
1368 * automatically entered as on 1.0 and prior.
1369 */
1370 if (link_state == USB_SS_PORT_LS_COMP_MOD) {
1371 if (!HCC2_CTC(xhci->hcc_params2)) {
1372 xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n");
1373 break;
1374 }
1375
1376 if ((temp & PORT_CONNECT)) {
1377 xhci_warn(xhci, "Can't set compliance mode when port is connected\n");
1378 goto error;
1379 }
1380
1381 xhci_dbg(xhci, "Enable compliance mode transition for port %d-%d\n",
1382 hcd->self.busnum, wIndex + 1);
1383 xhci_set_link_state(xhci, ports[wIndex],
1384 link_state);
1385
1386 temp = readl(ports[wIndex]->addr);
1387 break;
1388 }
1389 /* Port must be enabled */
1390 if (!(temp & PORT_PE)) {
1391 retval = -ENODEV;
1392 break;
1393 }
1394 /* Can't set port link state above '3' (U3) */
1395 if (link_state > USB_SS_PORT_LS_U3) {
1396 xhci_warn(xhci, "Cannot set port %d-%d link state %d\n",
1397 hcd->self.busnum, wIndex + 1,
1398 link_state);
1399 goto error;
1400 }
1401
1402 /*
1403 * set link to U0, steps depend on current link state.
1404 * U3: set link to U0 and wait for u3exit completion.
1405 * U1/U2: no PLC complete event, only set link to U0.
1406 * Resume/Recovery: device initiated U0, only wait for
1407 * completion
1408 */
1409 if (link_state == USB_SS_PORT_LS_U0) {
1410 u32 pls = temp & PORT_PLS_MASK;
1411 bool wait_u0 = false;
1412
1413 /* already in U0 */
1414 if (pls == XDEV_U0)
1415 break;
1416 if (pls == XDEV_U3 ||
1417 pls == XDEV_RESUME ||
1418 pls == XDEV_RECOVERY) {
1419 wait_u0 = true;
1420 reinit_completion(&bus_state->u3exit_done[wIndex]);
1421 }
1422 if (pls <= XDEV_U3) /* U1, U2, U3 */
1423 xhci_set_link_state(xhci, ports[wIndex],
1424 USB_SS_PORT_LS_U0);
1425 if (!wait_u0) {
1426 if (pls > XDEV_U3)
1427 goto error;
1428 break;
1429 }
1430 spin_unlock_irqrestore(&xhci->lock, flags);
1431 if (!wait_for_completion_timeout(&bus_state->u3exit_done[wIndex],
1432 msecs_to_jiffies(100)))
1433 xhci_dbg(xhci, "missing U0 port change event for port %d-%d\n",
1434 hcd->self.busnum, wIndex + 1);
1435 spin_lock_irqsave(&xhci->lock, flags);
1436 temp = readl(ports[wIndex]->addr);
1437 break;
1438 }
1439
1440 if (link_state == USB_SS_PORT_LS_U3) {
1441 int retries = 16;
1442 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1443 wIndex + 1);
1444 if (slot_id) {
1445 /* unlock to execute stop endpoint
1446 * commands */
1447 spin_unlock_irqrestore(&xhci->lock,
1448 flags);
1449 xhci_stop_device(xhci, slot_id, 1);
1450 spin_lock_irqsave(&xhci->lock, flags);
1451 }
1452 xhci_set_link_state(xhci, ports[wIndex], USB_SS_PORT_LS_U3);
1453 spin_unlock_irqrestore(&xhci->lock, flags);
1454 while (retries--) {
1455 usleep_range(4000, 8000);
1456 temp = readl(ports[wIndex]->addr);
1457 if ((temp & PORT_PLS_MASK) == XDEV_U3)
1458 break;
1459 }
1460 spin_lock_irqsave(&xhci->lock, flags);
1461 temp = readl(ports[wIndex]->addr);
1462 bus_state->suspended_ports |= 1 << wIndex;
1463 }
1464 break;
1465 case USB_PORT_FEAT_POWER:
1466 /*
1467 * Turn on ports, even if there isn't per-port switching.
1468 * HC will report connect events even before this is set.
1469 * However, hub_wq will ignore the roothub events until
1470 * the roothub is registered.
1471 */
1472 xhci_set_port_power(xhci, hcd, wIndex, true, &flags);
1473 break;
1474 case USB_PORT_FEAT_RESET:
1475 temp = (temp | PORT_RESET);
1476 writel(temp, ports[wIndex]->addr);
1477
1478 temp = readl(ports[wIndex]->addr);
1479 xhci_dbg(xhci, "set port reset, actual port %d-%d status = 0x%x\n",
1480 hcd->self.busnum, wIndex + 1, temp);
1481 break;
1482 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1483 xhci_set_remote_wake_mask(xhci, ports[wIndex],
1484 wake_mask);
1485 temp = readl(ports[wIndex]->addr);
1486 xhci_dbg(xhci, "set port remote wake mask, actual port %d-%d status = 0x%x\n",
1487 hcd->self.busnum, wIndex + 1, temp);
1488 break;
1489 case USB_PORT_FEAT_BH_PORT_RESET:
1490 temp |= PORT_WR;
1491 writel(temp, ports[wIndex]->addr);
1492 temp = readl(ports[wIndex]->addr);
1493 break;
1494 case USB_PORT_FEAT_U1_TIMEOUT:
1495 if (hcd->speed < HCD_USB3)
1496 goto error;
1497 temp = readl(ports[wIndex]->addr + PORTPMSC);
1498 temp &= ~PORT_U1_TIMEOUT_MASK;
1499 temp |= PORT_U1_TIMEOUT(timeout);
1500 writel(temp, ports[wIndex]->addr + PORTPMSC);
1501 break;
1502 case USB_PORT_FEAT_U2_TIMEOUT:
1503 if (hcd->speed < HCD_USB3)
1504 goto error;
1505 temp = readl(ports[wIndex]->addr + PORTPMSC);
1506 temp &= ~PORT_U2_TIMEOUT_MASK;
1507 temp |= PORT_U2_TIMEOUT(timeout);
1508 writel(temp, ports[wIndex]->addr + PORTPMSC);
1509 break;
1510 case USB_PORT_FEAT_TEST:
1511 /* 4.19.6 Port Test Modes (USB2 Test Mode) */
1512 if (hcd->speed != HCD_USB2)
1513 goto error;
1514 if (test_mode > USB_TEST_FORCE_ENABLE ||
1515 test_mode < USB_TEST_J)
1516 goto error;
1517 retval = xhci_enter_test_mode(xhci, test_mode, wIndex,
1518 &flags);
1519 break;
1520 default:
1521 goto error;
1522 }
1523 /* unblock any posted writes */
1524 temp = readl(ports[wIndex]->addr);
1525 break;
1526 case ClearPortFeature:
1527 if (!wIndex || wIndex > max_ports)
1528 goto error;
1529 wIndex--;
1530 temp = readl(ports[wIndex]->addr);
1531 if (temp == ~(u32)0) {
1532 xhci_hc_died(xhci);
1533 retval = -ENODEV;
1534 break;
1535 }
1536 /* FIXME: What new port features do we need to support? */
1537 temp = xhci_port_state_to_neutral(temp);
1538 switch (wValue) {
1539 case USB_PORT_FEAT_SUSPEND:
1540 temp = readl(ports[wIndex]->addr);
1541 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1542 xhci_dbg(xhci, "PORTSC %04x\n", temp);
1543 if (temp & PORT_RESET)
1544 goto error;
1545 if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1546 if ((temp & PORT_PE) == 0)
1547 goto error;
1548
1549 set_bit(wIndex, &bus_state->resuming_ports);
1550 usb_hcd_start_port_resume(&hcd->self, wIndex);
1551 xhci_set_link_state(xhci, ports[wIndex],
1552 XDEV_RESUME);
1553 spin_unlock_irqrestore(&xhci->lock, flags);
1554 msleep(USB_RESUME_TIMEOUT);
1555 spin_lock_irqsave(&xhci->lock, flags);
1556 xhci_set_link_state(xhci, ports[wIndex],
1557 XDEV_U0);
1558 clear_bit(wIndex, &bus_state->resuming_ports);
1559 usb_hcd_end_port_resume(&hcd->self, wIndex);
1560 }
1561 bus_state->port_c_suspend |= 1 << wIndex;
1562
1563 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1564 wIndex + 1);
1565 if (!slot_id) {
1566 xhci_dbg(xhci, "slot_id is zero\n");
1567 goto error;
1568 }
1569 xhci_ring_device(xhci, slot_id);
1570 break;
1571 case USB_PORT_FEAT_C_SUSPEND:
1572 bus_state->port_c_suspend &= ~(1 << wIndex);
1573 fallthrough;
1574 case USB_PORT_FEAT_C_RESET:
1575 case USB_PORT_FEAT_C_BH_PORT_RESET:
1576 case USB_PORT_FEAT_C_CONNECTION:
1577 case USB_PORT_FEAT_C_OVER_CURRENT:
1578 case USB_PORT_FEAT_C_ENABLE:
1579 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1580 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1581 xhci_clear_port_change_bit(xhci, wValue, wIndex,
1582 ports[wIndex]->addr, temp);
1583 break;
1584 case USB_PORT_FEAT_ENABLE:
1585 xhci_disable_port(hcd, xhci, wIndex,
1586 ports[wIndex]->addr, temp);
1587 break;
1588 case USB_PORT_FEAT_POWER:
1589 xhci_set_port_power(xhci, hcd, wIndex, false, &flags);
1590 break;
1591 case USB_PORT_FEAT_TEST:
1592 retval = xhci_exit_test_mode(xhci);
1593 break;
1594 default:
1595 goto error;
1596 }
1597 break;
1598 default:
1599 error:
1600 /* "stall" on error */
1601 retval = -EPIPE;
1602 }
1603 spin_unlock_irqrestore(&xhci->lock, flags);
1604 return retval;
1605 }
1606
1607 /*
1608 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1609 * Ports are 0-indexed from the HCD point of view,
1610 * and 1-indexed from the USB core pointer of view.
1611 *
1612 * Note that the status change bits will be cleared as soon as a port status
1613 * change event is generated, so we use the saved status from that event.
1614 */
1615 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1616 {
1617 unsigned long flags;
1618 u32 temp, status;
1619 u32 mask;
1620 int i, retval;
1621 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1622 int max_ports;
1623 struct xhci_bus_state *bus_state;
1624 bool reset_change = false;
1625 struct xhci_hub *rhub;
1626 struct xhci_port **ports;
1627
1628 rhub = xhci_get_rhub(hcd);
1629 ports = rhub->ports;
1630 max_ports = rhub->num_ports;
1631 bus_state = &rhub->bus_state;
1632
1633 /* Initial status is no changes */
1634 retval = (max_ports + 8) / 8;
1635 memset(buf, 0, retval);
1636
1637 /*
1638 * Inform the usbcore about resume-in-progress by returning
1639 * a non-zero value even if there are no status changes.
1640 */
1641 status = bus_state->resuming_ports;
1642
1643 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1644
1645 spin_lock_irqsave(&xhci->lock, flags);
1646 /* For each port, did anything change? If so, set that bit in buf. */
1647 for (i = 0; i < max_ports; i++) {
1648 temp = readl(ports[i]->addr);
1649 if (temp == ~(u32)0) {
1650 xhci_hc_died(xhci);
1651 retval = -ENODEV;
1652 break;
1653 }
1654 trace_xhci_hub_status_data(i, temp);
1655
1656 if ((temp & mask) != 0 ||
1657 (bus_state->port_c_suspend & 1 << i) ||
1658 (bus_state->resume_done[i] && time_after_eq(
1659 jiffies, bus_state->resume_done[i]))) {
1660 buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1661 status = 1;
1662 }
1663 if ((temp & PORT_RC))
1664 reset_change = true;
1665 if (temp & PORT_OC)
1666 status = 1;
1667 }
1668 if (!status && !reset_change) {
1669 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1670 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1671 }
1672 spin_unlock_irqrestore(&xhci->lock, flags);
1673 return status ? retval : 0;
1674 }
1675
1676 #ifdef CONFIG_PM
1677
1678 int xhci_bus_suspend(struct usb_hcd *hcd)
1679 {
1680 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1681 int max_ports, port_index;
1682 struct xhci_bus_state *bus_state;
1683 unsigned long flags;
1684 struct xhci_hub *rhub;
1685 struct xhci_port **ports;
1686 u32 portsc_buf[USB_MAXCHILDREN];
1687 bool wake_enabled;
1688
1689 rhub = xhci_get_rhub(hcd);
1690 ports = rhub->ports;
1691 max_ports = rhub->num_ports;
1692 bus_state = &rhub->bus_state;
1693 wake_enabled = hcd->self.root_hub->do_remote_wakeup;
1694
1695 spin_lock_irqsave(&xhci->lock, flags);
1696
1697 if (wake_enabled) {
1698 if (bus_state->resuming_ports || /* USB2 */
1699 bus_state->port_remote_wakeup) { /* USB3 */
1700 spin_unlock_irqrestore(&xhci->lock, flags);
1701 xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1702 return -EBUSY;
1703 }
1704 }
1705 /*
1706 * Prepare ports for suspend, but don't write anything before all ports
1707 * are checked and we know bus suspend can proceed
1708 */
1709 bus_state->bus_suspended = 0;
1710 port_index = max_ports;
1711 while (port_index--) {
1712 u32 t1, t2;
1713 int retries = 10;
1714 retry:
1715 t1 = readl(ports[port_index]->addr);
1716 t2 = xhci_port_state_to_neutral(t1);
1717 portsc_buf[port_index] = 0;
1718
1719 /*
1720 * Give a USB3 port in link training time to finish, but don't
1721 * prevent suspend as port might be stuck
1722 */
1723 if ((hcd->speed >= HCD_USB3) && retries-- &&
1724 (t1 & PORT_PLS_MASK) == XDEV_POLLING) {
1725 spin_unlock_irqrestore(&xhci->lock, flags);
1726 msleep(XHCI_PORT_POLLING_LFPS_TIME);
1727 spin_lock_irqsave(&xhci->lock, flags);
1728 xhci_dbg(xhci, "port %d-%d polling in bus suspend, waiting\n",
1729 hcd->self.busnum, port_index + 1);
1730 goto retry;
1731 }
1732 /* bail out if port detected a over-current condition */
1733 if (t1 & PORT_OC) {
1734 bus_state->bus_suspended = 0;
1735 spin_unlock_irqrestore(&xhci->lock, flags);
1736 xhci_dbg(xhci, "Bus suspend bailout, port over-current detected\n");
1737 return -EBUSY;
1738 }
1739 /* suspend ports in U0, or bail out for new connect changes */
1740 if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) {
1741 if ((t1 & PORT_CSC) && wake_enabled) {
1742 bus_state->bus_suspended = 0;
1743 spin_unlock_irqrestore(&xhci->lock, flags);
1744 xhci_dbg(xhci, "Bus suspend bailout, port connect change\n");
1745 return -EBUSY;
1746 }
1747 xhci_dbg(xhci, "port %d-%d not suspended\n",
1748 hcd->self.busnum, port_index + 1);
1749 t2 &= ~PORT_PLS_MASK;
1750 t2 |= PORT_LINK_STROBE | XDEV_U3;
1751 set_bit(port_index, &bus_state->bus_suspended);
1752 }
1753 /* USB core sets remote wake mask for USB 3.0 hubs,
1754 * including the USB 3.0 roothub, but only if CONFIG_PM
1755 * is enabled, so also enable remote wake here.
1756 */
1757 if (wake_enabled) {
1758 if (t1 & PORT_CONNECT) {
1759 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1760 t2 &= ~PORT_WKCONN_E;
1761 } else {
1762 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1763 t2 &= ~PORT_WKDISC_E;
1764 }
1765
1766 if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) &&
1767 (hcd->speed < HCD_USB3)) {
1768 if (usb_amd_pt_check_port(hcd->self.controller,
1769 port_index))
1770 t2 &= ~PORT_WAKE_BITS;
1771 }
1772 } else
1773 t2 &= ~PORT_WAKE_BITS;
1774
1775 t1 = xhci_port_state_to_neutral(t1);
1776 if (t1 != t2)
1777 portsc_buf[port_index] = t2;
1778 }
1779
1780 /* write port settings, stopping and suspending ports if needed */
1781 port_index = max_ports;
1782 while (port_index--) {
1783 if (!portsc_buf[port_index])
1784 continue;
1785 if (test_bit(port_index, &bus_state->bus_suspended)) {
1786 int slot_id;
1787
1788 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1789 port_index + 1);
1790 if (slot_id) {
1791 spin_unlock_irqrestore(&xhci->lock, flags);
1792 xhci_stop_device(xhci, slot_id, 1);
1793 spin_lock_irqsave(&xhci->lock, flags);
1794 }
1795 }
1796 writel(portsc_buf[port_index], ports[port_index]->addr);
1797 }
1798 hcd->state = HC_STATE_SUSPENDED;
1799 bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1800 spin_unlock_irqrestore(&xhci->lock, flags);
1801
1802 if (bus_state->bus_suspended)
1803 usleep_range(5000, 10000);
1804
1805 return 0;
1806 }
1807
1808 /*
1809 * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1810 * warm reset a USB3 device stuck in polling or compliance mode after resume.
1811 * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1812 */
1813 static bool xhci_port_missing_cas_quirk(struct xhci_port *port)
1814 {
1815 u32 portsc;
1816
1817 portsc = readl(port->addr);
1818
1819 /* if any of these are set we are not stuck */
1820 if (portsc & (PORT_CONNECT | PORT_CAS))
1821 return false;
1822
1823 if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1824 ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1825 return false;
1826
1827 /* clear wakeup/change bits, and do a warm port reset */
1828 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1829 portsc |= PORT_WR;
1830 writel(portsc, port->addr);
1831 /* flush write */
1832 readl(port->addr);
1833 return true;
1834 }
1835
1836 int xhci_bus_resume(struct usb_hcd *hcd)
1837 {
1838 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1839 struct xhci_bus_state *bus_state;
1840 unsigned long flags;
1841 int max_ports, port_index;
1842 int slot_id;
1843 int sret;
1844 u32 next_state;
1845 u32 temp, portsc;
1846 struct xhci_hub *rhub;
1847 struct xhci_port **ports;
1848
1849 rhub = xhci_get_rhub(hcd);
1850 ports = rhub->ports;
1851 max_ports = rhub->num_ports;
1852 bus_state = &rhub->bus_state;
1853
1854 if (time_before(jiffies, bus_state->next_statechange))
1855 msleep(5);
1856
1857 spin_lock_irqsave(&xhci->lock, flags);
1858 if (!HCD_HW_ACCESSIBLE(hcd)) {
1859 spin_unlock_irqrestore(&xhci->lock, flags);
1860 return -ESHUTDOWN;
1861 }
1862
1863 /* delay the irqs */
1864 temp = readl(&xhci->op_regs->command);
1865 temp &= ~CMD_EIE;
1866 writel(temp, &xhci->op_regs->command);
1867
1868 /* bus specific resume for ports we suspended at bus_suspend */
1869 if (hcd->speed >= HCD_USB3)
1870 next_state = XDEV_U0;
1871 else
1872 next_state = XDEV_RESUME;
1873
1874 port_index = max_ports;
1875 while (port_index--) {
1876 portsc = readl(ports[port_index]->addr);
1877
1878 /* warm reset CAS limited ports stuck in polling/compliance */
1879 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1880 (hcd->speed >= HCD_USB3) &&
1881 xhci_port_missing_cas_quirk(ports[port_index])) {
1882 xhci_dbg(xhci, "reset stuck port %d-%d\n",
1883 hcd->self.busnum, port_index + 1);
1884 clear_bit(port_index, &bus_state->bus_suspended);
1885 continue;
1886 }
1887 /* resume if we suspended the link, and it is still suspended */
1888 if (test_bit(port_index, &bus_state->bus_suspended))
1889 switch (portsc & PORT_PLS_MASK) {
1890 case XDEV_U3:
1891 portsc = xhci_port_state_to_neutral(portsc);
1892 portsc &= ~PORT_PLS_MASK;
1893 portsc |= PORT_LINK_STROBE | next_state;
1894 break;
1895 case XDEV_RESUME:
1896 /* resume already initiated */
1897 break;
1898 default:
1899 /* not in a resumeable state, ignore it */
1900 clear_bit(port_index,
1901 &bus_state->bus_suspended);
1902 break;
1903 }
1904 /* disable wake for all ports, write new link state if needed */
1905 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1906 writel(portsc, ports[port_index]->addr);
1907 }
1908
1909 /* USB2 specific resume signaling delay and U0 link state transition */
1910 if (hcd->speed < HCD_USB3) {
1911 if (bus_state->bus_suspended) {
1912 spin_unlock_irqrestore(&xhci->lock, flags);
1913 msleep(USB_RESUME_TIMEOUT);
1914 spin_lock_irqsave(&xhci->lock, flags);
1915 }
1916 for_each_set_bit(port_index, &bus_state->bus_suspended,
1917 BITS_PER_LONG) {
1918 /* Clear PLC to poll it later for U0 transition */
1919 xhci_test_and_clear_bit(xhci, ports[port_index],
1920 PORT_PLC);
1921 xhci_set_link_state(xhci, ports[port_index], XDEV_U0);
1922 }
1923 }
1924
1925 /* poll for U0 link state complete, both USB2 and USB3 */
1926 for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) {
1927 sret = xhci_handshake(ports[port_index]->addr, PORT_PLC,
1928 PORT_PLC, 10 * 1000);
1929 if (sret) {
1930 xhci_warn(xhci, "port %d-%d resume PLC timeout\n",
1931 hcd->self.busnum, port_index + 1);
1932 continue;
1933 }
1934 xhci_test_and_clear_bit(xhci, ports[port_index], PORT_PLC);
1935 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1936 if (slot_id)
1937 xhci_ring_device(xhci, slot_id);
1938 }
1939 (void) readl(&xhci->op_regs->command);
1940
1941 bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1942 /* re-enable irqs */
1943 temp = readl(&xhci->op_regs->command);
1944 temp |= CMD_EIE;
1945 writel(temp, &xhci->op_regs->command);
1946 temp = readl(&xhci->op_regs->command);
1947
1948 spin_unlock_irqrestore(&xhci->lock, flags);
1949 return 0;
1950 }
1951
1952 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd)
1953 {
1954 struct xhci_hub *rhub = xhci_get_rhub(hcd);
1955
1956 /* USB3 port wakeups are reported via usb_wakeup_notification() */
1957 return rhub->bus_state.resuming_ports; /* USB2 ports only */
1958 }
1959
1960 #endif /* CONFIG_PM */
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