1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
11 #include <linux/usb.h>
12 #include <linux/pci.h>
13 #include <linux/slab.h>
14 #include <linux/dmapool.h>
15 #include <linux/dma-mapping.h>
18 #include "xhci-trace.h"
19 #include "xhci-debugfs.h"
22 * Allocates a generic ring segment from the ring pool, sets the dma address,
23 * initializes the segment to zero, and sets the private next pointer to NULL.
26 * "All components of all Command and Transfer TRBs shall be initialized to '0'"
28 static struct xhci_segment
*xhci_segment_alloc(struct xhci_hcd
*xhci
,
29 unsigned int cycle_state
,
30 unsigned int max_packet
,
33 struct xhci_segment
*seg
;
37 seg
= kzalloc(sizeof *seg
, flags
);
41 seg
->trbs
= dma_pool_zalloc(xhci
->segment_pool
, flags
, &dma
);
48 seg
->bounce_buf
= kzalloc(max_packet
, flags
);
49 if (!seg
->bounce_buf
) {
50 dma_pool_free(xhci
->segment_pool
, seg
->trbs
, dma
);
55 /* If the cycle state is 0, set the cycle bit to 1 for all the TRBs */
56 if (cycle_state
== 0) {
57 for (i
= 0; i
< TRBS_PER_SEGMENT
; i
++)
58 seg
->trbs
[i
].link
.control
|= cpu_to_le32(TRB_CYCLE
);
66 static void xhci_segment_free(struct xhci_hcd
*xhci
, struct xhci_segment
*seg
)
69 dma_pool_free(xhci
->segment_pool
, seg
->trbs
, seg
->dma
);
72 kfree(seg
->bounce_buf
);
76 static void xhci_free_segments_for_ring(struct xhci_hcd
*xhci
,
77 struct xhci_segment
*first
)
79 struct xhci_segment
*seg
;
82 while (seg
!= first
) {
83 struct xhci_segment
*next
= seg
->next
;
84 xhci_segment_free(xhci
, seg
);
87 xhci_segment_free(xhci
, first
);
91 * Make the prev segment point to the next segment.
93 * Change the last TRB in the prev segment to be a Link TRB which points to the
94 * DMA address of the next segment. The caller needs to set any Link TRB
95 * related flags, such as End TRB, Toggle Cycle, and no snoop.
97 static void xhci_link_segments(struct xhci_hcd
*xhci
, struct xhci_segment
*prev
,
98 struct xhci_segment
*next
, enum xhci_ring_type type
)
105 if (type
!= TYPE_EVENT
) {
106 prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.segment_ptr
=
107 cpu_to_le64(next
->dma
);
109 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
110 val
= le32_to_cpu(prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
);
111 val
&= ~TRB_TYPE_BITMASK
;
112 val
|= TRB_TYPE(TRB_LINK
);
113 /* Always set the chain bit with 0.95 hardware */
114 /* Set chain bit for isoc rings on AMD 0.96 host */
115 if (xhci_link_trb_quirk(xhci
) ||
116 (type
== TYPE_ISOC
&&
117 (xhci
->quirks
& XHCI_AMD_0x96_HOST
)))
119 prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
= cpu_to_le32(val
);
124 * Link the ring to the new segments.
125 * Set Toggle Cycle for the new ring if needed.
127 static void xhci_link_rings(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
128 struct xhci_segment
*first
, struct xhci_segment
*last
,
129 unsigned int num_segs
)
131 struct xhci_segment
*next
;
133 if (!ring
|| !first
|| !last
)
136 next
= ring
->enq_seg
->next
;
137 xhci_link_segments(xhci
, ring
->enq_seg
, first
, ring
->type
);
138 xhci_link_segments(xhci
, last
, next
, ring
->type
);
139 ring
->num_segs
+= num_segs
;
140 ring
->num_trbs_free
+= (TRBS_PER_SEGMENT
- 1) * num_segs
;
142 if (ring
->type
!= TYPE_EVENT
&& ring
->enq_seg
== ring
->last_seg
) {
143 ring
->last_seg
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
144 &= ~cpu_to_le32(LINK_TOGGLE
);
145 last
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
146 |= cpu_to_le32(LINK_TOGGLE
);
147 ring
->last_seg
= last
;
152 * We need a radix tree for mapping physical addresses of TRBs to which stream
153 * ID they belong to. We need to do this because the host controller won't tell
154 * us which stream ring the TRB came from. We could store the stream ID in an
155 * event data TRB, but that doesn't help us for the cancellation case, since the
156 * endpoint may stop before it reaches that event data TRB.
158 * The radix tree maps the upper portion of the TRB DMA address to a ring
159 * segment that has the same upper portion of DMA addresses. For example, say I
160 * have segments of size 1KB, that are always 1KB aligned. A segment may
161 * start at 0x10c91000 and end at 0x10c913f0. If I use the upper 10 bits, the
162 * key to the stream ID is 0x43244. I can use the DMA address of the TRB to
163 * pass the radix tree a key to get the right stream ID:
165 * 0x10c90fff >> 10 = 0x43243
166 * 0x10c912c0 >> 10 = 0x43244
167 * 0x10c91400 >> 10 = 0x43245
169 * Obviously, only those TRBs with DMA addresses that are within the segment
170 * will make the radix tree return the stream ID for that ring.
172 * Caveats for the radix tree:
174 * The radix tree uses an unsigned long as a key pair. On 32-bit systems, an
175 * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
176 * 64-bits. Since we only request 32-bit DMA addresses, we can use that as the
177 * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
178 * PCI DMA addresses on a 64-bit system). There might be a problem on 32-bit
179 * extended systems (where the DMA address can be bigger than 32-bits),
180 * if we allow the PCI dma mask to be bigger than 32-bits. So don't do that.
182 static int xhci_insert_segment_mapping(struct radix_tree_root
*trb_address_map
,
183 struct xhci_ring
*ring
,
184 struct xhci_segment
*seg
,
190 key
= (unsigned long)(seg
->dma
>> TRB_SEGMENT_SHIFT
);
191 /* Skip any segments that were already added. */
192 if (radix_tree_lookup(trb_address_map
, key
))
195 ret
= radix_tree_maybe_preload(mem_flags
);
198 ret
= radix_tree_insert(trb_address_map
,
200 radix_tree_preload_end();
204 static void xhci_remove_segment_mapping(struct radix_tree_root
*trb_address_map
,
205 struct xhci_segment
*seg
)
209 key
= (unsigned long)(seg
->dma
>> TRB_SEGMENT_SHIFT
);
210 if (radix_tree_lookup(trb_address_map
, key
))
211 radix_tree_delete(trb_address_map
, key
);
214 static int xhci_update_stream_segment_mapping(
215 struct radix_tree_root
*trb_address_map
,
216 struct xhci_ring
*ring
,
217 struct xhci_segment
*first_seg
,
218 struct xhci_segment
*last_seg
,
221 struct xhci_segment
*seg
;
222 struct xhci_segment
*failed_seg
;
225 if (WARN_ON_ONCE(trb_address_map
== NULL
))
230 ret
= xhci_insert_segment_mapping(trb_address_map
,
231 ring
, seg
, mem_flags
);
237 } while (seg
!= first_seg
);
245 xhci_remove_segment_mapping(trb_address_map
, seg
);
246 if (seg
== failed_seg
)
249 } while (seg
!= first_seg
);
254 static void xhci_remove_stream_mapping(struct xhci_ring
*ring
)
256 struct xhci_segment
*seg
;
258 if (WARN_ON_ONCE(ring
->trb_address_map
== NULL
))
261 seg
= ring
->first_seg
;
263 xhci_remove_segment_mapping(ring
->trb_address_map
, seg
);
265 } while (seg
!= ring
->first_seg
);
268 static int xhci_update_stream_mapping(struct xhci_ring
*ring
, gfp_t mem_flags
)
270 return xhci_update_stream_segment_mapping(ring
->trb_address_map
, ring
,
271 ring
->first_seg
, ring
->last_seg
, mem_flags
);
274 /* XXX: Do we need the hcd structure in all these functions? */
275 void xhci_ring_free(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
)
280 trace_xhci_ring_free(ring
);
282 if (ring
->first_seg
) {
283 if (ring
->type
== TYPE_STREAM
)
284 xhci_remove_stream_mapping(ring
);
285 xhci_free_segments_for_ring(xhci
, ring
->first_seg
);
291 static void xhci_initialize_ring_info(struct xhci_ring
*ring
,
292 unsigned int cycle_state
)
294 /* The ring is empty, so the enqueue pointer == dequeue pointer */
295 ring
->enqueue
= ring
->first_seg
->trbs
;
296 ring
->enq_seg
= ring
->first_seg
;
297 ring
->dequeue
= ring
->enqueue
;
298 ring
->deq_seg
= ring
->first_seg
;
299 /* The ring is initialized to 0. The producer must write 1 to the cycle
300 * bit to handover ownership of the TRB, so PCS = 1. The consumer must
301 * compare CCS to the cycle bit to check ownership, so CCS = 1.
303 * New rings are initialized with cycle state equal to 1; if we are
304 * handling ring expansion, set the cycle state equal to the old ring.
306 ring
->cycle_state
= cycle_state
;
309 * Each segment has a link TRB, and leave an extra TRB for SW
312 ring
->num_trbs_free
= ring
->num_segs
* (TRBS_PER_SEGMENT
- 1) - 1;
315 /* Allocate segments and link them for a ring */
316 static int xhci_alloc_segments_for_ring(struct xhci_hcd
*xhci
,
317 struct xhci_segment
**first
, struct xhci_segment
**last
,
318 unsigned int num_segs
, unsigned int cycle_state
,
319 enum xhci_ring_type type
, unsigned int max_packet
, gfp_t flags
)
321 struct xhci_segment
*prev
;
323 prev
= xhci_segment_alloc(xhci
, cycle_state
, max_packet
, flags
);
329 while (num_segs
> 0) {
330 struct xhci_segment
*next
;
332 next
= xhci_segment_alloc(xhci
, cycle_state
, max_packet
, flags
);
337 xhci_segment_free(xhci
, prev
);
342 xhci_link_segments(xhci
, prev
, next
, type
);
347 xhci_link_segments(xhci
, prev
, *first
, type
);
354 * Create a new ring with zero or more segments.
356 * Link each segment together into a ring.
357 * Set the end flag and the cycle toggle bit on the last segment.
358 * See section 4.9.1 and figures 15 and 16.
360 struct xhci_ring
*xhci_ring_alloc(struct xhci_hcd
*xhci
,
361 unsigned int num_segs
, unsigned int cycle_state
,
362 enum xhci_ring_type type
, unsigned int max_packet
, gfp_t flags
)
364 struct xhci_ring
*ring
;
367 ring
= kzalloc(sizeof *(ring
), flags
);
371 ring
->num_segs
= num_segs
;
372 ring
->bounce_buf_len
= max_packet
;
373 INIT_LIST_HEAD(&ring
->td_list
);
378 ret
= xhci_alloc_segments_for_ring(xhci
, &ring
->first_seg
,
379 &ring
->last_seg
, num_segs
, cycle_state
, type
,
384 /* Only event ring does not use link TRB */
385 if (type
!= TYPE_EVENT
) {
386 /* See section 4.9.2.1 and 6.4.4.1 */
387 ring
->last_seg
->trbs
[TRBS_PER_SEGMENT
- 1].link
.control
|=
388 cpu_to_le32(LINK_TOGGLE
);
390 xhci_initialize_ring_info(ring
, cycle_state
);
391 trace_xhci_ring_alloc(ring
);
399 void xhci_free_endpoint_ring(struct xhci_hcd
*xhci
,
400 struct xhci_virt_device
*virt_dev
,
401 unsigned int ep_index
)
403 xhci_ring_free(xhci
, virt_dev
->eps
[ep_index
].ring
);
404 virt_dev
->eps
[ep_index
].ring
= NULL
;
408 * Expand an existing ring.
409 * Allocate a new ring which has same segment numbers and link the two rings.
411 int xhci_ring_expansion(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
412 unsigned int num_trbs
, gfp_t flags
)
414 struct xhci_segment
*first
;
415 struct xhci_segment
*last
;
416 unsigned int num_segs
;
417 unsigned int num_segs_needed
;
420 num_segs_needed
= (num_trbs
+ (TRBS_PER_SEGMENT
- 1) - 1) /
421 (TRBS_PER_SEGMENT
- 1);
423 /* Allocate number of segments we needed, or double the ring size */
424 num_segs
= ring
->num_segs
> num_segs_needed
?
425 ring
->num_segs
: num_segs_needed
;
427 ret
= xhci_alloc_segments_for_ring(xhci
, &first
, &last
,
428 num_segs
, ring
->cycle_state
, ring
->type
,
429 ring
->bounce_buf_len
, flags
);
433 if (ring
->type
== TYPE_STREAM
)
434 ret
= xhci_update_stream_segment_mapping(ring
->trb_address_map
,
435 ring
, first
, last
, flags
);
437 struct xhci_segment
*next
;
440 xhci_segment_free(xhci
, first
);
448 xhci_link_rings(xhci
, ring
, first
, last
, num_segs
);
449 trace_xhci_ring_expansion(ring
);
450 xhci_dbg_trace(xhci
, trace_xhci_dbg_ring_expansion
,
451 "ring expansion succeed, now has %d segments",
457 struct xhci_container_ctx
*xhci_alloc_container_ctx(struct xhci_hcd
*xhci
,
458 int type
, gfp_t flags
)
460 struct xhci_container_ctx
*ctx
;
462 if ((type
!= XHCI_CTX_TYPE_DEVICE
) && (type
!= XHCI_CTX_TYPE_INPUT
))
465 ctx
= kzalloc(sizeof(*ctx
), flags
);
470 ctx
->size
= HCC_64BYTE_CONTEXT(xhci
->hcc_params
) ? 2048 : 1024;
471 if (type
== XHCI_CTX_TYPE_INPUT
)
472 ctx
->size
+= CTX_SIZE(xhci
->hcc_params
);
474 ctx
->bytes
= dma_pool_zalloc(xhci
->device_pool
, flags
, &ctx
->dma
);
482 void xhci_free_container_ctx(struct xhci_hcd
*xhci
,
483 struct xhci_container_ctx
*ctx
)
487 dma_pool_free(xhci
->device_pool
, ctx
->bytes
, ctx
->dma
);
491 struct xhci_input_control_ctx
*xhci_get_input_control_ctx(
492 struct xhci_container_ctx
*ctx
)
494 if (ctx
->type
!= XHCI_CTX_TYPE_INPUT
)
497 return (struct xhci_input_control_ctx
*)ctx
->bytes
;
500 struct xhci_slot_ctx
*xhci_get_slot_ctx(struct xhci_hcd
*xhci
,
501 struct xhci_container_ctx
*ctx
)
503 if (ctx
->type
== XHCI_CTX_TYPE_DEVICE
)
504 return (struct xhci_slot_ctx
*)ctx
->bytes
;
506 return (struct xhci_slot_ctx
*)
507 (ctx
->bytes
+ CTX_SIZE(xhci
->hcc_params
));
510 struct xhci_ep_ctx
*xhci_get_ep_ctx(struct xhci_hcd
*xhci
,
511 struct xhci_container_ctx
*ctx
,
512 unsigned int ep_index
)
514 /* increment ep index by offset of start of ep ctx array */
516 if (ctx
->type
== XHCI_CTX_TYPE_INPUT
)
519 return (struct xhci_ep_ctx
*)
520 (ctx
->bytes
+ (ep_index
* CTX_SIZE(xhci
->hcc_params
)));
524 /***************** Streams structures manipulation *************************/
526 static void xhci_free_stream_ctx(struct xhci_hcd
*xhci
,
527 unsigned int num_stream_ctxs
,
528 struct xhci_stream_ctx
*stream_ctx
, dma_addr_t dma
)
530 struct device
*dev
= xhci_to_hcd(xhci
)->self
.sysdev
;
531 size_t size
= sizeof(struct xhci_stream_ctx
) * num_stream_ctxs
;
533 if (size
> MEDIUM_STREAM_ARRAY_SIZE
)
534 dma_free_coherent(dev
, size
,
536 else if (size
<= SMALL_STREAM_ARRAY_SIZE
)
537 return dma_pool_free(xhci
->small_streams_pool
,
540 return dma_pool_free(xhci
->medium_streams_pool
,
545 * The stream context array for each endpoint with bulk streams enabled can
546 * vary in size, based on:
547 * - how many streams the endpoint supports,
548 * - the maximum primary stream array size the host controller supports,
549 * - and how many streams the device driver asks for.
551 * The stream context array must be a power of 2, and can be as small as
552 * 64 bytes or as large as 1MB.
554 static struct xhci_stream_ctx
*xhci_alloc_stream_ctx(struct xhci_hcd
*xhci
,
555 unsigned int num_stream_ctxs
, dma_addr_t
*dma
,
558 struct device
*dev
= xhci_to_hcd(xhci
)->self
.sysdev
;
559 size_t size
= sizeof(struct xhci_stream_ctx
) * num_stream_ctxs
;
561 if (size
> MEDIUM_STREAM_ARRAY_SIZE
)
562 return dma_alloc_coherent(dev
, size
,
564 else if (size
<= SMALL_STREAM_ARRAY_SIZE
)
565 return dma_pool_alloc(xhci
->small_streams_pool
,
568 return dma_pool_alloc(xhci
->medium_streams_pool
,
572 struct xhci_ring
*xhci_dma_to_transfer_ring(
573 struct xhci_virt_ep
*ep
,
576 if (ep
->ep_state
& EP_HAS_STREAMS
)
577 return radix_tree_lookup(&ep
->stream_info
->trb_address_map
,
578 address
>> TRB_SEGMENT_SHIFT
);
582 struct xhci_ring
*xhci_stream_id_to_ring(
583 struct xhci_virt_device
*dev
,
584 unsigned int ep_index
,
585 unsigned int stream_id
)
587 struct xhci_virt_ep
*ep
= &dev
->eps
[ep_index
];
591 if (!ep
->stream_info
)
594 if (stream_id
> ep
->stream_info
->num_streams
)
596 return ep
->stream_info
->stream_rings
[stream_id
];
600 * Change an endpoint's internal structure so it supports stream IDs. The
601 * number of requested streams includes stream 0, which cannot be used by device
604 * The number of stream contexts in the stream context array may be bigger than
605 * the number of streams the driver wants to use. This is because the number of
606 * stream context array entries must be a power of two.
608 struct xhci_stream_info
*xhci_alloc_stream_info(struct xhci_hcd
*xhci
,
609 unsigned int num_stream_ctxs
,
610 unsigned int num_streams
,
611 unsigned int max_packet
, gfp_t mem_flags
)
613 struct xhci_stream_info
*stream_info
;
615 struct xhci_ring
*cur_ring
;
619 xhci_dbg(xhci
, "Allocating %u streams and %u "
620 "stream context array entries.\n",
621 num_streams
, num_stream_ctxs
);
622 if (xhci
->cmd_ring_reserved_trbs
== MAX_RSVD_CMD_TRBS
) {
623 xhci_dbg(xhci
, "Command ring has no reserved TRBs available\n");
626 xhci
->cmd_ring_reserved_trbs
++;
628 stream_info
= kzalloc(sizeof(struct xhci_stream_info
), mem_flags
);
632 stream_info
->num_streams
= num_streams
;
633 stream_info
->num_stream_ctxs
= num_stream_ctxs
;
635 /* Initialize the array of virtual pointers to stream rings. */
636 stream_info
->stream_rings
= kzalloc(
637 sizeof(struct xhci_ring
*)*num_streams
,
639 if (!stream_info
->stream_rings
)
642 /* Initialize the array of DMA addresses for stream rings for the HW. */
643 stream_info
->stream_ctx_array
= xhci_alloc_stream_ctx(xhci
,
644 num_stream_ctxs
, &stream_info
->ctx_array_dma
,
646 if (!stream_info
->stream_ctx_array
)
648 memset(stream_info
->stream_ctx_array
, 0,
649 sizeof(struct xhci_stream_ctx
)*num_stream_ctxs
);
651 /* Allocate everything needed to free the stream rings later */
652 stream_info
->free_streams_command
=
653 xhci_alloc_command_with_ctx(xhci
, true, mem_flags
);
654 if (!stream_info
->free_streams_command
)
657 INIT_RADIX_TREE(&stream_info
->trb_address_map
, GFP_ATOMIC
);
659 /* Allocate rings for all the streams that the driver will use,
660 * and add their segment DMA addresses to the radix tree.
661 * Stream 0 is reserved.
664 for (cur_stream
= 1; cur_stream
< num_streams
; cur_stream
++) {
665 stream_info
->stream_rings
[cur_stream
] =
666 xhci_ring_alloc(xhci
, 2, 1, TYPE_STREAM
, max_packet
,
668 cur_ring
= stream_info
->stream_rings
[cur_stream
];
671 cur_ring
->stream_id
= cur_stream
;
672 cur_ring
->trb_address_map
= &stream_info
->trb_address_map
;
673 /* Set deq ptr, cycle bit, and stream context type */
674 addr
= cur_ring
->first_seg
->dma
|
675 SCT_FOR_CTX(SCT_PRI_TR
) |
676 cur_ring
->cycle_state
;
677 stream_info
->stream_ctx_array
[cur_stream
].stream_ring
=
679 xhci_dbg(xhci
, "Setting stream %d ring ptr to 0x%08llx\n",
680 cur_stream
, (unsigned long long) addr
);
682 ret
= xhci_update_stream_mapping(cur_ring
, mem_flags
);
684 xhci_ring_free(xhci
, cur_ring
);
685 stream_info
->stream_rings
[cur_stream
] = NULL
;
689 /* Leave the other unused stream ring pointers in the stream context
690 * array initialized to zero. This will cause the xHC to give us an
691 * error if the device asks for a stream ID we don't have setup (if it
692 * was any other way, the host controller would assume the ring is
693 * "empty" and wait forever for data to be queued to that stream ID).
699 for (cur_stream
= 1; cur_stream
< num_streams
; cur_stream
++) {
700 cur_ring
= stream_info
->stream_rings
[cur_stream
];
702 xhci_ring_free(xhci
, cur_ring
);
703 stream_info
->stream_rings
[cur_stream
] = NULL
;
706 xhci_free_command(xhci
, stream_info
->free_streams_command
);
708 kfree(stream_info
->stream_rings
);
712 xhci
->cmd_ring_reserved_trbs
--;
716 * Sets the MaxPStreams field and the Linear Stream Array field.
717 * Sets the dequeue pointer to the stream context array.
719 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd
*xhci
,
720 struct xhci_ep_ctx
*ep_ctx
,
721 struct xhci_stream_info
*stream_info
)
723 u32 max_primary_streams
;
724 /* MaxPStreams is the number of stream context array entries, not the
725 * number we're actually using. Must be in 2^(MaxPstreams + 1) format.
726 * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
728 max_primary_streams
= fls(stream_info
->num_stream_ctxs
) - 2;
729 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
730 "Setting number of stream ctx array entries to %u",
731 1 << (max_primary_streams
+ 1));
732 ep_ctx
->ep_info
&= cpu_to_le32(~EP_MAXPSTREAMS_MASK
);
733 ep_ctx
->ep_info
|= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams
)
735 ep_ctx
->deq
= cpu_to_le64(stream_info
->ctx_array_dma
);
739 * Sets the MaxPStreams field and the Linear Stream Array field to 0.
740 * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
741 * not at the beginning of the ring).
743 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx
*ep_ctx
,
744 struct xhci_virt_ep
*ep
)
747 ep_ctx
->ep_info
&= cpu_to_le32(~(EP_MAXPSTREAMS_MASK
| EP_HAS_LSA
));
748 addr
= xhci_trb_virt_to_dma(ep
->ring
->deq_seg
, ep
->ring
->dequeue
);
749 ep_ctx
->deq
= cpu_to_le64(addr
| ep
->ring
->cycle_state
);
752 /* Frees all stream contexts associated with the endpoint,
754 * Caller should fix the endpoint context streams fields.
756 void xhci_free_stream_info(struct xhci_hcd
*xhci
,
757 struct xhci_stream_info
*stream_info
)
760 struct xhci_ring
*cur_ring
;
765 for (cur_stream
= 1; cur_stream
< stream_info
->num_streams
;
767 cur_ring
= stream_info
->stream_rings
[cur_stream
];
769 xhci_ring_free(xhci
, cur_ring
);
770 stream_info
->stream_rings
[cur_stream
] = NULL
;
773 xhci_free_command(xhci
, stream_info
->free_streams_command
);
774 xhci
->cmd_ring_reserved_trbs
--;
775 if (stream_info
->stream_ctx_array
)
776 xhci_free_stream_ctx(xhci
,
777 stream_info
->num_stream_ctxs
,
778 stream_info
->stream_ctx_array
,
779 stream_info
->ctx_array_dma
);
781 kfree(stream_info
->stream_rings
);
786 /***************** Device context manipulation *************************/
788 static void xhci_init_endpoint_timer(struct xhci_hcd
*xhci
,
789 struct xhci_virt_ep
*ep
)
791 timer_setup(&ep
->stop_cmd_timer
, xhci_stop_endpoint_command_watchdog
,
796 static void xhci_free_tt_info(struct xhci_hcd
*xhci
,
797 struct xhci_virt_device
*virt_dev
,
800 struct list_head
*tt_list_head
;
801 struct xhci_tt_bw_info
*tt_info
, *next
;
802 bool slot_found
= false;
804 /* If the device never made it past the Set Address stage,
805 * it may not have the real_port set correctly.
807 if (virt_dev
->real_port
== 0 ||
808 virt_dev
->real_port
> HCS_MAX_PORTS(xhci
->hcs_params1
)) {
809 xhci_dbg(xhci
, "Bad real port.\n");
813 tt_list_head
= &(xhci
->rh_bw
[virt_dev
->real_port
- 1].tts
);
814 list_for_each_entry_safe(tt_info
, next
, tt_list_head
, tt_list
) {
815 /* Multi-TT hubs will have more than one entry */
816 if (tt_info
->slot_id
== slot_id
) {
818 list_del(&tt_info
->tt_list
);
820 } else if (slot_found
) {
826 int xhci_alloc_tt_info(struct xhci_hcd
*xhci
,
827 struct xhci_virt_device
*virt_dev
,
828 struct usb_device
*hdev
,
829 struct usb_tt
*tt
, gfp_t mem_flags
)
831 struct xhci_tt_bw_info
*tt_info
;
832 unsigned int num_ports
;
838 num_ports
= hdev
->maxchild
;
840 for (i
= 0; i
< num_ports
; i
++, tt_info
++) {
841 struct xhci_interval_bw_table
*bw_table
;
843 tt_info
= kzalloc(sizeof(*tt_info
), mem_flags
);
846 INIT_LIST_HEAD(&tt_info
->tt_list
);
847 list_add(&tt_info
->tt_list
,
848 &xhci
->rh_bw
[virt_dev
->real_port
- 1].tts
);
849 tt_info
->slot_id
= virt_dev
->udev
->slot_id
;
851 tt_info
->ttport
= i
+1;
852 bw_table
= &tt_info
->bw_table
;
853 for (j
= 0; j
< XHCI_MAX_INTERVAL
; j
++)
854 INIT_LIST_HEAD(&bw_table
->interval_bw
[j
].endpoints
);
859 xhci_free_tt_info(xhci
, virt_dev
, virt_dev
->udev
->slot_id
);
864 /* All the xhci_tds in the ring's TD list should be freed at this point.
865 * Should be called with xhci->lock held if there is any chance the TT lists
866 * will be manipulated by the configure endpoint, allocate device, or update
867 * hub functions while this function is removing the TT entries from the list.
869 void xhci_free_virt_device(struct xhci_hcd
*xhci
, int slot_id
)
871 struct xhci_virt_device
*dev
;
873 int old_active_eps
= 0;
875 /* Slot ID 0 is reserved */
876 if (slot_id
== 0 || !xhci
->devs
[slot_id
])
879 dev
= xhci
->devs
[slot_id
];
881 trace_xhci_free_virt_device(dev
);
883 xhci
->dcbaa
->dev_context_ptrs
[slot_id
] = 0;
888 old_active_eps
= dev
->tt_info
->active_eps
;
890 for (i
= 0; i
< 31; i
++) {
891 if (dev
->eps
[i
].ring
)
892 xhci_ring_free(xhci
, dev
->eps
[i
].ring
);
893 if (dev
->eps
[i
].stream_info
)
894 xhci_free_stream_info(xhci
,
895 dev
->eps
[i
].stream_info
);
896 /* Endpoints on the TT/root port lists should have been removed
897 * when usb_disable_device() was called for the device.
898 * We can't drop them anyway, because the udev might have gone
899 * away by this point, and we can't tell what speed it was.
901 if (!list_empty(&dev
->eps
[i
].bw_endpoint_list
))
902 xhci_warn(xhci
, "Slot %u endpoint %u "
903 "not removed from BW list!\n",
906 /* If this is a hub, free the TT(s) from the TT list */
907 xhci_free_tt_info(xhci
, dev
, slot_id
);
908 /* If necessary, update the number of active TTs on this root port */
909 xhci_update_tt_active_eps(xhci
, dev
, old_active_eps
);
912 xhci_free_container_ctx(xhci
, dev
->in_ctx
);
914 xhci_free_container_ctx(xhci
, dev
->out_ctx
);
916 if (dev
->udev
&& dev
->udev
->slot_id
)
917 dev
->udev
->slot_id
= 0;
918 kfree(xhci
->devs
[slot_id
]);
919 xhci
->devs
[slot_id
] = NULL
;
923 * Free a virt_device structure.
924 * If the virt_device added a tt_info (a hub) and has children pointing to
925 * that tt_info, then free the child first. Recursive.
926 * We can't rely on udev at this point to find child-parent relationships.
928 void xhci_free_virt_devices_depth_first(struct xhci_hcd
*xhci
, int slot_id
)
930 struct xhci_virt_device
*vdev
;
931 struct list_head
*tt_list_head
;
932 struct xhci_tt_bw_info
*tt_info
, *next
;
935 vdev
= xhci
->devs
[slot_id
];
939 if (vdev
->real_port
== 0 ||
940 vdev
->real_port
> HCS_MAX_PORTS(xhci
->hcs_params1
)) {
941 xhci_dbg(xhci
, "Bad vdev->real_port.\n");
945 tt_list_head
= &(xhci
->rh_bw
[vdev
->real_port
- 1].tts
);
946 list_for_each_entry_safe(tt_info
, next
, tt_list_head
, tt_list
) {
947 /* is this a hub device that added a tt_info to the tts list */
948 if (tt_info
->slot_id
== slot_id
) {
949 /* are any devices using this tt_info? */
950 for (i
= 1; i
< HCS_MAX_SLOTS(xhci
->hcs_params1
); i
++) {
951 vdev
= xhci
->devs
[i
];
952 if (vdev
&& (vdev
->tt_info
== tt_info
))
953 xhci_free_virt_devices_depth_first(
959 /* we are now at a leaf device */
960 xhci_debugfs_remove_slot(xhci
, slot_id
);
961 xhci_free_virt_device(xhci
, slot_id
);
964 int xhci_alloc_virt_device(struct xhci_hcd
*xhci
, int slot_id
,
965 struct usb_device
*udev
, gfp_t flags
)
967 struct xhci_virt_device
*dev
;
970 /* Slot ID 0 is reserved */
971 if (slot_id
== 0 || xhci
->devs
[slot_id
]) {
972 xhci_warn(xhci
, "Bad Slot ID %d\n", slot_id
);
976 dev
= kzalloc(sizeof(*dev
), flags
);
980 /* Allocate the (output) device context that will be used in the HC. */
981 dev
->out_ctx
= xhci_alloc_container_ctx(xhci
, XHCI_CTX_TYPE_DEVICE
, flags
);
985 xhci_dbg(xhci
, "Slot %d output ctx = 0x%llx (dma)\n", slot_id
,
986 (unsigned long long)dev
->out_ctx
->dma
);
988 /* Allocate the (input) device context for address device command */
989 dev
->in_ctx
= xhci_alloc_container_ctx(xhci
, XHCI_CTX_TYPE_INPUT
, flags
);
993 xhci_dbg(xhci
, "Slot %d input ctx = 0x%llx (dma)\n", slot_id
,
994 (unsigned long long)dev
->in_ctx
->dma
);
996 /* Initialize the cancellation list and watchdog timers for each ep */
997 for (i
= 0; i
< 31; i
++) {
998 xhci_init_endpoint_timer(xhci
, &dev
->eps
[i
]);
999 INIT_LIST_HEAD(&dev
->eps
[i
].cancelled_td_list
);
1000 INIT_LIST_HEAD(&dev
->eps
[i
].bw_endpoint_list
);
1003 /* Allocate endpoint 0 ring */
1004 dev
->eps
[0].ring
= xhci_ring_alloc(xhci
, 2, 1, TYPE_CTRL
, 0, flags
);
1005 if (!dev
->eps
[0].ring
)
1010 /* Point to output device context in dcbaa. */
1011 xhci
->dcbaa
->dev_context_ptrs
[slot_id
] = cpu_to_le64(dev
->out_ctx
->dma
);
1012 xhci_dbg(xhci
, "Set slot id %d dcbaa entry %p to 0x%llx\n",
1014 &xhci
->dcbaa
->dev_context_ptrs
[slot_id
],
1015 le64_to_cpu(xhci
->dcbaa
->dev_context_ptrs
[slot_id
]));
1017 trace_xhci_alloc_virt_device(dev
);
1019 xhci
->devs
[slot_id
] = dev
;
1025 xhci_free_container_ctx(xhci
, dev
->in_ctx
);
1027 xhci_free_container_ctx(xhci
, dev
->out_ctx
);
1033 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd
*xhci
,
1034 struct usb_device
*udev
)
1036 struct xhci_virt_device
*virt_dev
;
1037 struct xhci_ep_ctx
*ep0_ctx
;
1038 struct xhci_ring
*ep_ring
;
1040 virt_dev
= xhci
->devs
[udev
->slot_id
];
1041 ep0_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->in_ctx
, 0);
1042 ep_ring
= virt_dev
->eps
[0].ring
;
1044 * FIXME we don't keep track of the dequeue pointer very well after a
1045 * Set TR dequeue pointer, so we're setting the dequeue pointer of the
1046 * host to our enqueue pointer. This should only be called after a
1047 * configured device has reset, so all control transfers should have
1048 * been completed or cancelled before the reset.
1050 ep0_ctx
->deq
= cpu_to_le64(xhci_trb_virt_to_dma(ep_ring
->enq_seg
,
1052 | ep_ring
->cycle_state
);
1056 * The xHCI roothub may have ports of differing speeds in any order in the port
1059 * The xHCI hardware wants to know the roothub port number that the USB device
1060 * is attached to (or the roothub port its ancestor hub is attached to). All we
1061 * know is the index of that port under either the USB 2.0 or the USB 3.0
1062 * roothub, but that doesn't give us the real index into the HW port status
1063 * registers. Call xhci_find_raw_port_number() to get real index.
1065 static u32
xhci_find_real_port_number(struct xhci_hcd
*xhci
,
1066 struct usb_device
*udev
)
1068 struct usb_device
*top_dev
;
1069 struct usb_hcd
*hcd
;
1071 if (udev
->speed
>= USB_SPEED_SUPER
)
1072 hcd
= xhci
->shared_hcd
;
1074 hcd
= xhci
->main_hcd
;
1076 for (top_dev
= udev
; top_dev
->parent
&& top_dev
->parent
->parent
;
1077 top_dev
= top_dev
->parent
)
1078 /* Found device below root hub */;
1080 return xhci_find_raw_port_number(hcd
, top_dev
->portnum
);
1083 /* Setup an xHCI virtual device for a Set Address command */
1084 int xhci_setup_addressable_virt_dev(struct xhci_hcd
*xhci
, struct usb_device
*udev
)
1086 struct xhci_virt_device
*dev
;
1087 struct xhci_ep_ctx
*ep0_ctx
;
1088 struct xhci_slot_ctx
*slot_ctx
;
1091 struct usb_device
*top_dev
;
1093 dev
= xhci
->devs
[udev
->slot_id
];
1094 /* Slot ID 0 is reserved */
1095 if (udev
->slot_id
== 0 || !dev
) {
1096 xhci_warn(xhci
, "Slot ID %d is not assigned to this device\n",
1100 ep0_ctx
= xhci_get_ep_ctx(xhci
, dev
->in_ctx
, 0);
1101 slot_ctx
= xhci_get_slot_ctx(xhci
, dev
->in_ctx
);
1103 /* 3) Only the control endpoint is valid - one endpoint context */
1104 slot_ctx
->dev_info
|= cpu_to_le32(LAST_CTX(1) | udev
->route
);
1105 switch (udev
->speed
) {
1106 case USB_SPEED_SUPER_PLUS
:
1107 slot_ctx
->dev_info
|= cpu_to_le32(SLOT_SPEED_SSP
);
1108 max_packets
= MAX_PACKET(512);
1110 case USB_SPEED_SUPER
:
1111 slot_ctx
->dev_info
|= cpu_to_le32(SLOT_SPEED_SS
);
1112 max_packets
= MAX_PACKET(512);
1114 case USB_SPEED_HIGH
:
1115 slot_ctx
->dev_info
|= cpu_to_le32(SLOT_SPEED_HS
);
1116 max_packets
= MAX_PACKET(64);
1118 /* USB core guesses at a 64-byte max packet first for FS devices */
1119 case USB_SPEED_FULL
:
1120 slot_ctx
->dev_info
|= cpu_to_le32(SLOT_SPEED_FS
);
1121 max_packets
= MAX_PACKET(64);
1124 slot_ctx
->dev_info
|= cpu_to_le32(SLOT_SPEED_LS
);
1125 max_packets
= MAX_PACKET(8);
1127 case USB_SPEED_WIRELESS
:
1128 xhci_dbg(xhci
, "FIXME xHCI doesn't support wireless speeds\n");
1132 /* Speed was set earlier, this shouldn't happen. */
1135 /* Find the root hub port this device is under */
1136 port_num
= xhci_find_real_port_number(xhci
, udev
);
1139 slot_ctx
->dev_info2
|= cpu_to_le32(ROOT_HUB_PORT(port_num
));
1140 /* Set the port number in the virtual_device to the faked port number */
1141 for (top_dev
= udev
; top_dev
->parent
&& top_dev
->parent
->parent
;
1142 top_dev
= top_dev
->parent
)
1143 /* Found device below root hub */;
1144 dev
->fake_port
= top_dev
->portnum
;
1145 dev
->real_port
= port_num
;
1146 xhci_dbg(xhci
, "Set root hub portnum to %d\n", port_num
);
1147 xhci_dbg(xhci
, "Set fake root hub portnum to %d\n", dev
->fake_port
);
1149 /* Find the right bandwidth table that this device will be a part of.
1150 * If this is a full speed device attached directly to a root port (or a
1151 * decendent of one), it counts as a primary bandwidth domain, not a
1152 * secondary bandwidth domain under a TT. An xhci_tt_info structure
1153 * will never be created for the HS root hub.
1155 if (!udev
->tt
|| !udev
->tt
->hub
->parent
) {
1156 dev
->bw_table
= &xhci
->rh_bw
[port_num
- 1].bw_table
;
1158 struct xhci_root_port_bw_info
*rh_bw
;
1159 struct xhci_tt_bw_info
*tt_bw
;
1161 rh_bw
= &xhci
->rh_bw
[port_num
- 1];
1162 /* Find the right TT. */
1163 list_for_each_entry(tt_bw
, &rh_bw
->tts
, tt_list
) {
1164 if (tt_bw
->slot_id
!= udev
->tt
->hub
->slot_id
)
1167 if (!dev
->udev
->tt
->multi
||
1169 tt_bw
->ttport
== dev
->udev
->ttport
)) {
1170 dev
->bw_table
= &tt_bw
->bw_table
;
1171 dev
->tt_info
= tt_bw
;
1176 xhci_warn(xhci
, "WARN: Didn't find a matching TT\n");
1179 /* Is this a LS/FS device under an external HS hub? */
1180 if (udev
->tt
&& udev
->tt
->hub
->parent
) {
1181 slot_ctx
->tt_info
= cpu_to_le32(udev
->tt
->hub
->slot_id
|
1182 (udev
->ttport
<< 8));
1183 if (udev
->tt
->multi
)
1184 slot_ctx
->dev_info
|= cpu_to_le32(DEV_MTT
);
1186 xhci_dbg(xhci
, "udev->tt = %p\n", udev
->tt
);
1187 xhci_dbg(xhci
, "udev->ttport = 0x%x\n", udev
->ttport
);
1189 /* Step 4 - ring already allocated */
1191 ep0_ctx
->ep_info2
= cpu_to_le32(EP_TYPE(CTRL_EP
));
1193 /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
1194 ep0_ctx
->ep_info2
|= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3) |
1197 ep0_ctx
->deq
= cpu_to_le64(dev
->eps
[0].ring
->first_seg
->dma
|
1198 dev
->eps
[0].ring
->cycle_state
);
1200 trace_xhci_setup_addressable_virt_device(dev
);
1202 /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
1208 * Convert interval expressed as 2^(bInterval - 1) == interval into
1209 * straight exponent value 2^n == interval.
1212 static unsigned int xhci_parse_exponent_interval(struct usb_device
*udev
,
1213 struct usb_host_endpoint
*ep
)
1215 unsigned int interval
;
1217 interval
= clamp_val(ep
->desc
.bInterval
, 1, 16) - 1;
1218 if (interval
!= ep
->desc
.bInterval
- 1)
1219 dev_warn(&udev
->dev
,
1220 "ep %#x - rounding interval to %d %sframes\n",
1221 ep
->desc
.bEndpointAddress
,
1223 udev
->speed
== USB_SPEED_FULL
? "" : "micro");
1225 if (udev
->speed
== USB_SPEED_FULL
) {
1227 * Full speed isoc endpoints specify interval in frames,
1228 * not microframes. We are using microframes everywhere,
1229 * so adjust accordingly.
1231 interval
+= 3; /* 1 frame = 2^3 uframes */
1238 * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
1239 * microframes, rounded down to nearest power of 2.
1241 static unsigned int xhci_microframes_to_exponent(struct usb_device
*udev
,
1242 struct usb_host_endpoint
*ep
, unsigned int desc_interval
,
1243 unsigned int min_exponent
, unsigned int max_exponent
)
1245 unsigned int interval
;
1247 interval
= fls(desc_interval
) - 1;
1248 interval
= clamp_val(interval
, min_exponent
, max_exponent
);
1249 if ((1 << interval
) != desc_interval
)
1251 "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n",
1252 ep
->desc
.bEndpointAddress
,
1259 static unsigned int xhci_parse_microframe_interval(struct usb_device
*udev
,
1260 struct usb_host_endpoint
*ep
)
1262 if (ep
->desc
.bInterval
== 0)
1264 return xhci_microframes_to_exponent(udev
, ep
,
1265 ep
->desc
.bInterval
, 0, 15);
1269 static unsigned int xhci_parse_frame_interval(struct usb_device
*udev
,
1270 struct usb_host_endpoint
*ep
)
1272 return xhci_microframes_to_exponent(udev
, ep
,
1273 ep
->desc
.bInterval
* 8, 3, 10);
1276 /* Return the polling or NAK interval.
1278 * The polling interval is expressed in "microframes". If xHCI's Interval field
1279 * is set to N, it will service the endpoint every 2^(Interval)*125us.
1281 * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
1284 static unsigned int xhci_get_endpoint_interval(struct usb_device
*udev
,
1285 struct usb_host_endpoint
*ep
)
1287 unsigned int interval
= 0;
1289 switch (udev
->speed
) {
1290 case USB_SPEED_HIGH
:
1292 if (usb_endpoint_xfer_control(&ep
->desc
) ||
1293 usb_endpoint_xfer_bulk(&ep
->desc
)) {
1294 interval
= xhci_parse_microframe_interval(udev
, ep
);
1297 /* Fall through - SS and HS isoc/int have same decoding */
1299 case USB_SPEED_SUPER_PLUS
:
1300 case USB_SPEED_SUPER
:
1301 if (usb_endpoint_xfer_int(&ep
->desc
) ||
1302 usb_endpoint_xfer_isoc(&ep
->desc
)) {
1303 interval
= xhci_parse_exponent_interval(udev
, ep
);
1307 case USB_SPEED_FULL
:
1308 if (usb_endpoint_xfer_isoc(&ep
->desc
)) {
1309 interval
= xhci_parse_exponent_interval(udev
, ep
);
1313 * Fall through for interrupt endpoint interval decoding
1314 * since it uses the same rules as low speed interrupt
1320 if (usb_endpoint_xfer_int(&ep
->desc
) ||
1321 usb_endpoint_xfer_isoc(&ep
->desc
)) {
1323 interval
= xhci_parse_frame_interval(udev
, ep
);
1333 /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
1334 * High speed endpoint descriptors can define "the number of additional
1335 * transaction opportunities per microframe", but that goes in the Max Burst
1336 * endpoint context field.
1338 static u32
xhci_get_endpoint_mult(struct usb_device
*udev
,
1339 struct usb_host_endpoint
*ep
)
1341 if (udev
->speed
< USB_SPEED_SUPER
||
1342 !usb_endpoint_xfer_isoc(&ep
->desc
))
1344 return ep
->ss_ep_comp
.bmAttributes
;
1347 static u32
xhci_get_endpoint_max_burst(struct usb_device
*udev
,
1348 struct usb_host_endpoint
*ep
)
1350 /* Super speed and Plus have max burst in ep companion desc */
1351 if (udev
->speed
>= USB_SPEED_SUPER
)
1352 return ep
->ss_ep_comp
.bMaxBurst
;
1354 if (udev
->speed
== USB_SPEED_HIGH
&&
1355 (usb_endpoint_xfer_isoc(&ep
->desc
) ||
1356 usb_endpoint_xfer_int(&ep
->desc
)))
1357 return usb_endpoint_maxp_mult(&ep
->desc
) - 1;
1362 static u32
xhci_get_endpoint_type(struct usb_host_endpoint
*ep
)
1366 in
= usb_endpoint_dir_in(&ep
->desc
);
1368 switch (usb_endpoint_type(&ep
->desc
)) {
1369 case USB_ENDPOINT_XFER_CONTROL
:
1371 case USB_ENDPOINT_XFER_BULK
:
1372 return in
? BULK_IN_EP
: BULK_OUT_EP
;
1373 case USB_ENDPOINT_XFER_ISOC
:
1374 return in
? ISOC_IN_EP
: ISOC_OUT_EP
;
1375 case USB_ENDPOINT_XFER_INT
:
1376 return in
? INT_IN_EP
: INT_OUT_EP
;
1381 /* Return the maximum endpoint service interval time (ESIT) payload.
1382 * Basically, this is the maxpacket size, multiplied by the burst size
1385 static u32
xhci_get_max_esit_payload(struct usb_device
*udev
,
1386 struct usb_host_endpoint
*ep
)
1391 /* Only applies for interrupt or isochronous endpoints */
1392 if (usb_endpoint_xfer_control(&ep
->desc
) ||
1393 usb_endpoint_xfer_bulk(&ep
->desc
))
1396 /* SuperSpeedPlus Isoc ep sending over 48k per esit */
1397 if ((udev
->speed
>= USB_SPEED_SUPER_PLUS
) &&
1398 USB_SS_SSP_ISOC_COMP(ep
->ss_ep_comp
.bmAttributes
))
1399 return le32_to_cpu(ep
->ssp_isoc_ep_comp
.dwBytesPerInterval
);
1400 /* SuperSpeed or SuperSpeedPlus Isoc ep with less than 48k per esit */
1401 else if (udev
->speed
>= USB_SPEED_SUPER
)
1402 return le16_to_cpu(ep
->ss_ep_comp
.wBytesPerInterval
);
1404 max_packet
= usb_endpoint_maxp(&ep
->desc
);
1405 max_burst
= usb_endpoint_maxp_mult(&ep
->desc
);
1406 /* A 0 in max burst means 1 transfer per ESIT */
1407 return max_packet
* max_burst
;
1410 /* Set up an endpoint with one ring segment. Do not allocate stream rings.
1411 * Drivers will have to call usb_alloc_streams() to do that.
1413 int xhci_endpoint_init(struct xhci_hcd
*xhci
,
1414 struct xhci_virt_device
*virt_dev
,
1415 struct usb_device
*udev
,
1416 struct usb_host_endpoint
*ep
,
1419 unsigned int ep_index
;
1420 struct xhci_ep_ctx
*ep_ctx
;
1421 struct xhci_ring
*ep_ring
;
1422 unsigned int max_packet
;
1423 enum xhci_ring_type ring_type
;
1424 u32 max_esit_payload
;
1426 unsigned int max_burst
;
1427 unsigned int interval
;
1429 unsigned int avg_trb_len
;
1430 unsigned int err_count
= 0;
1432 ep_index
= xhci_get_endpoint_index(&ep
->desc
);
1433 ep_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->in_ctx
, ep_index
);
1435 endpoint_type
= xhci_get_endpoint_type(ep
);
1439 ring_type
= usb_endpoint_type(&ep
->desc
);
1442 * Get values to fill the endpoint context, mostly from ep descriptor.
1443 * The average TRB buffer lengt for bulk endpoints is unclear as we
1444 * have no clue on scatter gather list entry size. For Isoc and Int,
1445 * set it to max available. See xHCI 1.1 spec 4.14.1.1 for details.
1447 max_esit_payload
= xhci_get_max_esit_payload(udev
, ep
);
1448 interval
= xhci_get_endpoint_interval(udev
, ep
);
1450 /* Periodic endpoint bInterval limit quirk */
1451 if (usb_endpoint_xfer_int(&ep
->desc
) ||
1452 usb_endpoint_xfer_isoc(&ep
->desc
)) {
1453 if ((xhci
->quirks
& XHCI_LIMIT_ENDPOINT_INTERVAL_7
) &&
1454 udev
->speed
>= USB_SPEED_HIGH
&&
1460 mult
= xhci_get_endpoint_mult(udev
, ep
);
1461 max_packet
= usb_endpoint_maxp(&ep
->desc
);
1462 max_burst
= xhci_get_endpoint_max_burst(udev
, ep
);
1463 avg_trb_len
= max_esit_payload
;
1465 /* FIXME dig Mult and streams info out of ep companion desc */
1467 /* Allow 3 retries for everything but isoc, set CErr = 3 */
1468 if (!usb_endpoint_xfer_isoc(&ep
->desc
))
1470 /* Some devices get this wrong */
1471 if (usb_endpoint_xfer_bulk(&ep
->desc
) && udev
->speed
== USB_SPEED_HIGH
)
1473 /* xHCI 1.0 and 1.1 indicates that ctrl ep avg TRB Length should be 8 */
1474 if (usb_endpoint_xfer_control(&ep
->desc
) && xhci
->hci_version
>= 0x100)
1476 /* xhci 1.1 with LEC support doesn't use mult field, use RsvdZ */
1477 if ((xhci
->hci_version
> 0x100) && HCC2_LEC(xhci
->hcc_params2
))
1480 /* Set up the endpoint ring */
1481 virt_dev
->eps
[ep_index
].new_ring
=
1482 xhci_ring_alloc(xhci
, 2, 1, ring_type
, max_packet
, mem_flags
);
1483 if (!virt_dev
->eps
[ep_index
].new_ring
)
1486 virt_dev
->eps
[ep_index
].skip
= false;
1487 ep_ring
= virt_dev
->eps
[ep_index
].new_ring
;
1489 /* Fill the endpoint context */
1490 ep_ctx
->ep_info
= cpu_to_le32(EP_MAX_ESIT_PAYLOAD_HI(max_esit_payload
) |
1491 EP_INTERVAL(interval
) |
1493 ep_ctx
->ep_info2
= cpu_to_le32(EP_TYPE(endpoint_type
) |
1494 MAX_PACKET(max_packet
) |
1495 MAX_BURST(max_burst
) |
1496 ERROR_COUNT(err_count
));
1497 ep_ctx
->deq
= cpu_to_le64(ep_ring
->first_seg
->dma
|
1498 ep_ring
->cycle_state
);
1500 ep_ctx
->tx_info
= cpu_to_le32(EP_MAX_ESIT_PAYLOAD_LO(max_esit_payload
) |
1501 EP_AVG_TRB_LENGTH(avg_trb_len
));
1506 void xhci_endpoint_zero(struct xhci_hcd
*xhci
,
1507 struct xhci_virt_device
*virt_dev
,
1508 struct usb_host_endpoint
*ep
)
1510 unsigned int ep_index
;
1511 struct xhci_ep_ctx
*ep_ctx
;
1513 ep_index
= xhci_get_endpoint_index(&ep
->desc
);
1514 ep_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->in_ctx
, ep_index
);
1516 ep_ctx
->ep_info
= 0;
1517 ep_ctx
->ep_info2
= 0;
1519 ep_ctx
->tx_info
= 0;
1520 /* Don't free the endpoint ring until the set interface or configuration
1525 void xhci_clear_endpoint_bw_info(struct xhci_bw_info
*bw_info
)
1527 bw_info
->ep_interval
= 0;
1529 bw_info
->num_packets
= 0;
1530 bw_info
->max_packet_size
= 0;
1532 bw_info
->max_esit_payload
= 0;
1535 void xhci_update_bw_info(struct xhci_hcd
*xhci
,
1536 struct xhci_container_ctx
*in_ctx
,
1537 struct xhci_input_control_ctx
*ctrl_ctx
,
1538 struct xhci_virt_device
*virt_dev
)
1540 struct xhci_bw_info
*bw_info
;
1541 struct xhci_ep_ctx
*ep_ctx
;
1542 unsigned int ep_type
;
1545 for (i
= 1; i
< 31; i
++) {
1546 bw_info
= &virt_dev
->eps
[i
].bw_info
;
1548 /* We can't tell what endpoint type is being dropped, but
1549 * unconditionally clearing the bandwidth info for non-periodic
1550 * endpoints should be harmless because the info will never be
1551 * set in the first place.
1553 if (!EP_IS_ADDED(ctrl_ctx
, i
) && EP_IS_DROPPED(ctrl_ctx
, i
)) {
1554 /* Dropped endpoint */
1555 xhci_clear_endpoint_bw_info(bw_info
);
1559 if (EP_IS_ADDED(ctrl_ctx
, i
)) {
1560 ep_ctx
= xhci_get_ep_ctx(xhci
, in_ctx
, i
);
1561 ep_type
= CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx
->ep_info2
));
1563 /* Ignore non-periodic endpoints */
1564 if (ep_type
!= ISOC_OUT_EP
&& ep_type
!= INT_OUT_EP
&&
1565 ep_type
!= ISOC_IN_EP
&&
1566 ep_type
!= INT_IN_EP
)
1569 /* Added or changed endpoint */
1570 bw_info
->ep_interval
= CTX_TO_EP_INTERVAL(
1571 le32_to_cpu(ep_ctx
->ep_info
));
1572 /* Number of packets and mult are zero-based in the
1573 * input context, but we want one-based for the
1576 bw_info
->mult
= CTX_TO_EP_MULT(
1577 le32_to_cpu(ep_ctx
->ep_info
)) + 1;
1578 bw_info
->num_packets
= CTX_TO_MAX_BURST(
1579 le32_to_cpu(ep_ctx
->ep_info2
)) + 1;
1580 bw_info
->max_packet_size
= MAX_PACKET_DECODED(
1581 le32_to_cpu(ep_ctx
->ep_info2
));
1582 bw_info
->type
= ep_type
;
1583 bw_info
->max_esit_payload
= CTX_TO_MAX_ESIT_PAYLOAD(
1584 le32_to_cpu(ep_ctx
->tx_info
));
1589 /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
1590 * Useful when you want to change one particular aspect of the endpoint and then
1591 * issue a configure endpoint command.
1593 void xhci_endpoint_copy(struct xhci_hcd
*xhci
,
1594 struct xhci_container_ctx
*in_ctx
,
1595 struct xhci_container_ctx
*out_ctx
,
1596 unsigned int ep_index
)
1598 struct xhci_ep_ctx
*out_ep_ctx
;
1599 struct xhci_ep_ctx
*in_ep_ctx
;
1601 out_ep_ctx
= xhci_get_ep_ctx(xhci
, out_ctx
, ep_index
);
1602 in_ep_ctx
= xhci_get_ep_ctx(xhci
, in_ctx
, ep_index
);
1604 in_ep_ctx
->ep_info
= out_ep_ctx
->ep_info
;
1605 in_ep_ctx
->ep_info2
= out_ep_ctx
->ep_info2
;
1606 in_ep_ctx
->deq
= out_ep_ctx
->deq
;
1607 in_ep_ctx
->tx_info
= out_ep_ctx
->tx_info
;
1610 /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
1611 * Useful when you want to change one particular aspect of the endpoint and then
1612 * issue a configure endpoint command. Only the context entries field matters,
1613 * but we'll copy the whole thing anyway.
1615 void xhci_slot_copy(struct xhci_hcd
*xhci
,
1616 struct xhci_container_ctx
*in_ctx
,
1617 struct xhci_container_ctx
*out_ctx
)
1619 struct xhci_slot_ctx
*in_slot_ctx
;
1620 struct xhci_slot_ctx
*out_slot_ctx
;
1622 in_slot_ctx
= xhci_get_slot_ctx(xhci
, in_ctx
);
1623 out_slot_ctx
= xhci_get_slot_ctx(xhci
, out_ctx
);
1625 in_slot_ctx
->dev_info
= out_slot_ctx
->dev_info
;
1626 in_slot_ctx
->dev_info2
= out_slot_ctx
->dev_info2
;
1627 in_slot_ctx
->tt_info
= out_slot_ctx
->tt_info
;
1628 in_slot_ctx
->dev_state
= out_slot_ctx
->dev_state
;
1631 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
1632 static int scratchpad_alloc(struct xhci_hcd
*xhci
, gfp_t flags
)
1635 struct device
*dev
= xhci_to_hcd(xhci
)->self
.sysdev
;
1636 int num_sp
= HCS_MAX_SCRATCHPAD(xhci
->hcs_params2
);
1638 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
1639 "Allocating %d scratchpad buffers", num_sp
);
1644 xhci
->scratchpad
= kzalloc(sizeof(*xhci
->scratchpad
), flags
);
1645 if (!xhci
->scratchpad
)
1648 xhci
->scratchpad
->sp_array
= dma_alloc_coherent(dev
,
1649 num_sp
* sizeof(u64
),
1650 &xhci
->scratchpad
->sp_dma
, flags
);
1651 if (!xhci
->scratchpad
->sp_array
)
1654 xhci
->scratchpad
->sp_buffers
= kzalloc(sizeof(void *) * num_sp
, flags
);
1655 if (!xhci
->scratchpad
->sp_buffers
)
1658 xhci
->dcbaa
->dev_context_ptrs
[0] = cpu_to_le64(xhci
->scratchpad
->sp_dma
);
1659 for (i
= 0; i
< num_sp
; i
++) {
1661 void *buf
= dma_zalloc_coherent(dev
, xhci
->page_size
, &dma
,
1666 xhci
->scratchpad
->sp_array
[i
] = dma
;
1667 xhci
->scratchpad
->sp_buffers
[i
] = buf
;
1673 for (i
= i
- 1; i
>= 0; i
--) {
1674 dma_free_coherent(dev
, xhci
->page_size
,
1675 xhci
->scratchpad
->sp_buffers
[i
],
1676 xhci
->scratchpad
->sp_array
[i
]);
1679 kfree(xhci
->scratchpad
->sp_buffers
);
1682 dma_free_coherent(dev
, num_sp
* sizeof(u64
),
1683 xhci
->scratchpad
->sp_array
,
1684 xhci
->scratchpad
->sp_dma
);
1687 kfree(xhci
->scratchpad
);
1688 xhci
->scratchpad
= NULL
;
1694 static void scratchpad_free(struct xhci_hcd
*xhci
)
1698 struct device
*dev
= xhci_to_hcd(xhci
)->self
.sysdev
;
1700 if (!xhci
->scratchpad
)
1703 num_sp
= HCS_MAX_SCRATCHPAD(xhci
->hcs_params2
);
1705 for (i
= 0; i
< num_sp
; i
++) {
1706 dma_free_coherent(dev
, xhci
->page_size
,
1707 xhci
->scratchpad
->sp_buffers
[i
],
1708 xhci
->scratchpad
->sp_array
[i
]);
1710 kfree(xhci
->scratchpad
->sp_buffers
);
1711 dma_free_coherent(dev
, num_sp
* sizeof(u64
),
1712 xhci
->scratchpad
->sp_array
,
1713 xhci
->scratchpad
->sp_dma
);
1714 kfree(xhci
->scratchpad
);
1715 xhci
->scratchpad
= NULL
;
1718 struct xhci_command
*xhci_alloc_command(struct xhci_hcd
*xhci
,
1719 bool allocate_completion
, gfp_t mem_flags
)
1721 struct xhci_command
*command
;
1723 command
= kzalloc(sizeof(*command
), mem_flags
);
1727 if (allocate_completion
) {
1728 command
->completion
=
1729 kzalloc(sizeof(struct completion
), mem_flags
);
1730 if (!command
->completion
) {
1734 init_completion(command
->completion
);
1737 command
->status
= 0;
1738 INIT_LIST_HEAD(&command
->cmd_list
);
1742 struct xhci_command
*xhci_alloc_command_with_ctx(struct xhci_hcd
*xhci
,
1743 bool allocate_completion
, gfp_t mem_flags
)
1745 struct xhci_command
*command
;
1747 command
= xhci_alloc_command(xhci
, allocate_completion
, mem_flags
);
1751 command
->in_ctx
= xhci_alloc_container_ctx(xhci
, XHCI_CTX_TYPE_INPUT
,
1753 if (!command
->in_ctx
) {
1754 kfree(command
->completion
);
1761 void xhci_urb_free_priv(struct urb_priv
*urb_priv
)
1766 void xhci_free_command(struct xhci_hcd
*xhci
,
1767 struct xhci_command
*command
)
1769 xhci_free_container_ctx(xhci
,
1771 kfree(command
->completion
);
1775 int xhci_alloc_erst(struct xhci_hcd
*xhci
,
1776 struct xhci_ring
*evt_ring
,
1777 struct xhci_erst
*erst
,
1782 struct xhci_segment
*seg
;
1783 struct xhci_erst_entry
*entry
;
1785 size
= sizeof(struct xhci_erst_entry
) * evt_ring
->num_segs
;
1786 erst
->entries
= dma_zalloc_coherent(xhci_to_hcd(xhci
)->self
.sysdev
,
1787 size
, &erst
->erst_dma_addr
, flags
);
1791 erst
->num_entries
= evt_ring
->num_segs
;
1793 seg
= evt_ring
->first_seg
;
1794 for (val
= 0; val
< evt_ring
->num_segs
; val
++) {
1795 entry
= &erst
->entries
[val
];
1796 entry
->seg_addr
= cpu_to_le64(seg
->dma
);
1797 entry
->seg_size
= cpu_to_le32(TRBS_PER_SEGMENT
);
1805 void xhci_free_erst(struct xhci_hcd
*xhci
, struct xhci_erst
*erst
)
1808 struct device
*dev
= xhci_to_hcd(xhci
)->self
.sysdev
;
1810 size
= sizeof(struct xhci_erst_entry
) * (erst
->num_entries
);
1812 dma_free_coherent(dev
, size
,
1814 erst
->erst_dma_addr
);
1815 erst
->entries
= NULL
;
1818 void xhci_mem_cleanup(struct xhci_hcd
*xhci
)
1820 struct device
*dev
= xhci_to_hcd(xhci
)->self
.sysdev
;
1821 int i
, j
, num_ports
;
1823 cancel_delayed_work_sync(&xhci
->cmd_timer
);
1825 xhci_free_erst(xhci
, &xhci
->erst
);
1827 if (xhci
->event_ring
)
1828 xhci_ring_free(xhci
, xhci
->event_ring
);
1829 xhci
->event_ring
= NULL
;
1830 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "Freed event ring");
1832 if (xhci
->lpm_command
)
1833 xhci_free_command(xhci
, xhci
->lpm_command
);
1834 xhci
->lpm_command
= NULL
;
1836 xhci_ring_free(xhci
, xhci
->cmd_ring
);
1837 xhci
->cmd_ring
= NULL
;
1838 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "Freed command ring");
1839 xhci_cleanup_command_queue(xhci
);
1841 num_ports
= HCS_MAX_PORTS(xhci
->hcs_params1
);
1842 for (i
= 0; i
< num_ports
&& xhci
->rh_bw
; i
++) {
1843 struct xhci_interval_bw_table
*bwt
= &xhci
->rh_bw
[i
].bw_table
;
1844 for (j
= 0; j
< XHCI_MAX_INTERVAL
; j
++) {
1845 struct list_head
*ep
= &bwt
->interval_bw
[j
].endpoints
;
1846 while (!list_empty(ep
))
1847 list_del_init(ep
->next
);
1851 for (i
= HCS_MAX_SLOTS(xhci
->hcs_params1
); i
> 0; i
--)
1852 xhci_free_virt_devices_depth_first(xhci
, i
);
1854 dma_pool_destroy(xhci
->segment_pool
);
1855 xhci
->segment_pool
= NULL
;
1856 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "Freed segment pool");
1858 dma_pool_destroy(xhci
->device_pool
);
1859 xhci
->device_pool
= NULL
;
1860 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "Freed device context pool");
1862 dma_pool_destroy(xhci
->small_streams_pool
);
1863 xhci
->small_streams_pool
= NULL
;
1864 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
1865 "Freed small stream array pool");
1867 dma_pool_destroy(xhci
->medium_streams_pool
);
1868 xhci
->medium_streams_pool
= NULL
;
1869 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
1870 "Freed medium stream array pool");
1873 dma_free_coherent(dev
, sizeof(*xhci
->dcbaa
),
1874 xhci
->dcbaa
, xhci
->dcbaa
->dma
);
1877 scratchpad_free(xhci
);
1882 for (i
= 0; i
< num_ports
; i
++) {
1883 struct xhci_tt_bw_info
*tt
, *n
;
1884 list_for_each_entry_safe(tt
, n
, &xhci
->rh_bw
[i
].tts
, tt_list
) {
1885 list_del(&tt
->tt_list
);
1891 xhci
->cmd_ring_reserved_trbs
= 0;
1892 xhci
->usb2_rhub
.num_ports
= 0;
1893 xhci
->usb3_rhub
.num_ports
= 0;
1894 xhci
->num_active_eps
= 0;
1895 kfree(xhci
->usb2_rhub
.ports
);
1896 kfree(xhci
->usb3_rhub
.ports
);
1897 kfree(xhci
->hw_ports
);
1899 kfree(xhci
->ext_caps
);
1901 xhci
->usb2_rhub
.ports
= NULL
;
1902 xhci
->usb3_rhub
.ports
= NULL
;
1903 xhci
->hw_ports
= NULL
;
1905 xhci
->ext_caps
= NULL
;
1907 xhci
->page_size
= 0;
1908 xhci
->page_shift
= 0;
1909 xhci
->bus_state
[0].bus_suspended
= 0;
1910 xhci
->bus_state
[1].bus_suspended
= 0;
1913 static int xhci_test_trb_in_td(struct xhci_hcd
*xhci
,
1914 struct xhci_segment
*input_seg
,
1915 union xhci_trb
*start_trb
,
1916 union xhci_trb
*end_trb
,
1917 dma_addr_t input_dma
,
1918 struct xhci_segment
*result_seg
,
1919 char *test_name
, int test_number
)
1921 unsigned long long start_dma
;
1922 unsigned long long end_dma
;
1923 struct xhci_segment
*seg
;
1925 start_dma
= xhci_trb_virt_to_dma(input_seg
, start_trb
);
1926 end_dma
= xhci_trb_virt_to_dma(input_seg
, end_trb
);
1928 seg
= trb_in_td(xhci
, input_seg
, start_trb
, end_trb
, input_dma
, false);
1929 if (seg
!= result_seg
) {
1930 xhci_warn(xhci
, "WARN: %s TRB math test %d failed!\n",
1931 test_name
, test_number
);
1932 xhci_warn(xhci
, "Tested TRB math w/ seg %p and "
1933 "input DMA 0x%llx\n",
1935 (unsigned long long) input_dma
);
1936 xhci_warn(xhci
, "starting TRB %p (0x%llx DMA), "
1937 "ending TRB %p (0x%llx DMA)\n",
1938 start_trb
, start_dma
,
1940 xhci_warn(xhci
, "Expected seg %p, got seg %p\n",
1942 trb_in_td(xhci
, input_seg
, start_trb
, end_trb
, input_dma
,
1949 /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
1950 static int xhci_check_trb_in_td_math(struct xhci_hcd
*xhci
)
1953 dma_addr_t input_dma
;
1954 struct xhci_segment
*result_seg
;
1955 } simple_test_vector
[] = {
1956 /* A zeroed DMA field should fail */
1958 /* One TRB before the ring start should fail */
1959 { xhci
->event_ring
->first_seg
->dma
- 16, NULL
},
1960 /* One byte before the ring start should fail */
1961 { xhci
->event_ring
->first_seg
->dma
- 1, NULL
},
1962 /* Starting TRB should succeed */
1963 { xhci
->event_ring
->first_seg
->dma
, xhci
->event_ring
->first_seg
},
1964 /* Ending TRB should succeed */
1965 { xhci
->event_ring
->first_seg
->dma
+ (TRBS_PER_SEGMENT
- 1)*16,
1966 xhci
->event_ring
->first_seg
},
1967 /* One byte after the ring end should fail */
1968 { xhci
->event_ring
->first_seg
->dma
+ (TRBS_PER_SEGMENT
- 1)*16 + 1, NULL
},
1969 /* One TRB after the ring end should fail */
1970 { xhci
->event_ring
->first_seg
->dma
+ (TRBS_PER_SEGMENT
)*16, NULL
},
1971 /* An address of all ones should fail */
1972 { (dma_addr_t
) (~0), NULL
},
1975 struct xhci_segment
*input_seg
;
1976 union xhci_trb
*start_trb
;
1977 union xhci_trb
*end_trb
;
1978 dma_addr_t input_dma
;
1979 struct xhci_segment
*result_seg
;
1980 } complex_test_vector
[] = {
1981 /* Test feeding a valid DMA address from a different ring */
1982 { .input_seg
= xhci
->event_ring
->first_seg
,
1983 .start_trb
= xhci
->event_ring
->first_seg
->trbs
,
1984 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 1],
1985 .input_dma
= xhci
->cmd_ring
->first_seg
->dma
,
1988 /* Test feeding a valid end TRB from a different ring */
1989 { .input_seg
= xhci
->event_ring
->first_seg
,
1990 .start_trb
= xhci
->event_ring
->first_seg
->trbs
,
1991 .end_trb
= &xhci
->cmd_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 1],
1992 .input_dma
= xhci
->cmd_ring
->first_seg
->dma
,
1995 /* Test feeding a valid start and end TRB from a different ring */
1996 { .input_seg
= xhci
->event_ring
->first_seg
,
1997 .start_trb
= xhci
->cmd_ring
->first_seg
->trbs
,
1998 .end_trb
= &xhci
->cmd_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 1],
1999 .input_dma
= xhci
->cmd_ring
->first_seg
->dma
,
2002 /* TRB in this ring, but after this TD */
2003 { .input_seg
= xhci
->event_ring
->first_seg
,
2004 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[0],
2005 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[3],
2006 .input_dma
= xhci
->event_ring
->first_seg
->dma
+ 4*16,
2009 /* TRB in this ring, but before this TD */
2010 { .input_seg
= xhci
->event_ring
->first_seg
,
2011 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[3],
2012 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[6],
2013 .input_dma
= xhci
->event_ring
->first_seg
->dma
+ 2*16,
2016 /* TRB in this ring, but after this wrapped TD */
2017 { .input_seg
= xhci
->event_ring
->first_seg
,
2018 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 3],
2019 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[1],
2020 .input_dma
= xhci
->event_ring
->first_seg
->dma
+ 2*16,
2023 /* TRB in this ring, but before this wrapped TD */
2024 { .input_seg
= xhci
->event_ring
->first_seg
,
2025 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 3],
2026 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[1],
2027 .input_dma
= xhci
->event_ring
->first_seg
->dma
+ (TRBS_PER_SEGMENT
- 4)*16,
2030 /* TRB not in this ring, and we have a wrapped TD */
2031 { .input_seg
= xhci
->event_ring
->first_seg
,
2032 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 3],
2033 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[1],
2034 .input_dma
= xhci
->cmd_ring
->first_seg
->dma
+ 2*16,
2039 unsigned int num_tests
;
2042 num_tests
= ARRAY_SIZE(simple_test_vector
);
2043 for (i
= 0; i
< num_tests
; i
++) {
2044 ret
= xhci_test_trb_in_td(xhci
,
2045 xhci
->event_ring
->first_seg
,
2046 xhci
->event_ring
->first_seg
->trbs
,
2047 &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 1],
2048 simple_test_vector
[i
].input_dma
,
2049 simple_test_vector
[i
].result_seg
,
2055 num_tests
= ARRAY_SIZE(complex_test_vector
);
2056 for (i
= 0; i
< num_tests
; i
++) {
2057 ret
= xhci_test_trb_in_td(xhci
,
2058 complex_test_vector
[i
].input_seg
,
2059 complex_test_vector
[i
].start_trb
,
2060 complex_test_vector
[i
].end_trb
,
2061 complex_test_vector
[i
].input_dma
,
2062 complex_test_vector
[i
].result_seg
,
2067 xhci_dbg(xhci
, "TRB math tests passed.\n");
2071 static void xhci_set_hc_event_deq(struct xhci_hcd
*xhci
)
2076 deq
= xhci_trb_virt_to_dma(xhci
->event_ring
->deq_seg
,
2077 xhci
->event_ring
->dequeue
);
2078 if (deq
== 0 && !in_interrupt())
2079 xhci_warn(xhci
, "WARN something wrong with SW event ring "
2081 /* Update HC event ring dequeue pointer */
2082 temp
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
2083 temp
&= ERST_PTR_MASK
;
2084 /* Don't clear the EHB bit (which is RW1C) because
2085 * there might be more events to service.
2088 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2089 "// Write event ring dequeue pointer, "
2090 "preserving EHB bit");
2091 xhci_write_64(xhci
, ((u64
) deq
& (u64
) ~ERST_PTR_MASK
) | temp
,
2092 &xhci
->ir_set
->erst_dequeue
);
2095 static void xhci_add_in_port(struct xhci_hcd
*xhci
, unsigned int num_ports
,
2096 __le32 __iomem
*addr
, int max_caps
)
2098 u32 temp
, port_offset
, port_count
;
2100 u8 major_revision
, minor_revision
;
2101 struct xhci_hub
*rhub
;
2104 major_revision
= XHCI_EXT_PORT_MAJOR(temp
);
2105 minor_revision
= XHCI_EXT_PORT_MINOR(temp
);
2107 if (major_revision
== 0x03) {
2108 rhub
= &xhci
->usb3_rhub
;
2109 } else if (major_revision
<= 0x02) {
2110 rhub
= &xhci
->usb2_rhub
;
2112 xhci_warn(xhci
, "Ignoring unknown port speed, "
2113 "Ext Cap %p, revision = 0x%x\n",
2114 addr
, major_revision
);
2115 /* Ignoring port protocol we can't understand. FIXME */
2118 rhub
->maj_rev
= XHCI_EXT_PORT_MAJOR(temp
);
2120 if (rhub
->min_rev
< minor_revision
)
2121 rhub
->min_rev
= minor_revision
;
2123 /* Port offset and count in the third dword, see section 7.2 */
2124 temp
= readl(addr
+ 2);
2125 port_offset
= XHCI_EXT_PORT_OFF(temp
);
2126 port_count
= XHCI_EXT_PORT_COUNT(temp
);
2127 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2128 "Ext Cap %p, port offset = %u, "
2129 "count = %u, revision = 0x%x",
2130 addr
, port_offset
, port_count
, major_revision
);
2131 /* Port count includes the current port offset */
2132 if (port_offset
== 0 || (port_offset
+ port_count
- 1) > num_ports
)
2133 /* WTF? "Valid values are ‘1’ to MaxPorts" */
2136 rhub
->psi_count
= XHCI_EXT_PORT_PSIC(temp
);
2137 if (rhub
->psi_count
) {
2138 rhub
->psi
= kcalloc(rhub
->psi_count
, sizeof(*rhub
->psi
),
2141 rhub
->psi_count
= 0;
2143 rhub
->psi_uid_count
++;
2144 for (i
= 0; i
< rhub
->psi_count
; i
++) {
2145 rhub
->psi
[i
] = readl(addr
+ 4 + i
);
2147 /* count unique ID values, two consecutive entries can
2148 * have the same ID if link is assymetric
2150 if (i
&& (XHCI_EXT_PORT_PSIV(rhub
->psi
[i
]) !=
2151 XHCI_EXT_PORT_PSIV(rhub
->psi
[i
- 1])))
2152 rhub
->psi_uid_count
++;
2154 xhci_dbg(xhci
, "PSIV:%d PSIE:%d PLT:%d PFD:%d LP:%d PSIM:%d\n",
2155 XHCI_EXT_PORT_PSIV(rhub
->psi
[i
]),
2156 XHCI_EXT_PORT_PSIE(rhub
->psi
[i
]),
2157 XHCI_EXT_PORT_PLT(rhub
->psi
[i
]),
2158 XHCI_EXT_PORT_PFD(rhub
->psi
[i
]),
2159 XHCI_EXT_PORT_LP(rhub
->psi
[i
]),
2160 XHCI_EXT_PORT_PSIM(rhub
->psi
[i
]));
2163 /* cache usb2 port capabilities */
2164 if (major_revision
< 0x03 && xhci
->num_ext_caps
< max_caps
)
2165 xhci
->ext_caps
[xhci
->num_ext_caps
++] = temp
;
2167 /* Check the host's USB2 LPM capability */
2168 if ((xhci
->hci_version
== 0x96) && (major_revision
!= 0x03) &&
2169 (temp
& XHCI_L1C
)) {
2170 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2171 "xHCI 0.96: support USB2 software lpm");
2172 xhci
->sw_lpm_support
= 1;
2175 if ((xhci
->hci_version
>= 0x100) && (major_revision
!= 0x03)) {
2176 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2177 "xHCI 1.0: support USB2 software lpm");
2178 xhci
->sw_lpm_support
= 1;
2179 if (temp
& XHCI_HLC
) {
2180 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2181 "xHCI 1.0: support USB2 hardware lpm");
2182 xhci
->hw_lpm_support
= 1;
2187 for (i
= port_offset
; i
< (port_offset
+ port_count
); i
++) {
2188 struct xhci_port
*hw_port
= &xhci
->hw_ports
[i
];
2189 /* Duplicate entry. Ignore the port if the revisions differ. */
2190 if (hw_port
->rhub
) {
2191 xhci_warn(xhci
, "Duplicate port entry, Ext Cap %p,"
2192 " port %u\n", addr
, i
);
2193 xhci_warn(xhci
, "Port was marked as USB %u, "
2194 "duplicated as USB %u\n",
2195 hw_port
->rhub
->maj_rev
, major_revision
);
2196 /* Only adjust the roothub port counts if we haven't
2197 * found a similar duplicate.
2199 if (hw_port
->rhub
!= rhub
&&
2200 hw_port
->hcd_portnum
!= DUPLICATE_ENTRY
) {
2201 hw_port
->rhub
->num_ports
--;
2202 hw_port
->hcd_portnum
= DUPLICATE_ENTRY
;
2206 hw_port
->rhub
= rhub
;
2209 /* FIXME: Should we disable ports not in the Extended Capabilities? */
2212 static void xhci_create_rhub_port_array(struct xhci_hcd
*xhci
,
2213 struct xhci_hub
*rhub
, gfp_t flags
)
2218 if (!rhub
->num_ports
)
2220 rhub
->ports
= kcalloc(rhub
->num_ports
, sizeof(rhub
->ports
), flags
);
2221 for (i
= 0; i
< HCS_MAX_PORTS(xhci
->hcs_params1
); i
++) {
2222 if (xhci
->hw_ports
[i
].rhub
!= rhub
||
2223 xhci
->hw_ports
[i
].hcd_portnum
== DUPLICATE_ENTRY
)
2225 xhci
->hw_ports
[i
].hcd_portnum
= port_index
;
2226 rhub
->ports
[port_index
] = &xhci
->hw_ports
[i
];
2228 if (port_index
== rhub
->num_ports
)
2234 * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
2235 * specify what speeds each port is supposed to be. We can't count on the port
2236 * speed bits in the PORTSC register being correct until a device is connected,
2237 * but we need to set up the two fake roothubs with the correct number of USB
2238 * 3.0 and USB 2.0 ports at host controller initialization time.
2240 static int xhci_setup_port_arrays(struct xhci_hcd
*xhci
, gfp_t flags
)
2244 unsigned int num_ports
;
2249 num_ports
= HCS_MAX_PORTS(xhci
->hcs_params1
);
2250 xhci
->hw_ports
= kcalloc(num_ports
, sizeof(*xhci
->hw_ports
), flags
);
2251 if (!xhci
->hw_ports
)
2254 for (i
= 0; i
< num_ports
; i
++) {
2255 xhci
->hw_ports
[i
].addr
= &xhci
->op_regs
->port_status_base
+
2257 xhci
->hw_ports
[i
].hw_portnum
= i
;
2260 xhci
->rh_bw
= kzalloc(sizeof(*xhci
->rh_bw
)*num_ports
, flags
);
2263 for (i
= 0; i
< num_ports
; i
++) {
2264 struct xhci_interval_bw_table
*bw_table
;
2266 INIT_LIST_HEAD(&xhci
->rh_bw
[i
].tts
);
2267 bw_table
= &xhci
->rh_bw
[i
].bw_table
;
2268 for (j
= 0; j
< XHCI_MAX_INTERVAL
; j
++)
2269 INIT_LIST_HEAD(&bw_table
->interval_bw
[j
].endpoints
);
2271 base
= &xhci
->cap_regs
->hc_capbase
;
2273 cap_start
= xhci_find_next_ext_cap(base
, 0, XHCI_EXT_CAPS_PROTOCOL
);
2275 xhci_err(xhci
, "No Extended Capability registers, unable to set up roothub\n");
2280 /* count extended protocol capability entries for later caching */
2283 offset
= xhci_find_next_ext_cap(base
, offset
,
2284 XHCI_EXT_CAPS_PROTOCOL
);
2287 xhci
->ext_caps
= kzalloc(sizeof(*xhci
->ext_caps
) * cap_count
, flags
);
2288 if (!xhci
->ext_caps
)
2294 xhci_add_in_port(xhci
, num_ports
, base
+ offset
, cap_count
);
2295 if (xhci
->usb2_rhub
.num_ports
+ xhci
->usb3_rhub
.num_ports
==
2298 offset
= xhci_find_next_ext_cap(base
, offset
,
2299 XHCI_EXT_CAPS_PROTOCOL
);
2301 if (xhci
->usb2_rhub
.num_ports
== 0 && xhci
->usb3_rhub
.num_ports
== 0) {
2302 xhci_warn(xhci
, "No ports on the roothubs?\n");
2305 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2306 "Found %u USB 2.0 ports and %u USB 3.0 ports.",
2307 xhci
->usb2_rhub
.num_ports
, xhci
->usb3_rhub
.num_ports
);
2309 /* Place limits on the number of roothub ports so that the hub
2310 * descriptors aren't longer than the USB core will allocate.
2312 if (xhci
->usb3_rhub
.num_ports
> USB_SS_MAXPORTS
) {
2313 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2314 "Limiting USB 3.0 roothub ports to %u.",
2316 xhci
->usb3_rhub
.num_ports
= USB_SS_MAXPORTS
;
2318 if (xhci
->usb2_rhub
.num_ports
> USB_MAXCHILDREN
) {
2319 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2320 "Limiting USB 2.0 roothub ports to %u.",
2322 xhci
->usb2_rhub
.num_ports
= USB_MAXCHILDREN
;
2326 * Note we could have all USB 3.0 ports, or all USB 2.0 ports.
2327 * Not sure how the USB core will handle a hub with no ports...
2330 xhci_create_rhub_port_array(xhci
, &xhci
->usb2_rhub
, flags
);
2331 xhci_create_rhub_port_array(xhci
, &xhci
->usb3_rhub
, flags
);
2336 int xhci_mem_init(struct xhci_hcd
*xhci
, gfp_t flags
)
2339 struct device
*dev
= xhci_to_hcd(xhci
)->self
.sysdev
;
2340 unsigned int val
, val2
;
2342 u32 page_size
, temp
;
2345 INIT_LIST_HEAD(&xhci
->cmd_list
);
2347 /* init command timeout work */
2348 INIT_DELAYED_WORK(&xhci
->cmd_timer
, xhci_handle_command_timeout
);
2349 init_completion(&xhci
->cmd_ring_stop_completion
);
2351 page_size
= readl(&xhci
->op_regs
->page_size
);
2352 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2353 "Supported page size register = 0x%x", page_size
);
2354 for (i
= 0; i
< 16; i
++) {
2355 if ((0x1 & page_size
) != 0)
2357 page_size
= page_size
>> 1;
2360 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2361 "Supported page size of %iK", (1 << (i
+12)) / 1024);
2363 xhci_warn(xhci
, "WARN: no supported page size\n");
2364 /* Use 4K pages, since that's common and the minimum the HC supports */
2365 xhci
->page_shift
= 12;
2366 xhci
->page_size
= 1 << xhci
->page_shift
;
2367 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2368 "HCD page size set to %iK", xhci
->page_size
/ 1024);
2371 * Program the Number of Device Slots Enabled field in the CONFIG
2372 * register with the max value of slots the HC can handle.
2374 val
= HCS_MAX_SLOTS(readl(&xhci
->cap_regs
->hcs_params1
));
2375 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2376 "// xHC can handle at most %d device slots.", val
);
2377 val2
= readl(&xhci
->op_regs
->config_reg
);
2378 val
|= (val2
& ~HCS_SLOTS_MASK
);
2379 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2380 "// Setting Max device slots reg = 0x%x.", val
);
2381 writel(val
, &xhci
->op_regs
->config_reg
);
2384 * xHCI section 5.4.6 - doorbell array must be
2385 * "physically contiguous and 64-byte (cache line) aligned".
2387 xhci
->dcbaa
= dma_alloc_coherent(dev
, sizeof(*xhci
->dcbaa
), &dma
,
2391 memset(xhci
->dcbaa
, 0, sizeof *(xhci
->dcbaa
));
2392 xhci
->dcbaa
->dma
= dma
;
2393 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2394 "// Device context base array address = 0x%llx (DMA), %p (virt)",
2395 (unsigned long long)xhci
->dcbaa
->dma
, xhci
->dcbaa
);
2396 xhci_write_64(xhci
, dma
, &xhci
->op_regs
->dcbaa_ptr
);
2399 * Initialize the ring segment pool. The ring must be a contiguous
2400 * structure comprised of TRBs. The TRBs must be 16 byte aligned,
2401 * however, the command ring segment needs 64-byte aligned segments
2402 * and our use of dma addresses in the trb_address_map radix tree needs
2403 * TRB_SEGMENT_SIZE alignment, so we pick the greater alignment need.
2405 xhci
->segment_pool
= dma_pool_create("xHCI ring segments", dev
,
2406 TRB_SEGMENT_SIZE
, TRB_SEGMENT_SIZE
, xhci
->page_size
);
2408 /* See Table 46 and Note on Figure 55 */
2409 xhci
->device_pool
= dma_pool_create("xHCI input/output contexts", dev
,
2410 2112, 64, xhci
->page_size
);
2411 if (!xhci
->segment_pool
|| !xhci
->device_pool
)
2414 /* Linear stream context arrays don't have any boundary restrictions,
2415 * and only need to be 16-byte aligned.
2417 xhci
->small_streams_pool
=
2418 dma_pool_create("xHCI 256 byte stream ctx arrays",
2419 dev
, SMALL_STREAM_ARRAY_SIZE
, 16, 0);
2420 xhci
->medium_streams_pool
=
2421 dma_pool_create("xHCI 1KB stream ctx arrays",
2422 dev
, MEDIUM_STREAM_ARRAY_SIZE
, 16, 0);
2423 /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE
2424 * will be allocated with dma_alloc_coherent()
2427 if (!xhci
->small_streams_pool
|| !xhci
->medium_streams_pool
)
2430 /* Set up the command ring to have one segments for now. */
2431 xhci
->cmd_ring
= xhci_ring_alloc(xhci
, 1, 1, TYPE_COMMAND
, 0, flags
);
2432 if (!xhci
->cmd_ring
)
2434 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2435 "Allocated command ring at %p", xhci
->cmd_ring
);
2436 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "First segment DMA is 0x%llx",
2437 (unsigned long long)xhci
->cmd_ring
->first_seg
->dma
);
2439 /* Set the address in the Command Ring Control register */
2440 val_64
= xhci_read_64(xhci
, &xhci
->op_regs
->cmd_ring
);
2441 val_64
= (val_64
& (u64
) CMD_RING_RSVD_BITS
) |
2442 (xhci
->cmd_ring
->first_seg
->dma
& (u64
) ~CMD_RING_RSVD_BITS
) |
2443 xhci
->cmd_ring
->cycle_state
;
2444 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2445 "// Setting command ring address to 0x%016llx", val_64
);
2446 xhci_write_64(xhci
, val_64
, &xhci
->op_regs
->cmd_ring
);
2448 xhci
->lpm_command
= xhci_alloc_command_with_ctx(xhci
, true, flags
);
2449 if (!xhci
->lpm_command
)
2452 /* Reserve one command ring TRB for disabling LPM.
2453 * Since the USB core grabs the shared usb_bus bandwidth mutex before
2454 * disabling LPM, we only need to reserve one TRB for all devices.
2456 xhci
->cmd_ring_reserved_trbs
++;
2458 val
= readl(&xhci
->cap_regs
->db_off
);
2460 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2461 "// Doorbell array is located at offset 0x%x"
2462 " from cap regs base addr", val
);
2463 xhci
->dba
= (void __iomem
*) xhci
->cap_regs
+ val
;
2464 /* Set ir_set to interrupt register set 0 */
2465 xhci
->ir_set
= &xhci
->run_regs
->ir_set
[0];
2468 * Event ring setup: Allocate a normal ring, but also setup
2469 * the event ring segment table (ERST). Section 4.9.3.
2471 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "// Allocating event ring");
2472 xhci
->event_ring
= xhci_ring_alloc(xhci
, ERST_NUM_SEGS
, 1, TYPE_EVENT
,
2474 if (!xhci
->event_ring
)
2476 if (xhci_check_trb_in_td_math(xhci
) < 0)
2479 ret
= xhci_alloc_erst(xhci
, xhci
->event_ring
, &xhci
->erst
, flags
);
2483 /* set ERST count with the number of entries in the segment table */
2484 val
= readl(&xhci
->ir_set
->erst_size
);
2485 val
&= ERST_SIZE_MASK
;
2486 val
|= ERST_NUM_SEGS
;
2487 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2488 "// Write ERST size = %i to ir_set 0 (some bits preserved)",
2490 writel(val
, &xhci
->ir_set
->erst_size
);
2492 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2493 "// Set ERST entries to point to event ring.");
2494 /* set the segment table base address */
2495 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2496 "// Set ERST base address for ir_set 0 = 0x%llx",
2497 (unsigned long long)xhci
->erst
.erst_dma_addr
);
2498 val_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_base
);
2499 val_64
&= ERST_PTR_MASK
;
2500 val_64
|= (xhci
->erst
.erst_dma_addr
& (u64
) ~ERST_PTR_MASK
);
2501 xhci_write_64(xhci
, val_64
, &xhci
->ir_set
->erst_base
);
2503 /* Set the event ring dequeue address */
2504 xhci_set_hc_event_deq(xhci
);
2505 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2506 "Wrote ERST address to ir_set 0.");
2509 * XXX: Might need to set the Interrupter Moderation Register to
2510 * something other than the default (~1ms minimum between interrupts).
2511 * See section 5.5.1.2.
2513 for (i
= 0; i
< MAX_HC_SLOTS
; i
++)
2514 xhci
->devs
[i
] = NULL
;
2515 for (i
= 0; i
< USB_MAXCHILDREN
; i
++) {
2516 xhci
->bus_state
[0].resume_done
[i
] = 0;
2517 xhci
->bus_state
[1].resume_done
[i
] = 0;
2518 /* Only the USB 2.0 completions will ever be used. */
2519 init_completion(&xhci
->bus_state
[1].rexit_done
[i
]);
2522 if (scratchpad_alloc(xhci
, flags
))
2524 if (xhci_setup_port_arrays(xhci
, flags
))
2527 /* Enable USB 3.0 device notifications for function remote wake, which
2528 * is necessary for allowing USB 3.0 devices to do remote wakeup from
2529 * U3 (device suspend).
2531 temp
= readl(&xhci
->op_regs
->dev_notification
);
2532 temp
&= ~DEV_NOTE_MASK
;
2533 temp
|= DEV_NOTE_FWAKE
;
2534 writel(temp
, &xhci
->op_regs
->dev_notification
);
2541 xhci_mem_cleanup(xhci
);