1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
11 #include <linux/usb.h>
12 #include <linux/pci.h>
13 #include <linux/slab.h>
14 #include <linux/dmapool.h>
15 #include <linux/dma-mapping.h>
18 #include "xhci-trace.h"
19 #include "xhci-debugfs.h"
22 * Allocates a generic ring segment from the ring pool, sets the dma address,
23 * initializes the segment to zero, and sets the private next pointer to NULL.
26 * "All components of all Command and Transfer TRBs shall be initialized to '0'"
28 static struct xhci_segment
*xhci_segment_alloc(struct xhci_hcd
*xhci
,
29 unsigned int cycle_state
,
30 unsigned int max_packet
,
33 struct xhci_segment
*seg
;
37 seg
= kzalloc(sizeof *seg
, flags
);
41 seg
->trbs
= dma_pool_zalloc(xhci
->segment_pool
, flags
, &dma
);
48 seg
->bounce_buf
= kzalloc(max_packet
, flags
);
49 if (!seg
->bounce_buf
) {
50 dma_pool_free(xhci
->segment_pool
, seg
->trbs
, dma
);
55 /* If the cycle state is 0, set the cycle bit to 1 for all the TRBs */
56 if (cycle_state
== 0) {
57 for (i
= 0; i
< TRBS_PER_SEGMENT
; i
++)
58 seg
->trbs
[i
].link
.control
|= cpu_to_le32(TRB_CYCLE
);
66 static void xhci_segment_free(struct xhci_hcd
*xhci
, struct xhci_segment
*seg
)
69 dma_pool_free(xhci
->segment_pool
, seg
->trbs
, seg
->dma
);
72 kfree(seg
->bounce_buf
);
76 static void xhci_free_segments_for_ring(struct xhci_hcd
*xhci
,
77 struct xhci_segment
*first
)
79 struct xhci_segment
*seg
;
82 while (seg
!= first
) {
83 struct xhci_segment
*next
= seg
->next
;
84 xhci_segment_free(xhci
, seg
);
87 xhci_segment_free(xhci
, first
);
91 * Make the prev segment point to the next segment.
93 * Change the last TRB in the prev segment to be a Link TRB which points to the
94 * DMA address of the next segment. The caller needs to set any Link TRB
95 * related flags, such as End TRB, Toggle Cycle, and no snoop.
97 static void xhci_link_segments(struct xhci_hcd
*xhci
, struct xhci_segment
*prev
,
98 struct xhci_segment
*next
, enum xhci_ring_type type
)
105 if (type
!= TYPE_EVENT
) {
106 prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.segment_ptr
=
107 cpu_to_le64(next
->dma
);
109 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
110 val
= le32_to_cpu(prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
);
111 val
&= ~TRB_TYPE_BITMASK
;
112 val
|= TRB_TYPE(TRB_LINK
);
113 /* Always set the chain bit with 0.95 hardware */
114 /* Set chain bit for isoc rings on AMD 0.96 host */
115 if (xhci_link_trb_quirk(xhci
) ||
116 (type
== TYPE_ISOC
&&
117 (xhci
->quirks
& XHCI_AMD_0x96_HOST
)))
119 prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
= cpu_to_le32(val
);
124 * Link the ring to the new segments.
125 * Set Toggle Cycle for the new ring if needed.
127 static void xhci_link_rings(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
128 struct xhci_segment
*first
, struct xhci_segment
*last
,
129 unsigned int num_segs
)
131 struct xhci_segment
*next
;
133 if (!ring
|| !first
|| !last
)
136 next
= ring
->enq_seg
->next
;
137 xhci_link_segments(xhci
, ring
->enq_seg
, first
, ring
->type
);
138 xhci_link_segments(xhci
, last
, next
, ring
->type
);
139 ring
->num_segs
+= num_segs
;
140 ring
->num_trbs_free
+= (TRBS_PER_SEGMENT
- 1) * num_segs
;
142 if (ring
->type
!= TYPE_EVENT
&& ring
->enq_seg
== ring
->last_seg
) {
143 ring
->last_seg
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
144 &= ~cpu_to_le32(LINK_TOGGLE
);
145 last
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
146 |= cpu_to_le32(LINK_TOGGLE
);
147 ring
->last_seg
= last
;
152 * We need a radix tree for mapping physical addresses of TRBs to which stream
153 * ID they belong to. We need to do this because the host controller won't tell
154 * us which stream ring the TRB came from. We could store the stream ID in an
155 * event data TRB, but that doesn't help us for the cancellation case, since the
156 * endpoint may stop before it reaches that event data TRB.
158 * The radix tree maps the upper portion of the TRB DMA address to a ring
159 * segment that has the same upper portion of DMA addresses. For example, say I
160 * have segments of size 1KB, that are always 1KB aligned. A segment may
161 * start at 0x10c91000 and end at 0x10c913f0. If I use the upper 10 bits, the
162 * key to the stream ID is 0x43244. I can use the DMA address of the TRB to
163 * pass the radix tree a key to get the right stream ID:
165 * 0x10c90fff >> 10 = 0x43243
166 * 0x10c912c0 >> 10 = 0x43244
167 * 0x10c91400 >> 10 = 0x43245
169 * Obviously, only those TRBs with DMA addresses that are within the segment
170 * will make the radix tree return the stream ID for that ring.
172 * Caveats for the radix tree:
174 * The radix tree uses an unsigned long as a key pair. On 32-bit systems, an
175 * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
176 * 64-bits. Since we only request 32-bit DMA addresses, we can use that as the
177 * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
178 * PCI DMA addresses on a 64-bit system). There might be a problem on 32-bit
179 * extended systems (where the DMA address can be bigger than 32-bits),
180 * if we allow the PCI dma mask to be bigger than 32-bits. So don't do that.
182 static int xhci_insert_segment_mapping(struct radix_tree_root
*trb_address_map
,
183 struct xhci_ring
*ring
,
184 struct xhci_segment
*seg
,
190 key
= (unsigned long)(seg
->dma
>> TRB_SEGMENT_SHIFT
);
191 /* Skip any segments that were already added. */
192 if (radix_tree_lookup(trb_address_map
, key
))
195 ret
= radix_tree_maybe_preload(mem_flags
);
198 ret
= radix_tree_insert(trb_address_map
,
200 radix_tree_preload_end();
204 static void xhci_remove_segment_mapping(struct radix_tree_root
*trb_address_map
,
205 struct xhci_segment
*seg
)
209 key
= (unsigned long)(seg
->dma
>> TRB_SEGMENT_SHIFT
);
210 if (radix_tree_lookup(trb_address_map
, key
))
211 radix_tree_delete(trb_address_map
, key
);
214 static int xhci_update_stream_segment_mapping(
215 struct radix_tree_root
*trb_address_map
,
216 struct xhci_ring
*ring
,
217 struct xhci_segment
*first_seg
,
218 struct xhci_segment
*last_seg
,
221 struct xhci_segment
*seg
;
222 struct xhci_segment
*failed_seg
;
225 if (WARN_ON_ONCE(trb_address_map
== NULL
))
230 ret
= xhci_insert_segment_mapping(trb_address_map
,
231 ring
, seg
, mem_flags
);
237 } while (seg
!= first_seg
);
245 xhci_remove_segment_mapping(trb_address_map
, seg
);
246 if (seg
== failed_seg
)
249 } while (seg
!= first_seg
);
254 static void xhci_remove_stream_mapping(struct xhci_ring
*ring
)
256 struct xhci_segment
*seg
;
258 if (WARN_ON_ONCE(ring
->trb_address_map
== NULL
))
261 seg
= ring
->first_seg
;
263 xhci_remove_segment_mapping(ring
->trb_address_map
, seg
);
265 } while (seg
!= ring
->first_seg
);
268 static int xhci_update_stream_mapping(struct xhci_ring
*ring
, gfp_t mem_flags
)
270 return xhci_update_stream_segment_mapping(ring
->trb_address_map
, ring
,
271 ring
->first_seg
, ring
->last_seg
, mem_flags
);
274 /* XXX: Do we need the hcd structure in all these functions? */
275 void xhci_ring_free(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
)
280 trace_xhci_ring_free(ring
);
282 if (ring
->first_seg
) {
283 if (ring
->type
== TYPE_STREAM
)
284 xhci_remove_stream_mapping(ring
);
285 xhci_free_segments_for_ring(xhci
, ring
->first_seg
);
291 static void xhci_initialize_ring_info(struct xhci_ring
*ring
,
292 unsigned int cycle_state
)
294 /* The ring is empty, so the enqueue pointer == dequeue pointer */
295 ring
->enqueue
= ring
->first_seg
->trbs
;
296 ring
->enq_seg
= ring
->first_seg
;
297 ring
->dequeue
= ring
->enqueue
;
298 ring
->deq_seg
= ring
->first_seg
;
299 /* The ring is initialized to 0. The producer must write 1 to the cycle
300 * bit to handover ownership of the TRB, so PCS = 1. The consumer must
301 * compare CCS to the cycle bit to check ownership, so CCS = 1.
303 * New rings are initialized with cycle state equal to 1; if we are
304 * handling ring expansion, set the cycle state equal to the old ring.
306 ring
->cycle_state
= cycle_state
;
309 * Each segment has a link TRB, and leave an extra TRB for SW
312 ring
->num_trbs_free
= ring
->num_segs
* (TRBS_PER_SEGMENT
- 1) - 1;
315 /* Allocate segments and link them for a ring */
316 static int xhci_alloc_segments_for_ring(struct xhci_hcd
*xhci
,
317 struct xhci_segment
**first
, struct xhci_segment
**last
,
318 unsigned int num_segs
, unsigned int cycle_state
,
319 enum xhci_ring_type type
, unsigned int max_packet
, gfp_t flags
)
321 struct xhci_segment
*prev
;
323 prev
= xhci_segment_alloc(xhci
, cycle_state
, max_packet
, flags
);
329 while (num_segs
> 0) {
330 struct xhci_segment
*next
;
332 next
= xhci_segment_alloc(xhci
, cycle_state
, max_packet
, flags
);
337 xhci_segment_free(xhci
, prev
);
342 xhci_link_segments(xhci
, prev
, next
, type
);
347 xhci_link_segments(xhci
, prev
, *first
, type
);
354 * Create a new ring with zero or more segments.
356 * Link each segment together into a ring.
357 * Set the end flag and the cycle toggle bit on the last segment.
358 * See section 4.9.1 and figures 15 and 16.
360 struct xhci_ring
*xhci_ring_alloc(struct xhci_hcd
*xhci
,
361 unsigned int num_segs
, unsigned int cycle_state
,
362 enum xhci_ring_type type
, unsigned int max_packet
, gfp_t flags
)
364 struct xhci_ring
*ring
;
367 ring
= kzalloc(sizeof *(ring
), flags
);
371 ring
->num_segs
= num_segs
;
372 ring
->bounce_buf_len
= max_packet
;
373 INIT_LIST_HEAD(&ring
->td_list
);
378 ret
= xhci_alloc_segments_for_ring(xhci
, &ring
->first_seg
,
379 &ring
->last_seg
, num_segs
, cycle_state
, type
,
384 /* Only event ring does not use link TRB */
385 if (type
!= TYPE_EVENT
) {
386 /* See section 4.9.2.1 and 6.4.4.1 */
387 ring
->last_seg
->trbs
[TRBS_PER_SEGMENT
- 1].link
.control
|=
388 cpu_to_le32(LINK_TOGGLE
);
390 xhci_initialize_ring_info(ring
, cycle_state
);
391 trace_xhci_ring_alloc(ring
);
399 void xhci_free_endpoint_ring(struct xhci_hcd
*xhci
,
400 struct xhci_virt_device
*virt_dev
,
401 unsigned int ep_index
)
403 xhci_ring_free(xhci
, virt_dev
->eps
[ep_index
].ring
);
404 virt_dev
->eps
[ep_index
].ring
= NULL
;
408 * Expand an existing ring.
409 * Allocate a new ring which has same segment numbers and link the two rings.
411 int xhci_ring_expansion(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
412 unsigned int num_trbs
, gfp_t flags
)
414 struct xhci_segment
*first
;
415 struct xhci_segment
*last
;
416 unsigned int num_segs
;
417 unsigned int num_segs_needed
;
420 num_segs_needed
= (num_trbs
+ (TRBS_PER_SEGMENT
- 1) - 1) /
421 (TRBS_PER_SEGMENT
- 1);
423 /* Allocate number of segments we needed, or double the ring size */
424 num_segs
= ring
->num_segs
> num_segs_needed
?
425 ring
->num_segs
: num_segs_needed
;
427 ret
= xhci_alloc_segments_for_ring(xhci
, &first
, &last
,
428 num_segs
, ring
->cycle_state
, ring
->type
,
429 ring
->bounce_buf_len
, flags
);
433 if (ring
->type
== TYPE_STREAM
)
434 ret
= xhci_update_stream_segment_mapping(ring
->trb_address_map
,
435 ring
, first
, last
, flags
);
437 struct xhci_segment
*next
;
440 xhci_segment_free(xhci
, first
);
448 xhci_link_rings(xhci
, ring
, first
, last
, num_segs
);
449 trace_xhci_ring_expansion(ring
);
450 xhci_dbg_trace(xhci
, trace_xhci_dbg_ring_expansion
,
451 "ring expansion succeed, now has %d segments",
457 struct xhci_container_ctx
*xhci_alloc_container_ctx(struct xhci_hcd
*xhci
,
458 int type
, gfp_t flags
)
460 struct xhci_container_ctx
*ctx
;
462 if ((type
!= XHCI_CTX_TYPE_DEVICE
) && (type
!= XHCI_CTX_TYPE_INPUT
))
465 ctx
= kzalloc(sizeof(*ctx
), flags
);
470 ctx
->size
= HCC_64BYTE_CONTEXT(xhci
->hcc_params
) ? 2048 : 1024;
471 if (type
== XHCI_CTX_TYPE_INPUT
)
472 ctx
->size
+= CTX_SIZE(xhci
->hcc_params
);
474 ctx
->bytes
= dma_pool_zalloc(xhci
->device_pool
, flags
, &ctx
->dma
);
482 void xhci_free_container_ctx(struct xhci_hcd
*xhci
,
483 struct xhci_container_ctx
*ctx
)
487 dma_pool_free(xhci
->device_pool
, ctx
->bytes
, ctx
->dma
);
491 struct xhci_input_control_ctx
*xhci_get_input_control_ctx(
492 struct xhci_container_ctx
*ctx
)
494 if (ctx
->type
!= XHCI_CTX_TYPE_INPUT
)
497 return (struct xhci_input_control_ctx
*)ctx
->bytes
;
500 struct xhci_slot_ctx
*xhci_get_slot_ctx(struct xhci_hcd
*xhci
,
501 struct xhci_container_ctx
*ctx
)
503 if (ctx
->type
== XHCI_CTX_TYPE_DEVICE
)
504 return (struct xhci_slot_ctx
*)ctx
->bytes
;
506 return (struct xhci_slot_ctx
*)
507 (ctx
->bytes
+ CTX_SIZE(xhci
->hcc_params
));
510 struct xhci_ep_ctx
*xhci_get_ep_ctx(struct xhci_hcd
*xhci
,
511 struct xhci_container_ctx
*ctx
,
512 unsigned int ep_index
)
514 /* increment ep index by offset of start of ep ctx array */
516 if (ctx
->type
== XHCI_CTX_TYPE_INPUT
)
519 return (struct xhci_ep_ctx
*)
520 (ctx
->bytes
+ (ep_index
* CTX_SIZE(xhci
->hcc_params
)));
524 /***************** Streams structures manipulation *************************/
526 static void xhci_free_stream_ctx(struct xhci_hcd
*xhci
,
527 unsigned int num_stream_ctxs
,
528 struct xhci_stream_ctx
*stream_ctx
, dma_addr_t dma
)
530 struct device
*dev
= xhci_to_hcd(xhci
)->self
.sysdev
;
531 size_t size
= sizeof(struct xhci_stream_ctx
) * num_stream_ctxs
;
533 if (size
> MEDIUM_STREAM_ARRAY_SIZE
)
534 dma_free_coherent(dev
, size
,
536 else if (size
<= SMALL_STREAM_ARRAY_SIZE
)
537 return dma_pool_free(xhci
->small_streams_pool
,
540 return dma_pool_free(xhci
->medium_streams_pool
,
545 * The stream context array for each endpoint with bulk streams enabled can
546 * vary in size, based on:
547 * - how many streams the endpoint supports,
548 * - the maximum primary stream array size the host controller supports,
549 * - and how many streams the device driver asks for.
551 * The stream context array must be a power of 2, and can be as small as
552 * 64 bytes or as large as 1MB.
554 static struct xhci_stream_ctx
*xhci_alloc_stream_ctx(struct xhci_hcd
*xhci
,
555 unsigned int num_stream_ctxs
, dma_addr_t
*dma
,
558 struct device
*dev
= xhci_to_hcd(xhci
)->self
.sysdev
;
559 size_t size
= sizeof(struct xhci_stream_ctx
) * num_stream_ctxs
;
561 if (size
> MEDIUM_STREAM_ARRAY_SIZE
)
562 return dma_alloc_coherent(dev
, size
,
564 else if (size
<= SMALL_STREAM_ARRAY_SIZE
)
565 return dma_pool_alloc(xhci
->small_streams_pool
,
568 return dma_pool_alloc(xhci
->medium_streams_pool
,
572 struct xhci_ring
*xhci_dma_to_transfer_ring(
573 struct xhci_virt_ep
*ep
,
576 if (ep
->ep_state
& EP_HAS_STREAMS
)
577 return radix_tree_lookup(&ep
->stream_info
->trb_address_map
,
578 address
>> TRB_SEGMENT_SHIFT
);
582 struct xhci_ring
*xhci_stream_id_to_ring(
583 struct xhci_virt_device
*dev
,
584 unsigned int ep_index
,
585 unsigned int stream_id
)
587 struct xhci_virt_ep
*ep
= &dev
->eps
[ep_index
];
591 if (!ep
->stream_info
)
594 if (stream_id
>= ep
->stream_info
->num_streams
)
596 return ep
->stream_info
->stream_rings
[stream_id
];
600 * Change an endpoint's internal structure so it supports stream IDs. The
601 * number of requested streams includes stream 0, which cannot be used by device
604 * The number of stream contexts in the stream context array may be bigger than
605 * the number of streams the driver wants to use. This is because the number of
606 * stream context array entries must be a power of two.
608 struct xhci_stream_info
*xhci_alloc_stream_info(struct xhci_hcd
*xhci
,
609 unsigned int num_stream_ctxs
,
610 unsigned int num_streams
,
611 unsigned int max_packet
, gfp_t mem_flags
)
613 struct xhci_stream_info
*stream_info
;
615 struct xhci_ring
*cur_ring
;
619 xhci_dbg(xhci
, "Allocating %u streams and %u "
620 "stream context array entries.\n",
621 num_streams
, num_stream_ctxs
);
622 if (xhci
->cmd_ring_reserved_trbs
== MAX_RSVD_CMD_TRBS
) {
623 xhci_dbg(xhci
, "Command ring has no reserved TRBs available\n");
626 xhci
->cmd_ring_reserved_trbs
++;
628 stream_info
= kzalloc(sizeof(struct xhci_stream_info
), mem_flags
);
632 stream_info
->num_streams
= num_streams
;
633 stream_info
->num_stream_ctxs
= num_stream_ctxs
;
635 /* Initialize the array of virtual pointers to stream rings. */
636 stream_info
->stream_rings
= kzalloc(
637 sizeof(struct xhci_ring
*)*num_streams
,
639 if (!stream_info
->stream_rings
)
642 /* Initialize the array of DMA addresses for stream rings for the HW. */
643 stream_info
->stream_ctx_array
= xhci_alloc_stream_ctx(xhci
,
644 num_stream_ctxs
, &stream_info
->ctx_array_dma
,
646 if (!stream_info
->stream_ctx_array
)
648 memset(stream_info
->stream_ctx_array
, 0,
649 sizeof(struct xhci_stream_ctx
)*num_stream_ctxs
);
651 /* Allocate everything needed to free the stream rings later */
652 stream_info
->free_streams_command
=
653 xhci_alloc_command(xhci
, true, true, mem_flags
);
654 if (!stream_info
->free_streams_command
)
657 INIT_RADIX_TREE(&stream_info
->trb_address_map
, GFP_ATOMIC
);
659 /* Allocate rings for all the streams that the driver will use,
660 * and add their segment DMA addresses to the radix tree.
661 * Stream 0 is reserved.
664 for (cur_stream
= 1; cur_stream
< num_streams
; cur_stream
++) {
665 stream_info
->stream_rings
[cur_stream
] =
666 xhci_ring_alloc(xhci
, 2, 1, TYPE_STREAM
, max_packet
,
668 cur_ring
= stream_info
->stream_rings
[cur_stream
];
671 cur_ring
->stream_id
= cur_stream
;
672 cur_ring
->trb_address_map
= &stream_info
->trb_address_map
;
673 /* Set deq ptr, cycle bit, and stream context type */
674 addr
= cur_ring
->first_seg
->dma
|
675 SCT_FOR_CTX(SCT_PRI_TR
) |
676 cur_ring
->cycle_state
;
677 stream_info
->stream_ctx_array
[cur_stream
].stream_ring
=
679 xhci_dbg(xhci
, "Setting stream %d ring ptr to 0x%08llx\n",
680 cur_stream
, (unsigned long long) addr
);
682 ret
= xhci_update_stream_mapping(cur_ring
, mem_flags
);
684 xhci_ring_free(xhci
, cur_ring
);
685 stream_info
->stream_rings
[cur_stream
] = NULL
;
689 /* Leave the other unused stream ring pointers in the stream context
690 * array initialized to zero. This will cause the xHC to give us an
691 * error if the device asks for a stream ID we don't have setup (if it
692 * was any other way, the host controller would assume the ring is
693 * "empty" and wait forever for data to be queued to that stream ID).
699 for (cur_stream
= 1; cur_stream
< num_streams
; cur_stream
++) {
700 cur_ring
= stream_info
->stream_rings
[cur_stream
];
702 xhci_ring_free(xhci
, cur_ring
);
703 stream_info
->stream_rings
[cur_stream
] = NULL
;
706 xhci_free_command(xhci
, stream_info
->free_streams_command
);
708 kfree(stream_info
->stream_rings
);
712 xhci
->cmd_ring_reserved_trbs
--;
716 * Sets the MaxPStreams field and the Linear Stream Array field.
717 * Sets the dequeue pointer to the stream context array.
719 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd
*xhci
,
720 struct xhci_ep_ctx
*ep_ctx
,
721 struct xhci_stream_info
*stream_info
)
723 u32 max_primary_streams
;
724 /* MaxPStreams is the number of stream context array entries, not the
725 * number we're actually using. Must be in 2^(MaxPstreams + 1) format.
726 * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
728 max_primary_streams
= fls(stream_info
->num_stream_ctxs
) - 2;
729 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
730 "Setting number of stream ctx array entries to %u",
731 1 << (max_primary_streams
+ 1));
732 ep_ctx
->ep_info
&= cpu_to_le32(~EP_MAXPSTREAMS_MASK
);
733 ep_ctx
->ep_info
|= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams
)
735 ep_ctx
->deq
= cpu_to_le64(stream_info
->ctx_array_dma
);
739 * Sets the MaxPStreams field and the Linear Stream Array field to 0.
740 * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
741 * not at the beginning of the ring).
743 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx
*ep_ctx
,
744 struct xhci_virt_ep
*ep
)
747 ep_ctx
->ep_info
&= cpu_to_le32(~(EP_MAXPSTREAMS_MASK
| EP_HAS_LSA
));
748 addr
= xhci_trb_virt_to_dma(ep
->ring
->deq_seg
, ep
->ring
->dequeue
);
749 ep_ctx
->deq
= cpu_to_le64(addr
| ep
->ring
->cycle_state
);
752 /* Frees all stream contexts associated with the endpoint,
754 * Caller should fix the endpoint context streams fields.
756 void xhci_free_stream_info(struct xhci_hcd
*xhci
,
757 struct xhci_stream_info
*stream_info
)
760 struct xhci_ring
*cur_ring
;
765 for (cur_stream
= 1; cur_stream
< stream_info
->num_streams
;
767 cur_ring
= stream_info
->stream_rings
[cur_stream
];
769 xhci_ring_free(xhci
, cur_ring
);
770 stream_info
->stream_rings
[cur_stream
] = NULL
;
773 xhci_free_command(xhci
, stream_info
->free_streams_command
);
774 xhci
->cmd_ring_reserved_trbs
--;
775 if (stream_info
->stream_ctx_array
)
776 xhci_free_stream_ctx(xhci
,
777 stream_info
->num_stream_ctxs
,
778 stream_info
->stream_ctx_array
,
779 stream_info
->ctx_array_dma
);
781 kfree(stream_info
->stream_rings
);
786 /***************** Device context manipulation *************************/
788 static void xhci_init_endpoint_timer(struct xhci_hcd
*xhci
,
789 struct xhci_virt_ep
*ep
)
791 timer_setup(&ep
->stop_cmd_timer
, xhci_stop_endpoint_command_watchdog
,
796 static void xhci_free_tt_info(struct xhci_hcd
*xhci
,
797 struct xhci_virt_device
*virt_dev
,
800 struct list_head
*tt_list_head
;
801 struct xhci_tt_bw_info
*tt_info
, *next
;
802 bool slot_found
= false;
804 /* If the device never made it past the Set Address stage,
805 * it may not have the real_port set correctly.
807 if (virt_dev
->real_port
== 0 ||
808 virt_dev
->real_port
> HCS_MAX_PORTS(xhci
->hcs_params1
)) {
809 xhci_dbg(xhci
, "Bad real port.\n");
813 tt_list_head
= &(xhci
->rh_bw
[virt_dev
->real_port
- 1].tts
);
814 list_for_each_entry_safe(tt_info
, next
, tt_list_head
, tt_list
) {
815 /* Multi-TT hubs will have more than one entry */
816 if (tt_info
->slot_id
== slot_id
) {
818 list_del(&tt_info
->tt_list
);
820 } else if (slot_found
) {
826 int xhci_alloc_tt_info(struct xhci_hcd
*xhci
,
827 struct xhci_virt_device
*virt_dev
,
828 struct usb_device
*hdev
,
829 struct usb_tt
*tt
, gfp_t mem_flags
)
831 struct xhci_tt_bw_info
*tt_info
;
832 unsigned int num_ports
;
838 num_ports
= hdev
->maxchild
;
840 for (i
= 0; i
< num_ports
; i
++, tt_info
++) {
841 struct xhci_interval_bw_table
*bw_table
;
843 tt_info
= kzalloc(sizeof(*tt_info
), mem_flags
);
846 INIT_LIST_HEAD(&tt_info
->tt_list
);
847 list_add(&tt_info
->tt_list
,
848 &xhci
->rh_bw
[virt_dev
->real_port
- 1].tts
);
849 tt_info
->slot_id
= virt_dev
->udev
->slot_id
;
851 tt_info
->ttport
= i
+1;
852 bw_table
= &tt_info
->bw_table
;
853 for (j
= 0; j
< XHCI_MAX_INTERVAL
; j
++)
854 INIT_LIST_HEAD(&bw_table
->interval_bw
[j
].endpoints
);
859 xhci_free_tt_info(xhci
, virt_dev
, virt_dev
->udev
->slot_id
);
864 /* All the xhci_tds in the ring's TD list should be freed at this point.
865 * Should be called with xhci->lock held if there is any chance the TT lists
866 * will be manipulated by the configure endpoint, allocate device, or update
867 * hub functions while this function is removing the TT entries from the list.
869 void xhci_free_virt_device(struct xhci_hcd
*xhci
, int slot_id
)
871 struct xhci_virt_device
*dev
;
873 int old_active_eps
= 0;
875 /* Slot ID 0 is reserved */
876 if (slot_id
== 0 || !xhci
->devs
[slot_id
])
879 dev
= xhci
->devs
[slot_id
];
881 xhci
->dcbaa
->dev_context_ptrs
[slot_id
] = 0;
885 trace_xhci_free_virt_device(dev
);
888 old_active_eps
= dev
->tt_info
->active_eps
;
890 for (i
= 0; i
< 31; i
++) {
891 if (dev
->eps
[i
].ring
)
892 xhci_ring_free(xhci
, dev
->eps
[i
].ring
);
893 if (dev
->eps
[i
].stream_info
)
894 xhci_free_stream_info(xhci
,
895 dev
->eps
[i
].stream_info
);
896 /* Endpoints on the TT/root port lists should have been removed
897 * when usb_disable_device() was called for the device.
898 * We can't drop them anyway, because the udev might have gone
899 * away by this point, and we can't tell what speed it was.
901 if (!list_empty(&dev
->eps
[i
].bw_endpoint_list
))
902 xhci_warn(xhci
, "Slot %u endpoint %u "
903 "not removed from BW list!\n",
906 /* If this is a hub, free the TT(s) from the TT list */
907 xhci_free_tt_info(xhci
, dev
, slot_id
);
908 /* If necessary, update the number of active TTs on this root port */
909 xhci_update_tt_active_eps(xhci
, dev
, old_active_eps
);
912 xhci_free_container_ctx(xhci
, dev
->in_ctx
);
914 xhci_free_container_ctx(xhci
, dev
->out_ctx
);
916 if (dev
->udev
&& dev
->udev
->slot_id
)
917 dev
->udev
->slot_id
= 0;
918 kfree(xhci
->devs
[slot_id
]);
919 xhci
->devs
[slot_id
] = NULL
;
923 * Free a virt_device structure.
924 * If the virt_device added a tt_info (a hub) and has children pointing to
925 * that tt_info, then free the child first. Recursive.
926 * We can't rely on udev at this point to find child-parent relationships.
928 void xhci_free_virt_devices_depth_first(struct xhci_hcd
*xhci
, int slot_id
)
930 struct xhci_virt_device
*vdev
;
931 struct list_head
*tt_list_head
;
932 struct xhci_tt_bw_info
*tt_info
, *next
;
935 vdev
= xhci
->devs
[slot_id
];
939 if (vdev
->real_port
== 0 ||
940 vdev
->real_port
> HCS_MAX_PORTS(xhci
->hcs_params1
)) {
941 xhci_dbg(xhci
, "Bad vdev->real_port.\n");
945 tt_list_head
= &(xhci
->rh_bw
[vdev
->real_port
- 1].tts
);
946 list_for_each_entry_safe(tt_info
, next
, tt_list_head
, tt_list
) {
947 /* is this a hub device that added a tt_info to the tts list */
948 if (tt_info
->slot_id
== slot_id
) {
949 /* are any devices using this tt_info? */
950 for (i
= 1; i
< HCS_MAX_SLOTS(xhci
->hcs_params1
); i
++) {
951 vdev
= xhci
->devs
[i
];
952 if (vdev
&& (vdev
->tt_info
== tt_info
))
953 xhci_free_virt_devices_depth_first(
959 /* we are now at a leaf device */
960 xhci_debugfs_remove_slot(xhci
, slot_id
);
961 xhci_free_virt_device(xhci
, slot_id
);
964 int xhci_alloc_virt_device(struct xhci_hcd
*xhci
, int slot_id
,
965 struct usb_device
*udev
, gfp_t flags
)
967 struct xhci_virt_device
*dev
;
970 /* Slot ID 0 is reserved */
971 if (slot_id
== 0 || xhci
->devs
[slot_id
]) {
972 xhci_warn(xhci
, "Bad Slot ID %d\n", slot_id
);
976 dev
= kzalloc(sizeof(*dev
), flags
);
980 /* Allocate the (output) device context that will be used in the HC. */
981 dev
->out_ctx
= xhci_alloc_container_ctx(xhci
, XHCI_CTX_TYPE_DEVICE
, flags
);
985 xhci_dbg(xhci
, "Slot %d output ctx = 0x%llx (dma)\n", slot_id
,
986 (unsigned long long)dev
->out_ctx
->dma
);
988 /* Allocate the (input) device context for address device command */
989 dev
->in_ctx
= xhci_alloc_container_ctx(xhci
, XHCI_CTX_TYPE_INPUT
, flags
);
993 xhci_dbg(xhci
, "Slot %d input ctx = 0x%llx (dma)\n", slot_id
,
994 (unsigned long long)dev
->in_ctx
->dma
);
996 /* Initialize the cancellation list and watchdog timers for each ep */
997 for (i
= 0; i
< 31; i
++) {
998 xhci_init_endpoint_timer(xhci
, &dev
->eps
[i
]);
999 INIT_LIST_HEAD(&dev
->eps
[i
].cancelled_td_list
);
1000 INIT_LIST_HEAD(&dev
->eps
[i
].bw_endpoint_list
);
1003 /* Allocate endpoint 0 ring */
1004 dev
->eps
[0].ring
= xhci_ring_alloc(xhci
, 2, 1, TYPE_CTRL
, 0, flags
);
1005 if (!dev
->eps
[0].ring
)
1010 /* Point to output device context in dcbaa. */
1011 xhci
->dcbaa
->dev_context_ptrs
[slot_id
] = cpu_to_le64(dev
->out_ctx
->dma
);
1012 xhci_dbg(xhci
, "Set slot id %d dcbaa entry %p to 0x%llx\n",
1014 &xhci
->dcbaa
->dev_context_ptrs
[slot_id
],
1015 le64_to_cpu(xhci
->dcbaa
->dev_context_ptrs
[slot_id
]));
1017 trace_xhci_alloc_virt_device(dev
);
1019 xhci
->devs
[slot_id
] = dev
;
1025 xhci_free_container_ctx(xhci
, dev
->in_ctx
);
1027 xhci_free_container_ctx(xhci
, dev
->out_ctx
);
1033 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd
*xhci
,
1034 struct usb_device
*udev
)
1036 struct xhci_virt_device
*virt_dev
;
1037 struct xhci_ep_ctx
*ep0_ctx
;
1038 struct xhci_ring
*ep_ring
;
1040 virt_dev
= xhci
->devs
[udev
->slot_id
];
1041 ep0_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->in_ctx
, 0);
1042 ep_ring
= virt_dev
->eps
[0].ring
;
1044 * FIXME we don't keep track of the dequeue pointer very well after a
1045 * Set TR dequeue pointer, so we're setting the dequeue pointer of the
1046 * host to our enqueue pointer. This should only be called after a
1047 * configured device has reset, so all control transfers should have
1048 * been completed or cancelled before the reset.
1050 ep0_ctx
->deq
= cpu_to_le64(xhci_trb_virt_to_dma(ep_ring
->enq_seg
,
1052 | ep_ring
->cycle_state
);
1056 * The xHCI roothub may have ports of differing speeds in any order in the port
1057 * status registers. xhci->port_array provides an array of the port speed for
1058 * each offset into the port status registers.
1060 * The xHCI hardware wants to know the roothub port number that the USB device
1061 * is attached to (or the roothub port its ancestor hub is attached to). All we
1062 * know is the index of that port under either the USB 2.0 or the USB 3.0
1063 * roothub, but that doesn't give us the real index into the HW port status
1064 * registers. Call xhci_find_raw_port_number() to get real index.
1066 static u32
xhci_find_real_port_number(struct xhci_hcd
*xhci
,
1067 struct usb_device
*udev
)
1069 struct usb_device
*top_dev
;
1070 struct usb_hcd
*hcd
;
1072 if (udev
->speed
>= USB_SPEED_SUPER
)
1073 hcd
= xhci
->shared_hcd
;
1075 hcd
= xhci
->main_hcd
;
1077 for (top_dev
= udev
; top_dev
->parent
&& top_dev
->parent
->parent
;
1078 top_dev
= top_dev
->parent
)
1079 /* Found device below root hub */;
1081 return xhci_find_raw_port_number(hcd
, top_dev
->portnum
);
1084 /* Setup an xHCI virtual device for a Set Address command */
1085 int xhci_setup_addressable_virt_dev(struct xhci_hcd
*xhci
, struct usb_device
*udev
)
1087 struct xhci_virt_device
*dev
;
1088 struct xhci_ep_ctx
*ep0_ctx
;
1089 struct xhci_slot_ctx
*slot_ctx
;
1092 struct usb_device
*top_dev
;
1094 dev
= xhci
->devs
[udev
->slot_id
];
1095 /* Slot ID 0 is reserved */
1096 if (udev
->slot_id
== 0 || !dev
) {
1097 xhci_warn(xhci
, "Slot ID %d is not assigned to this device\n",
1101 ep0_ctx
= xhci_get_ep_ctx(xhci
, dev
->in_ctx
, 0);
1102 slot_ctx
= xhci_get_slot_ctx(xhci
, dev
->in_ctx
);
1104 /* 3) Only the control endpoint is valid - one endpoint context */
1105 slot_ctx
->dev_info
|= cpu_to_le32(LAST_CTX(1) | udev
->route
);
1106 switch (udev
->speed
) {
1107 case USB_SPEED_SUPER_PLUS
:
1108 slot_ctx
->dev_info
|= cpu_to_le32(SLOT_SPEED_SSP
);
1109 max_packets
= MAX_PACKET(512);
1111 case USB_SPEED_SUPER
:
1112 slot_ctx
->dev_info
|= cpu_to_le32(SLOT_SPEED_SS
);
1113 max_packets
= MAX_PACKET(512);
1115 case USB_SPEED_HIGH
:
1116 slot_ctx
->dev_info
|= cpu_to_le32(SLOT_SPEED_HS
);
1117 max_packets
= MAX_PACKET(64);
1119 /* USB core guesses at a 64-byte max packet first for FS devices */
1120 case USB_SPEED_FULL
:
1121 slot_ctx
->dev_info
|= cpu_to_le32(SLOT_SPEED_FS
);
1122 max_packets
= MAX_PACKET(64);
1125 slot_ctx
->dev_info
|= cpu_to_le32(SLOT_SPEED_LS
);
1126 max_packets
= MAX_PACKET(8);
1128 case USB_SPEED_WIRELESS
:
1129 xhci_dbg(xhci
, "FIXME xHCI doesn't support wireless speeds\n");
1133 /* Speed was set earlier, this shouldn't happen. */
1136 /* Find the root hub port this device is under */
1137 port_num
= xhci_find_real_port_number(xhci
, udev
);
1140 slot_ctx
->dev_info2
|= cpu_to_le32(ROOT_HUB_PORT(port_num
));
1141 /* Set the port number in the virtual_device to the faked port number */
1142 for (top_dev
= udev
; top_dev
->parent
&& top_dev
->parent
->parent
;
1143 top_dev
= top_dev
->parent
)
1144 /* Found device below root hub */;
1145 dev
->fake_port
= top_dev
->portnum
;
1146 dev
->real_port
= port_num
;
1147 xhci_dbg(xhci
, "Set root hub portnum to %d\n", port_num
);
1148 xhci_dbg(xhci
, "Set fake root hub portnum to %d\n", dev
->fake_port
);
1150 /* Find the right bandwidth table that this device will be a part of.
1151 * If this is a full speed device attached directly to a root port (or a
1152 * decendent of one), it counts as a primary bandwidth domain, not a
1153 * secondary bandwidth domain under a TT. An xhci_tt_info structure
1154 * will never be created for the HS root hub.
1156 if (!udev
->tt
|| !udev
->tt
->hub
->parent
) {
1157 dev
->bw_table
= &xhci
->rh_bw
[port_num
- 1].bw_table
;
1159 struct xhci_root_port_bw_info
*rh_bw
;
1160 struct xhci_tt_bw_info
*tt_bw
;
1162 rh_bw
= &xhci
->rh_bw
[port_num
- 1];
1163 /* Find the right TT. */
1164 list_for_each_entry(tt_bw
, &rh_bw
->tts
, tt_list
) {
1165 if (tt_bw
->slot_id
!= udev
->tt
->hub
->slot_id
)
1168 if (!dev
->udev
->tt
->multi
||
1170 tt_bw
->ttport
== dev
->udev
->ttport
)) {
1171 dev
->bw_table
= &tt_bw
->bw_table
;
1172 dev
->tt_info
= tt_bw
;
1177 xhci_warn(xhci
, "WARN: Didn't find a matching TT\n");
1180 /* Is this a LS/FS device under an external HS hub? */
1181 if (udev
->tt
&& udev
->tt
->hub
->parent
) {
1182 slot_ctx
->tt_info
= cpu_to_le32(udev
->tt
->hub
->slot_id
|
1183 (udev
->ttport
<< 8));
1184 if (udev
->tt
->multi
)
1185 slot_ctx
->dev_info
|= cpu_to_le32(DEV_MTT
);
1187 xhci_dbg(xhci
, "udev->tt = %p\n", udev
->tt
);
1188 xhci_dbg(xhci
, "udev->ttport = 0x%x\n", udev
->ttport
);
1190 /* Step 4 - ring already allocated */
1192 ep0_ctx
->ep_info2
= cpu_to_le32(EP_TYPE(CTRL_EP
));
1194 /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
1195 ep0_ctx
->ep_info2
|= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3) |
1198 ep0_ctx
->deq
= cpu_to_le64(dev
->eps
[0].ring
->first_seg
->dma
|
1199 dev
->eps
[0].ring
->cycle_state
);
1201 trace_xhci_setup_addressable_virt_device(dev
);
1203 /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
1209 * Convert interval expressed as 2^(bInterval - 1) == interval into
1210 * straight exponent value 2^n == interval.
1213 static unsigned int xhci_parse_exponent_interval(struct usb_device
*udev
,
1214 struct usb_host_endpoint
*ep
)
1216 unsigned int interval
;
1218 interval
= clamp_val(ep
->desc
.bInterval
, 1, 16) - 1;
1219 if (interval
!= ep
->desc
.bInterval
- 1)
1220 dev_warn(&udev
->dev
,
1221 "ep %#x - rounding interval to %d %sframes\n",
1222 ep
->desc
.bEndpointAddress
,
1224 udev
->speed
== USB_SPEED_FULL
? "" : "micro");
1226 if (udev
->speed
== USB_SPEED_FULL
) {
1228 * Full speed isoc endpoints specify interval in frames,
1229 * not microframes. We are using microframes everywhere,
1230 * so adjust accordingly.
1232 interval
+= 3; /* 1 frame = 2^3 uframes */
1239 * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
1240 * microframes, rounded down to nearest power of 2.
1242 static unsigned int xhci_microframes_to_exponent(struct usb_device
*udev
,
1243 struct usb_host_endpoint
*ep
, unsigned int desc_interval
,
1244 unsigned int min_exponent
, unsigned int max_exponent
)
1246 unsigned int interval
;
1248 interval
= fls(desc_interval
) - 1;
1249 interval
= clamp_val(interval
, min_exponent
, max_exponent
);
1250 if ((1 << interval
) != desc_interval
)
1252 "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n",
1253 ep
->desc
.bEndpointAddress
,
1260 static unsigned int xhci_parse_microframe_interval(struct usb_device
*udev
,
1261 struct usb_host_endpoint
*ep
)
1263 if (ep
->desc
.bInterval
== 0)
1265 return xhci_microframes_to_exponent(udev
, ep
,
1266 ep
->desc
.bInterval
, 0, 15);
1270 static unsigned int xhci_parse_frame_interval(struct usb_device
*udev
,
1271 struct usb_host_endpoint
*ep
)
1273 return xhci_microframes_to_exponent(udev
, ep
,
1274 ep
->desc
.bInterval
* 8, 3, 10);
1277 /* Return the polling or NAK interval.
1279 * The polling interval is expressed in "microframes". If xHCI's Interval field
1280 * is set to N, it will service the endpoint every 2^(Interval)*125us.
1282 * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
1285 static unsigned int xhci_get_endpoint_interval(struct usb_device
*udev
,
1286 struct usb_host_endpoint
*ep
)
1288 unsigned int interval
= 0;
1290 switch (udev
->speed
) {
1291 case USB_SPEED_HIGH
:
1293 if (usb_endpoint_xfer_control(&ep
->desc
) ||
1294 usb_endpoint_xfer_bulk(&ep
->desc
)) {
1295 interval
= xhci_parse_microframe_interval(udev
, ep
);
1298 /* Fall through - SS and HS isoc/int have same decoding */
1300 case USB_SPEED_SUPER_PLUS
:
1301 case USB_SPEED_SUPER
:
1302 if (usb_endpoint_xfer_int(&ep
->desc
) ||
1303 usb_endpoint_xfer_isoc(&ep
->desc
)) {
1304 interval
= xhci_parse_exponent_interval(udev
, ep
);
1308 case USB_SPEED_FULL
:
1309 if (usb_endpoint_xfer_isoc(&ep
->desc
)) {
1310 interval
= xhci_parse_exponent_interval(udev
, ep
);
1314 * Fall through for interrupt endpoint interval decoding
1315 * since it uses the same rules as low speed interrupt
1321 if (usb_endpoint_xfer_int(&ep
->desc
) ||
1322 usb_endpoint_xfer_isoc(&ep
->desc
)) {
1324 interval
= xhci_parse_frame_interval(udev
, ep
);
1334 /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
1335 * High speed endpoint descriptors can define "the number of additional
1336 * transaction opportunities per microframe", but that goes in the Max Burst
1337 * endpoint context field.
1339 static u32
xhci_get_endpoint_mult(struct usb_device
*udev
,
1340 struct usb_host_endpoint
*ep
)
1342 if (udev
->speed
< USB_SPEED_SUPER
||
1343 !usb_endpoint_xfer_isoc(&ep
->desc
))
1345 return ep
->ss_ep_comp
.bmAttributes
;
1348 static u32
xhci_get_endpoint_max_burst(struct usb_device
*udev
,
1349 struct usb_host_endpoint
*ep
)
1351 /* Super speed and Plus have max burst in ep companion desc */
1352 if (udev
->speed
>= USB_SPEED_SUPER
)
1353 return ep
->ss_ep_comp
.bMaxBurst
;
1355 if (udev
->speed
== USB_SPEED_HIGH
&&
1356 (usb_endpoint_xfer_isoc(&ep
->desc
) ||
1357 usb_endpoint_xfer_int(&ep
->desc
)))
1358 return usb_endpoint_maxp_mult(&ep
->desc
) - 1;
1363 static u32
xhci_get_endpoint_type(struct usb_host_endpoint
*ep
)
1367 in
= usb_endpoint_dir_in(&ep
->desc
);
1369 switch (usb_endpoint_type(&ep
->desc
)) {
1370 case USB_ENDPOINT_XFER_CONTROL
:
1372 case USB_ENDPOINT_XFER_BULK
:
1373 return in
? BULK_IN_EP
: BULK_OUT_EP
;
1374 case USB_ENDPOINT_XFER_ISOC
:
1375 return in
? ISOC_IN_EP
: ISOC_OUT_EP
;
1376 case USB_ENDPOINT_XFER_INT
:
1377 return in
? INT_IN_EP
: INT_OUT_EP
;
1382 /* Return the maximum endpoint service interval time (ESIT) payload.
1383 * Basically, this is the maxpacket size, multiplied by the burst size
1386 static u32
xhci_get_max_esit_payload(struct usb_device
*udev
,
1387 struct usb_host_endpoint
*ep
)
1392 /* Only applies for interrupt or isochronous endpoints */
1393 if (usb_endpoint_xfer_control(&ep
->desc
) ||
1394 usb_endpoint_xfer_bulk(&ep
->desc
))
1397 /* SuperSpeedPlus Isoc ep sending over 48k per esit */
1398 if ((udev
->speed
>= USB_SPEED_SUPER_PLUS
) &&
1399 USB_SS_SSP_ISOC_COMP(ep
->ss_ep_comp
.bmAttributes
))
1400 return le32_to_cpu(ep
->ssp_isoc_ep_comp
.dwBytesPerInterval
);
1401 /* SuperSpeed or SuperSpeedPlus Isoc ep with less than 48k per esit */
1402 else if (udev
->speed
>= USB_SPEED_SUPER
)
1403 return le16_to_cpu(ep
->ss_ep_comp
.wBytesPerInterval
);
1405 max_packet
= usb_endpoint_maxp(&ep
->desc
);
1406 max_burst
= usb_endpoint_maxp_mult(&ep
->desc
);
1407 /* A 0 in max burst means 1 transfer per ESIT */
1408 return max_packet
* max_burst
;
1411 /* Set up an endpoint with one ring segment. Do not allocate stream rings.
1412 * Drivers will have to call usb_alloc_streams() to do that.
1414 int xhci_endpoint_init(struct xhci_hcd
*xhci
,
1415 struct xhci_virt_device
*virt_dev
,
1416 struct usb_device
*udev
,
1417 struct usb_host_endpoint
*ep
,
1420 unsigned int ep_index
;
1421 struct xhci_ep_ctx
*ep_ctx
;
1422 struct xhci_ring
*ep_ring
;
1423 unsigned int max_packet
;
1424 enum xhci_ring_type ring_type
;
1425 u32 max_esit_payload
;
1427 unsigned int max_burst
;
1428 unsigned int interval
;
1430 unsigned int avg_trb_len
;
1431 unsigned int err_count
= 0;
1433 ep_index
= xhci_get_endpoint_index(&ep
->desc
);
1434 ep_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->in_ctx
, ep_index
);
1436 endpoint_type
= xhci_get_endpoint_type(ep
);
1440 ring_type
= usb_endpoint_type(&ep
->desc
);
1443 * Get values to fill the endpoint context, mostly from ep descriptor.
1444 * The average TRB buffer lengt for bulk endpoints is unclear as we
1445 * have no clue on scatter gather list entry size. For Isoc and Int,
1446 * set it to max available. See xHCI 1.1 spec 4.14.1.1 for details.
1448 max_esit_payload
= xhci_get_max_esit_payload(udev
, ep
);
1449 interval
= xhci_get_endpoint_interval(udev
, ep
);
1451 /* Periodic endpoint bInterval limit quirk */
1452 if (usb_endpoint_xfer_int(&ep
->desc
) ||
1453 usb_endpoint_xfer_isoc(&ep
->desc
)) {
1454 if ((xhci
->quirks
& XHCI_LIMIT_ENDPOINT_INTERVAL_7
) &&
1455 udev
->speed
>= USB_SPEED_HIGH
&&
1461 mult
= xhci_get_endpoint_mult(udev
, ep
);
1462 max_packet
= usb_endpoint_maxp(&ep
->desc
);
1463 max_burst
= xhci_get_endpoint_max_burst(udev
, ep
);
1464 avg_trb_len
= max_esit_payload
;
1466 /* FIXME dig Mult and streams info out of ep companion desc */
1468 /* Allow 3 retries for everything but isoc, set CErr = 3 */
1469 if (!usb_endpoint_xfer_isoc(&ep
->desc
))
1471 /* Some devices get this wrong */
1472 if (usb_endpoint_xfer_bulk(&ep
->desc
) && udev
->speed
== USB_SPEED_HIGH
)
1474 /* xHCI 1.0 and 1.1 indicates that ctrl ep avg TRB Length should be 8 */
1475 if (usb_endpoint_xfer_control(&ep
->desc
) && xhci
->hci_version
>= 0x100)
1477 /* xhci 1.1 with LEC support doesn't use mult field, use RsvdZ */
1478 if ((xhci
->hci_version
> 0x100) && HCC2_LEC(xhci
->hcc_params2
))
1481 /* Set up the endpoint ring */
1482 virt_dev
->eps
[ep_index
].new_ring
=
1483 xhci_ring_alloc(xhci
, 2, 1, ring_type
, max_packet
, mem_flags
);
1484 if (!virt_dev
->eps
[ep_index
].new_ring
)
1487 virt_dev
->eps
[ep_index
].skip
= false;
1488 ep_ring
= virt_dev
->eps
[ep_index
].new_ring
;
1490 /* Fill the endpoint context */
1491 ep_ctx
->ep_info
= cpu_to_le32(EP_MAX_ESIT_PAYLOAD_HI(max_esit_payload
) |
1492 EP_INTERVAL(interval
) |
1494 ep_ctx
->ep_info2
= cpu_to_le32(EP_TYPE(endpoint_type
) |
1495 MAX_PACKET(max_packet
) |
1496 MAX_BURST(max_burst
) |
1497 ERROR_COUNT(err_count
));
1498 ep_ctx
->deq
= cpu_to_le64(ep_ring
->first_seg
->dma
|
1499 ep_ring
->cycle_state
);
1501 ep_ctx
->tx_info
= cpu_to_le32(EP_MAX_ESIT_PAYLOAD_LO(max_esit_payload
) |
1502 EP_AVG_TRB_LENGTH(avg_trb_len
));
1507 void xhci_endpoint_zero(struct xhci_hcd
*xhci
,
1508 struct xhci_virt_device
*virt_dev
,
1509 struct usb_host_endpoint
*ep
)
1511 unsigned int ep_index
;
1512 struct xhci_ep_ctx
*ep_ctx
;
1514 ep_index
= xhci_get_endpoint_index(&ep
->desc
);
1515 ep_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->in_ctx
, ep_index
);
1517 ep_ctx
->ep_info
= 0;
1518 ep_ctx
->ep_info2
= 0;
1520 ep_ctx
->tx_info
= 0;
1521 /* Don't free the endpoint ring until the set interface or configuration
1526 void xhci_clear_endpoint_bw_info(struct xhci_bw_info
*bw_info
)
1528 bw_info
->ep_interval
= 0;
1530 bw_info
->num_packets
= 0;
1531 bw_info
->max_packet_size
= 0;
1533 bw_info
->max_esit_payload
= 0;
1536 void xhci_update_bw_info(struct xhci_hcd
*xhci
,
1537 struct xhci_container_ctx
*in_ctx
,
1538 struct xhci_input_control_ctx
*ctrl_ctx
,
1539 struct xhci_virt_device
*virt_dev
)
1541 struct xhci_bw_info
*bw_info
;
1542 struct xhci_ep_ctx
*ep_ctx
;
1543 unsigned int ep_type
;
1546 for (i
= 1; i
< 31; i
++) {
1547 bw_info
= &virt_dev
->eps
[i
].bw_info
;
1549 /* We can't tell what endpoint type is being dropped, but
1550 * unconditionally clearing the bandwidth info for non-periodic
1551 * endpoints should be harmless because the info will never be
1552 * set in the first place.
1554 if (!EP_IS_ADDED(ctrl_ctx
, i
) && EP_IS_DROPPED(ctrl_ctx
, i
)) {
1555 /* Dropped endpoint */
1556 xhci_clear_endpoint_bw_info(bw_info
);
1560 if (EP_IS_ADDED(ctrl_ctx
, i
)) {
1561 ep_ctx
= xhci_get_ep_ctx(xhci
, in_ctx
, i
);
1562 ep_type
= CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx
->ep_info2
));
1564 /* Ignore non-periodic endpoints */
1565 if (ep_type
!= ISOC_OUT_EP
&& ep_type
!= INT_OUT_EP
&&
1566 ep_type
!= ISOC_IN_EP
&&
1567 ep_type
!= INT_IN_EP
)
1570 /* Added or changed endpoint */
1571 bw_info
->ep_interval
= CTX_TO_EP_INTERVAL(
1572 le32_to_cpu(ep_ctx
->ep_info
));
1573 /* Number of packets and mult are zero-based in the
1574 * input context, but we want one-based for the
1577 bw_info
->mult
= CTX_TO_EP_MULT(
1578 le32_to_cpu(ep_ctx
->ep_info
)) + 1;
1579 bw_info
->num_packets
= CTX_TO_MAX_BURST(
1580 le32_to_cpu(ep_ctx
->ep_info2
)) + 1;
1581 bw_info
->max_packet_size
= MAX_PACKET_DECODED(
1582 le32_to_cpu(ep_ctx
->ep_info2
));
1583 bw_info
->type
= ep_type
;
1584 bw_info
->max_esit_payload
= CTX_TO_MAX_ESIT_PAYLOAD(
1585 le32_to_cpu(ep_ctx
->tx_info
));
1590 /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
1591 * Useful when you want to change one particular aspect of the endpoint and then
1592 * issue a configure endpoint command.
1594 void xhci_endpoint_copy(struct xhci_hcd
*xhci
,
1595 struct xhci_container_ctx
*in_ctx
,
1596 struct xhci_container_ctx
*out_ctx
,
1597 unsigned int ep_index
)
1599 struct xhci_ep_ctx
*out_ep_ctx
;
1600 struct xhci_ep_ctx
*in_ep_ctx
;
1602 out_ep_ctx
= xhci_get_ep_ctx(xhci
, out_ctx
, ep_index
);
1603 in_ep_ctx
= xhci_get_ep_ctx(xhci
, in_ctx
, ep_index
);
1605 in_ep_ctx
->ep_info
= out_ep_ctx
->ep_info
;
1606 in_ep_ctx
->ep_info2
= out_ep_ctx
->ep_info2
;
1607 in_ep_ctx
->deq
= out_ep_ctx
->deq
;
1608 in_ep_ctx
->tx_info
= out_ep_ctx
->tx_info
;
1611 /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
1612 * Useful when you want to change one particular aspect of the endpoint and then
1613 * issue a configure endpoint command. Only the context entries field matters,
1614 * but we'll copy the whole thing anyway.
1616 void xhci_slot_copy(struct xhci_hcd
*xhci
,
1617 struct xhci_container_ctx
*in_ctx
,
1618 struct xhci_container_ctx
*out_ctx
)
1620 struct xhci_slot_ctx
*in_slot_ctx
;
1621 struct xhci_slot_ctx
*out_slot_ctx
;
1623 in_slot_ctx
= xhci_get_slot_ctx(xhci
, in_ctx
);
1624 out_slot_ctx
= xhci_get_slot_ctx(xhci
, out_ctx
);
1626 in_slot_ctx
->dev_info
= out_slot_ctx
->dev_info
;
1627 in_slot_ctx
->dev_info2
= out_slot_ctx
->dev_info2
;
1628 in_slot_ctx
->tt_info
= out_slot_ctx
->tt_info
;
1629 in_slot_ctx
->dev_state
= out_slot_ctx
->dev_state
;
1632 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
1633 static int scratchpad_alloc(struct xhci_hcd
*xhci
, gfp_t flags
)
1636 struct device
*dev
= xhci_to_hcd(xhci
)->self
.sysdev
;
1637 int num_sp
= HCS_MAX_SCRATCHPAD(xhci
->hcs_params2
);
1639 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
1640 "Allocating %d scratchpad buffers", num_sp
);
1645 xhci
->scratchpad
= kzalloc(sizeof(*xhci
->scratchpad
), flags
);
1646 if (!xhci
->scratchpad
)
1649 xhci
->scratchpad
->sp_array
= dma_alloc_coherent(dev
,
1650 num_sp
* sizeof(u64
),
1651 &xhci
->scratchpad
->sp_dma
, flags
);
1652 if (!xhci
->scratchpad
->sp_array
)
1655 xhci
->scratchpad
->sp_buffers
= kzalloc(sizeof(void *) * num_sp
, flags
);
1656 if (!xhci
->scratchpad
->sp_buffers
)
1659 xhci
->dcbaa
->dev_context_ptrs
[0] = cpu_to_le64(xhci
->scratchpad
->sp_dma
);
1660 for (i
= 0; i
< num_sp
; i
++) {
1662 void *buf
= dma_zalloc_coherent(dev
, xhci
->page_size
, &dma
,
1667 xhci
->scratchpad
->sp_array
[i
] = dma
;
1668 xhci
->scratchpad
->sp_buffers
[i
] = buf
;
1674 for (i
= i
- 1; i
>= 0; i
--) {
1675 dma_free_coherent(dev
, xhci
->page_size
,
1676 xhci
->scratchpad
->sp_buffers
[i
],
1677 xhci
->scratchpad
->sp_array
[i
]);
1680 kfree(xhci
->scratchpad
->sp_buffers
);
1683 dma_free_coherent(dev
, num_sp
* sizeof(u64
),
1684 xhci
->scratchpad
->sp_array
,
1685 xhci
->scratchpad
->sp_dma
);
1688 kfree(xhci
->scratchpad
);
1689 xhci
->scratchpad
= NULL
;
1695 static void scratchpad_free(struct xhci_hcd
*xhci
)
1699 struct device
*dev
= xhci_to_hcd(xhci
)->self
.sysdev
;
1701 if (!xhci
->scratchpad
)
1704 num_sp
= HCS_MAX_SCRATCHPAD(xhci
->hcs_params2
);
1706 for (i
= 0; i
< num_sp
; i
++) {
1707 dma_free_coherent(dev
, xhci
->page_size
,
1708 xhci
->scratchpad
->sp_buffers
[i
],
1709 xhci
->scratchpad
->sp_array
[i
]);
1711 kfree(xhci
->scratchpad
->sp_buffers
);
1712 dma_free_coherent(dev
, num_sp
* sizeof(u64
),
1713 xhci
->scratchpad
->sp_array
,
1714 xhci
->scratchpad
->sp_dma
);
1715 kfree(xhci
->scratchpad
);
1716 xhci
->scratchpad
= NULL
;
1719 struct xhci_command
*xhci_alloc_command(struct xhci_hcd
*xhci
,
1720 bool allocate_in_ctx
, bool allocate_completion
,
1723 struct xhci_command
*command
;
1725 command
= kzalloc(sizeof(*command
), mem_flags
);
1729 if (allocate_in_ctx
) {
1731 xhci_alloc_container_ctx(xhci
, XHCI_CTX_TYPE_INPUT
,
1733 if (!command
->in_ctx
) {
1739 if (allocate_completion
) {
1740 command
->completion
=
1741 kzalloc(sizeof(struct completion
), mem_flags
);
1742 if (!command
->completion
) {
1743 xhci_free_container_ctx(xhci
, command
->in_ctx
);
1747 init_completion(command
->completion
);
1750 command
->status
= 0;
1751 INIT_LIST_HEAD(&command
->cmd_list
);
1755 void xhci_urb_free_priv(struct urb_priv
*urb_priv
)
1760 void xhci_free_command(struct xhci_hcd
*xhci
,
1761 struct xhci_command
*command
)
1763 xhci_free_container_ctx(xhci
,
1765 kfree(command
->completion
);
1769 int xhci_alloc_erst(struct xhci_hcd
*xhci
,
1770 struct xhci_ring
*evt_ring
,
1771 struct xhci_erst
*erst
,
1776 struct xhci_segment
*seg
;
1777 struct xhci_erst_entry
*entry
;
1779 size
= sizeof(struct xhci_erst_entry
) * evt_ring
->num_segs
;
1780 erst
->entries
= dma_alloc_coherent(xhci_to_hcd(xhci
)->self
.sysdev
,
1782 &erst
->erst_dma_addr
,
1787 memset(erst
->entries
, 0, size
);
1788 erst
->num_entries
= evt_ring
->num_segs
;
1790 seg
= evt_ring
->first_seg
;
1791 for (val
= 0; val
< evt_ring
->num_segs
; val
++) {
1792 entry
= &erst
->entries
[val
];
1793 entry
->seg_addr
= cpu_to_le64(seg
->dma
);
1794 entry
->seg_size
= cpu_to_le32(TRBS_PER_SEGMENT
);
1802 void xhci_free_erst(struct xhci_hcd
*xhci
, struct xhci_erst
*erst
)
1805 struct device
*dev
= xhci_to_hcd(xhci
)->self
.sysdev
;
1807 size
= sizeof(struct xhci_erst_entry
) * (erst
->num_entries
);
1809 dma_free_coherent(dev
, size
,
1811 erst
->erst_dma_addr
);
1812 erst
->entries
= NULL
;
1815 void xhci_mem_cleanup(struct xhci_hcd
*xhci
)
1817 struct device
*dev
= xhci_to_hcd(xhci
)->self
.sysdev
;
1818 int i
, j
, num_ports
;
1820 cancel_delayed_work_sync(&xhci
->cmd_timer
);
1822 xhci_free_erst(xhci
, &xhci
->erst
);
1824 if (xhci
->event_ring
)
1825 xhci_ring_free(xhci
, xhci
->event_ring
);
1826 xhci
->event_ring
= NULL
;
1827 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "Freed event ring");
1829 if (xhci
->lpm_command
)
1830 xhci_free_command(xhci
, xhci
->lpm_command
);
1831 xhci
->lpm_command
= NULL
;
1833 xhci_ring_free(xhci
, xhci
->cmd_ring
);
1834 xhci
->cmd_ring
= NULL
;
1835 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "Freed command ring");
1836 xhci_cleanup_command_queue(xhci
);
1838 num_ports
= HCS_MAX_PORTS(xhci
->hcs_params1
);
1839 for (i
= 0; i
< num_ports
&& xhci
->rh_bw
; i
++) {
1840 struct xhci_interval_bw_table
*bwt
= &xhci
->rh_bw
[i
].bw_table
;
1841 for (j
= 0; j
< XHCI_MAX_INTERVAL
; j
++) {
1842 struct list_head
*ep
= &bwt
->interval_bw
[j
].endpoints
;
1843 while (!list_empty(ep
))
1844 list_del_init(ep
->next
);
1848 for (i
= HCS_MAX_SLOTS(xhci
->hcs_params1
); i
> 0; i
--)
1849 xhci_free_virt_devices_depth_first(xhci
, i
);
1851 dma_pool_destroy(xhci
->segment_pool
);
1852 xhci
->segment_pool
= NULL
;
1853 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "Freed segment pool");
1855 dma_pool_destroy(xhci
->device_pool
);
1856 xhci
->device_pool
= NULL
;
1857 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "Freed device context pool");
1859 dma_pool_destroy(xhci
->small_streams_pool
);
1860 xhci
->small_streams_pool
= NULL
;
1861 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
1862 "Freed small stream array pool");
1864 dma_pool_destroy(xhci
->medium_streams_pool
);
1865 xhci
->medium_streams_pool
= NULL
;
1866 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
1867 "Freed medium stream array pool");
1870 dma_free_coherent(dev
, sizeof(*xhci
->dcbaa
),
1871 xhci
->dcbaa
, xhci
->dcbaa
->dma
);
1874 scratchpad_free(xhci
);
1879 for (i
= 0; i
< num_ports
; i
++) {
1880 struct xhci_tt_bw_info
*tt
, *n
;
1881 list_for_each_entry_safe(tt
, n
, &xhci
->rh_bw
[i
].tts
, tt_list
) {
1882 list_del(&tt
->tt_list
);
1888 xhci
->cmd_ring_reserved_trbs
= 0;
1889 xhci
->num_usb2_ports
= 0;
1890 xhci
->num_usb3_ports
= 0;
1891 xhci
->num_active_eps
= 0;
1892 kfree(xhci
->usb2_ports
);
1893 kfree(xhci
->usb3_ports
);
1894 kfree(xhci
->port_array
);
1896 kfree(xhci
->ext_caps
);
1898 xhci
->usb2_ports
= NULL
;
1899 xhci
->usb3_ports
= NULL
;
1900 xhci
->port_array
= NULL
;
1902 xhci
->ext_caps
= NULL
;
1904 xhci
->page_size
= 0;
1905 xhci
->page_shift
= 0;
1906 xhci
->bus_state
[0].bus_suspended
= 0;
1907 xhci
->bus_state
[1].bus_suspended
= 0;
1910 static int xhci_test_trb_in_td(struct xhci_hcd
*xhci
,
1911 struct xhci_segment
*input_seg
,
1912 union xhci_trb
*start_trb
,
1913 union xhci_trb
*end_trb
,
1914 dma_addr_t input_dma
,
1915 struct xhci_segment
*result_seg
,
1916 char *test_name
, int test_number
)
1918 unsigned long long start_dma
;
1919 unsigned long long end_dma
;
1920 struct xhci_segment
*seg
;
1922 start_dma
= xhci_trb_virt_to_dma(input_seg
, start_trb
);
1923 end_dma
= xhci_trb_virt_to_dma(input_seg
, end_trb
);
1925 seg
= trb_in_td(xhci
, input_seg
, start_trb
, end_trb
, input_dma
, false);
1926 if (seg
!= result_seg
) {
1927 xhci_warn(xhci
, "WARN: %s TRB math test %d failed!\n",
1928 test_name
, test_number
);
1929 xhci_warn(xhci
, "Tested TRB math w/ seg %p and "
1930 "input DMA 0x%llx\n",
1932 (unsigned long long) input_dma
);
1933 xhci_warn(xhci
, "starting TRB %p (0x%llx DMA), "
1934 "ending TRB %p (0x%llx DMA)\n",
1935 start_trb
, start_dma
,
1937 xhci_warn(xhci
, "Expected seg %p, got seg %p\n",
1939 trb_in_td(xhci
, input_seg
, start_trb
, end_trb
, input_dma
,
1946 /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
1947 static int xhci_check_trb_in_td_math(struct xhci_hcd
*xhci
)
1950 dma_addr_t input_dma
;
1951 struct xhci_segment
*result_seg
;
1952 } simple_test_vector
[] = {
1953 /* A zeroed DMA field should fail */
1955 /* One TRB before the ring start should fail */
1956 { xhci
->event_ring
->first_seg
->dma
- 16, NULL
},
1957 /* One byte before the ring start should fail */
1958 { xhci
->event_ring
->first_seg
->dma
- 1, NULL
},
1959 /* Starting TRB should succeed */
1960 { xhci
->event_ring
->first_seg
->dma
, xhci
->event_ring
->first_seg
},
1961 /* Ending TRB should succeed */
1962 { xhci
->event_ring
->first_seg
->dma
+ (TRBS_PER_SEGMENT
- 1)*16,
1963 xhci
->event_ring
->first_seg
},
1964 /* One byte after the ring end should fail */
1965 { xhci
->event_ring
->first_seg
->dma
+ (TRBS_PER_SEGMENT
- 1)*16 + 1, NULL
},
1966 /* One TRB after the ring end should fail */
1967 { xhci
->event_ring
->first_seg
->dma
+ (TRBS_PER_SEGMENT
)*16, NULL
},
1968 /* An address of all ones should fail */
1969 { (dma_addr_t
) (~0), NULL
},
1972 struct xhci_segment
*input_seg
;
1973 union xhci_trb
*start_trb
;
1974 union xhci_trb
*end_trb
;
1975 dma_addr_t input_dma
;
1976 struct xhci_segment
*result_seg
;
1977 } complex_test_vector
[] = {
1978 /* Test feeding a valid DMA address from a different ring */
1979 { .input_seg
= xhci
->event_ring
->first_seg
,
1980 .start_trb
= xhci
->event_ring
->first_seg
->trbs
,
1981 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 1],
1982 .input_dma
= xhci
->cmd_ring
->first_seg
->dma
,
1985 /* Test feeding a valid end TRB from a different ring */
1986 { .input_seg
= xhci
->event_ring
->first_seg
,
1987 .start_trb
= xhci
->event_ring
->first_seg
->trbs
,
1988 .end_trb
= &xhci
->cmd_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 1],
1989 .input_dma
= xhci
->cmd_ring
->first_seg
->dma
,
1992 /* Test feeding a valid start and end TRB from a different ring */
1993 { .input_seg
= xhci
->event_ring
->first_seg
,
1994 .start_trb
= xhci
->cmd_ring
->first_seg
->trbs
,
1995 .end_trb
= &xhci
->cmd_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 1],
1996 .input_dma
= xhci
->cmd_ring
->first_seg
->dma
,
1999 /* TRB in this ring, but after this TD */
2000 { .input_seg
= xhci
->event_ring
->first_seg
,
2001 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[0],
2002 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[3],
2003 .input_dma
= xhci
->event_ring
->first_seg
->dma
+ 4*16,
2006 /* TRB in this ring, but before this TD */
2007 { .input_seg
= xhci
->event_ring
->first_seg
,
2008 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[3],
2009 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[6],
2010 .input_dma
= xhci
->event_ring
->first_seg
->dma
+ 2*16,
2013 /* TRB in this ring, but after this wrapped TD */
2014 { .input_seg
= xhci
->event_ring
->first_seg
,
2015 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 3],
2016 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[1],
2017 .input_dma
= xhci
->event_ring
->first_seg
->dma
+ 2*16,
2020 /* TRB in this ring, but before this wrapped TD */
2021 { .input_seg
= xhci
->event_ring
->first_seg
,
2022 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 3],
2023 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[1],
2024 .input_dma
= xhci
->event_ring
->first_seg
->dma
+ (TRBS_PER_SEGMENT
- 4)*16,
2027 /* TRB not in this ring, and we have a wrapped TD */
2028 { .input_seg
= xhci
->event_ring
->first_seg
,
2029 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 3],
2030 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[1],
2031 .input_dma
= xhci
->cmd_ring
->first_seg
->dma
+ 2*16,
2036 unsigned int num_tests
;
2039 num_tests
= ARRAY_SIZE(simple_test_vector
);
2040 for (i
= 0; i
< num_tests
; i
++) {
2041 ret
= xhci_test_trb_in_td(xhci
,
2042 xhci
->event_ring
->first_seg
,
2043 xhci
->event_ring
->first_seg
->trbs
,
2044 &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 1],
2045 simple_test_vector
[i
].input_dma
,
2046 simple_test_vector
[i
].result_seg
,
2052 num_tests
= ARRAY_SIZE(complex_test_vector
);
2053 for (i
= 0; i
< num_tests
; i
++) {
2054 ret
= xhci_test_trb_in_td(xhci
,
2055 complex_test_vector
[i
].input_seg
,
2056 complex_test_vector
[i
].start_trb
,
2057 complex_test_vector
[i
].end_trb
,
2058 complex_test_vector
[i
].input_dma
,
2059 complex_test_vector
[i
].result_seg
,
2064 xhci_dbg(xhci
, "TRB math tests passed.\n");
2068 static void xhci_set_hc_event_deq(struct xhci_hcd
*xhci
)
2073 deq
= xhci_trb_virt_to_dma(xhci
->event_ring
->deq_seg
,
2074 xhci
->event_ring
->dequeue
);
2075 if (deq
== 0 && !in_interrupt())
2076 xhci_warn(xhci
, "WARN something wrong with SW event ring "
2078 /* Update HC event ring dequeue pointer */
2079 temp
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
2080 temp
&= ERST_PTR_MASK
;
2081 /* Don't clear the EHB bit (which is RW1C) because
2082 * there might be more events to service.
2085 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2086 "// Write event ring dequeue pointer, "
2087 "preserving EHB bit");
2088 xhci_write_64(xhci
, ((u64
) deq
& (u64
) ~ERST_PTR_MASK
) | temp
,
2089 &xhci
->ir_set
->erst_dequeue
);
2092 static void xhci_add_in_port(struct xhci_hcd
*xhci
, unsigned int num_ports
,
2093 __le32 __iomem
*addr
, int max_caps
)
2095 u32 temp
, port_offset
, port_count
;
2097 u8 major_revision
, minor_revision
;
2098 struct xhci_hub
*rhub
;
2101 major_revision
= XHCI_EXT_PORT_MAJOR(temp
);
2102 minor_revision
= XHCI_EXT_PORT_MINOR(temp
);
2104 if (major_revision
== 0x03) {
2105 rhub
= &xhci
->usb3_rhub
;
2106 } else if (major_revision
<= 0x02) {
2107 rhub
= &xhci
->usb2_rhub
;
2109 xhci_warn(xhci
, "Ignoring unknown port speed, "
2110 "Ext Cap %p, revision = 0x%x\n",
2111 addr
, major_revision
);
2112 /* Ignoring port protocol we can't understand. FIXME */
2115 rhub
->maj_rev
= XHCI_EXT_PORT_MAJOR(temp
);
2117 if (rhub
->min_rev
< minor_revision
)
2118 rhub
->min_rev
= minor_revision
;
2120 /* Port offset and count in the third dword, see section 7.2 */
2121 temp
= readl(addr
+ 2);
2122 port_offset
= XHCI_EXT_PORT_OFF(temp
);
2123 port_count
= XHCI_EXT_PORT_COUNT(temp
);
2124 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2125 "Ext Cap %p, port offset = %u, "
2126 "count = %u, revision = 0x%x",
2127 addr
, port_offset
, port_count
, major_revision
);
2128 /* Port count includes the current port offset */
2129 if (port_offset
== 0 || (port_offset
+ port_count
- 1) > num_ports
)
2130 /* WTF? "Valid values are ‘1’ to MaxPorts" */
2133 rhub
->psi_count
= XHCI_EXT_PORT_PSIC(temp
);
2134 if (rhub
->psi_count
) {
2135 rhub
->psi
= kcalloc(rhub
->psi_count
, sizeof(*rhub
->psi
),
2138 rhub
->psi_count
= 0;
2140 rhub
->psi_uid_count
++;
2141 for (i
= 0; i
< rhub
->psi_count
; i
++) {
2142 rhub
->psi
[i
] = readl(addr
+ 4 + i
);
2144 /* count unique ID values, two consecutive entries can
2145 * have the same ID if link is assymetric
2147 if (i
&& (XHCI_EXT_PORT_PSIV(rhub
->psi
[i
]) !=
2148 XHCI_EXT_PORT_PSIV(rhub
->psi
[i
- 1])))
2149 rhub
->psi_uid_count
++;
2151 xhci_dbg(xhci
, "PSIV:%d PSIE:%d PLT:%d PFD:%d LP:%d PSIM:%d\n",
2152 XHCI_EXT_PORT_PSIV(rhub
->psi
[i
]),
2153 XHCI_EXT_PORT_PSIE(rhub
->psi
[i
]),
2154 XHCI_EXT_PORT_PLT(rhub
->psi
[i
]),
2155 XHCI_EXT_PORT_PFD(rhub
->psi
[i
]),
2156 XHCI_EXT_PORT_LP(rhub
->psi
[i
]),
2157 XHCI_EXT_PORT_PSIM(rhub
->psi
[i
]));
2160 /* cache usb2 port capabilities */
2161 if (major_revision
< 0x03 && xhci
->num_ext_caps
< max_caps
)
2162 xhci
->ext_caps
[xhci
->num_ext_caps
++] = temp
;
2164 /* Check the host's USB2 LPM capability */
2165 if ((xhci
->hci_version
== 0x96) && (major_revision
!= 0x03) &&
2166 (temp
& XHCI_L1C
)) {
2167 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2168 "xHCI 0.96: support USB2 software lpm");
2169 xhci
->sw_lpm_support
= 1;
2172 if ((xhci
->hci_version
>= 0x100) && (major_revision
!= 0x03)) {
2173 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2174 "xHCI 1.0: support USB2 software lpm");
2175 xhci
->sw_lpm_support
= 1;
2176 if (temp
& XHCI_HLC
) {
2177 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2178 "xHCI 1.0: support USB2 hardware lpm");
2179 xhci
->hw_lpm_support
= 1;
2184 for (i
= port_offset
; i
< (port_offset
+ port_count
); i
++) {
2185 /* Duplicate entry. Ignore the port if the revisions differ. */
2186 if (xhci
->port_array
[i
] != 0) {
2187 xhci_warn(xhci
, "Duplicate port entry, Ext Cap %p,"
2188 " port %u\n", addr
, i
);
2189 xhci_warn(xhci
, "Port was marked as USB %u, "
2190 "duplicated as USB %u\n",
2191 xhci
->port_array
[i
], major_revision
);
2192 /* Only adjust the roothub port counts if we haven't
2193 * found a similar duplicate.
2195 if (xhci
->port_array
[i
] != major_revision
&&
2196 xhci
->port_array
[i
] != DUPLICATE_ENTRY
) {
2197 if (xhci
->port_array
[i
] == 0x03)
2198 xhci
->num_usb3_ports
--;
2200 xhci
->num_usb2_ports
--;
2201 xhci
->port_array
[i
] = DUPLICATE_ENTRY
;
2203 /* FIXME: Should we disable the port? */
2206 xhci
->port_array
[i
] = major_revision
;
2207 if (major_revision
== 0x03)
2208 xhci
->num_usb3_ports
++;
2210 xhci
->num_usb2_ports
++;
2212 /* FIXME: Should we disable ports not in the Extended Capabilities? */
2216 * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
2217 * specify what speeds each port is supposed to be. We can't count on the port
2218 * speed bits in the PORTSC register being correct until a device is connected,
2219 * but we need to set up the two fake roothubs with the correct number of USB
2220 * 3.0 and USB 2.0 ports at host controller initialization time.
2222 static int xhci_setup_port_arrays(struct xhci_hcd
*xhci
, gfp_t flags
)
2226 unsigned int num_ports
;
2227 int i
, j
, port_index
;
2231 num_ports
= HCS_MAX_PORTS(xhci
->hcs_params1
);
2232 xhci
->port_array
= kzalloc(sizeof(*xhci
->port_array
)*num_ports
, flags
);
2233 if (!xhci
->port_array
)
2236 xhci
->rh_bw
= kzalloc(sizeof(*xhci
->rh_bw
)*num_ports
, flags
);
2239 for (i
= 0; i
< num_ports
; i
++) {
2240 struct xhci_interval_bw_table
*bw_table
;
2242 INIT_LIST_HEAD(&xhci
->rh_bw
[i
].tts
);
2243 bw_table
= &xhci
->rh_bw
[i
].bw_table
;
2244 for (j
= 0; j
< XHCI_MAX_INTERVAL
; j
++)
2245 INIT_LIST_HEAD(&bw_table
->interval_bw
[j
].endpoints
);
2247 base
= &xhci
->cap_regs
->hc_capbase
;
2249 cap_start
= xhci_find_next_ext_cap(base
, 0, XHCI_EXT_CAPS_PROTOCOL
);
2251 xhci_err(xhci
, "No Extended Capability registers, unable to set up roothub\n");
2256 /* count extended protocol capability entries for later caching */
2259 offset
= xhci_find_next_ext_cap(base
, offset
,
2260 XHCI_EXT_CAPS_PROTOCOL
);
2263 xhci
->ext_caps
= kzalloc(sizeof(*xhci
->ext_caps
) * cap_count
, flags
);
2264 if (!xhci
->ext_caps
)
2270 xhci_add_in_port(xhci
, num_ports
, base
+ offset
, cap_count
);
2271 if (xhci
->num_usb2_ports
+ xhci
->num_usb3_ports
== num_ports
)
2273 offset
= xhci_find_next_ext_cap(base
, offset
,
2274 XHCI_EXT_CAPS_PROTOCOL
);
2277 if (xhci
->num_usb2_ports
== 0 && xhci
->num_usb3_ports
== 0) {
2278 xhci_warn(xhci
, "No ports on the roothubs?\n");
2281 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2282 "Found %u USB 2.0 ports and %u USB 3.0 ports.",
2283 xhci
->num_usb2_ports
, xhci
->num_usb3_ports
);
2285 /* Place limits on the number of roothub ports so that the hub
2286 * descriptors aren't longer than the USB core will allocate.
2288 if (xhci
->num_usb3_ports
> USB_SS_MAXPORTS
) {
2289 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2290 "Limiting USB 3.0 roothub ports to %u.",
2292 xhci
->num_usb3_ports
= USB_SS_MAXPORTS
;
2294 if (xhci
->num_usb2_ports
> USB_MAXCHILDREN
) {
2295 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2296 "Limiting USB 2.0 roothub ports to %u.",
2298 xhci
->num_usb2_ports
= USB_MAXCHILDREN
;
2302 * Note we could have all USB 3.0 ports, or all USB 2.0 ports.
2303 * Not sure how the USB core will handle a hub with no ports...
2305 if (xhci
->num_usb2_ports
) {
2306 xhci
->usb2_ports
= kmalloc(sizeof(*xhci
->usb2_ports
)*
2307 xhci
->num_usb2_ports
, flags
);
2308 if (!xhci
->usb2_ports
)
2312 for (i
= 0; i
< num_ports
; i
++) {
2313 if (xhci
->port_array
[i
] == 0x03 ||
2314 xhci
->port_array
[i
] == 0 ||
2315 xhci
->port_array
[i
] == DUPLICATE_ENTRY
)
2318 xhci
->usb2_ports
[port_index
] =
2319 &xhci
->op_regs
->port_status_base
+
2321 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2322 "USB 2.0 port at index %u, "
2324 xhci
->usb2_ports
[port_index
]);
2326 if (port_index
== xhci
->num_usb2_ports
)
2330 if (xhci
->num_usb3_ports
) {
2331 xhci
->usb3_ports
= kmalloc(sizeof(*xhci
->usb3_ports
)*
2332 xhci
->num_usb3_ports
, flags
);
2333 if (!xhci
->usb3_ports
)
2337 for (i
= 0; i
< num_ports
; i
++)
2338 if (xhci
->port_array
[i
] == 0x03) {
2339 xhci
->usb3_ports
[port_index
] =
2340 &xhci
->op_regs
->port_status_base
+
2342 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2343 "USB 3.0 port at index %u, "
2345 xhci
->usb3_ports
[port_index
]);
2347 if (port_index
== xhci
->num_usb3_ports
)
2354 int xhci_mem_init(struct xhci_hcd
*xhci
, gfp_t flags
)
2357 struct device
*dev
= xhci_to_hcd(xhci
)->self
.sysdev
;
2358 unsigned int val
, val2
;
2360 u32 page_size
, temp
;
2363 INIT_LIST_HEAD(&xhci
->cmd_list
);
2365 /* init command timeout work */
2366 INIT_DELAYED_WORK(&xhci
->cmd_timer
, xhci_handle_command_timeout
);
2367 init_completion(&xhci
->cmd_ring_stop_completion
);
2369 page_size
= readl(&xhci
->op_regs
->page_size
);
2370 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2371 "Supported page size register = 0x%x", page_size
);
2372 for (i
= 0; i
< 16; i
++) {
2373 if ((0x1 & page_size
) != 0)
2375 page_size
= page_size
>> 1;
2378 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2379 "Supported page size of %iK", (1 << (i
+12)) / 1024);
2381 xhci_warn(xhci
, "WARN: no supported page size\n");
2382 /* Use 4K pages, since that's common and the minimum the HC supports */
2383 xhci
->page_shift
= 12;
2384 xhci
->page_size
= 1 << xhci
->page_shift
;
2385 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2386 "HCD page size set to %iK", xhci
->page_size
/ 1024);
2389 * Program the Number of Device Slots Enabled field in the CONFIG
2390 * register with the max value of slots the HC can handle.
2392 val
= HCS_MAX_SLOTS(readl(&xhci
->cap_regs
->hcs_params1
));
2393 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2394 "// xHC can handle at most %d device slots.", val
);
2395 val2
= readl(&xhci
->op_regs
->config_reg
);
2396 val
|= (val2
& ~HCS_SLOTS_MASK
);
2397 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2398 "// Setting Max device slots reg = 0x%x.", val
);
2399 writel(val
, &xhci
->op_regs
->config_reg
);
2402 * xHCI section 5.4.6 - doorbell array must be
2403 * "physically contiguous and 64-byte (cache line) aligned".
2405 xhci
->dcbaa
= dma_alloc_coherent(dev
, sizeof(*xhci
->dcbaa
), &dma
,
2409 memset(xhci
->dcbaa
, 0, sizeof *(xhci
->dcbaa
));
2410 xhci
->dcbaa
->dma
= dma
;
2411 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2412 "// Device context base array address = 0x%llx (DMA), %p (virt)",
2413 (unsigned long long)xhci
->dcbaa
->dma
, xhci
->dcbaa
);
2414 xhci_write_64(xhci
, dma
, &xhci
->op_regs
->dcbaa_ptr
);
2417 * Initialize the ring segment pool. The ring must be a contiguous
2418 * structure comprised of TRBs. The TRBs must be 16 byte aligned,
2419 * however, the command ring segment needs 64-byte aligned segments
2420 * and our use of dma addresses in the trb_address_map radix tree needs
2421 * TRB_SEGMENT_SIZE alignment, so we pick the greater alignment need.
2423 xhci
->segment_pool
= dma_pool_create("xHCI ring segments", dev
,
2424 TRB_SEGMENT_SIZE
, TRB_SEGMENT_SIZE
, xhci
->page_size
);
2426 /* See Table 46 and Note on Figure 55 */
2427 xhci
->device_pool
= dma_pool_create("xHCI input/output contexts", dev
,
2428 2112, 64, xhci
->page_size
);
2429 if (!xhci
->segment_pool
|| !xhci
->device_pool
)
2432 /* Linear stream context arrays don't have any boundary restrictions,
2433 * and only need to be 16-byte aligned.
2435 xhci
->small_streams_pool
=
2436 dma_pool_create("xHCI 256 byte stream ctx arrays",
2437 dev
, SMALL_STREAM_ARRAY_SIZE
, 16, 0);
2438 xhci
->medium_streams_pool
=
2439 dma_pool_create("xHCI 1KB stream ctx arrays",
2440 dev
, MEDIUM_STREAM_ARRAY_SIZE
, 16, 0);
2441 /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE
2442 * will be allocated with dma_alloc_coherent()
2445 if (!xhci
->small_streams_pool
|| !xhci
->medium_streams_pool
)
2448 /* Set up the command ring to have one segments for now. */
2449 xhci
->cmd_ring
= xhci_ring_alloc(xhci
, 1, 1, TYPE_COMMAND
, 0, flags
);
2450 if (!xhci
->cmd_ring
)
2452 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2453 "Allocated command ring at %p", xhci
->cmd_ring
);
2454 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "First segment DMA is 0x%llx",
2455 (unsigned long long)xhci
->cmd_ring
->first_seg
->dma
);
2457 /* Set the address in the Command Ring Control register */
2458 val_64
= xhci_read_64(xhci
, &xhci
->op_regs
->cmd_ring
);
2459 val_64
= (val_64
& (u64
) CMD_RING_RSVD_BITS
) |
2460 (xhci
->cmd_ring
->first_seg
->dma
& (u64
) ~CMD_RING_RSVD_BITS
) |
2461 xhci
->cmd_ring
->cycle_state
;
2462 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2463 "// Setting command ring address to 0x%016llx", val_64
);
2464 xhci_write_64(xhci
, val_64
, &xhci
->op_regs
->cmd_ring
);
2465 xhci_dbg_cmd_ptrs(xhci
);
2467 xhci
->lpm_command
= xhci_alloc_command(xhci
, true, true, flags
);
2468 if (!xhci
->lpm_command
)
2471 /* Reserve one command ring TRB for disabling LPM.
2472 * Since the USB core grabs the shared usb_bus bandwidth mutex before
2473 * disabling LPM, we only need to reserve one TRB for all devices.
2475 xhci
->cmd_ring_reserved_trbs
++;
2477 val
= readl(&xhci
->cap_regs
->db_off
);
2479 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2480 "// Doorbell array is located at offset 0x%x"
2481 " from cap regs base addr", val
);
2482 xhci
->dba
= (void __iomem
*) xhci
->cap_regs
+ val
;
2483 xhci_dbg_regs(xhci
);
2484 xhci_print_run_regs(xhci
);
2485 /* Set ir_set to interrupt register set 0 */
2486 xhci
->ir_set
= &xhci
->run_regs
->ir_set
[0];
2489 * Event ring setup: Allocate a normal ring, but also setup
2490 * the event ring segment table (ERST). Section 4.9.3.
2492 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "// Allocating event ring");
2493 xhci
->event_ring
= xhci_ring_alloc(xhci
, ERST_NUM_SEGS
, 1, TYPE_EVENT
,
2495 if (!xhci
->event_ring
)
2497 if (xhci_check_trb_in_td_math(xhci
) < 0)
2500 ret
= xhci_alloc_erst(xhci
, xhci
->event_ring
, &xhci
->erst
, flags
);
2504 /* set ERST count with the number of entries in the segment table */
2505 val
= readl(&xhci
->ir_set
->erst_size
);
2506 val
&= ERST_SIZE_MASK
;
2507 val
|= ERST_NUM_SEGS
;
2508 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2509 "// Write ERST size = %i to ir_set 0 (some bits preserved)",
2511 writel(val
, &xhci
->ir_set
->erst_size
);
2513 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2514 "// Set ERST entries to point to event ring.");
2515 /* set the segment table base address */
2516 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2517 "// Set ERST base address for ir_set 0 = 0x%llx",
2518 (unsigned long long)xhci
->erst
.erst_dma_addr
);
2519 val_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_base
);
2520 val_64
&= ERST_PTR_MASK
;
2521 val_64
|= (xhci
->erst
.erst_dma_addr
& (u64
) ~ERST_PTR_MASK
);
2522 xhci_write_64(xhci
, val_64
, &xhci
->ir_set
->erst_base
);
2524 /* Set the event ring dequeue address */
2525 xhci_set_hc_event_deq(xhci
);
2526 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2527 "Wrote ERST address to ir_set 0.");
2528 xhci_print_ir_set(xhci
, 0);
2531 * XXX: Might need to set the Interrupter Moderation Register to
2532 * something other than the default (~1ms minimum between interrupts).
2533 * See section 5.5.1.2.
2535 for (i
= 0; i
< MAX_HC_SLOTS
; i
++)
2536 xhci
->devs
[i
] = NULL
;
2537 for (i
= 0; i
< USB_MAXCHILDREN
; i
++) {
2538 xhci
->bus_state
[0].resume_done
[i
] = 0;
2539 xhci
->bus_state
[1].resume_done
[i
] = 0;
2540 /* Only the USB 2.0 completions will ever be used. */
2541 init_completion(&xhci
->bus_state
[1].rexit_done
[i
]);
2544 if (scratchpad_alloc(xhci
, flags
))
2546 if (xhci_setup_port_arrays(xhci
, flags
))
2549 /* Enable USB 3.0 device notifications for function remote wake, which
2550 * is necessary for allowing USB 3.0 devices to do remote wakeup from
2551 * U3 (device suspend).
2553 temp
= readl(&xhci
->op_regs
->dev_notification
);
2554 temp
&= ~DEV_NOTE_MASK
;
2555 temp
|= DEV_NOTE_FWAKE
;
2556 writel(temp
, &xhci
->op_regs
->dev_notification
);
2563 xhci_mem_cleanup(xhci
);