2 * MediaTek xHCI Host Controller Driver
4 * Copyright (c) 2015 MediaTek Inc.
6 * Chunfeng Yun <chunfeng.yun@mediatek.com>
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/clk.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/iopoll.h>
22 #include <linux/kernel.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/module.h>
26 #include <linux/phy/phy.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/regmap.h>
30 #include <linux/regulator/consumer.h>
35 /* ip_pw_ctrl0 register */
36 #define CTRL0_IP_SW_RST BIT(0)
38 /* ip_pw_ctrl1 register */
39 #define CTRL1_IP_HOST_PDN BIT(0)
41 /* ip_pw_ctrl2 register */
42 #define CTRL2_IP_DEV_PDN BIT(0)
44 /* ip_pw_sts1 register */
45 #define STS1_IP_SLEEP_STS BIT(30)
46 #define STS1_XHCI_RST BIT(11)
47 #define STS1_SYS125_RST BIT(10)
48 #define STS1_REF_RST BIT(8)
49 #define STS1_SYSPLL_STABLE BIT(0)
51 /* ip_xhci_cap register */
52 #define CAP_U3_PORT_NUM(p) ((p) & 0xff)
53 #define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff)
55 /* u3_ctrl_p register */
56 #define CTRL_U3_PORT_HOST_SEL BIT(2)
57 #define CTRL_U3_PORT_PDN BIT(1)
58 #define CTRL_U3_PORT_DIS BIT(0)
60 /* u2_ctrl_p register */
61 #define CTRL_U2_PORT_HOST_SEL BIT(2)
62 #define CTRL_U2_PORT_PDN BIT(1)
63 #define CTRL_U2_PORT_DIS BIT(0)
65 /* u2_phy_pll register */
66 #define CTRL_U2_FORCE_PLL_STB BIT(28)
68 #define PERI_WK_CTRL0 0x400
69 #define UWK_CTR0_0P_LS_PE BIT(8) /* posedge */
70 #define UWK_CTR0_0P_LS_NE BIT(7) /* negedge for 0p linestate*/
71 #define UWK_CTL1_1P_LS_C(x) (((x) & 0xf) << 1)
72 #define UWK_CTL1_1P_LS_E BIT(0)
74 #define PERI_WK_CTRL1 0x404
75 #define UWK_CTL1_IS_C(x) (((x) & 0xf) << 26)
76 #define UWK_CTL1_IS_E BIT(25)
77 #define UWK_CTL1_0P_LS_C(x) (((x) & 0xf) << 21)
78 #define UWK_CTL1_0P_LS_E BIT(20)
79 #define UWK_CTL1_IDDIG_C(x) (((x) & 0xf) << 11) /* cycle debounce */
80 #define UWK_CTL1_IDDIG_E BIT(10) /* enable debounce */
81 #define UWK_CTL1_IDDIG_P BIT(9) /* polarity */
82 #define UWK_CTL1_0P_LS_P BIT(7)
83 #define UWK_CTL1_IS_P BIT(6) /* polarity for ip sleep */
85 enum ssusb_wakeup_src
{
86 SSUSB_WK_IP_SLEEP
= 1,
87 SSUSB_WK_LINE_STATE
= 2,
90 static int xhci_mtk_host_enable(struct xhci_hcd_mtk
*mtk
)
92 struct mu3c_ippc_regs __iomem
*ippc
= mtk
->ippc_regs
;
100 /* power on host ip */
101 value
= readl(&ippc
->ip_pw_ctr1
);
102 value
&= ~CTRL1_IP_HOST_PDN
;
103 writel(value
, &ippc
->ip_pw_ctr1
);
105 /* power on and enable all u3 ports */
106 for (i
= 0; i
< mtk
->num_u3_ports
; i
++) {
107 value
= readl(&ippc
->u3_ctrl_p
[i
]);
108 value
&= ~(CTRL_U3_PORT_PDN
| CTRL_U3_PORT_DIS
);
109 value
|= CTRL_U3_PORT_HOST_SEL
;
110 writel(value
, &ippc
->u3_ctrl_p
[i
]);
113 /* power on and enable all u2 ports */
114 for (i
= 0; i
< mtk
->num_u2_ports
; i
++) {
115 value
= readl(&ippc
->u2_ctrl_p
[i
]);
116 value
&= ~(CTRL_U2_PORT_PDN
| CTRL_U2_PORT_DIS
);
117 value
|= CTRL_U2_PORT_HOST_SEL
;
118 writel(value
, &ippc
->u2_ctrl_p
[i
]);
122 * wait for clocks to be stable, and clock domains reset to
123 * be inactive after power on and enable ports
125 check_val
= STS1_SYSPLL_STABLE
| STS1_REF_RST
|
126 STS1_SYS125_RST
| STS1_XHCI_RST
;
128 ret
= readl_poll_timeout(&ippc
->ip_pw_sts1
, value
,
129 (check_val
== (value
& check_val
)), 100, 20000);
131 dev_err(mtk
->dev
, "clocks are not stable (0x%x)\n", value
);
138 static int xhci_mtk_host_disable(struct xhci_hcd_mtk
*mtk
)
140 struct mu3c_ippc_regs __iomem
*ippc
= mtk
->ippc_regs
;
148 /* power down all u3 ports */
149 for (i
= 0; i
< mtk
->num_u3_ports
; i
++) {
150 value
= readl(&ippc
->u3_ctrl_p
[i
]);
151 value
|= CTRL_U3_PORT_PDN
;
152 writel(value
, &ippc
->u3_ctrl_p
[i
]);
155 /* power down all u2 ports */
156 for (i
= 0; i
< mtk
->num_u2_ports
; i
++) {
157 value
= readl(&ippc
->u2_ctrl_p
[i
]);
158 value
|= CTRL_U2_PORT_PDN
;
159 writel(value
, &ippc
->u2_ctrl_p
[i
]);
162 /* power down host ip */
163 value
= readl(&ippc
->ip_pw_ctr1
);
164 value
|= CTRL1_IP_HOST_PDN
;
165 writel(value
, &ippc
->ip_pw_ctr1
);
167 /* wait for host ip to sleep */
168 ret
= readl_poll_timeout(&ippc
->ip_pw_sts1
, value
,
169 (value
& STS1_IP_SLEEP_STS
), 100, 100000);
171 dev_err(mtk
->dev
, "ip sleep failed!!!\n");
177 static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk
*mtk
)
179 struct mu3c_ippc_regs __iomem
*ippc
= mtk
->ippc_regs
;
186 value
= readl(&ippc
->ip_pw_ctr0
);
187 value
|= CTRL0_IP_SW_RST
;
188 writel(value
, &ippc
->ip_pw_ctr0
);
190 value
= readl(&ippc
->ip_pw_ctr0
);
191 value
&= ~CTRL0_IP_SW_RST
;
192 writel(value
, &ippc
->ip_pw_ctr0
);
195 * device ip is default power-on in fact
196 * power down device ip, otherwise ip-sleep will fail
198 value
= readl(&ippc
->ip_pw_ctr2
);
199 value
|= CTRL2_IP_DEV_PDN
;
200 writel(value
, &ippc
->ip_pw_ctr2
);
202 value
= readl(&ippc
->ip_xhci_cap
);
203 mtk
->num_u3_ports
= CAP_U3_PORT_NUM(value
);
204 mtk
->num_u2_ports
= CAP_U2_PORT_NUM(value
);
205 dev_dbg(mtk
->dev
, "%s u2p:%d, u3p:%d\n", __func__
,
206 mtk
->num_u2_ports
, mtk
->num_u3_ports
);
208 return xhci_mtk_host_enable(mtk
);
211 static int xhci_mtk_clks_enable(struct xhci_hcd_mtk
*mtk
)
215 ret
= clk_prepare_enable(mtk
->sys_clk
);
217 dev_err(mtk
->dev
, "failed to enable sys_clk\n");
221 if (mtk
->wakeup_src
) {
222 ret
= clk_prepare_enable(mtk
->wk_deb_p0
);
224 dev_err(mtk
->dev
, "failed to enable wk_deb_p0\n");
228 ret
= clk_prepare_enable(mtk
->wk_deb_p1
);
230 dev_err(mtk
->dev
, "failed to enable wk_deb_p1\n");
237 clk_disable_unprepare(mtk
->wk_deb_p0
);
239 clk_disable_unprepare(mtk
->sys_clk
);
244 static void xhci_mtk_clks_disable(struct xhci_hcd_mtk
*mtk
)
246 if (mtk
->wakeup_src
) {
247 clk_disable_unprepare(mtk
->wk_deb_p1
);
248 clk_disable_unprepare(mtk
->wk_deb_p0
);
250 clk_disable_unprepare(mtk
->sys_clk
);
253 /* only clocks can be turn off for ip-sleep wakeup mode */
254 static void usb_wakeup_ip_sleep_en(struct xhci_hcd_mtk
*mtk
)
257 struct regmap
*pericfg
= mtk
->pericfg
;
259 regmap_read(pericfg
, PERI_WK_CTRL1
, &tmp
);
260 tmp
&= ~UWK_CTL1_IS_P
;
261 tmp
&= ~(UWK_CTL1_IS_C(0xf));
262 tmp
|= UWK_CTL1_IS_C(0x8);
263 regmap_write(pericfg
, PERI_WK_CTRL1
, tmp
);
264 regmap_write(pericfg
, PERI_WK_CTRL1
, tmp
| UWK_CTL1_IS_E
);
266 regmap_read(pericfg
, PERI_WK_CTRL1
, &tmp
);
267 dev_dbg(mtk
->dev
, "%s(): WK_CTRL1[P6,E25,C26:29]=%#x\n",
271 static void usb_wakeup_ip_sleep_dis(struct xhci_hcd_mtk
*mtk
)
275 regmap_read(mtk
->pericfg
, PERI_WK_CTRL1
, &tmp
);
276 tmp
&= ~UWK_CTL1_IS_E
;
277 regmap_write(mtk
->pericfg
, PERI_WK_CTRL1
, tmp
);
281 * for line-state wakeup mode, phy's power should not power-down
282 * and only support cable plug in/out
284 static void usb_wakeup_line_state_en(struct xhci_hcd_mtk
*mtk
)
287 struct regmap
*pericfg
= mtk
->pericfg
;
289 /* line-state of u2-port0 */
290 regmap_read(pericfg
, PERI_WK_CTRL1
, &tmp
);
291 tmp
&= ~UWK_CTL1_0P_LS_P
;
292 tmp
&= ~(UWK_CTL1_0P_LS_C(0xf));
293 tmp
|= UWK_CTL1_0P_LS_C(0x8);
294 regmap_write(pericfg
, PERI_WK_CTRL1
, tmp
);
295 regmap_read(pericfg
, PERI_WK_CTRL1
, &tmp
);
296 regmap_write(pericfg
, PERI_WK_CTRL1
, tmp
| UWK_CTL1_0P_LS_E
);
298 /* line-state of u2-port1 */
299 regmap_read(pericfg
, PERI_WK_CTRL0
, &tmp
);
300 tmp
&= ~(UWK_CTL1_1P_LS_C(0xf));
301 tmp
|= UWK_CTL1_1P_LS_C(0x8);
302 regmap_write(pericfg
, PERI_WK_CTRL0
, tmp
);
303 regmap_write(pericfg
, PERI_WK_CTRL0
, tmp
| UWK_CTL1_1P_LS_E
);
306 static void usb_wakeup_line_state_dis(struct xhci_hcd_mtk
*mtk
)
309 struct regmap
*pericfg
= mtk
->pericfg
;
311 /* line-state of u2-port0 */
312 regmap_read(pericfg
, PERI_WK_CTRL1
, &tmp
);
313 tmp
&= ~UWK_CTL1_0P_LS_E
;
314 regmap_write(pericfg
, PERI_WK_CTRL1
, tmp
);
316 /* line-state of u2-port1 */
317 regmap_read(pericfg
, PERI_WK_CTRL0
, &tmp
);
318 tmp
&= ~UWK_CTL1_1P_LS_E
;
319 regmap_write(pericfg
, PERI_WK_CTRL0
, tmp
);
322 static void usb_wakeup_enable(struct xhci_hcd_mtk
*mtk
)
324 if (mtk
->wakeup_src
== SSUSB_WK_IP_SLEEP
)
325 usb_wakeup_ip_sleep_en(mtk
);
326 else if (mtk
->wakeup_src
== SSUSB_WK_LINE_STATE
)
327 usb_wakeup_line_state_en(mtk
);
330 static void usb_wakeup_disable(struct xhci_hcd_mtk
*mtk
)
332 if (mtk
->wakeup_src
== SSUSB_WK_IP_SLEEP
)
333 usb_wakeup_ip_sleep_dis(mtk
);
334 else if (mtk
->wakeup_src
== SSUSB_WK_LINE_STATE
)
335 usb_wakeup_line_state_dis(mtk
);
338 static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk
*mtk
,
339 struct device_node
*dn
)
341 struct device
*dev
= mtk
->dev
;
344 * wakeup function is optional, so it is not an error if this property
345 * does not exist, and in such case, no need to get relative
346 * properties anymore.
348 of_property_read_u32(dn
, "mediatek,wakeup-src", &mtk
->wakeup_src
);
349 if (!mtk
->wakeup_src
)
352 mtk
->wk_deb_p0
= devm_clk_get(dev
, "wakeup_deb_p0");
353 if (IS_ERR(mtk
->wk_deb_p0
)) {
354 dev_err(dev
, "fail to get wakeup_deb_p0\n");
355 return PTR_ERR(mtk
->wk_deb_p0
);
358 mtk
->wk_deb_p1
= devm_clk_get(dev
, "wakeup_deb_p1");
359 if (IS_ERR(mtk
->wk_deb_p1
)) {
360 dev_err(dev
, "fail to get wakeup_deb_p1\n");
361 return PTR_ERR(mtk
->wk_deb_p1
);
364 mtk
->pericfg
= syscon_regmap_lookup_by_phandle(dn
,
365 "mediatek,syscon-wakeup");
366 if (IS_ERR(mtk
->pericfg
)) {
367 dev_err(dev
, "fail to get pericfg regs\n");
368 return PTR_ERR(mtk
->pericfg
);
374 static int xhci_mtk_setup(struct usb_hcd
*hcd
);
375 static const struct xhci_driver_overrides xhci_mtk_overrides __initconst
= {
376 .extra_priv_size
= sizeof(struct xhci_hcd
),
377 .reset
= xhci_mtk_setup
,
380 static struct hc_driver __read_mostly xhci_mtk_hc_driver
;
382 static int xhci_mtk_phy_init(struct xhci_hcd_mtk
*mtk
)
387 for (i
= 0; i
< mtk
->num_phys
; i
++) {
388 ret
= phy_init(mtk
->phys
[i
]);
396 phy_exit(mtk
->phys
[i
- 1]);
401 static int xhci_mtk_phy_exit(struct xhci_hcd_mtk
*mtk
)
405 for (i
= 0; i
< mtk
->num_phys
; i
++)
406 phy_exit(mtk
->phys
[i
]);
411 static int xhci_mtk_phy_power_on(struct xhci_hcd_mtk
*mtk
)
416 for (i
= 0; i
< mtk
->num_phys
; i
++) {
417 ret
= phy_power_on(mtk
->phys
[i
]);
425 phy_power_off(mtk
->phys
[i
- 1]);
430 static void xhci_mtk_phy_power_off(struct xhci_hcd_mtk
*mtk
)
434 for (i
= 0; i
< mtk
->num_phys
; i
++)
435 phy_power_off(mtk
->phys
[i
]);
438 static int xhci_mtk_ldos_enable(struct xhci_hcd_mtk
*mtk
)
442 ret
= regulator_enable(mtk
->vbus
);
444 dev_err(mtk
->dev
, "failed to enable vbus\n");
448 ret
= regulator_enable(mtk
->vusb33
);
450 dev_err(mtk
->dev
, "failed to enable vusb33\n");
451 regulator_disable(mtk
->vbus
);
457 static void xhci_mtk_ldos_disable(struct xhci_hcd_mtk
*mtk
)
459 regulator_disable(mtk
->vbus
);
460 regulator_disable(mtk
->vusb33
);
463 static void xhci_mtk_quirks(struct device
*dev
, struct xhci_hcd
*xhci
)
465 struct usb_hcd
*hcd
= xhci_to_hcd(xhci
);
466 struct xhci_hcd_mtk
*mtk
= hcd_to_mtk(hcd
);
469 * As of now platform drivers don't provide MSI support so we ensure
470 * here that the generic code does not try to make a pci_dev from our
471 * dev struct in order to setup MSI
473 xhci
->quirks
|= XHCI_PLAT
;
474 xhci
->quirks
|= XHCI_MTK_HOST
;
476 * MTK host controller gives a spurious successful event after a
477 * short transfer. Ignore it.
479 xhci
->quirks
|= XHCI_SPURIOUS_SUCCESS
;
480 if (mtk
->lpm_support
)
481 xhci
->quirks
|= XHCI_LPM_SUPPORT
;
484 /* called during probe() after chip reset completes */
485 static int xhci_mtk_setup(struct usb_hcd
*hcd
)
487 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
488 struct xhci_hcd_mtk
*mtk
= hcd_to_mtk(hcd
);
491 if (usb_hcd_is_primary_hcd(hcd
)) {
492 ret
= xhci_mtk_ssusb_config(mtk
);
497 ret
= xhci_gen_setup(hcd
, xhci_mtk_quirks
);
501 if (usb_hcd_is_primary_hcd(hcd
)) {
502 mtk
->num_u3_ports
= xhci
->num_usb3_ports
;
503 mtk
->num_u2_ports
= xhci
->num_usb2_ports
;
504 ret
= xhci_mtk_sch_init(mtk
);
512 static int xhci_mtk_probe(struct platform_device
*pdev
)
514 struct device
*dev
= &pdev
->dev
;
515 struct device_node
*node
= dev
->of_node
;
516 struct xhci_hcd_mtk
*mtk
;
517 const struct hc_driver
*driver
;
518 struct xhci_hcd
*xhci
;
519 struct resource
*res
;
529 driver
= &xhci_mtk_hc_driver
;
530 mtk
= devm_kzalloc(dev
, sizeof(*mtk
), GFP_KERNEL
);
535 mtk
->vbus
= devm_regulator_get(dev
, "vbus");
536 if (IS_ERR(mtk
->vbus
)) {
537 dev_err(dev
, "fail to get vbus\n");
538 return PTR_ERR(mtk
->vbus
);
541 mtk
->vusb33
= devm_regulator_get(dev
, "vusb33");
542 if (IS_ERR(mtk
->vusb33
)) {
543 dev_err(dev
, "fail to get vusb33\n");
544 return PTR_ERR(mtk
->vusb33
);
547 mtk
->sys_clk
= devm_clk_get(dev
, "sys_ck");
548 if (IS_ERR(mtk
->sys_clk
)) {
549 dev_err(dev
, "fail to get sys_ck\n");
550 return PTR_ERR(mtk
->sys_clk
);
553 mtk
->lpm_support
= of_property_read_bool(node
, "usb3-lpm-capable");
555 ret
= usb_wakeup_of_property_parse(mtk
, node
);
559 mtk
->num_phys
= of_count_phandle_with_args(node
,
560 "phys", "#phy-cells");
561 if (mtk
->num_phys
> 0) {
562 mtk
->phys
= devm_kcalloc(dev
, mtk
->num_phys
,
563 sizeof(*mtk
->phys
), GFP_KERNEL
);
569 pm_runtime_enable(dev
);
570 pm_runtime_get_sync(dev
);
571 device_enable_async_suspend(dev
);
573 ret
= xhci_mtk_ldos_enable(mtk
);
577 ret
= xhci_mtk_clks_enable(mtk
);
581 irq
= platform_get_irq(pdev
, 0);
587 /* Initialize dma_mask and coherent_dma_mask to 32-bits */
588 ret
= dma_set_coherent_mask(dev
, DMA_BIT_MASK(32));
593 dev
->dma_mask
= &dev
->coherent_dma_mask
;
595 dma_set_mask(dev
, DMA_BIT_MASK(32));
597 hcd
= usb_create_hcd(driver
, dev
, dev_name(dev
));
604 * USB 2.0 roothub is stored in the platform_device.
605 * Swap it with mtk HCD.
607 mtk
->hcd
= platform_get_drvdata(pdev
);
608 platform_set_drvdata(pdev
, mtk
);
610 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "mac");
611 hcd
->regs
= devm_ioremap_resource(dev
, res
);
612 if (IS_ERR(hcd
->regs
)) {
613 ret
= PTR_ERR(hcd
->regs
);
616 hcd
->rsrc_start
= res
->start
;
617 hcd
->rsrc_len
= resource_size(res
);
619 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "ippc");
620 if (res
) { /* ippc register is optional */
621 mtk
->ippc_regs
= devm_ioremap_resource(dev
, res
);
622 if (IS_ERR(mtk
->ippc_regs
)) {
623 ret
= PTR_ERR(mtk
->ippc_regs
);
626 mtk
->has_ippc
= true;
628 mtk
->has_ippc
= false;
631 for (phy_num
= 0; phy_num
< mtk
->num_phys
; phy_num
++) {
632 phy
= devm_of_phy_get_by_index(dev
, node
, phy_num
);
637 mtk
->phys
[phy_num
] = phy
;
640 ret
= xhci_mtk_phy_init(mtk
);
644 ret
= xhci_mtk_phy_power_on(mtk
);
648 device_init_wakeup(dev
, true);
650 xhci
= hcd_to_xhci(hcd
);
651 xhci
->main_hcd
= hcd
;
652 xhci
->shared_hcd
= usb_create_shared_hcd(driver
, dev
,
654 if (!xhci
->shared_hcd
) {
659 if (HCC_MAX_PSA(xhci
->hcc_params
) >= 4)
660 xhci
->shared_hcd
->can_do_streams
= 1;
662 ret
= usb_add_hcd(hcd
, irq
, IRQF_SHARED
);
666 ret
= usb_add_hcd(xhci
->shared_hcd
, irq
, IRQF_SHARED
);
668 goto dealloc_usb2_hcd
;
676 xhci_mtk_sch_exit(mtk
);
677 usb_put_hcd(xhci
->shared_hcd
);
680 xhci_mtk_phy_power_off(mtk
);
681 device_init_wakeup(dev
, false);
684 xhci_mtk_phy_exit(mtk
);
690 xhci_mtk_clks_disable(mtk
);
693 xhci_mtk_ldos_disable(mtk
);
696 pm_runtime_put_sync(dev
);
697 pm_runtime_disable(dev
);
701 static int xhci_mtk_remove(struct platform_device
*dev
)
703 struct xhci_hcd_mtk
*mtk
= platform_get_drvdata(dev
);
704 struct usb_hcd
*hcd
= mtk
->hcd
;
705 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
707 usb_remove_hcd(xhci
->shared_hcd
);
708 xhci_mtk_phy_power_off(mtk
);
709 xhci_mtk_phy_exit(mtk
);
710 device_init_wakeup(&dev
->dev
, false);
713 usb_put_hcd(xhci
->shared_hcd
);
715 xhci_mtk_sch_exit(mtk
);
716 xhci_mtk_clks_disable(mtk
);
717 xhci_mtk_ldos_disable(mtk
);
718 pm_runtime_put_sync(&dev
->dev
);
719 pm_runtime_disable(&dev
->dev
);
725 * if ip sleep fails, and all clocks are disabled, access register will hang
726 * AHB bus, so stop polling roothubs to avoid regs access on bus suspend.
727 * and no need to check whether ip sleep failed or not; this will cause SPM
728 * to wake up system immediately after system suspend complete if ip sleep
729 * fails, it is what we wanted.
731 static int __maybe_unused
xhci_mtk_suspend(struct device
*dev
)
733 struct xhci_hcd_mtk
*mtk
= dev_get_drvdata(dev
);
734 struct usb_hcd
*hcd
= mtk
->hcd
;
735 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
737 xhci_dbg(xhci
, "%s: stop port polling\n", __func__
);
738 clear_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
739 del_timer_sync(&hcd
->rh_timer
);
740 clear_bit(HCD_FLAG_POLL_RH
, &xhci
->shared_hcd
->flags
);
741 del_timer_sync(&xhci
->shared_hcd
->rh_timer
);
743 xhci_mtk_host_disable(mtk
);
744 xhci_mtk_phy_power_off(mtk
);
745 xhci_mtk_clks_disable(mtk
);
746 usb_wakeup_enable(mtk
);
750 static int __maybe_unused
xhci_mtk_resume(struct device
*dev
)
752 struct xhci_hcd_mtk
*mtk
= dev_get_drvdata(dev
);
753 struct usb_hcd
*hcd
= mtk
->hcd
;
754 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
756 usb_wakeup_disable(mtk
);
757 xhci_mtk_clks_enable(mtk
);
758 xhci_mtk_phy_power_on(mtk
);
759 xhci_mtk_host_enable(mtk
);
761 xhci_dbg(xhci
, "%s: restart port polling\n", __func__
);
762 set_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
763 usb_hcd_poll_rh_status(hcd
);
764 set_bit(HCD_FLAG_POLL_RH
, &xhci
->shared_hcd
->flags
);
765 usb_hcd_poll_rh_status(xhci
->shared_hcd
);
769 static const struct dev_pm_ops xhci_mtk_pm_ops
= {
770 SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend
, xhci_mtk_resume
)
772 #define DEV_PM_OPS IS_ENABLED(CONFIG_PM) ? &xhci_mtk_pm_ops : NULL
775 static const struct of_device_id mtk_xhci_of_match
[] = {
776 { .compatible
= "mediatek,mt8173-xhci"},
779 MODULE_DEVICE_TABLE(of
, mtk_xhci_of_match
);
782 static struct platform_driver mtk_xhci_driver
= {
783 .probe
= xhci_mtk_probe
,
784 .remove
= xhci_mtk_remove
,
788 .of_match_table
= of_match_ptr(mtk_xhci_of_match
),
791 MODULE_ALIAS("platform:xhci-mtk");
793 static int __init
xhci_mtk_init(void)
795 xhci_init_driver(&xhci_mtk_hc_driver
, &xhci_mtk_overrides
);
796 return platform_driver_register(&mtk_xhci_driver
);
798 module_init(xhci_mtk_init
);
800 static void __exit
xhci_mtk_exit(void)
802 platform_driver_unregister(&mtk_xhci_driver
);
804 module_exit(xhci_mtk_exit
);
806 MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
807 MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver");
808 MODULE_LICENSE("GPL v2");