drivers/usb/host/xhci-pci.c

   1 /*
   2  * xHCI host controller driver PCI Bus Glue.
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/pci.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/acpi.h>
  27
  28 #include "xhci.h"
  29 #include "xhci-trace.h"
  30
  31 #define SSIC_PORT_NUM           2
  32 #define SSIC_PORT_CFG2          0x880c
  33 #define SSIC_PORT_CFG2_OFFSET   0x30
  34 #define PROG_DONE               (1 << 30)
  35 #define SSIC_PORT_UNUSED        (1 << 31)
  36
  37 /* Device for a quirk */
  38 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
  39 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
  40 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400       0x1400
  41
  42 #define PCI_VENDOR_ID_ETRON             0x1b6f
  43 #define PCI_DEVICE_ID_EJ168             0x7023
  44
  45 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI      0x8c31
  46 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI   0x9c31
  47 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI             0x22b5
  48 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI         0xa12f
  49 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI        0x9d2f
  50 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI              0x0aa8
  51
  52 static const char hcd_name[] = "xhci_hcd";
  53
  54 static struct hc_driver __read_mostly xhci_pci_hc_driver;
  55
  56 static int xhci_pci_setup(struct usb_hcd *hcd);
  57
  58 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
  59         .reset = xhci_pci_setup,
  60 };
  61
  62 /* called after powerup, by probe or system-pm "wakeup" */
  63 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  64 {
  65         /*
  66          * TODO: Implement finding debug ports later.
  67          * TODO: see if there are any quirks that need to be added to handle
  68          * new extended capabilities.
  69          */
  70
  71         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  72         if (!pci_set_mwi(pdev))
  73                 xhci_dbg(xhci, "MWI active\n");
  74
  75         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
  76         return 0;
  77 }
  78
  79 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
  80 {
  81         struct pci_dev          *pdev = to_pci_dev(dev);
  82
  83         /* Look for vendor-specific quirks */
  84         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
  85                         (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
  86                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
  87                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
  88                                 pdev->revision == 0x0) {
  89                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
  90                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  91                                 "QUIRK: Fresco Logic xHC needs configure"
  92                                 " endpoint cmd after reset endpoint");
  93                 }
  94                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
  95                                 pdev->revision == 0x4) {
  96                         xhci->quirks |= XHCI_SLOW_SUSPEND;
  97                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  98                                 "QUIRK: Fresco Logic xHC revision %u"
  99                                 "must be suspended extra slowly",
 100                                 pdev->revision);
 101                 }
 102                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
 103                         xhci->quirks |= XHCI_BROKEN_STREAMS;
 104                 /* Fresco Logic confirms: all revisions of this chip do not
 105                  * support MSI, even though some of them claim to in their PCI
 106                  * capabilities.
 107                  */
 108                 xhci->quirks |= XHCI_BROKEN_MSI;
 109                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 110                                 "QUIRK: Fresco Logic revision %u "
 111                                 "has broken MSI implementation",
 112                                 pdev->revision);
 113                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 114         }
 115
 116         if (pdev->vendor == PCI_VENDOR_ID_NEC)
 117                 xhci->quirks |= XHCI_NEC_HOST;
 118
 119         if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
 120                 xhci->quirks |= XHCI_AMD_0x96_HOST;
 121
 122         /* AMD PLL quirk */
 123         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
 124                 xhci->quirks |= XHCI_AMD_PLL_FIX;
 125
 126         if (pdev->vendor == PCI_VENDOR_ID_AMD)
 127                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 128
 129         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 130                 xhci->quirks |= XHCI_LPM_SUPPORT;
 131                 xhci->quirks |= XHCI_INTEL_HOST;
 132                 xhci->quirks |= XHCI_AVOID_BEI;
 133         }
 134         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 135                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
 136                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
 137                 xhci->limit_active_eps = 64;
 138                 xhci->quirks |= XHCI_SW_BW_CHECKING;
 139                 /*
 140                  * PPT desktop boards DH77EB and DH77DF will power back on after
 141                  * a few seconds of being shutdown.  The fix for this is to
 142                  * switch the ports from xHCI to EHCI on shutdown.  We can't use
 143                  * DMI information to find those particular boards (since each
 144                  * vendor will change the board name), so we have to key off all
 145                  * PPT chipsets.
 146                  */
 147                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 148         }
 149         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 150                 pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI) {
 151                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 152                 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
 153         }
 154         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 155                 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 156                  pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 157                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 158                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI)) {
 159                 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
 160         }
 161         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 162                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
 163                 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
 164         }
 165         if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
 166                         pdev->device == PCI_DEVICE_ID_EJ168) {
 167                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 168                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 169                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 170         }
 171         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 172                         pdev->device == 0x0015)
 173                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 174         if (pdev->vendor == PCI_VENDOR_ID_VIA)
 175                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 176
 177         /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
 178         if (pdev->vendor == PCI_VENDOR_ID_VIA &&
 179                         pdev->device == 0x3432)
 180                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 181
 182         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 183                         pdev->device == 0x1042)
 184                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 185
 186         if (xhci->quirks & XHCI_RESET_ON_RESUME)
 187                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 188                                 "QUIRK: Resetting on resume");
 189 }
 190
 191 #ifdef CONFIG_ACPI
 192 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
 193 {
 194         static const u8 intel_dsm_uuid[] = {
 195                 0xb7, 0x0c, 0x34, 0xac, 0x01, 0xe9, 0xbf, 0x45,
 196                 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23,
 197         };
 198         union acpi_object *obj;
 199
 200         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), intel_dsm_uuid, 3, 1,
 201                                 NULL);
 202         ACPI_FREE(obj);
 203 }
 204 #else
 205 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
 206 #endif /* CONFIG_ACPI */
 207
 208 /* called during probe() after chip reset completes */
 209 static int xhci_pci_setup(struct usb_hcd *hcd)
 210 {
 211         struct xhci_hcd         *xhci;
 212         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 213         int                     retval;
 214
 215         xhci = hcd_to_xhci(hcd);
 216         if (!xhci->sbrn)
 217                 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 218
 219         retval = xhci_gen_setup(hcd, xhci_pci_quirks);
 220         if (retval)
 221                 return retval;
 222
 223         if (!usb_hcd_is_primary_hcd(hcd))
 224                 return 0;
 225
 226         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 227
 228         /* Find any debug ports */
 229         retval = xhci_pci_reinit(xhci, pdev);
 230         if (!retval)
 231                 return retval;
 232
 233         return retval;
 234 }
 235
 236 /*
 237  * We need to register our own PCI probe function (instead of the USB core's
 238  * function) in order to create a second roothub under xHCI.
 239  */
 240 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 241 {
 242         int retval;
 243         struct xhci_hcd *xhci;
 244         struct hc_driver *driver;
 245         struct usb_hcd *hcd;
 246
 247         driver = (struct hc_driver *)id->driver_data;
 248
 249         /* Prevent runtime suspending between USB-2 and USB-3 initialization */
 250         pm_runtime_get_noresume(&dev->dev);
 251
 252         /* Register the USB 2.0 roothub.
 253          * FIXME: USB core must know to register the USB 2.0 roothub first.
 254          * This is sort of silly, because we could just set the HCD driver flags
 255          * to say USB 2.0, but I'm not sure what the implications would be in
 256          * the other parts of the HCD code.
 257          */
 258         retval = usb_hcd_pci_probe(dev, id);
 259
 260         if (retval)
 261                 goto put_runtime_pm;
 262
 263         /* USB 2.0 roothub is stored in the PCI device now. */
 264         hcd = dev_get_drvdata(&dev->dev);
 265         xhci = hcd_to_xhci(hcd);
 266         xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
 267                                 pci_name(dev), hcd);
 268         if (!xhci->shared_hcd) {
 269                 retval = -ENOMEM;
 270                 goto dealloc_usb2_hcd;
 271         }
 272
 273         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 274                         IRQF_SHARED);
 275         if (retval)
 276                 goto put_usb3_hcd;
 277         /* Roothub already marked as USB 3.0 speed */
 278
 279         if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
 280                         HCC_MAX_PSA(xhci->hcc_params) >= 4)
 281                 xhci->shared_hcd->can_do_streams = 1;
 282
 283         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 284                 xhci_pme_acpi_rtd3_enable(dev);
 285
 286         /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
 287         pm_runtime_put_noidle(&dev->dev);
 288
 289         return 0;
 290
 291 put_usb3_hcd:
 292         usb_put_hcd(xhci->shared_hcd);
 293 dealloc_usb2_hcd:
 294         usb_hcd_pci_remove(dev);
 295 put_runtime_pm:
 296         pm_runtime_put_noidle(&dev->dev);
 297         return retval;
 298 }
 299
 300 static void xhci_pci_remove(struct pci_dev *dev)
 301 {
 302         struct xhci_hcd *xhci;
 303
 304         xhci = hcd_to_xhci(pci_get_drvdata(dev));
 305         if (xhci->shared_hcd) {
 306                 usb_remove_hcd(xhci->shared_hcd);
 307                 usb_put_hcd(xhci->shared_hcd);
 308         }
 309         usb_hcd_pci_remove(dev);
 310
 311         /* Workaround for spurious wakeups at shutdown with HSW */
 312         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 313                 pci_set_power_state(dev, PCI_D3hot);
 314 }
 315
 316 #ifdef CONFIG_PM
 317 /*
 318  * In some Intel xHCI controllers, in order to get D3 working,
 319  * through a vendor specific SSIC CONFIG register at offset 0x883c,
 320  * SSIC PORT need to be marked as "unused" before putting xHCI
 321  * into D3. After D3 exit, the SSIC port need to be marked as "used".
 322  * Without this change, xHCI might not enter D3 state.
 323  */
 324 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
 325 {
 326         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 327         u32 val;
 328         void __iomem *reg;
 329         int i;
 330
 331         for (i = 0; i < SSIC_PORT_NUM; i++) {
 332                 reg = (void __iomem *) xhci->cap_regs +
 333                                 SSIC_PORT_CFG2 +
 334                                 i * SSIC_PORT_CFG2_OFFSET;
 335
 336                 /* Notify SSIC that SSIC profile programming is not done. */
 337                 val = readl(reg) & ~PROG_DONE;
 338                 writel(val, reg);
 339
 340                 /* Mark SSIC port as unused(suspend) or used(resume) */
 341                 val = readl(reg);
 342                 if (suspend)
 343                         val |= SSIC_PORT_UNUSED;
 344                 else
 345                         val &= ~SSIC_PORT_UNUSED;
 346                 writel(val, reg);
 347
 348                 /* Notify SSIC that SSIC profile programming is done */
 349                 val = readl(reg) | PROG_DONE;
 350                 writel(val, reg);
 351                 readl(reg);
 352         }
 353 }
 354
 355 /*
 356  * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 357  * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 358  */
 359 static void xhci_pme_quirk(struct usb_hcd *hcd)
 360 {
 361         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 362         void __iomem *reg;
 363         u32 val;
 364
 365         reg = (void __iomem *) xhci->cap_regs + 0x80a4;
 366         val = readl(reg);
 367         writel(val | BIT(28), reg);
 368         readl(reg);
 369 }
 370
 371 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 372 {
 373         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 374         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 375         int                     ret;
 376
 377         /*
 378          * Systems with the TI redriver that loses port status change events
 379          * need to have the registers polled during D3, so avoid D3cold.
 380          */
 381         if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
 382                 pdev->no_d3cold = true;
 383
 384         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 385                 xhci_pme_quirk(hcd);
 386
 387         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 388                 xhci_ssic_port_unused_quirk(hcd, true);
 389
 390         ret = xhci_suspend(xhci, do_wakeup);
 391         if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
 392                 xhci_ssic_port_unused_quirk(hcd, false);
 393
 394         return ret;
 395 }
 396
 397 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 398 {
 399         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 400         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 401         int                     retval = 0;
 402
 403         /* The BIOS on systems with the Intel Panther Point chipset may or may
 404          * not support xHCI natively.  That means that during system resume, it
 405          * may switch the ports back to EHCI so that users can use their
 406          * keyboard to select a kernel from GRUB after resume from hibernate.
 407          *
 408          * The BIOS is supposed to remember whether the OS had xHCI ports
 409          * enabled before resume, and switch the ports back to xHCI when the
 410          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 411          * writers.
 412          *
 413          * Unconditionally switch the ports back to xHCI after a system resume.
 414          * It should not matter whether the EHCI or xHCI controller is
 415          * resumed first. It's enough to do the switchover in xHCI because
 416          * USB core won't notice anything as the hub driver doesn't start
 417          * running again until after all the devices (including both EHCI and
 418          * xHCI host controllers) have been resumed.
 419          */
 420
 421         if (pdev->vendor == PCI_VENDOR_ID_INTEL)
 422                 usb_enable_intel_xhci_ports(pdev);
 423
 424         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 425                 xhci_ssic_port_unused_quirk(hcd, false);
 426
 427         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 428                 xhci_pme_quirk(hcd);
 429
 430         retval = xhci_resume(xhci, hibernated);
 431         return retval;
 432 }
 433 #endif /* CONFIG_PM */
 434
 435 /*-------------------------------------------------------------------------*/
 436
 437 /* PCI driver selection metadata; PCI hotplugging uses this */
 438 static const struct pci_device_id pci_ids[] = { {
 439         /* handle any USB 3.0 xHCI controller */
 440         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
 441         .driver_data =  (unsigned long) &xhci_pci_hc_driver,
 442         },
 443         { /* end: all zeroes */ }
 444 };
 445 MODULE_DEVICE_TABLE(pci, pci_ids);
 446
 447 /* pci driver glue; this is a "new style" PCI driver module */
 448 static struct pci_driver xhci_pci_driver = {
 449         .name =         (char *) hcd_name,
 450         .id_table =     pci_ids,
 451
 452         .probe =        xhci_pci_probe,
 453         .remove =       xhci_pci_remove,
 454         /* suspend and resume implemented later */
 455
 456         .shutdown =     usb_hcd_pci_shutdown,
 457 #ifdef CONFIG_PM
 458         .driver = {
 459                 .pm = &usb_hcd_pci_pm_ops
 460         },
 461 #endif
 462 };
 463
 464 static int __init xhci_pci_init(void)
 465 {
 466         xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
 467 #ifdef CONFIG_PM
 468         xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
 469         xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
 470 #endif
 471         return pci_register_driver(&xhci_pci_driver);
 472 }
 473 module_init(xhci_pci_init);
 474
 475 static void __exit xhci_pci_exit(void)
 476 {
 477         pci_unregister_driver(&xhci_pci_driver);
 478 }
 479 module_exit(xhci_pci_exit);
 480
 481 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
 482 MODULE_LICENSE("GPL");