drivers/usb/host/xhci-pci.c

   1 /*
   2  * xHCI host controller driver PCI Bus Glue.
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/pci.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/acpi.h>
  27
  28 #include "xhci.h"
  29 #include "xhci-trace.h"
  30
  31 #define SSIC_PORT_NUM           2
  32 #define SSIC_PORT_CFG2          0x880c
  33 #define SSIC_PORT_CFG2_OFFSET   0x30
  34 #define PROG_DONE               (1 << 30)
  35 #define SSIC_PORT_UNUSED        (1 << 31)
  36
  37 /* Device for a quirk */
  38 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
  39 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
  40 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009       0x1009
  41 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400       0x1400
  42
  43 #define PCI_VENDOR_ID_ETRON             0x1b6f
  44 #define PCI_DEVICE_ID_EJ168             0x7023
  45
  46 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI      0x8c31
  47 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI   0x9c31
  48 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI        0x9cb1
  49 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI             0x22b5
  50 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI         0xa12f
  51 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI        0x9d2f
  52 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI              0x0aa8
  53 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI              0x1aa8
  54 #define PCI_DEVICE_ID_INTEL_APL_XHCI                    0x5aa8
  55 #define PCI_DEVICE_ID_INTEL_DNV_XHCI                    0x19d0
  56
  57 static const char hcd_name[] = "xhci_hcd";
  58
  59 static struct hc_driver __read_mostly xhci_pci_hc_driver;
  60
  61 static int xhci_pci_setup(struct usb_hcd *hcd);
  62
  63 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
  64         .reset = xhci_pci_setup,
  65 };
  66
  67 /* called after powerup, by probe or system-pm "wakeup" */
  68 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  69 {
  70         /*
  71          * TODO: Implement finding debug ports later.
  72          * TODO: see if there are any quirks that need to be added to handle
  73          * new extended capabilities.
  74          */
  75
  76         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  77         if (!pci_set_mwi(pdev))
  78                 xhci_dbg(xhci, "MWI active\n");
  79
  80         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
  81         return 0;
  82 }
  83
  84 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
  85 {
  86         struct pci_dev          *pdev = to_pci_dev(dev);
  87
  88         /* Look for vendor-specific quirks */
  89         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
  90                         (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
  91                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
  92                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
  93                                 pdev->revision == 0x0) {
  94                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
  95                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  96                                 "QUIRK: Fresco Logic xHC needs configure"
  97                                 " endpoint cmd after reset endpoint");
  98                 }
  99                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 100                                 pdev->revision == 0x4) {
 101                         xhci->quirks |= XHCI_SLOW_SUSPEND;
 102                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 103                                 "QUIRK: Fresco Logic xHC revision %u"
 104                                 "must be suspended extra slowly",
 105                                 pdev->revision);
 106                 }
 107                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
 108                         xhci->quirks |= XHCI_BROKEN_STREAMS;
 109                 /* Fresco Logic confirms: all revisions of this chip do not
 110                  * support MSI, even though some of them claim to in their PCI
 111                  * capabilities.
 112                  */
 113                 xhci->quirks |= XHCI_BROKEN_MSI;
 114                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 115                                 "QUIRK: Fresco Logic revision %u "
 116                                 "has broken MSI implementation",
 117                                 pdev->revision);
 118                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 119         }
 120
 121         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 122                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
 123                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 124
 125         if (pdev->vendor == PCI_VENDOR_ID_NEC)
 126                 xhci->quirks |= XHCI_NEC_HOST;
 127
 128         if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
 129                 xhci->quirks |= XHCI_AMD_0x96_HOST;
 130
 131         /* AMD PLL quirk */
 132         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
 133                 xhci->quirks |= XHCI_AMD_PLL_FIX;
 134
 135         if (pdev->vendor == PCI_VENDOR_ID_AMD)
 136                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 137
 138         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 139                 xhci->quirks |= XHCI_LPM_SUPPORT;
 140                 xhci->quirks |= XHCI_INTEL_HOST;
 141                 xhci->quirks |= XHCI_AVOID_BEI;
 142         }
 143         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 144                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
 145                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
 146                 xhci->limit_active_eps = 64;
 147                 xhci->quirks |= XHCI_SW_BW_CHECKING;
 148                 /*
 149                  * PPT desktop boards DH77EB and DH77DF will power back on after
 150                  * a few seconds of being shutdown.  The fix for this is to
 151                  * switch the ports from xHCI to EHCI on shutdown.  We can't use
 152                  * DMI information to find those particular boards (since each
 153                  * vendor will change the board name), so we have to key off all
 154                  * PPT chipsets.
 155                  */
 156                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 157         }
 158         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 159                 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
 160                  pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
 161                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 162                 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
 163         }
 164         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 165                 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 166                  pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 167                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 168                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
 169                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
 170                  pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 171                  pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) {
 172                 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
 173         }
 174         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 175                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
 176                 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
 177         }
 178         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 179             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 180              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 181              pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
 182                 xhci->quirks |= XHCI_MISSING_CAS;
 183
 184         if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
 185                         pdev->device == PCI_DEVICE_ID_EJ168) {
 186                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 187                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 188                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 189         }
 190         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 191                         pdev->device == 0x0015)
 192                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 193         if (pdev->vendor == PCI_VENDOR_ID_VIA)
 194                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 195
 196         /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
 197         if (pdev->vendor == PCI_VENDOR_ID_VIA &&
 198                         pdev->device == 0x3432)
 199                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 200
 201         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 202                         pdev->device == 0x1042)
 203                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 204
 205         if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
 206                 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
 207
 208         if (xhci->quirks & XHCI_RESET_ON_RESUME)
 209                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 210                                 "QUIRK: Resetting on resume");
 211 }
 212
 213 #ifdef CONFIG_ACPI
 214 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
 215 {
 216         static const u8 intel_dsm_uuid[] = {
 217                 0xb7, 0x0c, 0x34, 0xac, 0x01, 0xe9, 0xbf, 0x45,
 218                 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23,
 219         };
 220         union acpi_object *obj;
 221
 222         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), intel_dsm_uuid, 3, 1,
 223                                 NULL);
 224         ACPI_FREE(obj);
 225 }
 226 #else
 227 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
 228 #endif /* CONFIG_ACPI */
 229
 230 /* called during probe() after chip reset completes */
 231 static int xhci_pci_setup(struct usb_hcd *hcd)
 232 {
 233         struct xhci_hcd         *xhci;
 234         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 235         int                     retval;
 236
 237         xhci = hcd_to_xhci(hcd);
 238         if (!xhci->sbrn)
 239                 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 240
 241         retval = xhci_gen_setup(hcd, xhci_pci_quirks);
 242         if (retval)
 243                 return retval;
 244
 245         if (!usb_hcd_is_primary_hcd(hcd))
 246                 return 0;
 247
 248         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 249
 250         /* Find any debug ports */
 251         return xhci_pci_reinit(xhci, pdev);
 252 }
 253
 254 /*
 255  * We need to register our own PCI probe function (instead of the USB core's
 256  * function) in order to create a second roothub under xHCI.
 257  */
 258 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 259 {
 260         int retval;
 261         struct xhci_hcd *xhci;
 262         struct hc_driver *driver;
 263         struct usb_hcd *hcd;
 264
 265         driver = (struct hc_driver *)id->driver_data;
 266
 267         /* Prevent runtime suspending between USB-2 and USB-3 initialization */
 268         pm_runtime_get_noresume(&dev->dev);
 269
 270         /* Register the USB 2.0 roothub.
 271          * FIXME: USB core must know to register the USB 2.0 roothub first.
 272          * This is sort of silly, because we could just set the HCD driver flags
 273          * to say USB 2.0, but I'm not sure what the implications would be in
 274          * the other parts of the HCD code.
 275          */
 276         retval = usb_hcd_pci_probe(dev, id);
 277
 278         if (retval)
 279                 goto put_runtime_pm;
 280
 281         /* USB 2.0 roothub is stored in the PCI device now. */
 282         hcd = dev_get_drvdata(&dev->dev);
 283         xhci = hcd_to_xhci(hcd);
 284         xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
 285                                 pci_name(dev), hcd);
 286         if (!xhci->shared_hcd) {
 287                 retval = -ENOMEM;
 288                 goto dealloc_usb2_hcd;
 289         }
 290
 291         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 292                         IRQF_SHARED);
 293         if (retval)
 294                 goto put_usb3_hcd;
 295         /* Roothub already marked as USB 3.0 speed */
 296
 297         if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
 298                         HCC_MAX_PSA(xhci->hcc_params) >= 4)
 299                 xhci->shared_hcd->can_do_streams = 1;
 300
 301         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 302                 xhci_pme_acpi_rtd3_enable(dev);
 303
 304         /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
 305         pm_runtime_put_noidle(&dev->dev);
 306
 307         return 0;
 308
 309 put_usb3_hcd:
 310         usb_put_hcd(xhci->shared_hcd);
 311 dealloc_usb2_hcd:
 312         usb_hcd_pci_remove(dev);
 313 put_runtime_pm:
 314         pm_runtime_put_noidle(&dev->dev);
 315         return retval;
 316 }
 317
 318 static void xhci_pci_remove(struct pci_dev *dev)
 319 {
 320         struct xhci_hcd *xhci;
 321
 322         xhci = hcd_to_xhci(pci_get_drvdata(dev));
 323         xhci->xhc_state |= XHCI_STATE_REMOVING;
 324         if (xhci->shared_hcd) {
 325                 usb_remove_hcd(xhci->shared_hcd);
 326                 usb_put_hcd(xhci->shared_hcd);
 327         }
 328
 329         /* Workaround for spurious wakeups at shutdown with HSW */
 330         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 331                 pci_set_power_state(dev, PCI_D3hot);
 332
 333         usb_hcd_pci_remove(dev);
 334 }
 335
 336 #ifdef CONFIG_PM
 337 /*
 338  * In some Intel xHCI controllers, in order to get D3 working,
 339  * through a vendor specific SSIC CONFIG register at offset 0x883c,
 340  * SSIC PORT need to be marked as "unused" before putting xHCI
 341  * into D3. After D3 exit, the SSIC port need to be marked as "used".
 342  * Without this change, xHCI might not enter D3 state.
 343  */
 344 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
 345 {
 346         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 347         u32 val;
 348         void __iomem *reg;
 349         int i;
 350
 351         for (i = 0; i < SSIC_PORT_NUM; i++) {
 352                 reg = (void __iomem *) xhci->cap_regs +
 353                                 SSIC_PORT_CFG2 +
 354                                 i * SSIC_PORT_CFG2_OFFSET;
 355
 356                 /* Notify SSIC that SSIC profile programming is not done. */
 357                 val = readl(reg) & ~PROG_DONE;
 358                 writel(val, reg);
 359
 360                 /* Mark SSIC port as unused(suspend) or used(resume) */
 361                 val = readl(reg);
 362                 if (suspend)
 363                         val |= SSIC_PORT_UNUSED;
 364                 else
 365                         val &= ~SSIC_PORT_UNUSED;
 366                 writel(val, reg);
 367
 368                 /* Notify SSIC that SSIC profile programming is done */
 369                 val = readl(reg) | PROG_DONE;
 370                 writel(val, reg);
 371                 readl(reg);
 372         }
 373 }
 374
 375 /*
 376  * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 377  * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 378  */
 379 static void xhci_pme_quirk(struct usb_hcd *hcd)
 380 {
 381         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 382         void __iomem *reg;
 383         u32 val;
 384
 385         reg = (void __iomem *) xhci->cap_regs + 0x80a4;
 386         val = readl(reg);
 387         writel(val | BIT(28), reg);
 388         readl(reg);
 389 }
 390
 391 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 392 {
 393         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 394         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 395         int                     ret;
 396
 397         /*
 398          * Systems with the TI redriver that loses port status change events
 399          * need to have the registers polled during D3, so avoid D3cold.
 400          */
 401         if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
 402                 pci_d3cold_disable(pdev);
 403
 404         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 405                 xhci_pme_quirk(hcd);
 406
 407         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 408                 xhci_ssic_port_unused_quirk(hcd, true);
 409
 410         ret = xhci_suspend(xhci, do_wakeup);
 411         if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
 412                 xhci_ssic_port_unused_quirk(hcd, false);
 413
 414         return ret;
 415 }
 416
 417 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 418 {
 419         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 420         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 421         int                     retval = 0;
 422
 423         /* The BIOS on systems with the Intel Panther Point chipset may or may
 424          * not support xHCI natively.  That means that during system resume, it
 425          * may switch the ports back to EHCI so that users can use their
 426          * keyboard to select a kernel from GRUB after resume from hibernate.
 427          *
 428          * The BIOS is supposed to remember whether the OS had xHCI ports
 429          * enabled before resume, and switch the ports back to xHCI when the
 430          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 431          * writers.
 432          *
 433          * Unconditionally switch the ports back to xHCI after a system resume.
 434          * It should not matter whether the EHCI or xHCI controller is
 435          * resumed first. It's enough to do the switchover in xHCI because
 436          * USB core won't notice anything as the hub driver doesn't start
 437          * running again until after all the devices (including both EHCI and
 438          * xHCI host controllers) have been resumed.
 439          */
 440
 441         if (pdev->vendor == PCI_VENDOR_ID_INTEL)
 442                 usb_enable_intel_xhci_ports(pdev);
 443
 444         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 445                 xhci_ssic_port_unused_quirk(hcd, false);
 446
 447         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 448                 xhci_pme_quirk(hcd);
 449
 450         retval = xhci_resume(xhci, hibernated);
 451         return retval;
 452 }
 453 #endif /* CONFIG_PM */
 454
 455 /*-------------------------------------------------------------------------*/
 456
 457 /* PCI driver selection metadata; PCI hotplugging uses this */
 458 static const struct pci_device_id pci_ids[] = { {
 459         /* handle any USB 3.0 xHCI controller */
 460         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
 461         .driver_data =  (unsigned long) &xhci_pci_hc_driver,
 462         },
 463         { /* end: all zeroes */ }
 464 };
 465 MODULE_DEVICE_TABLE(pci, pci_ids);
 466
 467 /* pci driver glue; this is a "new style" PCI driver module */
 468 static struct pci_driver xhci_pci_driver = {
 469         .name =         (char *) hcd_name,
 470         .id_table =     pci_ids,
 471
 472         .probe =        xhci_pci_probe,
 473         .remove =       xhci_pci_remove,
 474         /* suspend and resume implemented later */
 475
 476         .shutdown =     usb_hcd_pci_shutdown,
 477 #ifdef CONFIG_PM
 478         .driver = {
 479                 .pm = &usb_hcd_pci_pm_ops
 480         },
 481 #endif
 482 };
 483
 484 static int __init xhci_pci_init(void)
 485 {
 486         xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
 487 #ifdef CONFIG_PM
 488         xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
 489         xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
 490 #endif
 491         return pci_register_driver(&xhci_pci_driver);
 492 }
 493 module_init(xhci_pci_init);
 494
 495 static void __exit xhci_pci_exit(void)
 496 {
 497         pci_unregister_driver(&xhci_pci_driver);
 498 }
 499 module_exit(xhci_pci_exit);
 500
 501 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
 502 MODULE_LICENSE("GPL");