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Merge branch 'immutable-devfreq-v5.13-rc1' into devfreq-next
[mirror_ubuntu-jammy-kernel.git] / drivers / usb / host / xhci-pci.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * xHCI host controller driver PCI Bus Glue.
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11 #include <linux/pci.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/acpi.h>
15 #include <linux/reset.h>
16
17 #include "xhci.h"
18 #include "xhci-trace.h"
19 #include "xhci-pci.h"
20
21 #define SSIC_PORT_NUM 2
22 #define SSIC_PORT_CFG2 0x880c
23 #define SSIC_PORT_CFG2_OFFSET 0x30
24 #define PROG_DONE (1 << 30)
25 #define SSIC_PORT_UNUSED (1 << 31)
26 #define SPARSE_DISABLE_BIT 17
27 #define SPARSE_CNTL_ENABLE 0xC12C
28
29 /* Device for a quirk */
30 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
31 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
32 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009
33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
34
35 #define PCI_VENDOR_ID_ETRON 0x1b6f
36 #define PCI_DEVICE_ID_EJ168 0x7023
37
38 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
39 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
40 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1
41 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
42 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
43 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
44 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
45 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
46 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
47 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0
48 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5
49 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6
50 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1
51 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db
52 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4
53 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9
54 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec
55 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0
56 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13
57 #define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af
58 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13
59 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138
60
61 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9
62 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba
63 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb
64 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc
65 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042
66 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142
67 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242
68 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142
69 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242
70
71 static const char hcd_name[] = "xhci_hcd";
72
73 static struct hc_driver __read_mostly xhci_pci_hc_driver;
74
75 static int xhci_pci_setup(struct usb_hcd *hcd);
76
77 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
78 .reset = xhci_pci_setup,
79 };
80
81 /* called after powerup, by probe or system-pm "wakeup" */
82 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
83 {
84 /*
85 * TODO: Implement finding debug ports later.
86 * TODO: see if there are any quirks that need to be added to handle
87 * new extended capabilities.
88 */
89
90 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
91 if (!pci_set_mwi(pdev))
92 xhci_dbg(xhci, "MWI active\n");
93
94 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
95 return 0;
96 }
97
98 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
99 {
100 struct pci_dev *pdev = to_pci_dev(dev);
101 struct xhci_driver_data *driver_data;
102 const struct pci_device_id *id;
103
104 id = pci_match_id(pdev->driver->id_table, pdev);
105
106 if (id && id->driver_data) {
107 driver_data = (struct xhci_driver_data *)id->driver_data;
108 xhci->quirks |= driver_data->quirks;
109 }
110
111 /* Look for vendor-specific quirks */
112 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
113 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
114 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
115 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
116 pdev->revision == 0x0) {
117 xhci->quirks |= XHCI_RESET_EP_QUIRK;
118 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
119 "QUIRK: Fresco Logic xHC needs configure"
120 " endpoint cmd after reset endpoint");
121 }
122 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
123 pdev->revision == 0x4) {
124 xhci->quirks |= XHCI_SLOW_SUSPEND;
125 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
126 "QUIRK: Fresco Logic xHC revision %u"
127 "must be suspended extra slowly",
128 pdev->revision);
129 }
130 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
131 xhci->quirks |= XHCI_BROKEN_STREAMS;
132 /* Fresco Logic confirms: all revisions of this chip do not
133 * support MSI, even though some of them claim to in their PCI
134 * capabilities.
135 */
136 xhci->quirks |= XHCI_BROKEN_MSI;
137 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
138 "QUIRK: Fresco Logic revision %u "
139 "has broken MSI implementation",
140 pdev->revision);
141 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
142 }
143
144 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
145 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
146 xhci->quirks |= XHCI_BROKEN_STREAMS;
147
148 if (pdev->vendor == PCI_VENDOR_ID_NEC)
149 xhci->quirks |= XHCI_NEC_HOST;
150
151 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
152 xhci->quirks |= XHCI_AMD_0x96_HOST;
153
154 /* AMD PLL quirk */
155 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check())
156 xhci->quirks |= XHCI_AMD_PLL_FIX;
157
158 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
159 (pdev->device == 0x145c ||
160 pdev->device == 0x15e0 ||
161 pdev->device == 0x15e1 ||
162 pdev->device == 0x43bb))
163 xhci->quirks |= XHCI_SUSPEND_DELAY;
164
165 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
166 (pdev->device == 0x15e0 || pdev->device == 0x15e1))
167 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
168
169 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5)
170 xhci->quirks |= XHCI_DISABLE_SPARSE;
171
172 if (pdev->vendor == PCI_VENDOR_ID_AMD)
173 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
174
175 if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
176 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
177 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
178 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
179 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
180 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
181
182 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
183 xhci->quirks |= XHCI_LPM_SUPPORT;
184 xhci->quirks |= XHCI_INTEL_HOST;
185 xhci->quirks |= XHCI_AVOID_BEI;
186 }
187 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
188 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
189 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
190 xhci->limit_active_eps = 64;
191 xhci->quirks |= XHCI_SW_BW_CHECKING;
192 /*
193 * PPT desktop boards DH77EB and DH77DF will power back on after
194 * a few seconds of being shutdown. The fix for this is to
195 * switch the ports from xHCI to EHCI on shutdown. We can't use
196 * DMI information to find those particular boards (since each
197 * vendor will change the board name), so we have to key off all
198 * PPT chipsets.
199 */
200 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
201 }
202 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
203 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
204 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
205 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
206 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
207 }
208 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
209 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
210 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
211 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
212 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
213 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
214 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
215 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
216 pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
217 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
218 }
219 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
220 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
221 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
222 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
223 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
224 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
225 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
226 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
227 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
228 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
229 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
230 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
231 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
232 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
233 xhci->quirks |= XHCI_MISSING_CAS;
234
235 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
236 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
237 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
238 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI ||
239 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
240 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
241 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
242 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
243 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
244 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI ||
245 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI ||
246 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI))
247 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
248
249 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
250 pdev->device == PCI_DEVICE_ID_EJ168) {
251 xhci->quirks |= XHCI_RESET_ON_RESUME;
252 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
253 xhci->quirks |= XHCI_BROKEN_STREAMS;
254 }
255 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
256 pdev->device == 0x0014) {
257 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
258 xhci->quirks |= XHCI_ZERO_64B_REGS;
259 }
260 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
261 pdev->device == 0x0015) {
262 xhci->quirks |= XHCI_RESET_ON_RESUME;
263 xhci->quirks |= XHCI_ZERO_64B_REGS;
264 }
265 if (pdev->vendor == PCI_VENDOR_ID_VIA)
266 xhci->quirks |= XHCI_RESET_ON_RESUME;
267
268 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
269 if (pdev->vendor == PCI_VENDOR_ID_VIA &&
270 pdev->device == 0x3432)
271 xhci->quirks |= XHCI_BROKEN_STREAMS;
272
273 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483)
274 xhci->quirks |= XHCI_LPM_SUPPORT;
275
276 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
277 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI)
278 xhci->quirks |= XHCI_BROKEN_STREAMS;
279 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
280 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) {
281 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
282 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
283 }
284 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
285 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
286 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI ||
287 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI))
288 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
289
290 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
291 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
292 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
293
294 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
295 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
296
297 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
298 pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
299 pdev->device == 0x9026)
300 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
301
302 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
303 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 ||
304 pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4))
305 xhci->quirks |= XHCI_NO_SOFT_RETRY;
306
307 if (xhci->quirks & XHCI_RESET_ON_RESUME)
308 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
309 "QUIRK: Resetting on resume");
310 }
311
312 #ifdef CONFIG_ACPI
313 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
314 {
315 static const guid_t intel_dsm_guid =
316 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
317 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
318 union acpi_object *obj;
319
320 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
321 NULL);
322 ACPI_FREE(obj);
323 }
324 #else
325 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
326 #endif /* CONFIG_ACPI */
327
328 /* called during probe() after chip reset completes */
329 static int xhci_pci_setup(struct usb_hcd *hcd)
330 {
331 struct xhci_hcd *xhci;
332 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
333 int retval;
334
335 xhci = hcd_to_xhci(hcd);
336 if (!xhci->sbrn)
337 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
338
339 /* imod_interval is the interrupt moderation value in nanoseconds. */
340 xhci->imod_interval = 40000;
341
342 retval = xhci_gen_setup(hcd, xhci_pci_quirks);
343 if (retval)
344 return retval;
345
346 if (!usb_hcd_is_primary_hcd(hcd))
347 return 0;
348
349 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
350 xhci_pme_acpi_rtd3_enable(pdev);
351
352 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
353
354 /* Find any debug ports */
355 return xhci_pci_reinit(xhci, pdev);
356 }
357
358 /*
359 * We need to register our own PCI probe function (instead of the USB core's
360 * function) in order to create a second roothub under xHCI.
361 */
362 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
363 {
364 int retval;
365 struct xhci_hcd *xhci;
366 struct usb_hcd *hcd;
367 struct xhci_driver_data *driver_data;
368 struct reset_control *reset;
369
370 driver_data = (struct xhci_driver_data *)id->driver_data;
371 if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) {
372 retval = renesas_xhci_check_request_fw(dev, id);
373 if (retval)
374 return retval;
375 }
376
377 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
378 if (IS_ERR(reset))
379 return PTR_ERR(reset);
380 reset_control_reset(reset);
381
382 /* Prevent runtime suspending between USB-2 and USB-3 initialization */
383 pm_runtime_get_noresume(&dev->dev);
384
385 /* Register the USB 2.0 roothub.
386 * FIXME: USB core must know to register the USB 2.0 roothub first.
387 * This is sort of silly, because we could just set the HCD driver flags
388 * to say USB 2.0, but I'm not sure what the implications would be in
389 * the other parts of the HCD code.
390 */
391 retval = usb_hcd_pci_probe(dev, id, &xhci_pci_hc_driver);
392
393 if (retval)
394 goto put_runtime_pm;
395
396 /* USB 2.0 roothub is stored in the PCI device now. */
397 hcd = dev_get_drvdata(&dev->dev);
398 xhci = hcd_to_xhci(hcd);
399 xhci->reset = reset;
400 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev,
401 pci_name(dev), hcd);
402 if (!xhci->shared_hcd) {
403 retval = -ENOMEM;
404 goto dealloc_usb2_hcd;
405 }
406
407 retval = xhci_ext_cap_init(xhci);
408 if (retval)
409 goto put_usb3_hcd;
410
411 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
412 IRQF_SHARED);
413 if (retval)
414 goto put_usb3_hcd;
415 /* Roothub already marked as USB 3.0 speed */
416
417 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
418 HCC_MAX_PSA(xhci->hcc_params) >= 4)
419 xhci->shared_hcd->can_do_streams = 1;
420
421 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
422 pm_runtime_put_noidle(&dev->dev);
423
424 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
425 pm_runtime_allow(&dev->dev);
426
427 return 0;
428
429 put_usb3_hcd:
430 usb_put_hcd(xhci->shared_hcd);
431 dealloc_usb2_hcd:
432 usb_hcd_pci_remove(dev);
433 put_runtime_pm:
434 pm_runtime_put_noidle(&dev->dev);
435 return retval;
436 }
437
438 static void xhci_pci_remove(struct pci_dev *dev)
439 {
440 struct xhci_hcd *xhci;
441
442 xhci = hcd_to_xhci(pci_get_drvdata(dev));
443 if (xhci->quirks & XHCI_RENESAS_FW_QUIRK)
444 renesas_xhci_pci_exit(dev);
445
446 xhci->xhc_state |= XHCI_STATE_REMOVING;
447
448 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
449 pm_runtime_forbid(&dev->dev);
450
451 if (xhci->shared_hcd) {
452 usb_remove_hcd(xhci->shared_hcd);
453 usb_put_hcd(xhci->shared_hcd);
454 xhci->shared_hcd = NULL;
455 }
456
457 /* Workaround for spurious wakeups at shutdown with HSW */
458 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
459 pci_set_power_state(dev, PCI_D3hot);
460
461 usb_hcd_pci_remove(dev);
462 }
463
464 #ifdef CONFIG_PM
465 /*
466 * In some Intel xHCI controllers, in order to get D3 working,
467 * through a vendor specific SSIC CONFIG register at offset 0x883c,
468 * SSIC PORT need to be marked as "unused" before putting xHCI
469 * into D3. After D3 exit, the SSIC port need to be marked as "used".
470 * Without this change, xHCI might not enter D3 state.
471 */
472 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
473 {
474 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
475 u32 val;
476 void __iomem *reg;
477 int i;
478
479 for (i = 0; i < SSIC_PORT_NUM; i++) {
480 reg = (void __iomem *) xhci->cap_regs +
481 SSIC_PORT_CFG2 +
482 i * SSIC_PORT_CFG2_OFFSET;
483
484 /* Notify SSIC that SSIC profile programming is not done. */
485 val = readl(reg) & ~PROG_DONE;
486 writel(val, reg);
487
488 /* Mark SSIC port as unused(suspend) or used(resume) */
489 val = readl(reg);
490 if (suspend)
491 val |= SSIC_PORT_UNUSED;
492 else
493 val &= ~SSIC_PORT_UNUSED;
494 writel(val, reg);
495
496 /* Notify SSIC that SSIC profile programming is done */
497 val = readl(reg) | PROG_DONE;
498 writel(val, reg);
499 readl(reg);
500 }
501 }
502
503 /*
504 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
505 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
506 */
507 static void xhci_pme_quirk(struct usb_hcd *hcd)
508 {
509 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
510 void __iomem *reg;
511 u32 val;
512
513 reg = (void __iomem *) xhci->cap_regs + 0x80a4;
514 val = readl(reg);
515 writel(val | BIT(28), reg);
516 readl(reg);
517 }
518
519 static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
520 {
521 u32 reg;
522
523 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
524 reg &= ~BIT(SPARSE_DISABLE_BIT);
525 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
526 }
527
528 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
529 {
530 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
531 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
532 int ret;
533
534 /*
535 * Systems with the TI redriver that loses port status change events
536 * need to have the registers polled during D3, so avoid D3cold.
537 */
538 if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
539 pci_d3cold_disable(pdev);
540
541 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
542 xhci_pme_quirk(hcd);
543
544 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
545 xhci_ssic_port_unused_quirk(hcd, true);
546
547 if (xhci->quirks & XHCI_DISABLE_SPARSE)
548 xhci_sparse_control_quirk(hcd);
549
550 ret = xhci_suspend(xhci, do_wakeup);
551 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
552 xhci_ssic_port_unused_quirk(hcd, false);
553
554 return ret;
555 }
556
557 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
558 {
559 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
560 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
561 int retval = 0;
562
563 reset_control_reset(xhci->reset);
564
565 /* The BIOS on systems with the Intel Panther Point chipset may or may
566 * not support xHCI natively. That means that during system resume, it
567 * may switch the ports back to EHCI so that users can use their
568 * keyboard to select a kernel from GRUB after resume from hibernate.
569 *
570 * The BIOS is supposed to remember whether the OS had xHCI ports
571 * enabled before resume, and switch the ports back to xHCI when the
572 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
573 * writers.
574 *
575 * Unconditionally switch the ports back to xHCI after a system resume.
576 * It should not matter whether the EHCI or xHCI controller is
577 * resumed first. It's enough to do the switchover in xHCI because
578 * USB core won't notice anything as the hub driver doesn't start
579 * running again until after all the devices (including both EHCI and
580 * xHCI host controllers) have been resumed.
581 */
582
583 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
584 usb_enable_intel_xhci_ports(pdev);
585
586 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
587 xhci_ssic_port_unused_quirk(hcd, false);
588
589 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
590 xhci_pme_quirk(hcd);
591
592 retval = xhci_resume(xhci, hibernated);
593 return retval;
594 }
595
596 static void xhci_pci_shutdown(struct usb_hcd *hcd)
597 {
598 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
599 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
600
601 xhci_shutdown(hcd);
602
603 /* Yet another workaround for spurious wakeups at shutdown with HSW */
604 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
605 pci_set_power_state(pdev, PCI_D3hot);
606 }
607 #endif /* CONFIG_PM */
608
609 /*-------------------------------------------------------------------------*/
610
611 static const struct xhci_driver_data reneses_data = {
612 .quirks = XHCI_RENESAS_FW_QUIRK,
613 .firmware = "renesas_usb_fw.mem",
614 };
615
616 /* PCI driver selection metadata; PCI hotplugging uses this */
617 static const struct pci_device_id pci_ids[] = {
618 { PCI_DEVICE(0x1912, 0x0014),
619 .driver_data = (unsigned long)&reneses_data,
620 },
621 { PCI_DEVICE(0x1912, 0x0015),
622 .driver_data = (unsigned long)&reneses_data,
623 },
624 /* handle any USB 3.0 xHCI controller */
625 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
626 },
627 { /* end: all zeroes */ }
628 };
629 MODULE_DEVICE_TABLE(pci, pci_ids);
630 MODULE_FIRMWARE("renesas_usb_fw.mem");
631
632 /* pci driver glue; this is a "new style" PCI driver module */
633 static struct pci_driver xhci_pci_driver = {
634 .name = hcd_name,
635 .id_table = pci_ids,
636
637 .probe = xhci_pci_probe,
638 .remove = xhci_pci_remove,
639 /* suspend and resume implemented later */
640
641 .shutdown = usb_hcd_pci_shutdown,
642 #ifdef CONFIG_PM
643 .driver = {
644 .pm = &usb_hcd_pci_pm_ops
645 },
646 #endif
647 };
648
649 static int __init xhci_pci_init(void)
650 {
651 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
652 #ifdef CONFIG_PM
653 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
654 xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
655 xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
656 #endif
657 return pci_register_driver(&xhci_pci_driver);
658 }
659 module_init(xhci_pci_init);
660
661 static void __exit xhci_pci_exit(void)
662 {
663 pci_unregister_driver(&xhci_pci_driver);
664 }
665 module_exit(xhci_pci_exit);
666
667 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
668 MODULE_LICENSE("GPL");
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