2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
71 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
74 dma_addr_t
xhci_trb_virt_to_dma(struct xhci_segment
*seg
,
77 unsigned long segment_offset
;
79 if (!seg
|| !trb
|| trb
< seg
->trbs
)
82 segment_offset
= trb
- seg
->trbs
;
83 if (segment_offset
> TRBS_PER_SEGMENT
)
85 return seg
->dma
+ (segment_offset
* sizeof(*trb
));
88 /* Does this link TRB point to the first segment in a ring,
89 * or was the previous TRB the last TRB on the last segment in the ERST?
91 static inline bool last_trb_on_last_seg(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
92 struct xhci_segment
*seg
, union xhci_trb
*trb
)
94 if (ring
== xhci
->event_ring
)
95 return (trb
== &seg
->trbs
[TRBS_PER_SEGMENT
]) &&
96 (seg
->next
== xhci
->event_ring
->first_seg
);
98 return trb
->link
.control
& LINK_TOGGLE
;
101 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
102 * segment? I.e. would the updated event TRB pointer step off the end of the
105 static inline int last_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
106 struct xhci_segment
*seg
, union xhci_trb
*trb
)
108 if (ring
== xhci
->event_ring
)
109 return trb
== &seg
->trbs
[TRBS_PER_SEGMENT
];
111 return (trb
->link
.control
& TRB_TYPE_BITMASK
) == TRB_TYPE(TRB_LINK
);
114 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
115 * TRB is in a new segment. This does not skip over link TRBs, and it does not
116 * effect the ring dequeue or enqueue pointers.
118 static void next_trb(struct xhci_hcd
*xhci
,
119 struct xhci_ring
*ring
,
120 struct xhci_segment
**seg
,
121 union xhci_trb
**trb
)
123 if (last_trb(xhci
, ring
, *seg
, *trb
)) {
125 *trb
= ((*seg
)->trbs
);
132 * See Cycle bit rules. SW is the consumer for the event ring only.
133 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
135 static void inc_deq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
, bool consumer
)
137 union xhci_trb
*next
= ++(ring
->dequeue
);
138 unsigned long long addr
;
141 /* Update the dequeue pointer further if that was a link TRB or we're at
142 * the end of an event ring segment (which doesn't have link TRBS)
144 while (last_trb(xhci
, ring
, ring
->deq_seg
, next
)) {
145 if (consumer
&& last_trb_on_last_seg(xhci
, ring
, ring
->deq_seg
, next
)) {
146 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
148 xhci_dbg(xhci
, "Toggle cycle state for ring %p = %i\n",
150 (unsigned int) ring
->cycle_state
);
152 ring
->deq_seg
= ring
->deq_seg
->next
;
153 ring
->dequeue
= ring
->deq_seg
->trbs
;
154 next
= ring
->dequeue
;
156 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->deq_seg
, ring
->dequeue
);
157 if (ring
== xhci
->event_ring
)
158 xhci_dbg(xhci
, "Event ring deq = 0x%llx (DMA)\n", addr
);
159 else if (ring
== xhci
->cmd_ring
)
160 xhci_dbg(xhci
, "Command ring deq = 0x%llx (DMA)\n", addr
);
162 xhci_dbg(xhci
, "Ring deq = 0x%llx (DMA)\n", addr
);
166 * See Cycle bit rules. SW is the consumer for the event ring only.
167 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
169 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
170 * chain bit is set), then set the chain bit in all the following link TRBs.
171 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
172 * have their chain bit cleared (so that each Link TRB is a separate TD).
174 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
175 * set, but other sections talk about dealing with the chain bit set. This was
176 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
177 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
179 static void inc_enq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
, bool consumer
)
182 union xhci_trb
*next
;
183 unsigned long long addr
;
185 chain
= ring
->enqueue
->generic
.field
[3] & TRB_CHAIN
;
186 next
= ++(ring
->enqueue
);
189 /* Update the dequeue pointer further if that was a link TRB or we're at
190 * the end of an event ring segment (which doesn't have link TRBS)
192 while (last_trb(xhci
, ring
, ring
->enq_seg
, next
)) {
194 if (ring
!= xhci
->event_ring
) {
195 /* If we're not dealing with 0.95 hardware,
196 * carry over the chain bit of the previous TRB
197 * (which may mean the chain bit is cleared).
199 if (!xhci_link_trb_quirk(xhci
)) {
200 next
->link
.control
&= ~TRB_CHAIN
;
201 next
->link
.control
|= chain
;
203 /* Give this link TRB to the hardware */
205 if (next
->link
.control
& TRB_CYCLE
)
206 next
->link
.control
&= (u32
) ~TRB_CYCLE
;
208 next
->link
.control
|= (u32
) TRB_CYCLE
;
210 /* Toggle the cycle bit after the last ring segment. */
211 if (last_trb_on_last_seg(xhci
, ring
, ring
->enq_seg
, next
)) {
212 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
214 xhci_dbg(xhci
, "Toggle cycle state for ring %p = %i\n",
216 (unsigned int) ring
->cycle_state
);
219 ring
->enq_seg
= ring
->enq_seg
->next
;
220 ring
->enqueue
= ring
->enq_seg
->trbs
;
221 next
= ring
->enqueue
;
223 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->enq_seg
, ring
->enqueue
);
224 if (ring
== xhci
->event_ring
)
225 xhci_dbg(xhci
, "Event ring enq = 0x%llx (DMA)\n", addr
);
226 else if (ring
== xhci
->cmd_ring
)
227 xhci_dbg(xhci
, "Command ring enq = 0x%llx (DMA)\n", addr
);
229 xhci_dbg(xhci
, "Ring enq = 0x%llx (DMA)\n", addr
);
233 * Check to see if there's room to enqueue num_trbs on the ring. See rules
235 * FIXME: this would be simpler and faster if we just kept track of the number
236 * of free TRBs in a ring.
238 static int room_on_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
239 unsigned int num_trbs
)
242 union xhci_trb
*enq
= ring
->enqueue
;
243 struct xhci_segment
*enq_seg
= ring
->enq_seg
;
245 /* Check if ring is empty */
246 if (enq
== ring
->dequeue
)
248 /* Make sure there's an extra empty TRB available */
249 for (i
= 0; i
<= num_trbs
; ++i
) {
250 if (enq
== ring
->dequeue
)
253 while (last_trb(xhci
, ring
, enq_seg
, enq
)) {
254 enq_seg
= enq_seg
->next
;
261 void xhci_set_hc_event_deq(struct xhci_hcd
*xhci
)
266 deq
= xhci_trb_virt_to_dma(xhci
->event_ring
->deq_seg
,
267 xhci
->event_ring
->dequeue
);
268 if (deq
== 0 && !in_interrupt())
269 xhci_warn(xhci
, "WARN something wrong with SW event ring "
271 /* Update HC event ring dequeue pointer */
272 temp
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
273 temp
&= ERST_PTR_MASK
;
274 /* Don't clear the EHB bit (which is RW1C) because
275 * there might be more events to service.
278 xhci_dbg(xhci
, "// Write event ring dequeue pointer, preserving EHB bit\n");
279 xhci_write_64(xhci
, ((u64
) deq
& (u64
) ~ERST_PTR_MASK
) | temp
,
280 &xhci
->ir_set
->erst_dequeue
);
283 /* Ring the host controller doorbell after placing a command on the ring */
284 void xhci_ring_cmd_db(struct xhci_hcd
*xhci
)
288 xhci_dbg(xhci
, "// Ding dong!\n");
289 temp
= xhci_readl(xhci
, &xhci
->dba
->doorbell
[0]) & DB_MASK
;
290 xhci_writel(xhci
, temp
| DB_TARGET_HOST
, &xhci
->dba
->doorbell
[0]);
291 /* Flush PCI posted writes */
292 xhci_readl(xhci
, &xhci
->dba
->doorbell
[0]);
295 static void ring_ep_doorbell(struct xhci_hcd
*xhci
,
296 unsigned int slot_id
,
297 unsigned int ep_index
)
299 struct xhci_virt_ep
*ep
;
300 unsigned int ep_state
;
302 __u32 __iomem
*db_addr
= &xhci
->dba
->doorbell
[slot_id
];
304 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
305 ep_state
= ep
->ep_state
;
306 /* Don't ring the doorbell for this endpoint if there are pending
307 * cancellations because the we don't want to interrupt processing.
309 if (!(ep_state
& EP_HALT_PENDING
) && !(ep_state
& SET_DEQ_PENDING
)
310 && !(ep_state
& EP_HALTED
)) {
311 field
= xhci_readl(xhci
, db_addr
) & DB_MASK
;
312 xhci_writel(xhci
, field
| EPI_TO_DB(ep_index
), db_addr
);
313 /* Flush PCI posted writes - FIXME Matthew Wilcox says this
314 * isn't time-critical and we shouldn't make the CPU wait for
317 xhci_readl(xhci
, db_addr
);
322 * Find the segment that trb is in. Start searching in start_seg.
323 * If we must move past a segment that has a link TRB with a toggle cycle state
324 * bit set, then we will toggle the value pointed at by cycle_state.
326 static struct xhci_segment
*find_trb_seg(
327 struct xhci_segment
*start_seg
,
328 union xhci_trb
*trb
, int *cycle_state
)
330 struct xhci_segment
*cur_seg
= start_seg
;
331 struct xhci_generic_trb
*generic_trb
;
333 while (cur_seg
->trbs
> trb
||
334 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1] < trb
) {
335 generic_trb
= &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1].generic
;
336 if (TRB_TYPE(generic_trb
->field
[3]) == TRB_LINK
&&
337 (generic_trb
->field
[3] & LINK_TOGGLE
))
338 *cycle_state
= ~(*cycle_state
) & 0x1;
339 cur_seg
= cur_seg
->next
;
340 if (cur_seg
== start_seg
)
341 /* Looped over the entire list. Oops! */
348 * Move the xHC's endpoint ring dequeue pointer past cur_td.
349 * Record the new state of the xHC's endpoint ring dequeue segment,
350 * dequeue pointer, and new consumer cycle state in state.
351 * Update our internal representation of the ring's dequeue pointer.
353 * We do this in three jumps:
354 * - First we update our new ring state to be the same as when the xHC stopped.
355 * - Then we traverse the ring to find the segment that contains
356 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
357 * any link TRBs with the toggle cycle bit set.
358 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
359 * if we've moved it past a link TRB with the toggle cycle bit set.
361 void xhci_find_new_dequeue_state(struct xhci_hcd
*xhci
,
362 unsigned int slot_id
, unsigned int ep_index
,
363 struct xhci_td
*cur_td
, struct xhci_dequeue_state
*state
)
365 struct xhci_virt_device
*dev
= xhci
->devs
[slot_id
];
366 struct xhci_ring
*ep_ring
= dev
->eps
[ep_index
].ring
;
367 struct xhci_generic_trb
*trb
;
368 struct xhci_ep_ctx
*ep_ctx
;
371 state
->new_cycle_state
= 0;
372 xhci_dbg(xhci
, "Finding segment containing stopped TRB.\n");
373 state
->new_deq_seg
= find_trb_seg(cur_td
->start_seg
,
374 dev
->eps
[ep_index
].stopped_trb
,
375 &state
->new_cycle_state
);
376 if (!state
->new_deq_seg
)
378 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
379 xhci_dbg(xhci
, "Finding endpoint context\n");
380 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
381 state
->new_cycle_state
= 0x1 & ep_ctx
->deq
;
383 state
->new_deq_ptr
= cur_td
->last_trb
;
384 xhci_dbg(xhci
, "Finding segment containing last TRB in TD.\n");
385 state
->new_deq_seg
= find_trb_seg(state
->new_deq_seg
,
387 &state
->new_cycle_state
);
388 if (!state
->new_deq_seg
)
391 trb
= &state
->new_deq_ptr
->generic
;
392 if (TRB_TYPE(trb
->field
[3]) == TRB_LINK
&&
393 (trb
->field
[3] & LINK_TOGGLE
))
394 state
->new_cycle_state
= ~(state
->new_cycle_state
) & 0x1;
395 next_trb(xhci
, ep_ring
, &state
->new_deq_seg
, &state
->new_deq_ptr
);
397 /* Don't update the ring cycle state for the producer (us). */
398 xhci_dbg(xhci
, "New dequeue segment = %p (virtual)\n",
400 addr
= xhci_trb_virt_to_dma(state
->new_deq_seg
, state
->new_deq_ptr
);
401 xhci_dbg(xhci
, "New dequeue pointer = 0x%llx (DMA)\n",
402 (unsigned long long) addr
);
403 xhci_dbg(xhci
, "Setting dequeue pointer in internal ring state.\n");
404 ep_ring
->dequeue
= state
->new_deq_ptr
;
405 ep_ring
->deq_seg
= state
->new_deq_seg
;
408 static void td_to_noop(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
409 struct xhci_td
*cur_td
)
411 struct xhci_segment
*cur_seg
;
412 union xhci_trb
*cur_trb
;
414 for (cur_seg
= cur_td
->start_seg
, cur_trb
= cur_td
->first_trb
;
416 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
417 if ((cur_trb
->generic
.field
[3] & TRB_TYPE_BITMASK
) ==
418 TRB_TYPE(TRB_LINK
)) {
419 /* Unchain any chained Link TRBs, but
420 * leave the pointers intact.
422 cur_trb
->generic
.field
[3] &= ~TRB_CHAIN
;
423 xhci_dbg(xhci
, "Cancel (unchain) link TRB\n");
424 xhci_dbg(xhci
, "Address = %p (0x%llx dma); "
425 "in seg %p (0x%llx dma)\n",
427 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
429 (unsigned long long)cur_seg
->dma
);
431 cur_trb
->generic
.field
[0] = 0;
432 cur_trb
->generic
.field
[1] = 0;
433 cur_trb
->generic
.field
[2] = 0;
434 /* Preserve only the cycle bit of this TRB */
435 cur_trb
->generic
.field
[3] &= TRB_CYCLE
;
436 cur_trb
->generic
.field
[3] |= TRB_TYPE(TRB_TR_NOOP
);
437 xhci_dbg(xhci
, "Cancel TRB %p (0x%llx dma) "
438 "in seg %p (0x%llx dma)\n",
440 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
442 (unsigned long long)cur_seg
->dma
);
444 if (cur_trb
== cur_td
->last_trb
)
449 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
450 unsigned int ep_index
, struct xhci_segment
*deq_seg
,
451 union xhci_trb
*deq_ptr
, u32 cycle_state
);
453 void xhci_queue_new_dequeue_state(struct xhci_hcd
*xhci
,
454 unsigned int slot_id
, unsigned int ep_index
,
455 struct xhci_dequeue_state
*deq_state
)
457 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
459 xhci_dbg(xhci
, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
460 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
461 deq_state
->new_deq_seg
,
462 (unsigned long long)deq_state
->new_deq_seg
->dma
,
463 deq_state
->new_deq_ptr
,
464 (unsigned long long)xhci_trb_virt_to_dma(deq_state
->new_deq_seg
, deq_state
->new_deq_ptr
),
465 deq_state
->new_cycle_state
);
466 queue_set_tr_deq(xhci
, slot_id
, ep_index
,
467 deq_state
->new_deq_seg
,
468 deq_state
->new_deq_ptr
,
469 (u32
) deq_state
->new_cycle_state
);
470 /* Stop the TD queueing code from ringing the doorbell until
471 * this command completes. The HC won't set the dequeue pointer
472 * if the ring is running, and ringing the doorbell starts the
475 ep
->ep_state
|= SET_DEQ_PENDING
;
479 * When we get a command completion for a Stop Endpoint Command, we need to
480 * unlink any cancelled TDs from the ring. There are two ways to do that:
482 * 1. If the HW was in the middle of processing the TD that needs to be
483 * cancelled, then we must move the ring's dequeue pointer past the last TRB
484 * in the TD with a Set Dequeue Pointer Command.
485 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
486 * bit cleared) so that the HW will skip over them.
488 static void handle_stopped_endpoint(struct xhci_hcd
*xhci
,
491 unsigned int slot_id
;
492 unsigned int ep_index
;
493 struct xhci_ring
*ep_ring
;
494 struct xhci_virt_ep
*ep
;
495 struct list_head
*entry
;
496 struct xhci_td
*cur_td
= 0;
497 struct xhci_td
*last_unlinked_td
;
499 struct xhci_dequeue_state deq_state
;
500 #ifdef CONFIG_USB_HCD_STAT
501 ktime_t stop_time
= ktime_get();
504 memset(&deq_state
, 0, sizeof(deq_state
));
505 slot_id
= TRB_TO_SLOT_ID(trb
->generic
.field
[3]);
506 ep_index
= TRB_TO_EP_INDEX(trb
->generic
.field
[3]);
507 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
510 if (list_empty(&ep
->cancelled_td_list
)) {
511 ep
->ep_state
&= ~EP_HALT_PENDING
;
512 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
516 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
517 * We have the xHCI lock, so nothing can modify this list until we drop
518 * it. We're also in the event handler, so we can't get re-interrupted
519 * if another Stop Endpoint command completes
521 list_for_each(entry
, &ep
->cancelled_td_list
) {
522 cur_td
= list_entry(entry
, struct xhci_td
, cancelled_td_list
);
523 xhci_dbg(xhci
, "Cancelling TD starting at %p, 0x%llx (dma).\n",
525 (unsigned long long)xhci_trb_virt_to_dma(cur_td
->start_seg
, cur_td
->first_trb
));
527 * If we stopped on the TD we need to cancel, then we have to
528 * move the xHC endpoint ring dequeue pointer past this TD.
530 if (cur_td
== ep
->stopped_td
)
531 xhci_find_new_dequeue_state(xhci
, slot_id
, ep_index
, cur_td
,
534 td_to_noop(xhci
, ep_ring
, cur_td
);
536 * The event handler won't see a completion for this TD anymore,
537 * so remove it from the endpoint ring's TD list. Keep it in
538 * the cancelled TD list for URB completion later.
540 list_del(&cur_td
->td_list
);
542 last_unlinked_td
= cur_td
;
543 ep
->ep_state
&= ~EP_HALT_PENDING
;
545 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
546 if (deq_state
.new_deq_ptr
&& deq_state
.new_deq_seg
) {
547 xhci_queue_new_dequeue_state(xhci
,
548 slot_id
, ep_index
, &deq_state
);
549 xhci_ring_cmd_db(xhci
);
551 /* Otherwise just ring the doorbell to restart the ring */
552 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
556 * Drop the lock and complete the URBs in the cancelled TD list.
557 * New TDs to be cancelled might be added to the end of the list before
558 * we can complete all the URBs for the TDs we already unlinked.
559 * So stop when we've completed the URB for the last TD we unlinked.
562 cur_td
= list_entry(ep
->cancelled_td_list
.next
,
563 struct xhci_td
, cancelled_td_list
);
564 list_del(&cur_td
->cancelled_td_list
);
566 /* Clean up the cancelled URB */
567 #ifdef CONFIG_USB_HCD_STAT
568 hcd_stat_update(xhci
->tp_stat
, cur_td
->urb
->actual_length
,
569 ktime_sub(stop_time
, cur_td
->start_time
));
571 cur_td
->urb
->hcpriv
= NULL
;
572 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci
), cur_td
->urb
);
574 xhci_dbg(xhci
, "Giveback cancelled URB %p\n", cur_td
->urb
);
575 spin_unlock(&xhci
->lock
);
576 /* Doesn't matter what we pass for status, since the core will
577 * just overwrite it (because the URB has been unlinked).
579 usb_hcd_giveback_urb(xhci_to_hcd(xhci
), cur_td
->urb
, 0);
582 spin_lock(&xhci
->lock
);
583 } while (cur_td
!= last_unlinked_td
);
585 /* Return to the event handler with xhci->lock re-acquired */
589 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
590 * we need to clear the set deq pending flag in the endpoint ring state, so that
591 * the TD queueing code can ring the doorbell again. We also need to ring the
592 * endpoint doorbell to restart the ring, but only if there aren't more
593 * cancellations pending.
595 static void handle_set_deq_completion(struct xhci_hcd
*xhci
,
596 struct xhci_event_cmd
*event
,
599 unsigned int slot_id
;
600 unsigned int ep_index
;
601 struct xhci_ring
*ep_ring
;
602 struct xhci_virt_device
*dev
;
603 struct xhci_ep_ctx
*ep_ctx
;
604 struct xhci_slot_ctx
*slot_ctx
;
606 slot_id
= TRB_TO_SLOT_ID(trb
->generic
.field
[3]);
607 ep_index
= TRB_TO_EP_INDEX(trb
->generic
.field
[3]);
608 dev
= xhci
->devs
[slot_id
];
609 ep_ring
= dev
->eps
[ep_index
].ring
;
610 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
611 slot_ctx
= xhci_get_slot_ctx(xhci
, dev
->out_ctx
);
613 if (GET_COMP_CODE(event
->status
) != COMP_SUCCESS
) {
614 unsigned int ep_state
;
615 unsigned int slot_state
;
617 switch (GET_COMP_CODE(event
->status
)) {
619 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd invalid because "
620 "of stream ID configuration\n");
623 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed due "
624 "to incorrect slot or ep state.\n");
625 ep_state
= ep_ctx
->ep_info
;
626 ep_state
&= EP_STATE_MASK
;
627 slot_state
= slot_ctx
->dev_state
;
628 slot_state
= GET_SLOT_STATE(slot_state
);
629 xhci_dbg(xhci
, "Slot state = %u, EP state = %u\n",
630 slot_state
, ep_state
);
633 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed because "
634 "slot %u was not enabled.\n", slot_id
);
637 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd with unknown "
638 "completion code of %u.\n",
639 GET_COMP_CODE(event
->status
));
642 /* OK what do we do now? The endpoint state is hosed, and we
643 * should never get to this point if the synchronization between
644 * queueing, and endpoint state are correct. This might happen
645 * if the device gets disconnected after we've finished
646 * cancelling URBs, which might not be an error...
649 xhci_dbg(xhci
, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
653 dev
->eps
[ep_index
].ep_state
&= ~SET_DEQ_PENDING
;
654 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
657 static void handle_reset_ep_completion(struct xhci_hcd
*xhci
,
658 struct xhci_event_cmd
*event
,
662 unsigned int ep_index
;
663 struct xhci_ring
*ep_ring
;
665 slot_id
= TRB_TO_SLOT_ID(trb
->generic
.field
[3]);
666 ep_index
= TRB_TO_EP_INDEX(trb
->generic
.field
[3]);
667 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
668 /* This command will only fail if the endpoint wasn't halted,
671 xhci_dbg(xhci
, "Ignoring reset ep completion code of %u\n",
672 (unsigned int) GET_COMP_CODE(event
->status
));
674 /* HW with the reset endpoint quirk needs to have a configure endpoint
675 * command complete before the endpoint can be used. Queue that here
676 * because the HW can't handle two commands being queued in a row.
678 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
) {
679 xhci_dbg(xhci
, "Queueing configure endpoint command\n");
680 xhci_queue_configure_endpoint(xhci
,
681 xhci
->devs
[slot_id
]->in_ctx
->dma
, slot_id
,
683 xhci_ring_cmd_db(xhci
);
685 /* Clear our internal halted state and restart the ring */
686 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&= ~EP_HALTED
;
687 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
691 /* Check to see if a command in the device's command queue matches this one.
692 * Signal the completion or free the command, and return 1. Return 0 if the
693 * completed command isn't at the head of the command list.
695 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd
*xhci
,
696 struct xhci_virt_device
*virt_dev
,
697 struct xhci_event_cmd
*event
)
699 struct xhci_command
*command
;
701 if (list_empty(&virt_dev
->cmd_list
))
704 command
= list_entry(virt_dev
->cmd_list
.next
,
705 struct xhci_command
, cmd_list
);
706 if (xhci
->cmd_ring
->dequeue
!= command
->command_trb
)
710 GET_COMP_CODE(event
->status
);
711 list_del(&command
->cmd_list
);
712 if (command
->completion
)
713 complete(command
->completion
);
715 xhci_free_command(xhci
, command
);
719 static void handle_cmd_completion(struct xhci_hcd
*xhci
,
720 struct xhci_event_cmd
*event
)
722 int slot_id
= TRB_TO_SLOT_ID(event
->flags
);
724 dma_addr_t cmd_dequeue_dma
;
725 struct xhci_input_control_ctx
*ctrl_ctx
;
726 struct xhci_virt_device
*virt_dev
;
727 unsigned int ep_index
;
728 struct xhci_ring
*ep_ring
;
729 unsigned int ep_state
;
731 cmd_dma
= event
->cmd_trb
;
732 cmd_dequeue_dma
= xhci_trb_virt_to_dma(xhci
->cmd_ring
->deq_seg
,
733 xhci
->cmd_ring
->dequeue
);
734 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
735 if (cmd_dequeue_dma
== 0) {
736 xhci
->error_bitmask
|= 1 << 4;
739 /* Does the DMA address match our internal dequeue pointer address? */
740 if (cmd_dma
!= (u64
) cmd_dequeue_dma
) {
741 xhci
->error_bitmask
|= 1 << 5;
744 switch (xhci
->cmd_ring
->dequeue
->generic
.field
[3] & TRB_TYPE_BITMASK
) {
745 case TRB_TYPE(TRB_ENABLE_SLOT
):
746 if (GET_COMP_CODE(event
->status
) == COMP_SUCCESS
)
747 xhci
->slot_id
= slot_id
;
750 complete(&xhci
->addr_dev
);
752 case TRB_TYPE(TRB_DISABLE_SLOT
):
753 if (xhci
->devs
[slot_id
])
754 xhci_free_virt_device(xhci
, slot_id
);
756 case TRB_TYPE(TRB_CONFIG_EP
):
757 virt_dev
= xhci
->devs
[slot_id
];
758 if (handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
))
761 * Configure endpoint commands can come from the USB core
762 * configuration or alt setting changes, or because the HW
763 * needed an extra configure endpoint command after a reset
764 * endpoint command. In the latter case, the xHCI driver is
765 * not waiting on the configure endpoint command.
767 ctrl_ctx
= xhci_get_input_control_ctx(xhci
,
769 /* Input ctx add_flags are the endpoint index plus one */
770 ep_index
= xhci_last_valid_endpoint(ctrl_ctx
->add_flags
) - 1;
771 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
773 /* This must have been an initial configure endpoint */
774 xhci
->devs
[slot_id
]->cmd_status
=
775 GET_COMP_CODE(event
->status
);
776 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
779 ep_state
= xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
;
780 xhci_dbg(xhci
, "Completed config ep cmd - last ep index = %d, "
781 "state = %d\n", ep_index
, ep_state
);
782 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
&&
783 ep_state
& EP_HALTED
) {
784 /* Clear our internal halted state and restart ring */
785 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&=
787 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
789 xhci
->devs
[slot_id
]->cmd_status
=
790 GET_COMP_CODE(event
->status
);
791 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
794 case TRB_TYPE(TRB_EVAL_CONTEXT
):
795 virt_dev
= xhci
->devs
[slot_id
];
796 if (handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
))
798 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(event
->status
);
799 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
801 case TRB_TYPE(TRB_ADDR_DEV
):
802 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(event
->status
);
803 complete(&xhci
->addr_dev
);
805 case TRB_TYPE(TRB_STOP_RING
):
806 handle_stopped_endpoint(xhci
, xhci
->cmd_ring
->dequeue
);
808 case TRB_TYPE(TRB_SET_DEQ
):
809 handle_set_deq_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
811 case TRB_TYPE(TRB_CMD_NOOP
):
812 ++xhci
->noops_handled
;
814 case TRB_TYPE(TRB_RESET_EP
):
815 handle_reset_ep_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
818 /* Skip over unknown commands on the event ring */
819 xhci
->error_bitmask
|= 1 << 6;
822 inc_deq(xhci
, xhci
->cmd_ring
, false);
825 static void handle_port_status(struct xhci_hcd
*xhci
,
826 union xhci_trb
*event
)
830 /* Port status change events always have a successful completion code */
831 if (GET_COMP_CODE(event
->generic
.field
[2]) != COMP_SUCCESS
) {
832 xhci_warn(xhci
, "WARN: xHC returned failed port status event\n");
833 xhci
->error_bitmask
|= 1 << 8;
835 /* FIXME: core doesn't care about all port link state changes yet */
836 port_id
= GET_PORT_ID(event
->generic
.field
[0]);
837 xhci_dbg(xhci
, "Port Status Change Event for port %d\n", port_id
);
839 /* Update event ring dequeue pointer before dropping the lock */
840 inc_deq(xhci
, xhci
->event_ring
, true);
841 xhci_set_hc_event_deq(xhci
);
843 spin_unlock(&xhci
->lock
);
844 /* Pass this up to the core */
845 usb_hcd_poll_rh_status(xhci_to_hcd(xhci
));
846 spin_lock(&xhci
->lock
);
850 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
851 * at end_trb, which may be in another segment. If the suspect DMA address is a
852 * TRB in this TD, this function returns that TRB's segment. Otherwise it
855 static struct xhci_segment
*trb_in_td(
856 struct xhci_segment
*start_seg
,
857 union xhci_trb
*start_trb
,
858 union xhci_trb
*end_trb
,
859 dma_addr_t suspect_dma
)
861 dma_addr_t start_dma
;
862 dma_addr_t end_seg_dma
;
863 dma_addr_t end_trb_dma
;
864 struct xhci_segment
*cur_seg
;
866 start_dma
= xhci_trb_virt_to_dma(start_seg
, start_trb
);
872 /* We may get an event for a Link TRB in the middle of a TD */
873 end_seg_dma
= xhci_trb_virt_to_dma(cur_seg
,
874 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1]);
875 /* If the end TRB isn't in this segment, this is set to 0 */
876 end_trb_dma
= xhci_trb_virt_to_dma(cur_seg
, end_trb
);
878 if (end_trb_dma
> 0) {
879 /* The end TRB is in this segment, so suspect should be here */
880 if (start_dma
<= end_trb_dma
) {
881 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_trb_dma
)
884 /* Case for one segment with
885 * a TD wrapped around to the top
887 if ((suspect_dma
>= start_dma
&&
888 suspect_dma
<= end_seg_dma
) ||
889 (suspect_dma
>= cur_seg
->dma
&&
890 suspect_dma
<= end_trb_dma
))
895 /* Might still be somewhere in this segment */
896 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_seg_dma
)
899 cur_seg
= cur_seg
->next
;
900 start_dma
= xhci_trb_virt_to_dma(cur_seg
, &cur_seg
->trbs
[0]);
901 } while (cur_seg
!= start_seg
);
907 * If this function returns an error condition, it means it got a Transfer
908 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
909 * At this point, the host controller is probably hosed and should be reset.
911 static int handle_tx_event(struct xhci_hcd
*xhci
,
912 struct xhci_transfer_event
*event
)
914 struct xhci_virt_device
*xdev
;
915 struct xhci_virt_ep
*ep
;
916 struct xhci_ring
*ep_ring
;
917 unsigned int slot_id
;
919 struct xhci_td
*td
= 0;
920 dma_addr_t event_dma
;
921 struct xhci_segment
*event_seg
;
922 union xhci_trb
*event_trb
;
924 int status
= -EINPROGRESS
;
925 struct xhci_ep_ctx
*ep_ctx
;
928 xhci_dbg(xhci
, "In %s\n", __func__
);
929 slot_id
= TRB_TO_SLOT_ID(event
->flags
);
930 xdev
= xhci
->devs
[slot_id
];
932 xhci_err(xhci
, "ERROR Transfer event pointed to bad slot\n");
936 /* Endpoint ID is 1 based, our index is zero based */
937 ep_index
= TRB_TO_EP_ID(event
->flags
) - 1;
938 xhci_dbg(xhci
, "%s - ep index = %d\n", __func__
, ep_index
);
939 ep
= &xdev
->eps
[ep_index
];
941 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
942 if (!ep_ring
|| (ep_ctx
->ep_info
& EP_STATE_MASK
) == EP_STATE_DISABLED
) {
943 xhci_err(xhci
, "ERROR Transfer event pointed to disabled endpoint\n");
947 event_dma
= event
->buffer
;
948 /* This TRB should be in the TD at the head of this ring's TD list */
949 xhci_dbg(xhci
, "%s - checking for list empty\n", __func__
);
950 if (list_empty(&ep_ring
->td_list
)) {
951 xhci_warn(xhci
, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
952 TRB_TO_SLOT_ID(event
->flags
), ep_index
);
953 xhci_dbg(xhci
, "Event TRB with TRB type ID %u\n",
954 (unsigned int) (event
->flags
& TRB_TYPE_BITMASK
)>>10);
955 xhci_print_trb_offsets(xhci
, (union xhci_trb
*) event
);
959 xhci_dbg(xhci
, "%s - getting list entry\n", __func__
);
960 td
= list_entry(ep_ring
->td_list
.next
, struct xhci_td
, td_list
);
962 /* Is this a TRB in the currently executing TD? */
963 xhci_dbg(xhci
, "%s - looking for TD\n", __func__
);
964 event_seg
= trb_in_td(ep_ring
->deq_seg
, ep_ring
->dequeue
,
965 td
->last_trb
, event_dma
);
966 xhci_dbg(xhci
, "%s - found event_seg = %p\n", __func__
, event_seg
);
968 /* HC is busted, give up! */
969 xhci_err(xhci
, "ERROR Transfer event TRB DMA ptr not part of current TD\n");
972 event_trb
= &event_seg
->trbs
[(event_dma
- event_seg
->dma
) / sizeof(*event_trb
)];
973 xhci_dbg(xhci
, "Event TRB with TRB type ID %u\n",
974 (unsigned int) (event
->flags
& TRB_TYPE_BITMASK
)>>10);
975 xhci_dbg(xhci
, "Offset 0x00 (buffer lo) = 0x%x\n",
976 lower_32_bits(event
->buffer
));
977 xhci_dbg(xhci
, "Offset 0x04 (buffer hi) = 0x%x\n",
978 upper_32_bits(event
->buffer
));
979 xhci_dbg(xhci
, "Offset 0x08 (transfer length) = 0x%x\n",
980 (unsigned int) event
->transfer_len
);
981 xhci_dbg(xhci
, "Offset 0x0C (flags) = 0x%x\n",
982 (unsigned int) event
->flags
);
984 /* Look for common error cases */
985 trb_comp_code
= GET_COMP_CODE(event
->transfer_len
);
986 switch (trb_comp_code
) {
987 /* Skip codes that require special handling depending on
994 xhci_dbg(xhci
, "Stopped on Transfer TRB\n");
996 case COMP_STOP_INVAL
:
997 xhci_dbg(xhci
, "Stopped on No-op or Link TRB\n");
1000 xhci_warn(xhci
, "WARN: Stalled endpoint\n");
1001 ep
->ep_state
|= EP_HALTED
;
1005 xhci_warn(xhci
, "WARN: TRB error on endpoint\n");
1009 xhci_warn(xhci
, "WARN: transfer error on endpoint\n");
1013 xhci_warn(xhci
, "WARN: babble error on endpoint\n");
1014 status
= -EOVERFLOW
;
1017 xhci_warn(xhci
, "WARN: HC couldn't access mem fast enough\n");
1021 xhci_warn(xhci
, "ERROR Unknown event condition, HC probably busted\n");
1025 /* Now update the urb's actual_length and give back to the core */
1026 /* Was this a control transfer? */
1027 if (usb_endpoint_xfer_control(&td
->urb
->ep
->desc
)) {
1028 xhci_debug_trb(xhci
, xhci
->event_ring
->dequeue
);
1029 switch (trb_comp_code
) {
1031 if (event_trb
== ep_ring
->dequeue
) {
1032 xhci_warn(xhci
, "WARN: Success on ctrl setup TRB without IOC set??\n");
1033 status
= -ESHUTDOWN
;
1034 } else if (event_trb
!= td
->last_trb
) {
1035 xhci_warn(xhci
, "WARN: Success on ctrl data TRB without IOC set??\n");
1036 status
= -ESHUTDOWN
;
1038 xhci_dbg(xhci
, "Successful control transfer!\n");
1043 xhci_warn(xhci
, "WARN: short transfer on control ep\n");
1044 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1045 status
= -EREMOTEIO
;
1050 /* The 0.96 spec says a babbling control endpoint
1051 * is not halted. The 0.96 spec says it is. Some HW
1052 * claims to be 0.95 compliant, but it halts the control
1053 * endpoint anyway. Check if a babble halted the
1056 if (ep_ctx
->ep_info
!= EP_STATE_HALTED
)
1058 /* else fall through */
1060 /* Did we transfer part of the data (middle) phase? */
1061 if (event_trb
!= ep_ring
->dequeue
&&
1062 event_trb
!= td
->last_trb
)
1063 td
->urb
->actual_length
=
1064 td
->urb
->transfer_buffer_length
1065 - TRB_LEN(event
->transfer_len
);
1067 td
->urb
->actual_length
= 0;
1069 ep
->stopped_td
= td
;
1070 ep
->stopped_trb
= event_trb
;
1071 xhci_queue_reset_ep(xhci
, slot_id
, ep_index
);
1072 xhci_cleanup_stalled_ring(xhci
, td
->urb
->dev
, ep_index
);
1073 xhci_ring_cmd_db(xhci
);
1076 /* Others already handled above */
1080 * Did we transfer any data, despite the errors that might have
1081 * happened? I.e. did we get past the setup stage?
1083 if (event_trb
!= ep_ring
->dequeue
) {
1084 /* The event was for the status stage */
1085 if (event_trb
== td
->last_trb
) {
1086 if (td
->urb
->actual_length
!= 0) {
1087 /* Don't overwrite a previously set error code */
1088 if ((status
== -EINPROGRESS
||
1090 (td
->urb
->transfer_flags
1091 & URB_SHORT_NOT_OK
))
1092 /* Did we already see a short data stage? */
1093 status
= -EREMOTEIO
;
1095 td
->urb
->actual_length
=
1096 td
->urb
->transfer_buffer_length
;
1099 /* Maybe the event was for the data stage? */
1100 if (trb_comp_code
!= COMP_STOP_INVAL
) {
1101 /* We didn't stop on a link TRB in the middle */
1102 td
->urb
->actual_length
=
1103 td
->urb
->transfer_buffer_length
-
1104 TRB_LEN(event
->transfer_len
);
1105 xhci_dbg(xhci
, "Waiting for status stage event\n");
1112 switch (trb_comp_code
) {
1114 /* Double check that the HW transferred everything. */
1115 if (event_trb
!= td
->last_trb
) {
1116 xhci_warn(xhci
, "WARN Successful completion "
1118 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1119 status
= -EREMOTEIO
;
1123 if (usb_endpoint_xfer_bulk(&td
->urb
->ep
->desc
))
1124 xhci_dbg(xhci
, "Successful bulk "
1127 xhci_dbg(xhci
, "Successful interrupt "
1133 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1134 status
= -EREMOTEIO
;
1139 /* Others already handled above */
1142 dev_dbg(&td
->urb
->dev
->dev
,
1143 "ep %#x - asked for %d bytes, "
1144 "%d bytes untransferred\n",
1145 td
->urb
->ep
->desc
.bEndpointAddress
,
1146 td
->urb
->transfer_buffer_length
,
1147 TRB_LEN(event
->transfer_len
));
1148 /* Fast path - was this the last TRB in the TD for this URB? */
1149 if (event_trb
== td
->last_trb
) {
1150 if (TRB_LEN(event
->transfer_len
) != 0) {
1151 td
->urb
->actual_length
=
1152 td
->urb
->transfer_buffer_length
-
1153 TRB_LEN(event
->transfer_len
);
1154 if (td
->urb
->transfer_buffer_length
<
1155 td
->urb
->actual_length
) {
1156 xhci_warn(xhci
, "HC gave bad length "
1157 "of %d bytes left\n",
1158 TRB_LEN(event
->transfer_len
));
1159 td
->urb
->actual_length
= 0;
1160 if (td
->urb
->transfer_flags
&
1162 status
= -EREMOTEIO
;
1166 /* Don't overwrite a previously set error code */
1167 if (status
== -EINPROGRESS
) {
1168 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1169 status
= -EREMOTEIO
;
1174 td
->urb
->actual_length
= td
->urb
->transfer_buffer_length
;
1175 /* Ignore a short packet completion if the
1176 * untransferred length was zero.
1178 if (status
== -EREMOTEIO
)
1182 /* Slow path - walk the list, starting from the dequeue
1183 * pointer, to get the actual length transferred.
1185 union xhci_trb
*cur_trb
;
1186 struct xhci_segment
*cur_seg
;
1188 td
->urb
->actual_length
= 0;
1189 for (cur_trb
= ep_ring
->dequeue
, cur_seg
= ep_ring
->deq_seg
;
1190 cur_trb
!= event_trb
;
1191 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
1192 if (TRB_TYPE(cur_trb
->generic
.field
[3]) != TRB_TR_NOOP
&&
1193 TRB_TYPE(cur_trb
->generic
.field
[3]) != TRB_LINK
)
1194 td
->urb
->actual_length
+=
1195 TRB_LEN(cur_trb
->generic
.field
[2]);
1197 /* If the ring didn't stop on a Link or No-op TRB, add
1198 * in the actual bytes transferred from the Normal TRB
1200 if (trb_comp_code
!= COMP_STOP_INVAL
)
1201 td
->urb
->actual_length
+=
1202 TRB_LEN(cur_trb
->generic
.field
[2]) -
1203 TRB_LEN(event
->transfer_len
);
1206 if (trb_comp_code
== COMP_STOP_INVAL
||
1207 trb_comp_code
== COMP_STOP
) {
1208 /* The Endpoint Stop Command completion will take care of any
1209 * stopped TDs. A stopped TD may be restarted, so don't update
1210 * the ring dequeue pointer or take this TD off any lists yet.
1212 ep
->stopped_td
= td
;
1213 ep
->stopped_trb
= event_trb
;
1215 if (trb_comp_code
== COMP_STALL
||
1216 trb_comp_code
== COMP_BABBLE
) {
1217 /* The transfer is completed from the driver's
1218 * perspective, but we need to issue a set dequeue
1219 * command for this stalled endpoint to move the dequeue
1220 * pointer past the TD. We can't do that here because
1221 * the halt condition must be cleared first.
1223 ep
->stopped_td
= td
;
1224 ep
->stopped_trb
= event_trb
;
1226 /* Update ring dequeue pointer */
1227 while (ep_ring
->dequeue
!= td
->last_trb
)
1228 inc_deq(xhci
, ep_ring
, false);
1229 inc_deq(xhci
, ep_ring
, false);
1233 /* Clean up the endpoint's TD list */
1235 /* Do one last check of the actual transfer length.
1236 * If the host controller said we transferred more data than
1237 * the buffer length, urb->actual_length will be a very big
1238 * number (since it's unsigned). Play it safe and say we didn't
1239 * transfer anything.
1241 if (urb
->actual_length
> urb
->transfer_buffer_length
) {
1242 xhci_warn(xhci
, "URB transfer length is wrong, "
1243 "xHC issue? req. len = %u, "
1245 urb
->transfer_buffer_length
,
1246 urb
->actual_length
);
1247 urb
->actual_length
= 0;
1248 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1249 status
= -EREMOTEIO
;
1253 list_del(&td
->td_list
);
1254 /* Was this TD slated to be cancelled but completed anyway? */
1255 if (!list_empty(&td
->cancelled_td_list
))
1256 list_del(&td
->cancelled_td_list
);
1258 /* Leave the TD around for the reset endpoint function to use
1259 * (but only if it's not a control endpoint, since we already
1260 * queued the Set TR dequeue pointer command for stalled
1261 * control endpoints).
1263 if (usb_endpoint_xfer_control(&urb
->ep
->desc
) ||
1264 (trb_comp_code
!= COMP_STALL
&&
1265 trb_comp_code
!= COMP_BABBLE
)) {
1271 inc_deq(xhci
, xhci
->event_ring
, true);
1272 xhci_set_hc_event_deq(xhci
);
1274 /* FIXME for multi-TD URBs (who have buffers bigger than 64MB) */
1276 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci
), urb
);
1277 xhci_dbg(xhci
, "Giveback URB %p, len = %d, status = %d\n",
1278 urb
, urb
->actual_length
, status
);
1279 spin_unlock(&xhci
->lock
);
1280 usb_hcd_giveback_urb(xhci_to_hcd(xhci
), urb
, status
);
1281 spin_lock(&xhci
->lock
);
1287 * This function handles all OS-owned events on the event ring. It may drop
1288 * xhci->lock between event processing (e.g. to pass up port status changes).
1290 void xhci_handle_event(struct xhci_hcd
*xhci
)
1292 union xhci_trb
*event
;
1293 int update_ptrs
= 1;
1296 xhci_dbg(xhci
, "In %s\n", __func__
);
1297 if (!xhci
->event_ring
|| !xhci
->event_ring
->dequeue
) {
1298 xhci
->error_bitmask
|= 1 << 1;
1302 event
= xhci
->event_ring
->dequeue
;
1303 /* Does the HC or OS own the TRB? */
1304 if ((event
->event_cmd
.flags
& TRB_CYCLE
) !=
1305 xhci
->event_ring
->cycle_state
) {
1306 xhci
->error_bitmask
|= 1 << 2;
1309 xhci_dbg(xhci
, "%s - OS owns TRB\n", __func__
);
1311 /* FIXME: Handle more event types. */
1312 switch ((event
->event_cmd
.flags
& TRB_TYPE_BITMASK
)) {
1313 case TRB_TYPE(TRB_COMPLETION
):
1314 xhci_dbg(xhci
, "%s - calling handle_cmd_completion\n", __func__
);
1315 handle_cmd_completion(xhci
, &event
->event_cmd
);
1316 xhci_dbg(xhci
, "%s - returned from handle_cmd_completion\n", __func__
);
1318 case TRB_TYPE(TRB_PORT_STATUS
):
1319 xhci_dbg(xhci
, "%s - calling handle_port_status\n", __func__
);
1320 handle_port_status(xhci
, event
);
1321 xhci_dbg(xhci
, "%s - returned from handle_port_status\n", __func__
);
1324 case TRB_TYPE(TRB_TRANSFER
):
1325 xhci_dbg(xhci
, "%s - calling handle_tx_event\n", __func__
);
1326 ret
= handle_tx_event(xhci
, &event
->trans_event
);
1327 xhci_dbg(xhci
, "%s - returned from handle_tx_event\n", __func__
);
1329 xhci
->error_bitmask
|= 1 << 9;
1334 xhci
->error_bitmask
|= 1 << 3;
1338 /* Update SW and HC event ring dequeue pointer */
1339 inc_deq(xhci
, xhci
->event_ring
, true);
1340 xhci_set_hc_event_deq(xhci
);
1342 /* Are there more items on the event ring? */
1343 xhci_handle_event(xhci
);
1346 /**** Endpoint Ring Operations ****/
1349 * Generic function for queueing a TRB on a ring.
1350 * The caller must have checked to make sure there's room on the ring.
1352 static void queue_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
1354 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
1356 struct xhci_generic_trb
*trb
;
1358 trb
= &ring
->enqueue
->generic
;
1359 trb
->field
[0] = field1
;
1360 trb
->field
[1] = field2
;
1361 trb
->field
[2] = field3
;
1362 trb
->field
[3] = field4
;
1363 inc_enq(xhci
, ring
, consumer
);
1367 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
1368 * FIXME allocate segments if the ring is full.
1370 static int prepare_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
1371 u32 ep_state
, unsigned int num_trbs
, gfp_t mem_flags
)
1373 /* Make sure the endpoint has been added to xHC schedule */
1374 xhci_dbg(xhci
, "Endpoint state = 0x%x\n", ep_state
);
1376 case EP_STATE_DISABLED
:
1378 * USB core changed config/interfaces without notifying us,
1379 * or hardware is reporting the wrong state.
1381 xhci_warn(xhci
, "WARN urb submitted to disabled ep\n");
1383 case EP_STATE_ERROR
:
1384 xhci_warn(xhci
, "WARN waiting for error on ep to be cleared\n");
1385 /* FIXME event handling code for error needs to clear it */
1386 /* XXX not sure if this should be -ENOENT or not */
1388 case EP_STATE_HALTED
:
1389 xhci_dbg(xhci
, "WARN halted endpoint, queueing URB anyway.\n");
1390 case EP_STATE_STOPPED
:
1391 case EP_STATE_RUNNING
:
1394 xhci_err(xhci
, "ERROR unknown endpoint state for ep\n");
1396 * FIXME issue Configure Endpoint command to try to get the HC
1397 * back into a known state.
1401 if (!room_on_ring(xhci
, ep_ring
, num_trbs
)) {
1402 /* FIXME allocate more room */
1403 xhci_err(xhci
, "ERROR no room on ep ring\n");
1409 static int prepare_transfer(struct xhci_hcd
*xhci
,
1410 struct xhci_virt_device
*xdev
,
1411 unsigned int ep_index
,
1412 unsigned int num_trbs
,
1414 struct xhci_td
**td
,
1418 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1419 ret
= prepare_ring(xhci
, xdev
->eps
[ep_index
].ring
,
1420 ep_ctx
->ep_info
& EP_STATE_MASK
,
1421 num_trbs
, mem_flags
);
1424 *td
= kzalloc(sizeof(struct xhci_td
), mem_flags
);
1427 INIT_LIST_HEAD(&(*td
)->td_list
);
1428 INIT_LIST_HEAD(&(*td
)->cancelled_td_list
);
1430 ret
= usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci
), urb
);
1431 if (unlikely(ret
)) {
1437 urb
->hcpriv
= (void *) (*td
);
1438 /* Add this TD to the tail of the endpoint ring's TD list */
1439 list_add_tail(&(*td
)->td_list
, &xdev
->eps
[ep_index
].ring
->td_list
);
1440 (*td
)->start_seg
= xdev
->eps
[ep_index
].ring
->enq_seg
;
1441 (*td
)->first_trb
= xdev
->eps
[ep_index
].ring
->enqueue
;
1446 static unsigned int count_sg_trbs_needed(struct xhci_hcd
*xhci
, struct urb
*urb
)
1448 int num_sgs
, num_trbs
, running_total
, temp
, i
;
1449 struct scatterlist
*sg
;
1452 num_sgs
= urb
->num_sgs
;
1453 temp
= urb
->transfer_buffer_length
;
1455 xhci_dbg(xhci
, "count sg list trbs: \n");
1457 for_each_sg(urb
->sg
->sg
, sg
, num_sgs
, i
) {
1458 unsigned int previous_total_trbs
= num_trbs
;
1459 unsigned int len
= sg_dma_len(sg
);
1461 /* Scatter gather list entries may cross 64KB boundaries */
1462 running_total
= TRB_MAX_BUFF_SIZE
-
1463 (sg_dma_address(sg
) & ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1464 if (running_total
!= 0)
1467 /* How many more 64KB chunks to transfer, how many more TRBs? */
1468 while (running_total
< sg_dma_len(sg
)) {
1470 running_total
+= TRB_MAX_BUFF_SIZE
;
1472 xhci_dbg(xhci
, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
1473 i
, (unsigned long long)sg_dma_address(sg
),
1474 len
, len
, num_trbs
- previous_total_trbs
);
1476 len
= min_t(int, len
, temp
);
1481 xhci_dbg(xhci
, "\n");
1482 if (!in_interrupt())
1483 dev_dbg(&urb
->dev
->dev
, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n",
1484 urb
->ep
->desc
.bEndpointAddress
,
1485 urb
->transfer_buffer_length
,
1490 static void check_trb_math(struct urb
*urb
, int num_trbs
, int running_total
)
1493 dev_dbg(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated number of "
1494 "TRBs, %d left\n", __func__
,
1495 urb
->ep
->desc
.bEndpointAddress
, num_trbs
);
1496 if (running_total
!= urb
->transfer_buffer_length
)
1497 dev_dbg(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated tx length, "
1498 "queued %#x (%d), asked for %#x (%d)\n",
1500 urb
->ep
->desc
.bEndpointAddress
,
1501 running_total
, running_total
,
1502 urb
->transfer_buffer_length
,
1503 urb
->transfer_buffer_length
);
1506 static void giveback_first_trb(struct xhci_hcd
*xhci
, int slot_id
,
1507 unsigned int ep_index
, int start_cycle
,
1508 struct xhci_generic_trb
*start_trb
, struct xhci_td
*td
)
1511 * Pass all the TRBs to the hardware at once and make sure this write
1515 start_trb
->field
[3] |= start_cycle
;
1516 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
1520 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
1521 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
1522 * (comprised of sg list entries) can take several service intervals to
1525 int xhci_queue_intr_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
1526 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
1528 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
,
1529 xhci
->devs
[slot_id
]->out_ctx
, ep_index
);
1533 xhci_interval
= EP_INTERVAL_TO_UFRAMES(ep_ctx
->ep_info
);
1534 ep_interval
= urb
->interval
;
1535 /* Convert to microframes */
1536 if (urb
->dev
->speed
== USB_SPEED_LOW
||
1537 urb
->dev
->speed
== USB_SPEED_FULL
)
1539 /* FIXME change this to a warning and a suggestion to use the new API
1540 * to set the polling interval (once the API is added).
1542 if (xhci_interval
!= ep_interval
) {
1543 if (!printk_ratelimit())
1544 dev_dbg(&urb
->dev
->dev
, "Driver uses different interval"
1545 " (%d microframe%s) than xHCI "
1546 "(%d microframe%s)\n",
1548 ep_interval
== 1 ? "" : "s",
1550 xhci_interval
== 1 ? "" : "s");
1551 urb
->interval
= xhci_interval
;
1552 /* Convert back to frames for LS/FS devices */
1553 if (urb
->dev
->speed
== USB_SPEED_LOW
||
1554 urb
->dev
->speed
== USB_SPEED_FULL
)
1557 return xhci_queue_bulk_tx(xhci
, GFP_ATOMIC
, urb
, slot_id
, ep_index
);
1560 static int queue_bulk_sg_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
1561 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
1563 struct xhci_ring
*ep_ring
;
1564 unsigned int num_trbs
;
1566 struct scatterlist
*sg
;
1568 int trb_buff_len
, this_sg_len
, running_total
;
1572 struct xhci_generic_trb
*start_trb
;
1575 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
1576 num_trbs
= count_sg_trbs_needed(xhci
, urb
);
1577 num_sgs
= urb
->num_sgs
;
1579 trb_buff_len
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
1580 ep_index
, num_trbs
, urb
, &td
, mem_flags
);
1581 if (trb_buff_len
< 0)
1582 return trb_buff_len
;
1584 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1585 * until we've finished creating all the other TRBs. The ring's cycle
1586 * state may change as we enqueue the other TRBs, so save it too.
1588 start_trb
= &ep_ring
->enqueue
->generic
;
1589 start_cycle
= ep_ring
->cycle_state
;
1593 * How much data is in the first TRB?
1595 * There are three forces at work for TRB buffer pointers and lengths:
1596 * 1. We don't want to walk off the end of this sg-list entry buffer.
1597 * 2. The transfer length that the driver requested may be smaller than
1598 * the amount of memory allocated for this scatter-gather list.
1599 * 3. TRBs buffers can't cross 64KB boundaries.
1602 addr
= (u64
) sg_dma_address(sg
);
1603 this_sg_len
= sg_dma_len(sg
);
1604 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
1605 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1606 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
1607 if (trb_buff_len
> urb
->transfer_buffer_length
)
1608 trb_buff_len
= urb
->transfer_buffer_length
;
1609 xhci_dbg(xhci
, "First length to xfer from 1st sglist entry = %u\n",
1613 /* Queue the first TRB, even if it's zero-length */
1616 u32 length_field
= 0;
1618 /* Don't change the cycle bit of the first TRB until later */
1622 field
|= ep_ring
->cycle_state
;
1624 /* Chain all the TRBs together; clear the chain bit in the last
1625 * TRB to indicate it's the last TRB in the chain.
1630 /* FIXME - add check for ZERO_PACKET flag before this */
1631 td
->last_trb
= ep_ring
->enqueue
;
1634 xhci_dbg(xhci
, " sg entry: dma = %#x, len = %#x (%d), "
1635 "64KB boundary at %#x, end dma = %#x\n",
1636 (unsigned int) addr
, trb_buff_len
, trb_buff_len
,
1637 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
1638 (unsigned int) addr
+ trb_buff_len
);
1639 if (TRB_MAX_BUFF_SIZE
-
1640 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1)) < trb_buff_len
) {
1641 xhci_warn(xhci
, "WARN: sg dma xfer crosses 64KB boundaries!\n");
1642 xhci_dbg(xhci
, "Next boundary at %#x, end dma = %#x\n",
1643 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
1644 (unsigned int) addr
+ trb_buff_len
);
1646 length_field
= TRB_LEN(trb_buff_len
) |
1647 TD_REMAINDER(urb
->transfer_buffer_length
- running_total
) |
1649 queue_trb(xhci
, ep_ring
, false,
1650 lower_32_bits(addr
),
1651 upper_32_bits(addr
),
1653 /* We always want to know if the TRB was short,
1654 * or we won't get an event when it completes.
1655 * (Unless we use event data TRBs, which are a
1656 * waste of space and HC resources.)
1658 field
| TRB_ISP
| TRB_TYPE(TRB_NORMAL
));
1660 running_total
+= trb_buff_len
;
1662 /* Calculate length for next transfer --
1663 * Are we done queueing all the TRBs for this sg entry?
1665 this_sg_len
-= trb_buff_len
;
1666 if (this_sg_len
== 0) {
1671 addr
= (u64
) sg_dma_address(sg
);
1672 this_sg_len
= sg_dma_len(sg
);
1674 addr
+= trb_buff_len
;
1677 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
1678 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1679 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
1680 if (running_total
+ trb_buff_len
> urb
->transfer_buffer_length
)
1682 urb
->transfer_buffer_length
- running_total
;
1683 } while (running_total
< urb
->transfer_buffer_length
);
1685 check_trb_math(urb
, num_trbs
, running_total
);
1686 giveback_first_trb(xhci
, slot_id
, ep_index
, start_cycle
, start_trb
, td
);
1690 /* This is very similar to what ehci-q.c qtd_fill() does */
1691 int xhci_queue_bulk_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
1692 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
1694 struct xhci_ring
*ep_ring
;
1697 struct xhci_generic_trb
*start_trb
;
1700 u32 field
, length_field
;
1702 int running_total
, trb_buff_len
, ret
;
1706 return queue_bulk_sg_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
1708 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
1711 /* How much data is (potentially) left before the 64KB boundary? */
1712 running_total
= TRB_MAX_BUFF_SIZE
-
1713 (urb
->transfer_dma
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1715 /* If there's some data on this 64KB chunk, or we have to send a
1716 * zero-length transfer, we need at least one TRB
1718 if (running_total
!= 0 || urb
->transfer_buffer_length
== 0)
1720 /* How many more 64KB chunks to transfer, how many more TRBs? */
1721 while (running_total
< urb
->transfer_buffer_length
) {
1723 running_total
+= TRB_MAX_BUFF_SIZE
;
1725 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
1727 if (!in_interrupt())
1728 dev_dbg(&urb
->dev
->dev
, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n",
1729 urb
->ep
->desc
.bEndpointAddress
,
1730 urb
->transfer_buffer_length
,
1731 urb
->transfer_buffer_length
,
1732 (unsigned long long)urb
->transfer_dma
,
1735 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
], ep_index
,
1736 num_trbs
, urb
, &td
, mem_flags
);
1741 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1742 * until we've finished creating all the other TRBs. The ring's cycle
1743 * state may change as we enqueue the other TRBs, so save it too.
1745 start_trb
= &ep_ring
->enqueue
->generic
;
1746 start_cycle
= ep_ring
->cycle_state
;
1749 /* How much data is in the first TRB? */
1750 addr
= (u64
) urb
->transfer_dma
;
1751 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
1752 (urb
->transfer_dma
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1753 if (urb
->transfer_buffer_length
< trb_buff_len
)
1754 trb_buff_len
= urb
->transfer_buffer_length
;
1758 /* Queue the first TRB, even if it's zero-length */
1762 /* Don't change the cycle bit of the first TRB until later */
1766 field
|= ep_ring
->cycle_state
;
1768 /* Chain all the TRBs together; clear the chain bit in the last
1769 * TRB to indicate it's the last TRB in the chain.
1774 /* FIXME - add check for ZERO_PACKET flag before this */
1775 td
->last_trb
= ep_ring
->enqueue
;
1778 length_field
= TRB_LEN(trb_buff_len
) |
1779 TD_REMAINDER(urb
->transfer_buffer_length
- running_total
) |
1781 queue_trb(xhci
, ep_ring
, false,
1782 lower_32_bits(addr
),
1783 upper_32_bits(addr
),
1785 /* We always want to know if the TRB was short,
1786 * or we won't get an event when it completes.
1787 * (Unless we use event data TRBs, which are a
1788 * waste of space and HC resources.)
1790 field
| TRB_ISP
| TRB_TYPE(TRB_NORMAL
));
1792 running_total
+= trb_buff_len
;
1794 /* Calculate length for next transfer */
1795 addr
+= trb_buff_len
;
1796 trb_buff_len
= urb
->transfer_buffer_length
- running_total
;
1797 if (trb_buff_len
> TRB_MAX_BUFF_SIZE
)
1798 trb_buff_len
= TRB_MAX_BUFF_SIZE
;
1799 } while (running_total
< urb
->transfer_buffer_length
);
1801 check_trb_math(urb
, num_trbs
, running_total
);
1802 giveback_first_trb(xhci
, slot_id
, ep_index
, start_cycle
, start_trb
, td
);
1806 /* Caller must have locked xhci->lock */
1807 int xhci_queue_ctrl_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
1808 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
1810 struct xhci_ring
*ep_ring
;
1813 struct usb_ctrlrequest
*setup
;
1814 struct xhci_generic_trb
*start_trb
;
1816 u32 field
, length_field
;
1819 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
1822 * Need to copy setup packet into setup TRB, so we can't use the setup
1825 if (!urb
->setup_packet
)
1828 if (!in_interrupt())
1829 xhci_dbg(xhci
, "Queueing ctrl tx for slot id %d, ep %d\n",
1831 /* 1 TRB for setup, 1 for status */
1834 * Don't need to check if we need additional event data and normal TRBs,
1835 * since data in control transfers will never get bigger than 16MB
1836 * XXX: can we get a buffer that crosses 64KB boundaries?
1838 if (urb
->transfer_buffer_length
> 0)
1840 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
], ep_index
, num_trbs
,
1841 urb
, &td
, mem_flags
);
1846 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1847 * until we've finished creating all the other TRBs. The ring's cycle
1848 * state may change as we enqueue the other TRBs, so save it too.
1850 start_trb
= &ep_ring
->enqueue
->generic
;
1851 start_cycle
= ep_ring
->cycle_state
;
1853 /* Queue setup TRB - see section 6.4.1.2.1 */
1854 /* FIXME better way to translate setup_packet into two u32 fields? */
1855 setup
= (struct usb_ctrlrequest
*) urb
->setup_packet
;
1856 queue_trb(xhci
, ep_ring
, false,
1857 /* FIXME endianness is probably going to bite my ass here. */
1858 setup
->bRequestType
| setup
->bRequest
<< 8 | setup
->wValue
<< 16,
1859 setup
->wIndex
| setup
->wLength
<< 16,
1860 TRB_LEN(8) | TRB_INTR_TARGET(0),
1861 /* Immediate data in pointer */
1862 TRB_IDT
| TRB_TYPE(TRB_SETUP
));
1864 /* If there's data, queue data TRBs */
1866 length_field
= TRB_LEN(urb
->transfer_buffer_length
) |
1867 TD_REMAINDER(urb
->transfer_buffer_length
) |
1869 if (urb
->transfer_buffer_length
> 0) {
1870 if (setup
->bRequestType
& USB_DIR_IN
)
1871 field
|= TRB_DIR_IN
;
1872 queue_trb(xhci
, ep_ring
, false,
1873 lower_32_bits(urb
->transfer_dma
),
1874 upper_32_bits(urb
->transfer_dma
),
1876 /* Event on short tx */
1877 field
| TRB_ISP
| TRB_TYPE(TRB_DATA
) | ep_ring
->cycle_state
);
1880 /* Save the DMA address of the last TRB in the TD */
1881 td
->last_trb
= ep_ring
->enqueue
;
1883 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
1884 /* If the device sent data, the status stage is an OUT transfer */
1885 if (urb
->transfer_buffer_length
> 0 && setup
->bRequestType
& USB_DIR_IN
)
1889 queue_trb(xhci
, ep_ring
, false,
1893 /* Event on completion */
1894 field
| TRB_IOC
| TRB_TYPE(TRB_STATUS
) | ep_ring
->cycle_state
);
1896 giveback_first_trb(xhci
, slot_id
, ep_index
, start_cycle
, start_trb
, td
);
1900 /**** Command Ring Operations ****/
1902 /* Generic function for queueing a command TRB on the command ring.
1903 * Check to make sure there's room on the command ring for one command TRB.
1904 * Also check that there's room reserved for commands that must not fail.
1905 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
1906 * then only check for the number of reserved spots.
1907 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
1908 * because the command event handler may want to resubmit a failed command.
1910 static int queue_command(struct xhci_hcd
*xhci
, u32 field1
, u32 field2
,
1911 u32 field3
, u32 field4
, bool command_must_succeed
)
1913 int reserved_trbs
= xhci
->cmd_ring_reserved_trbs
;
1914 if (!command_must_succeed
)
1917 if (!room_on_ring(xhci
, xhci
->cmd_ring
, reserved_trbs
)) {
1918 if (!in_interrupt())
1919 xhci_err(xhci
, "ERR: No room for command on command ring\n");
1920 if (command_must_succeed
)
1921 xhci_err(xhci
, "ERR: Reserved TRB counting for "
1922 "unfailable commands failed.\n");
1925 queue_trb(xhci
, xhci
->cmd_ring
, false, field1
, field2
, field3
,
1926 field4
| xhci
->cmd_ring
->cycle_state
);
1930 /* Queue a no-op command on the command ring */
1931 static int queue_cmd_noop(struct xhci_hcd
*xhci
)
1933 return queue_command(xhci
, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP
), false);
1937 * Place a no-op command on the command ring to test the command and
1940 void *xhci_setup_one_noop(struct xhci_hcd
*xhci
)
1942 if (queue_cmd_noop(xhci
) < 0)
1944 xhci
->noops_submitted
++;
1945 return xhci_ring_cmd_db
;
1948 /* Queue a slot enable or disable request on the command ring */
1949 int xhci_queue_slot_control(struct xhci_hcd
*xhci
, u32 trb_type
, u32 slot_id
)
1951 return queue_command(xhci
, 0, 0, 0,
1952 TRB_TYPE(trb_type
) | SLOT_ID_FOR_TRB(slot_id
), false);
1955 /* Queue an address device command TRB */
1956 int xhci_queue_address_device(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
1959 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
1960 upper_32_bits(in_ctx_ptr
), 0,
1961 TRB_TYPE(TRB_ADDR_DEV
) | SLOT_ID_FOR_TRB(slot_id
),
1965 /* Queue a configure endpoint command TRB */
1966 int xhci_queue_configure_endpoint(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
1967 u32 slot_id
, bool command_must_succeed
)
1969 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
1970 upper_32_bits(in_ctx_ptr
), 0,
1971 TRB_TYPE(TRB_CONFIG_EP
) | SLOT_ID_FOR_TRB(slot_id
),
1972 command_must_succeed
);
1975 /* Queue an evaluate context command TRB */
1976 int xhci_queue_evaluate_context(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
1979 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
1980 upper_32_bits(in_ctx_ptr
), 0,
1981 TRB_TYPE(TRB_EVAL_CONTEXT
) | SLOT_ID_FOR_TRB(slot_id
),
1985 int xhci_queue_stop_endpoint(struct xhci_hcd
*xhci
, int slot_id
,
1986 unsigned int ep_index
)
1988 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
1989 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
1990 u32 type
= TRB_TYPE(TRB_STOP_RING
);
1992 return queue_command(xhci
, 0, 0, 0,
1993 trb_slot_id
| trb_ep_index
| type
, false);
1996 /* Set Transfer Ring Dequeue Pointer command.
1997 * This should not be used for endpoints that have streams enabled.
1999 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
2000 unsigned int ep_index
, struct xhci_segment
*deq_seg
,
2001 union xhci_trb
*deq_ptr
, u32 cycle_state
)
2004 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
2005 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
2006 u32 type
= TRB_TYPE(TRB_SET_DEQ
);
2008 addr
= xhci_trb_virt_to_dma(deq_seg
, deq_ptr
);
2010 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr\n");
2011 xhci_warn(xhci
, "WARN deq seg = %p, deq pt = %p\n",
2015 return queue_command(xhci
, lower_32_bits(addr
) | cycle_state
,
2016 upper_32_bits(addr
), 0,
2017 trb_slot_id
| trb_ep_index
| type
, false);
2020 int xhci_queue_reset_ep(struct xhci_hcd
*xhci
, int slot_id
,
2021 unsigned int ep_index
)
2023 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
2024 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
2025 u32 type
= TRB_TYPE(TRB_RESET_EP
);
2027 return queue_command(xhci
, 0, 0, 0, trb_slot_id
| trb_ep_index
| type
,