1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
12 * Ring initialization rules:
13 * 1. Each segment is initialized to zero, except for link TRBs.
14 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
15 * Consumer Cycle State (CCS), depending on ring function.
16 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
18 * Ring behavior rules:
19 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
20 * least one free TRB in the ring. This is useful if you want to turn that
21 * into a link TRB and expand the ring.
22 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
23 * link TRB, then load the pointer with the address in the link TRB. If the
24 * link TRB had its toggle bit set, you may need to update the ring cycle
25 * state (see cycle bit rules). You may have to do this multiple times
26 * until you reach a non-link TRB.
27 * 3. A ring is full if enqueue++ (for the definition of increment above)
28 * equals the dequeue pointer.
31 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
32 * in a link TRB, it must toggle the ring cycle state.
33 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
34 * in a link TRB, it must toggle the ring cycle state.
37 * 1. Check if ring is full before you enqueue.
38 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
39 * Update enqueue pointer between each write (which may update the ring
41 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
42 * and endpoint rings. If HC is the producer for the event ring,
43 * and it generates an interrupt according to interrupt modulation rules.
46 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
47 * the TRB is owned by the consumer.
48 * 2. Update dequeue pointer (which may update the ring cycle state) and
49 * continue processing TRBs until you reach a TRB which is not owned by you.
50 * 3. Notify the producer. SW is the consumer for the event ring, and it
51 * updates event ring dequeue pointer. HC is the consumer for the command and
52 * endpoint rings; it generates events on the event ring for these.
55 #include <linux/scatterlist.h>
56 #include <linux/slab.h>
57 #include <linux/dma-mapping.h>
59 #include "xhci-trace.h"
62 static int queue_command(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
63 u32 field1
, u32 field2
,
64 u32 field3
, u32 field4
, bool command_must_succeed
);
67 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
70 dma_addr_t
xhci_trb_virt_to_dma(struct xhci_segment
*seg
,
73 unsigned long segment_offset
;
75 if (!seg
|| !trb
|| trb
< seg
->trbs
)
78 segment_offset
= trb
- seg
->trbs
;
79 if (segment_offset
>= TRBS_PER_SEGMENT
)
81 return seg
->dma
+ (segment_offset
* sizeof(*trb
));
84 static bool trb_is_noop(union xhci_trb
*trb
)
86 return TRB_TYPE_NOOP_LE32(trb
->generic
.field
[3]);
89 static bool trb_is_link(union xhci_trb
*trb
)
91 return TRB_TYPE_LINK_LE32(trb
->link
.control
);
94 static bool last_trb_on_seg(struct xhci_segment
*seg
, union xhci_trb
*trb
)
96 return trb
== &seg
->trbs
[TRBS_PER_SEGMENT
- 1];
99 static bool last_trb_on_ring(struct xhci_ring
*ring
,
100 struct xhci_segment
*seg
, union xhci_trb
*trb
)
102 return last_trb_on_seg(seg
, trb
) && (seg
->next
== ring
->first_seg
);
105 static bool link_trb_toggles_cycle(union xhci_trb
*trb
)
107 return le32_to_cpu(trb
->link
.control
) & LINK_TOGGLE
;
110 static bool last_td_in_urb(struct xhci_td
*td
)
112 struct urb_priv
*urb_priv
= td
->urb
->hcpriv
;
114 return urb_priv
->num_tds_done
== urb_priv
->num_tds
;
117 static void inc_td_cnt(struct urb
*urb
)
119 struct urb_priv
*urb_priv
= urb
->hcpriv
;
121 urb_priv
->num_tds_done
++;
124 static void trb_to_noop(union xhci_trb
*trb
, u32 noop_type
)
126 if (trb_is_link(trb
)) {
127 /* unchain chained link TRBs */
128 trb
->link
.control
&= cpu_to_le32(~TRB_CHAIN
);
130 trb
->generic
.field
[0] = 0;
131 trb
->generic
.field
[1] = 0;
132 trb
->generic
.field
[2] = 0;
133 /* Preserve only the cycle bit of this TRB */
134 trb
->generic
.field
[3] &= cpu_to_le32(TRB_CYCLE
);
135 trb
->generic
.field
[3] |= cpu_to_le32(TRB_TYPE(noop_type
));
139 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
140 * TRB is in a new segment. This does not skip over link TRBs, and it does not
141 * effect the ring dequeue or enqueue pointers.
143 static void next_trb(struct xhci_hcd
*xhci
,
144 struct xhci_ring
*ring
,
145 struct xhci_segment
**seg
,
146 union xhci_trb
**trb
)
148 if (trb_is_link(*trb
)) {
150 *trb
= ((*seg
)->trbs
);
157 * See Cycle bit rules. SW is the consumer for the event ring only.
159 void inc_deq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
)
161 unsigned int link_trb_count
= 0;
163 /* event ring doesn't have link trbs, check for last trb */
164 if (ring
->type
== TYPE_EVENT
) {
165 if (!last_trb_on_seg(ring
->deq_seg
, ring
->dequeue
)) {
169 if (last_trb_on_ring(ring
, ring
->deq_seg
, ring
->dequeue
))
170 ring
->cycle_state
^= 1;
171 ring
->deq_seg
= ring
->deq_seg
->next
;
172 ring
->dequeue
= ring
->deq_seg
->trbs
;
176 /* All other rings have link trbs */
177 if (!trb_is_link(ring
->dequeue
)) {
178 if (last_trb_on_seg(ring
->deq_seg
, ring
->dequeue
)) {
179 xhci_warn(xhci
, "Missing link TRB at end of segment\n");
182 ring
->num_trbs_free
++;
186 while (trb_is_link(ring
->dequeue
)) {
187 ring
->deq_seg
= ring
->deq_seg
->next
;
188 ring
->dequeue
= ring
->deq_seg
->trbs
;
190 if (link_trb_count
++ > ring
->num_segs
) {
191 xhci_warn(xhci
, "Ring is an endless link TRB loop\n");
196 trace_xhci_inc_deq(ring
);
202 * See Cycle bit rules. SW is the consumer for the event ring only.
204 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
205 * chain bit is set), then set the chain bit in all the following link TRBs.
206 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
207 * have their chain bit cleared (so that each Link TRB is a separate TD).
209 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
210 * set, but other sections talk about dealing with the chain bit set. This was
211 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
212 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
214 * @more_trbs_coming: Will you enqueue more TRBs before calling
215 * prepare_transfer()?
217 static void inc_enq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
218 bool more_trbs_coming
)
221 union xhci_trb
*next
;
222 unsigned int link_trb_count
= 0;
224 chain
= le32_to_cpu(ring
->enqueue
->generic
.field
[3]) & TRB_CHAIN
;
225 /* If this is not event ring, there is one less usable TRB */
226 if (!trb_is_link(ring
->enqueue
))
227 ring
->num_trbs_free
--;
229 if (last_trb_on_seg(ring
->enq_seg
, ring
->enqueue
)) {
230 xhci_err(xhci
, "Tried to move enqueue past ring segment\n");
234 next
= ++(ring
->enqueue
);
236 /* Update the dequeue pointer further if that was a link TRB */
237 while (trb_is_link(next
)) {
240 * If the caller doesn't plan on enqueueing more TDs before
241 * ringing the doorbell, then we don't want to give the link TRB
242 * to the hardware just yet. We'll give the link TRB back in
243 * prepare_ring() just before we enqueue the TD at the top of
246 if (!chain
&& !more_trbs_coming
)
249 /* If we're not dealing with 0.95 hardware or isoc rings on
250 * AMD 0.96 host, carry over the chain bit of the previous TRB
251 * (which may mean the chain bit is cleared).
253 if (!(ring
->type
== TYPE_ISOC
&&
254 (xhci
->quirks
& XHCI_AMD_0x96_HOST
)) &&
255 !xhci_link_trb_quirk(xhci
)) {
256 next
->link
.control
&= cpu_to_le32(~TRB_CHAIN
);
257 next
->link
.control
|= cpu_to_le32(chain
);
259 /* Give this link TRB to the hardware */
261 next
->link
.control
^= cpu_to_le32(TRB_CYCLE
);
263 /* Toggle the cycle bit after the last ring segment. */
264 if (link_trb_toggles_cycle(next
))
265 ring
->cycle_state
^= 1;
267 ring
->enq_seg
= ring
->enq_seg
->next
;
268 ring
->enqueue
= ring
->enq_seg
->trbs
;
269 next
= ring
->enqueue
;
271 if (link_trb_count
++ > ring
->num_segs
) {
272 xhci_warn(xhci
, "%s: Ring link TRB loop\n", __func__
);
277 trace_xhci_inc_enq(ring
);
281 * Check to see if there's room to enqueue num_trbs on the ring and make sure
282 * enqueue pointer will not advance into dequeue segment. See rules above.
284 static inline int room_on_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
285 unsigned int num_trbs
)
287 int num_trbs_in_deq_seg
;
289 if (ring
->num_trbs_free
< num_trbs
)
292 if (ring
->type
!= TYPE_COMMAND
&& ring
->type
!= TYPE_EVENT
) {
293 num_trbs_in_deq_seg
= ring
->dequeue
- ring
->deq_seg
->trbs
;
294 if (ring
->num_trbs_free
< num_trbs
+ num_trbs_in_deq_seg
)
301 /* Ring the host controller doorbell after placing a command on the ring */
302 void xhci_ring_cmd_db(struct xhci_hcd
*xhci
)
304 if (!(xhci
->cmd_ring_state
& CMD_RING_STATE_RUNNING
))
307 xhci_dbg(xhci
, "// Ding dong!\n");
309 trace_xhci_ring_host_doorbell(0, DB_VALUE_HOST
);
311 writel(DB_VALUE_HOST
, &xhci
->dba
->doorbell
[0]);
312 /* Flush PCI posted writes */
313 readl(&xhci
->dba
->doorbell
[0]);
316 static bool xhci_mod_cmd_timer(struct xhci_hcd
*xhci
, unsigned long delay
)
318 return mod_delayed_work(system_wq
, &xhci
->cmd_timer
, delay
);
321 static struct xhci_command
*xhci_next_queued_cmd(struct xhci_hcd
*xhci
)
323 return list_first_entry_or_null(&xhci
->cmd_list
, struct xhci_command
,
328 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
329 * If there are other commands waiting then restart the ring and kick the timer.
330 * This must be called with command ring stopped and xhci->lock held.
332 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd
*xhci
,
333 struct xhci_command
*cur_cmd
)
335 struct xhci_command
*i_cmd
;
337 /* Turn all aborted commands in list to no-ops, then restart */
338 list_for_each_entry(i_cmd
, &xhci
->cmd_list
, cmd_list
) {
340 if (i_cmd
->status
!= COMP_COMMAND_ABORTED
)
343 i_cmd
->status
= COMP_COMMAND_RING_STOPPED
;
345 xhci_dbg(xhci
, "Turn aborted command %p to no-op\n",
348 trb_to_noop(i_cmd
->command_trb
, TRB_CMD_NOOP
);
351 * caller waiting for completion is called when command
352 * completion event is received for these no-op commands
356 xhci
->cmd_ring_state
= CMD_RING_STATE_RUNNING
;
358 /* ring command ring doorbell to restart the command ring */
359 if ((xhci
->cmd_ring
->dequeue
!= xhci
->cmd_ring
->enqueue
) &&
360 !(xhci
->xhc_state
& XHCI_STATE_DYING
)) {
361 xhci
->current_cmd
= cur_cmd
;
362 xhci_mod_cmd_timer(xhci
, XHCI_CMD_DEFAULT_TIMEOUT
);
363 xhci_ring_cmd_db(xhci
);
367 /* Must be called with xhci->lock held, releases and aquires lock back */
368 static int xhci_abort_cmd_ring(struct xhci_hcd
*xhci
, unsigned long flags
)
373 xhci_dbg(xhci
, "Abort command ring\n");
375 reinit_completion(&xhci
->cmd_ring_stop_completion
);
377 temp_64
= xhci_read_64(xhci
, &xhci
->op_regs
->cmd_ring
);
378 xhci_write_64(xhci
, temp_64
| CMD_RING_ABORT
,
379 &xhci
->op_regs
->cmd_ring
);
381 /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the
382 * completion of the Command Abort operation. If CRR is not negated in 5
383 * seconds then driver handles it as if host died (-ENODEV).
384 * In the future we should distinguish between -ENODEV and -ETIMEDOUT
385 * and try to recover a -ETIMEDOUT with a host controller reset.
387 ret
= xhci_handshake(&xhci
->op_regs
->cmd_ring
,
388 CMD_RING_RUNNING
, 0, 5 * 1000 * 1000);
390 xhci_err(xhci
, "Abort failed to stop command ring: %d\n", ret
);
396 * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
397 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
398 * but the completion event in never sent. Wait 2 secs (arbitrary
399 * number) to handle those cases after negation of CMD_RING_RUNNING.
401 spin_unlock_irqrestore(&xhci
->lock
, flags
);
402 ret
= wait_for_completion_timeout(&xhci
->cmd_ring_stop_completion
,
403 msecs_to_jiffies(2000));
404 spin_lock_irqsave(&xhci
->lock
, flags
);
406 xhci_dbg(xhci
, "No stop event for abort, ring start fail?\n");
407 xhci_cleanup_command_queue(xhci
);
409 xhci_handle_stopped_cmd_ring(xhci
, xhci_next_queued_cmd(xhci
));
414 void xhci_ring_ep_doorbell(struct xhci_hcd
*xhci
,
415 unsigned int slot_id
,
416 unsigned int ep_index
,
417 unsigned int stream_id
)
419 __le32 __iomem
*db_addr
= &xhci
->dba
->doorbell
[slot_id
];
420 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
421 unsigned int ep_state
= ep
->ep_state
;
423 /* Don't ring the doorbell for this endpoint if there are pending
424 * cancellations because we don't want to interrupt processing.
425 * We don't want to restart any stream rings if there's a set dequeue
426 * pointer command pending because the device can choose to start any
427 * stream once the endpoint is on the HW schedule.
429 if ((ep_state
& EP_STOP_CMD_PENDING
) || (ep_state
& SET_DEQ_PENDING
) ||
430 (ep_state
& EP_HALTED
) || (ep_state
& EP_CLEARING_TT
))
433 trace_xhci_ring_ep_doorbell(slot_id
, DB_VALUE(ep_index
, stream_id
));
435 writel(DB_VALUE(ep_index
, stream_id
), db_addr
);
436 /* flush the write */
440 /* Ring the doorbell for any rings with pending URBs */
441 static void ring_doorbell_for_active_rings(struct xhci_hcd
*xhci
,
442 unsigned int slot_id
,
443 unsigned int ep_index
)
445 unsigned int stream_id
;
446 struct xhci_virt_ep
*ep
;
448 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
450 /* A ring has pending URBs if its TD list is not empty */
451 if (!(ep
->ep_state
& EP_HAS_STREAMS
)) {
452 if (ep
->ring
&& !(list_empty(&ep
->ring
->td_list
)))
453 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
, 0);
457 for (stream_id
= 1; stream_id
< ep
->stream_info
->num_streams
;
459 struct xhci_stream_info
*stream_info
= ep
->stream_info
;
460 if (!list_empty(&stream_info
->stream_rings
[stream_id
]->td_list
))
461 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
,
466 void xhci_ring_doorbell_for_active_rings(struct xhci_hcd
*xhci
,
467 unsigned int slot_id
,
468 unsigned int ep_index
)
470 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
473 static struct xhci_virt_ep
*xhci_get_virt_ep(struct xhci_hcd
*xhci
,
474 unsigned int slot_id
,
475 unsigned int ep_index
)
477 if (slot_id
== 0 || slot_id
>= MAX_HC_SLOTS
) {
478 xhci_warn(xhci
, "Invalid slot_id %u\n", slot_id
);
481 if (ep_index
>= EP_CTX_PER_DEV
) {
482 xhci_warn(xhci
, "Invalid endpoint index %u\n", ep_index
);
485 if (!xhci
->devs
[slot_id
]) {
486 xhci_warn(xhci
, "No xhci virt device for slot_id %u\n", slot_id
);
490 return &xhci
->devs
[slot_id
]->eps
[ep_index
];
493 static struct xhci_ring
*xhci_virt_ep_to_ring(struct xhci_hcd
*xhci
,
494 struct xhci_virt_ep
*ep
,
495 unsigned int stream_id
)
497 /* common case, no streams */
498 if (!(ep
->ep_state
& EP_HAS_STREAMS
))
501 if (!ep
->stream_info
)
504 if (stream_id
== 0 || stream_id
>= ep
->stream_info
->num_streams
) {
505 xhci_warn(xhci
, "Invalid stream_id %u request for slot_id %u ep_index %u\n",
506 stream_id
, ep
->vdev
->slot_id
, ep
->ep_index
);
510 return ep
->stream_info
->stream_rings
[stream_id
];
513 /* Get the right ring for the given slot_id, ep_index and stream_id.
514 * If the endpoint supports streams, boundary check the URB's stream ID.
515 * If the endpoint doesn't support streams, return the singular endpoint ring.
517 struct xhci_ring
*xhci_triad_to_transfer_ring(struct xhci_hcd
*xhci
,
518 unsigned int slot_id
, unsigned int ep_index
,
519 unsigned int stream_id
)
521 struct xhci_virt_ep
*ep
;
523 ep
= xhci_get_virt_ep(xhci
, slot_id
, ep_index
);
527 return xhci_virt_ep_to_ring(xhci
, ep
, stream_id
);
532 * Get the hw dequeue pointer xHC stopped on, either directly from the
533 * endpoint context, or if streams are in use from the stream context.
534 * The returned hw_dequeue contains the lowest four bits with cycle state
535 * and possbile stream context type.
537 static u64
xhci_get_hw_deq(struct xhci_hcd
*xhci
, struct xhci_virt_device
*vdev
,
538 unsigned int ep_index
, unsigned int stream_id
)
540 struct xhci_ep_ctx
*ep_ctx
;
541 struct xhci_stream_ctx
*st_ctx
;
542 struct xhci_virt_ep
*ep
;
544 ep
= &vdev
->eps
[ep_index
];
546 if (ep
->ep_state
& EP_HAS_STREAMS
) {
547 st_ctx
= &ep
->stream_info
->stream_ctx_array
[stream_id
];
548 return le64_to_cpu(st_ctx
->stream_ring
);
550 ep_ctx
= xhci_get_ep_ctx(xhci
, vdev
->out_ctx
, ep_index
);
551 return le64_to_cpu(ep_ctx
->deq
);
554 static int xhci_move_dequeue_past_td(struct xhci_hcd
*xhci
,
555 unsigned int slot_id
, unsigned int ep_index
,
556 unsigned int stream_id
, struct xhci_td
*td
)
558 struct xhci_virt_device
*dev
= xhci
->devs
[slot_id
];
559 struct xhci_virt_ep
*ep
= &dev
->eps
[ep_index
];
560 struct xhci_ring
*ep_ring
;
561 struct xhci_command
*cmd
;
562 struct xhci_segment
*new_seg
;
563 union xhci_trb
*new_deq
;
567 bool cycle_found
= false;
568 bool td_last_trb_found
= false;
572 ep_ring
= xhci_triad_to_transfer_ring(xhci
, slot_id
,
573 ep_index
, stream_id
);
575 xhci_warn(xhci
, "WARN can't find new dequeue, invalid stream ID %u\n",
580 * A cancelled TD can complete with a stall if HW cached the trb.
581 * In this case driver can't find td, but if the ring is empty we
582 * can move the dequeue pointer to the current enqueue position.
583 * We shouldn't hit this anymore as cached cancelled TRBs are given back
584 * after clearing the cache, but be on the safe side and keep it anyway
587 if (list_empty(&ep_ring
->td_list
)) {
588 new_seg
= ep_ring
->enq_seg
;
589 new_deq
= ep_ring
->enqueue
;
590 new_cycle
= ep_ring
->cycle_state
;
591 xhci_dbg(xhci
, "ep ring empty, Set new dequeue = enqueue");
594 xhci_warn(xhci
, "Can't find new dequeue state, missing td\n");
599 hw_dequeue
= xhci_get_hw_deq(xhci
, dev
, ep_index
, stream_id
);
600 new_seg
= ep_ring
->deq_seg
;
601 new_deq
= ep_ring
->dequeue
;
602 new_cycle
= hw_dequeue
& 0x1;
605 * We want to find the pointer, segment and cycle state of the new trb
606 * (the one after current TD's last_trb). We know the cycle state at
607 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
611 if (!cycle_found
&& xhci_trb_virt_to_dma(new_seg
, new_deq
)
612 == (dma_addr_t
)(hw_dequeue
& ~0xf)) {
614 if (td_last_trb_found
)
617 if (new_deq
== td
->last_trb
)
618 td_last_trb_found
= true;
620 if (cycle_found
&& trb_is_link(new_deq
) &&
621 link_trb_toggles_cycle(new_deq
))
624 next_trb(xhci
, ep_ring
, &new_seg
, &new_deq
);
626 /* Search wrapped around, bail out */
627 if (new_deq
== ep
->ring
->dequeue
) {
628 xhci_err(xhci
, "Error: Failed finding new dequeue state\n");
632 } while (!cycle_found
|| !td_last_trb_found
);
636 /* Don't update the ring cycle state for the producer (us). */
637 addr
= xhci_trb_virt_to_dma(new_seg
, new_deq
);
639 xhci_warn(xhci
, "Can't find dma of new dequeue ptr\n");
640 xhci_warn(xhci
, "deq seg = %p, deq ptr = %p\n", new_seg
, new_deq
);
644 if ((ep
->ep_state
& SET_DEQ_PENDING
)) {
645 xhci_warn(xhci
, "Set TR Deq already pending, don't submit for 0x%pad\n",
650 /* This function gets called from contexts where it cannot sleep */
651 cmd
= xhci_alloc_command(xhci
, false, GFP_ATOMIC
);
653 xhci_warn(xhci
, "Can't alloc Set TR Deq cmd 0x%pad\n", &addr
);
658 trb_sct
= SCT_FOR_TRB(SCT_PRI_TR
);
659 ret
= queue_command(xhci
, cmd
,
660 lower_32_bits(addr
) | trb_sct
| new_cycle
,
662 STREAM_ID_FOR_TRB(stream_id
), SLOT_ID_FOR_TRB(slot_id
) |
663 EP_ID_FOR_TRB(ep_index
) | TRB_TYPE(TRB_SET_DEQ
), false);
665 xhci_free_command(xhci
, cmd
);
668 ep
->queued_deq_seg
= new_seg
;
669 ep
->queued_deq_ptr
= new_deq
;
671 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
672 "Set TR Deq ptr 0x%llx, cycle %u\n", addr
, new_cycle
);
674 /* Stop the TD queueing code from ringing the doorbell until
675 * this command completes. The HC won't set the dequeue pointer
676 * if the ring is running, and ringing the doorbell starts the
679 ep
->ep_state
|= SET_DEQ_PENDING
;
680 xhci_ring_cmd_db(xhci
);
684 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
685 * (The last TRB actually points to the ring enqueue pointer, which is not part
686 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
688 static void td_to_noop(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
689 struct xhci_td
*td
, bool flip_cycle
)
691 struct xhci_segment
*seg
= td
->start_seg
;
692 union xhci_trb
*trb
= td
->first_trb
;
695 trb_to_noop(trb
, TRB_TR_NOOP
);
697 /* flip cycle if asked to */
698 if (flip_cycle
&& trb
!= td
->first_trb
&& trb
!= td
->last_trb
)
699 trb
->generic
.field
[3] ^= cpu_to_le32(TRB_CYCLE
);
701 if (trb
== td
->last_trb
)
704 next_trb(xhci
, ep_ring
, &seg
, &trb
);
708 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd
*xhci
,
709 struct xhci_virt_ep
*ep
)
711 ep
->ep_state
&= ~EP_STOP_CMD_PENDING
;
712 /* Can't del_timer_sync in interrupt */
713 del_timer(&ep
->stop_cmd_timer
);
717 * Must be called with xhci->lock held in interrupt context,
718 * releases and re-acquires xhci->lock
720 static void xhci_giveback_urb_in_irq(struct xhci_hcd
*xhci
,
721 struct xhci_td
*cur_td
, int status
)
723 struct urb
*urb
= cur_td
->urb
;
724 struct urb_priv
*urb_priv
= urb
->hcpriv
;
725 struct usb_hcd
*hcd
= bus_to_hcd(urb
->dev
->bus
);
727 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
728 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
--;
729 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
== 0) {
730 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
731 usb_amd_quirk_pll_enable();
734 xhci_urb_free_priv(urb_priv
);
735 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
736 trace_xhci_urb_giveback(urb
);
737 usb_hcd_giveback_urb(hcd
, urb
, status
);
740 static void xhci_unmap_td_bounce_buffer(struct xhci_hcd
*xhci
,
741 struct xhci_ring
*ring
, struct xhci_td
*td
)
743 struct device
*dev
= xhci_to_hcd(xhci
)->self
.controller
;
744 struct xhci_segment
*seg
= td
->bounce_seg
;
745 struct urb
*urb
= td
->urb
;
748 if (!ring
|| !seg
|| !urb
)
751 if (usb_urb_dir_out(urb
)) {
752 dma_unmap_single(dev
, seg
->bounce_dma
, ring
->bounce_buf_len
,
757 dma_unmap_single(dev
, seg
->bounce_dma
, ring
->bounce_buf_len
,
759 /* for in tranfers we need to copy the data from bounce to sg */
761 len
= sg_pcopy_from_buffer(urb
->sg
, urb
->num_sgs
, seg
->bounce_buf
,
762 seg
->bounce_len
, seg
->bounce_offs
);
763 if (len
!= seg
->bounce_len
)
764 xhci_warn(xhci
, "WARN Wrong bounce buffer read length: %zu != %d\n",
765 len
, seg
->bounce_len
);
767 memcpy(urb
->transfer_buffer
+ seg
->bounce_offs
, seg
->bounce_buf
,
771 seg
->bounce_offs
= 0;
774 static int xhci_td_cleanup(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
775 struct xhci_ring
*ep_ring
, int status
)
777 struct urb
*urb
= NULL
;
779 /* Clean up the endpoint's TD list */
782 /* if a bounce buffer was used to align this td then unmap it */
783 xhci_unmap_td_bounce_buffer(xhci
, ep_ring
, td
);
785 /* Do one last check of the actual transfer length.
786 * If the host controller said we transferred more data than the buffer
787 * length, urb->actual_length will be a very big number (since it's
788 * unsigned). Play it safe and say we didn't transfer anything.
790 if (urb
->actual_length
> urb
->transfer_buffer_length
) {
791 xhci_warn(xhci
, "URB req %u and actual %u transfer length mismatch\n",
792 urb
->transfer_buffer_length
, urb
->actual_length
);
793 urb
->actual_length
= 0;
796 /* TD might be removed from td_list if we are giving back a cancelled URB */
797 if (!list_empty(&td
->td_list
))
798 list_del_init(&td
->td_list
);
799 /* Giving back a cancelled URB, or if a slated TD completed anyway */
800 if (!list_empty(&td
->cancelled_td_list
))
801 list_del_init(&td
->cancelled_td_list
);
804 /* Giveback the urb when all the tds are completed */
805 if (last_td_in_urb(td
)) {
806 if ((urb
->actual_length
!= urb
->transfer_buffer_length
&&
807 (urb
->transfer_flags
& URB_SHORT_NOT_OK
)) ||
808 (status
!= 0 && !usb_endpoint_xfer_isoc(&urb
->ep
->desc
)))
809 xhci_dbg(xhci
, "Giveback URB %p, len = %d, expected = %d, status = %d\n",
810 urb
, urb
->actual_length
,
811 urb
->transfer_buffer_length
, status
);
813 /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */
814 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
)
816 xhci_giveback_urb_in_irq(xhci
, td
, status
);
823 /* Complete the cancelled URBs we unlinked from td_list. */
824 static void xhci_giveback_invalidated_tds(struct xhci_virt_ep
*ep
)
826 struct xhci_ring
*ring
;
827 struct xhci_td
*td
, *tmp_td
;
829 list_for_each_entry_safe(td
, tmp_td
, &ep
->cancelled_td_list
,
833 * Doesn't matter what we pass for status, since the core will
834 * just overwrite it (because the URB has been unlinked).
836 ring
= xhci_urb_to_transfer_ring(ep
->xhci
, td
->urb
);
838 if (td
->cancel_status
== TD_CLEARED
)
839 xhci_td_cleanup(ep
->xhci
, td
, ring
, 0);
841 if (ep
->xhci
->xhc_state
& XHCI_STATE_DYING
)
846 static int xhci_reset_halted_ep(struct xhci_hcd
*xhci
, unsigned int slot_id
,
847 unsigned int ep_index
, enum xhci_ep_reset_type reset_type
)
849 struct xhci_command
*command
;
852 command
= xhci_alloc_command(xhci
, false, GFP_ATOMIC
);
858 ret
= xhci_queue_reset_ep(xhci
, command
, slot_id
, ep_index
, reset_type
);
861 xhci_err(xhci
, "ERROR queuing reset endpoint for slot %d ep_index %d, %d\n",
862 slot_id
, ep_index
, ret
);
866 static void xhci_handle_halted_endpoint(struct xhci_hcd
*xhci
,
867 struct xhci_virt_ep
*ep
, unsigned int stream_id
,
869 enum xhci_ep_reset_type reset_type
)
871 unsigned int slot_id
= ep
->vdev
->slot_id
;
875 * Avoid resetting endpoint if link is inactive. Can cause host hang.
876 * Device will be reset soon to recover the link so don't do anything
878 if (ep
->vdev
->flags
& VDEV_PORT_ERROR
)
881 /* add td to cancelled list and let reset ep handler take care of it */
882 if (reset_type
== EP_HARD_RESET
) {
883 ep
->ep_state
|= EP_HARD_CLEAR_TOGGLE
;
884 if (td
&& list_empty(&td
->cancelled_td_list
)) {
885 list_add_tail(&td
->cancelled_td_list
, &ep
->cancelled_td_list
);
886 td
->cancel_status
= TD_HALTED
;
890 if (ep
->ep_state
& EP_HALTED
) {
891 xhci_dbg(xhci
, "Reset ep command already pending\n");
895 err
= xhci_reset_halted_ep(xhci
, slot_id
, ep
->ep_index
, reset_type
);
899 ep
->ep_state
|= EP_HALTED
;
901 xhci_ring_cmd_db(xhci
);
905 * Fix up the ep ring first, so HW stops executing cancelled TDs.
906 * We have the xHCI lock, so nothing can modify this list until we drop it.
907 * We're also in the event handler, so we can't get re-interrupted if another
908 * Stop Endpoint command completes.
910 * only call this when ring is not in a running state
913 static int xhci_invalidate_cancelled_tds(struct xhci_virt_ep
*ep
)
915 struct xhci_hcd
*xhci
;
916 struct xhci_td
*td
= NULL
;
917 struct xhci_td
*tmp_td
= NULL
;
918 struct xhci_td
*cached_td
= NULL
;
919 struct xhci_ring
*ring
;
921 unsigned int slot_id
= ep
->vdev
->slot_id
;
926 list_for_each_entry_safe(td
, tmp_td
, &ep
->cancelled_td_list
, cancelled_td_list
) {
927 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
928 "Removing canceled TD starting at 0x%llx (dma).",
929 (unsigned long long)xhci_trb_virt_to_dma(
930 td
->start_seg
, td
->first_trb
));
931 list_del_init(&td
->td_list
);
932 ring
= xhci_urb_to_transfer_ring(xhci
, td
->urb
);
934 xhci_warn(xhci
, "WARN Cancelled URB %p has invalid stream ID %u.\n",
935 td
->urb
, td
->urb
->stream_id
);
939 * If ring stopped on the TD we need to cancel, then we have to
940 * move the xHC endpoint ring dequeue pointer past this TD.
942 hw_deq
= xhci_get_hw_deq(xhci
, ep
->vdev
, ep
->ep_index
,
946 if (trb_in_td(xhci
, td
->start_seg
, td
->first_trb
,
947 td
->last_trb
, hw_deq
, false)) {
948 switch (td
->cancel_status
) {
949 case TD_CLEARED
: /* TD is already no-op */
950 case TD_CLEARING_CACHE
: /* set TR deq command already queued */
952 case TD_DIRTY
: /* TD is cached, clear it */
954 /* FIXME stream case, several stopped rings */
959 td_to_noop(xhci
, ring
, td
, false);
960 td
->cancel_status
= TD_CLEARED
;
964 cached_td
->cancel_status
= TD_CLEARING_CACHE
;
966 err
= xhci_move_dequeue_past_td(xhci
, slot_id
, ep
->ep_index
,
967 cached_td
->urb
->stream_id
,
969 /* Failed to move past cached td, try just setting it noop */
971 td_to_noop(xhci
, ring
, cached_td
, false);
972 cached_td
->cancel_status
= TD_CLEARED
;
980 * Returns the TD the endpoint ring halted on.
981 * Only call for non-running rings without streams.
983 static struct xhci_td
*find_halted_td(struct xhci_virt_ep
*ep
)
988 if (!list_empty(&ep
->ring
->td_list
)) { /* Not streams compatible */
989 hw_deq
= xhci_get_hw_deq(ep
->xhci
, ep
->vdev
, ep
->ep_index
, 0);
991 td
= list_first_entry(&ep
->ring
->td_list
, struct xhci_td
, td_list
);
992 if (trb_in_td(ep
->xhci
, td
->start_seg
, td
->first_trb
,
993 td
->last_trb
, hw_deq
, false))
1000 * When we get a command completion for a Stop Endpoint Command, we need to
1001 * unlink any cancelled TDs from the ring. There are two ways to do that:
1003 * 1. If the HW was in the middle of processing the TD that needs to be
1004 * cancelled, then we must move the ring's dequeue pointer past the last TRB
1005 * in the TD with a Set Dequeue Pointer Command.
1006 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
1007 * bit cleared) so that the HW will skip over them.
1009 static void xhci_handle_cmd_stop_ep(struct xhci_hcd
*xhci
, int slot_id
,
1010 union xhci_trb
*trb
, u32 comp_code
)
1012 unsigned int ep_index
;
1013 struct xhci_virt_ep
*ep
;
1014 struct xhci_ep_ctx
*ep_ctx
;
1015 struct xhci_td
*td
= NULL
;
1016 enum xhci_ep_reset_type reset_type
;
1017 struct xhci_command
*command
;
1019 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb
->generic
.field
[3])))) {
1020 if (!xhci
->devs
[slot_id
])
1021 xhci_warn(xhci
, "Stop endpoint command completion for disabled slot %u\n",
1026 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
1027 ep
= xhci_get_virt_ep(xhci
, slot_id
, ep_index
);
1031 ep_ctx
= xhci_get_ep_ctx(xhci
, ep
->vdev
->out_ctx
, ep_index
);
1033 trace_xhci_handle_cmd_stop_ep(ep_ctx
);
1035 if (comp_code
== COMP_CONTEXT_STATE_ERROR
) {
1037 * If stop endpoint command raced with a halting endpoint we need to
1038 * reset the host side endpoint first.
1039 * If the TD we halted on isn't cancelled the TD should be given back
1040 * with a proper error code, and the ring dequeue moved past the TD.
1041 * If streams case we can't find hw_deq, or the TD we halted on so do a
1044 * Proper error code is unknown here, it would be -EPIPE if device side
1045 * of enadpoit halted (aka STALL), and -EPROTO if not (transaction error)
1046 * We use -EPROTO, if device is stalled it should return a stall error on
1047 * next transfer, which then will return -EPIPE, and device side stall is
1048 * noted and cleared by class driver.
1050 switch (GET_EP_CTX_STATE(ep_ctx
)) {
1051 case EP_STATE_HALTED
:
1052 xhci_dbg(xhci
, "Stop ep completion raced with stall, reset ep\n");
1053 if (ep
->ep_state
& EP_HAS_STREAMS
) {
1054 reset_type
= EP_SOFT_RESET
;
1056 reset_type
= EP_HARD_RESET
;
1057 td
= find_halted_td(ep
);
1059 td
->status
= -EPROTO
;
1061 /* reset ep, reset handler cleans up cancelled tds */
1062 xhci_handle_halted_endpoint(xhci
, ep
, 0, td
, reset_type
);
1063 xhci_stop_watchdog_timer_in_irq(xhci
, ep
);
1065 case EP_STATE_RUNNING
:
1066 /* Race, HW handled stop ep cmd before ep was running */
1067 command
= xhci_alloc_command(xhci
, false, GFP_ATOMIC
);
1069 xhci_stop_watchdog_timer_in_irq(xhci
, ep
);
1071 mod_timer(&ep
->stop_cmd_timer
,
1072 jiffies
+ XHCI_STOP_EP_CMD_TIMEOUT
* HZ
);
1073 xhci_queue_stop_endpoint(xhci
, command
, slot_id
, ep_index
, 0);
1074 xhci_ring_cmd_db(xhci
);
1081 /* will queue a set TR deq if stopped on a cancelled, uncleared TD */
1082 xhci_invalidate_cancelled_tds(ep
);
1083 xhci_stop_watchdog_timer_in_irq(xhci
, ep
);
1085 /* Otherwise ring the doorbell(s) to restart queued transfers */
1086 xhci_giveback_invalidated_tds(ep
);
1087 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1090 static void xhci_kill_ring_urbs(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
)
1092 struct xhci_td
*cur_td
;
1093 struct xhci_td
*tmp
;
1095 list_for_each_entry_safe(cur_td
, tmp
, &ring
->td_list
, td_list
) {
1096 list_del_init(&cur_td
->td_list
);
1098 if (!list_empty(&cur_td
->cancelled_td_list
))
1099 list_del_init(&cur_td
->cancelled_td_list
);
1101 xhci_unmap_td_bounce_buffer(xhci
, ring
, cur_td
);
1103 inc_td_cnt(cur_td
->urb
);
1104 if (last_td_in_urb(cur_td
))
1105 xhci_giveback_urb_in_irq(xhci
, cur_td
, -ESHUTDOWN
);
1109 static void xhci_kill_endpoint_urbs(struct xhci_hcd
*xhci
,
1110 int slot_id
, int ep_index
)
1112 struct xhci_td
*cur_td
;
1113 struct xhci_td
*tmp
;
1114 struct xhci_virt_ep
*ep
;
1115 struct xhci_ring
*ring
;
1117 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
1118 if ((ep
->ep_state
& EP_HAS_STREAMS
) ||
1119 (ep
->ep_state
& EP_GETTING_NO_STREAMS
)) {
1122 for (stream_id
= 1; stream_id
< ep
->stream_info
->num_streams
;
1124 ring
= ep
->stream_info
->stream_rings
[stream_id
];
1128 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
1129 "Killing URBs for slot ID %u, ep index %u, stream %u",
1130 slot_id
, ep_index
, stream_id
);
1131 xhci_kill_ring_urbs(xhci
, ring
);
1137 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
1138 "Killing URBs for slot ID %u, ep index %u",
1140 xhci_kill_ring_urbs(xhci
, ring
);
1143 list_for_each_entry_safe(cur_td
, tmp
, &ep
->cancelled_td_list
,
1144 cancelled_td_list
) {
1145 list_del_init(&cur_td
->cancelled_td_list
);
1146 inc_td_cnt(cur_td
->urb
);
1148 if (last_td_in_urb(cur_td
))
1149 xhci_giveback_urb_in_irq(xhci
, cur_td
, -ESHUTDOWN
);
1154 * host controller died, register read returns 0xffffffff
1155 * Complete pending commands, mark them ABORTED.
1156 * URBs need to be given back as usb core might be waiting with device locks
1157 * held for the URBs to finish during device disconnect, blocking host remove.
1159 * Call with xhci->lock held.
1160 * lock is relased and re-acquired while giving back urb.
1162 void xhci_hc_died(struct xhci_hcd
*xhci
)
1166 if (xhci
->xhc_state
& XHCI_STATE_DYING
)
1169 xhci_err(xhci
, "xHCI host controller not responding, assume dead\n");
1170 xhci
->xhc_state
|= XHCI_STATE_DYING
;
1172 xhci_cleanup_command_queue(xhci
);
1174 /* return any pending urbs, remove may be waiting for them */
1175 for (i
= 0; i
<= HCS_MAX_SLOTS(xhci
->hcs_params1
); i
++) {
1178 for (j
= 0; j
< 31; j
++)
1179 xhci_kill_endpoint_urbs(xhci
, i
, j
);
1182 /* inform usb core hc died if PCI remove isn't already handling it */
1183 if (!(xhci
->xhc_state
& XHCI_STATE_REMOVING
))
1184 usb_hc_died(xhci_to_hcd(xhci
));
1187 /* Watchdog timer function for when a stop endpoint command fails to complete.
1188 * In this case, we assume the host controller is broken or dying or dead. The
1189 * host may still be completing some other events, so we have to be careful to
1190 * let the event ring handler and the URB dequeueing/enqueueing functions know
1191 * through xhci->state.
1193 * The timer may also fire if the host takes a very long time to respond to the
1194 * command, and the stop endpoint command completion handler cannot delete the
1195 * timer before the timer function is called. Another endpoint cancellation may
1196 * sneak in before the timer function can grab the lock, and that may queue
1197 * another stop endpoint command and add the timer back. So we cannot use a
1198 * simple flag to say whether there is a pending stop endpoint command for a
1199 * particular endpoint.
1201 * Instead we use a combination of that flag and checking if a new timer is
1204 void xhci_stop_endpoint_command_watchdog(struct timer_list
*t
)
1206 struct xhci_virt_ep
*ep
= from_timer(ep
, t
, stop_cmd_timer
);
1207 struct xhci_hcd
*xhci
= ep
->xhci
;
1208 unsigned long flags
;
1211 spin_lock_irqsave(&xhci
->lock
, flags
);
1213 /* bail out if cmd completed but raced with stop ep watchdog timer.*/
1214 if (!(ep
->ep_state
& EP_STOP_CMD_PENDING
) ||
1215 timer_pending(&ep
->stop_cmd_timer
)) {
1216 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1217 xhci_dbg(xhci
, "Stop EP timer raced with cmd completion, exit");
1220 usbsts
= readl(&xhci
->op_regs
->status
);
1222 xhci_warn(xhci
, "xHCI host not responding to stop endpoint command.\n");
1223 xhci_warn(xhci
, "USBSTS:%s\n", xhci_decode_usbsts(usbsts
));
1225 ep
->ep_state
&= ~EP_STOP_CMD_PENDING
;
1230 * handle a stop endpoint cmd timeout as if host died (-ENODEV).
1231 * In the future we could distinguish between -ENODEV and -ETIMEDOUT
1232 * and try to recover a -ETIMEDOUT with a host controller reset
1236 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1237 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
1238 "xHCI host controller is dead.");
1241 static void update_ring_for_set_deq_completion(struct xhci_hcd
*xhci
,
1242 struct xhci_virt_device
*dev
,
1243 struct xhci_ring
*ep_ring
,
1244 unsigned int ep_index
)
1246 union xhci_trb
*dequeue_temp
;
1247 int num_trbs_free_temp
;
1248 bool revert
= false;
1250 num_trbs_free_temp
= ep_ring
->num_trbs_free
;
1251 dequeue_temp
= ep_ring
->dequeue
;
1253 /* If we get two back-to-back stalls, and the first stalled transfer
1254 * ends just before a link TRB, the dequeue pointer will be left on
1255 * the link TRB by the code in the while loop. So we have to update
1256 * the dequeue pointer one segment further, or we'll jump off
1257 * the segment into la-la-land.
1259 if (trb_is_link(ep_ring
->dequeue
)) {
1260 ep_ring
->deq_seg
= ep_ring
->deq_seg
->next
;
1261 ep_ring
->dequeue
= ep_ring
->deq_seg
->trbs
;
1264 while (ep_ring
->dequeue
!= dev
->eps
[ep_index
].queued_deq_ptr
) {
1265 /* We have more usable TRBs */
1266 ep_ring
->num_trbs_free
++;
1268 if (trb_is_link(ep_ring
->dequeue
)) {
1269 if (ep_ring
->dequeue
==
1270 dev
->eps
[ep_index
].queued_deq_ptr
)
1272 ep_ring
->deq_seg
= ep_ring
->deq_seg
->next
;
1273 ep_ring
->dequeue
= ep_ring
->deq_seg
->trbs
;
1275 if (ep_ring
->dequeue
== dequeue_temp
) {
1282 xhci_dbg(xhci
, "Unable to find new dequeue pointer\n");
1283 ep_ring
->num_trbs_free
= num_trbs_free_temp
;
1288 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1289 * we need to clear the set deq pending flag in the endpoint ring state, so that
1290 * the TD queueing code can ring the doorbell again. We also need to ring the
1291 * endpoint doorbell to restart the ring, but only if there aren't more
1292 * cancellations pending.
1294 static void xhci_handle_cmd_set_deq(struct xhci_hcd
*xhci
, int slot_id
,
1295 union xhci_trb
*trb
, u32 cmd_comp_code
)
1297 unsigned int ep_index
;
1298 unsigned int stream_id
;
1299 struct xhci_ring
*ep_ring
;
1300 struct xhci_virt_ep
*ep
;
1301 struct xhci_ep_ctx
*ep_ctx
;
1302 struct xhci_slot_ctx
*slot_ctx
;
1303 struct xhci_td
*td
, *tmp_td
;
1305 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
1306 stream_id
= TRB_TO_STREAM_ID(le32_to_cpu(trb
->generic
.field
[2]));
1307 ep
= xhci_get_virt_ep(xhci
, slot_id
, ep_index
);
1311 ep_ring
= xhci_virt_ep_to_ring(xhci
, ep
, stream_id
);
1313 xhci_warn(xhci
, "WARN Set TR deq ptr command for freed stream ID %u\n",
1315 /* XXX: Harmless??? */
1319 ep_ctx
= xhci_get_ep_ctx(xhci
, ep
->vdev
->out_ctx
, ep_index
);
1320 slot_ctx
= xhci_get_slot_ctx(xhci
, ep
->vdev
->out_ctx
);
1321 trace_xhci_handle_cmd_set_deq(slot_ctx
);
1322 trace_xhci_handle_cmd_set_deq_ep(ep_ctx
);
1324 if (cmd_comp_code
!= COMP_SUCCESS
) {
1325 unsigned int ep_state
;
1326 unsigned int slot_state
;
1328 switch (cmd_comp_code
) {
1329 case COMP_TRB_ERROR
:
1330 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1332 case COMP_CONTEXT_STATE_ERROR
:
1333 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1334 ep_state
= GET_EP_CTX_STATE(ep_ctx
);
1335 slot_state
= le32_to_cpu(slot_ctx
->dev_state
);
1336 slot_state
= GET_SLOT_STATE(slot_state
);
1337 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
1338 "Slot state = %u, EP state = %u",
1339 slot_state
, ep_state
);
1341 case COMP_SLOT_NOT_ENABLED_ERROR
:
1342 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1346 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1350 /* OK what do we do now? The endpoint state is hosed, and we
1351 * should never get to this point if the synchronization between
1352 * queueing, and endpoint state are correct. This might happen
1353 * if the device gets disconnected after we've finished
1354 * cancelling URBs, which might not be an error...
1358 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1359 if (ep
->ep_state
& EP_HAS_STREAMS
) {
1360 struct xhci_stream_ctx
*ctx
=
1361 &ep
->stream_info
->stream_ctx_array
[stream_id
];
1362 deq
= le64_to_cpu(ctx
->stream_ring
) & SCTX_DEQ_MASK
;
1364 deq
= le64_to_cpu(ep_ctx
->deq
) & ~EP_CTX_CYCLE_MASK
;
1366 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
1367 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq
);
1368 if (xhci_trb_virt_to_dma(ep
->queued_deq_seg
,
1369 ep
->queued_deq_ptr
) == deq
) {
1370 /* Update the ring's dequeue segment and dequeue pointer
1371 * to reflect the new position.
1373 update_ring_for_set_deq_completion(xhci
, ep
->vdev
,
1376 xhci_warn(xhci
, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1377 xhci_warn(xhci
, "ep deq seg = %p, deq ptr = %p\n",
1378 ep
->queued_deq_seg
, ep
->queued_deq_ptr
);
1381 /* HW cached TDs cleared from cache, give them back */
1382 list_for_each_entry_safe(td
, tmp_td
, &ep
->cancelled_td_list
,
1383 cancelled_td_list
) {
1384 ep_ring
= xhci_urb_to_transfer_ring(ep
->xhci
, td
->urb
);
1385 if (td
->cancel_status
== TD_CLEARING_CACHE
) {
1386 td
->cancel_status
= TD_CLEARED
;
1387 xhci_td_cleanup(ep
->xhci
, td
, ep_ring
, td
->status
);
1391 ep
->ep_state
&= ~SET_DEQ_PENDING
;
1392 ep
->queued_deq_seg
= NULL
;
1393 ep
->queued_deq_ptr
= NULL
;
1394 /* Restart any rings with pending URBs */
1395 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1398 static void xhci_handle_cmd_reset_ep(struct xhci_hcd
*xhci
, int slot_id
,
1399 union xhci_trb
*trb
, u32 cmd_comp_code
)
1401 struct xhci_virt_ep
*ep
;
1402 struct xhci_ep_ctx
*ep_ctx
;
1403 unsigned int ep_index
;
1405 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
1406 ep
= xhci_get_virt_ep(xhci
, slot_id
, ep_index
);
1410 ep_ctx
= xhci_get_ep_ctx(xhci
, ep
->vdev
->out_ctx
, ep_index
);
1411 trace_xhci_handle_cmd_reset_ep(ep_ctx
);
1413 /* This command will only fail if the endpoint wasn't halted,
1414 * but we don't care.
1416 xhci_dbg_trace(xhci
, trace_xhci_dbg_reset_ep
,
1417 "Ignoring reset ep completion code of %u", cmd_comp_code
);
1419 /* Cleanup cancelled TDs as ep is stopped. May queue a Set TR Deq cmd */
1420 xhci_invalidate_cancelled_tds(ep
);
1422 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
)
1423 xhci_dbg(xhci
, "Note: Removed workaround to queue config ep for this hw");
1424 /* Clear our internal halted state */
1425 ep
->ep_state
&= ~EP_HALTED
;
1427 xhci_giveback_invalidated_tds(ep
);
1429 /* if this was a soft reset, then restart */
1430 if ((le32_to_cpu(trb
->generic
.field
[3])) & TRB_TSP
)
1431 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1434 static void xhci_handle_cmd_enable_slot(struct xhci_hcd
*xhci
, int slot_id
,
1435 struct xhci_command
*command
, u32 cmd_comp_code
)
1437 if (cmd_comp_code
== COMP_SUCCESS
)
1438 command
->slot_id
= slot_id
;
1440 command
->slot_id
= 0;
1443 static void xhci_handle_cmd_disable_slot(struct xhci_hcd
*xhci
, int slot_id
)
1445 struct xhci_virt_device
*virt_dev
;
1446 struct xhci_slot_ctx
*slot_ctx
;
1448 virt_dev
= xhci
->devs
[slot_id
];
1452 slot_ctx
= xhci_get_slot_ctx(xhci
, virt_dev
->out_ctx
);
1453 trace_xhci_handle_cmd_disable_slot(slot_ctx
);
1455 if (xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
)
1456 /* Delete default control endpoint resources */
1457 xhci_free_device_endpoint_resources(xhci
, virt_dev
, true);
1458 xhci_free_virt_device(xhci
, slot_id
);
1461 static void xhci_handle_cmd_config_ep(struct xhci_hcd
*xhci
, int slot_id
,
1464 struct xhci_virt_device
*virt_dev
;
1465 struct xhci_input_control_ctx
*ctrl_ctx
;
1466 struct xhci_ep_ctx
*ep_ctx
;
1467 unsigned int ep_index
;
1468 unsigned int ep_state
;
1469 u32 add_flags
, drop_flags
;
1472 * Configure endpoint commands can come from the USB core
1473 * configuration or alt setting changes, or because the HW
1474 * needed an extra configure endpoint command after a reset
1475 * endpoint command or streams were being configured.
1476 * If the command was for a halted endpoint, the xHCI driver
1477 * is not waiting on the configure endpoint command.
1479 virt_dev
= xhci
->devs
[slot_id
];
1482 ctrl_ctx
= xhci_get_input_control_ctx(virt_dev
->in_ctx
);
1484 xhci_warn(xhci
, "Could not get input context, bad type.\n");
1488 add_flags
= le32_to_cpu(ctrl_ctx
->add_flags
);
1489 drop_flags
= le32_to_cpu(ctrl_ctx
->drop_flags
);
1490 /* Input ctx add_flags are the endpoint index plus one */
1491 ep_index
= xhci_last_valid_endpoint(add_flags
) - 1;
1493 ep_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->out_ctx
, ep_index
);
1494 trace_xhci_handle_cmd_config_ep(ep_ctx
);
1496 /* A usb_set_interface() call directly after clearing a halted
1497 * condition may race on this quirky hardware. Not worth
1498 * worrying about, since this is prototype hardware. Not sure
1499 * if this will work for streams, but streams support was
1500 * untested on this prototype.
1502 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
&&
1503 ep_index
!= (unsigned int) -1 &&
1504 add_flags
- SLOT_FLAG
== drop_flags
) {
1505 ep_state
= virt_dev
->eps
[ep_index
].ep_state
;
1506 if (!(ep_state
& EP_HALTED
))
1508 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
1509 "Completed config ep cmd - "
1510 "last ep index = %d, state = %d",
1511 ep_index
, ep_state
);
1512 /* Clear internal halted state and restart ring(s) */
1513 virt_dev
->eps
[ep_index
].ep_state
&= ~EP_HALTED
;
1514 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1520 static void xhci_handle_cmd_addr_dev(struct xhci_hcd
*xhci
, int slot_id
)
1522 struct xhci_virt_device
*vdev
;
1523 struct xhci_slot_ctx
*slot_ctx
;
1525 vdev
= xhci
->devs
[slot_id
];
1528 slot_ctx
= xhci_get_slot_ctx(xhci
, vdev
->out_ctx
);
1529 trace_xhci_handle_cmd_addr_dev(slot_ctx
);
1532 static void xhci_handle_cmd_reset_dev(struct xhci_hcd
*xhci
, int slot_id
)
1534 struct xhci_virt_device
*vdev
;
1535 struct xhci_slot_ctx
*slot_ctx
;
1537 vdev
= xhci
->devs
[slot_id
];
1539 xhci_warn(xhci
, "Reset device command completion for disabled slot %u\n",
1543 slot_ctx
= xhci_get_slot_ctx(xhci
, vdev
->out_ctx
);
1544 trace_xhci_handle_cmd_reset_dev(slot_ctx
);
1546 xhci_dbg(xhci
, "Completed reset device command.\n");
1549 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd
*xhci
,
1550 struct xhci_event_cmd
*event
)
1552 if (!(xhci
->quirks
& XHCI_NEC_HOST
)) {
1553 xhci_warn(xhci
, "WARN NEC_GET_FW command on non-NEC host\n");
1556 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
1557 "NEC firmware version %2x.%02x",
1558 NEC_FW_MAJOR(le32_to_cpu(event
->status
)),
1559 NEC_FW_MINOR(le32_to_cpu(event
->status
)));
1562 static void xhci_complete_del_and_free_cmd(struct xhci_command
*cmd
, u32 status
)
1564 list_del(&cmd
->cmd_list
);
1566 if (cmd
->completion
) {
1567 cmd
->status
= status
;
1568 complete(cmd
->completion
);
1574 void xhci_cleanup_command_queue(struct xhci_hcd
*xhci
)
1576 struct xhci_command
*cur_cmd
, *tmp_cmd
;
1577 xhci
->current_cmd
= NULL
;
1578 list_for_each_entry_safe(cur_cmd
, tmp_cmd
, &xhci
->cmd_list
, cmd_list
)
1579 xhci_complete_del_and_free_cmd(cur_cmd
, COMP_COMMAND_ABORTED
);
1582 void xhci_handle_command_timeout(struct work_struct
*work
)
1584 struct xhci_hcd
*xhci
;
1585 unsigned long flags
;
1588 xhci
= container_of(to_delayed_work(work
), struct xhci_hcd
, cmd_timer
);
1590 spin_lock_irqsave(&xhci
->lock
, flags
);
1593 * If timeout work is pending, or current_cmd is NULL, it means we
1594 * raced with command completion. Command is handled so just return.
1596 if (!xhci
->current_cmd
|| delayed_work_pending(&xhci
->cmd_timer
)) {
1597 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1600 /* mark this command to be cancelled */
1601 xhci
->current_cmd
->status
= COMP_COMMAND_ABORTED
;
1603 /* Make sure command ring is running before aborting it */
1604 hw_ring_state
= xhci_read_64(xhci
, &xhci
->op_regs
->cmd_ring
);
1605 if (hw_ring_state
== ~(u64
)0) {
1607 goto time_out_completed
;
1610 if ((xhci
->cmd_ring_state
& CMD_RING_STATE_RUNNING
) &&
1611 (hw_ring_state
& CMD_RING_RUNNING
)) {
1612 /* Prevent new doorbell, and start command abort */
1613 xhci
->cmd_ring_state
= CMD_RING_STATE_ABORTED
;
1614 xhci_dbg(xhci
, "Command timeout\n");
1615 xhci_abort_cmd_ring(xhci
, flags
);
1616 goto time_out_completed
;
1619 /* host removed. Bail out */
1620 if (xhci
->xhc_state
& XHCI_STATE_REMOVING
) {
1621 xhci_dbg(xhci
, "host removed, ring start fail?\n");
1622 xhci_cleanup_command_queue(xhci
);
1624 goto time_out_completed
;
1627 /* command timeout on stopped ring, ring can't be aborted */
1628 xhci_dbg(xhci
, "Command timeout on stopped ring\n");
1629 xhci_handle_stopped_cmd_ring(xhci
, xhci
->current_cmd
);
1632 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1636 static void handle_cmd_completion(struct xhci_hcd
*xhci
,
1637 struct xhci_event_cmd
*event
)
1639 unsigned int slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1641 dma_addr_t cmd_dequeue_dma
;
1643 union xhci_trb
*cmd_trb
;
1644 struct xhci_command
*cmd
;
1647 if (slot_id
>= MAX_HC_SLOTS
) {
1648 xhci_warn(xhci
, "Invalid slot_id %u\n", slot_id
);
1652 cmd_dma
= le64_to_cpu(event
->cmd_trb
);
1653 cmd_trb
= xhci
->cmd_ring
->dequeue
;
1655 trace_xhci_handle_command(xhci
->cmd_ring
, &cmd_trb
->generic
);
1657 cmd_dequeue_dma
= xhci_trb_virt_to_dma(xhci
->cmd_ring
->deq_seg
,
1660 * Check whether the completion event is for our internal kept
1663 if (!cmd_dequeue_dma
|| cmd_dma
!= (u64
)cmd_dequeue_dma
) {
1665 "ERROR mismatched command completion event\n");
1669 cmd
= list_first_entry(&xhci
->cmd_list
, struct xhci_command
, cmd_list
);
1671 cancel_delayed_work(&xhci
->cmd_timer
);
1673 cmd_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->status
));
1675 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1676 if (cmd_comp_code
== COMP_COMMAND_RING_STOPPED
) {
1677 complete_all(&xhci
->cmd_ring_stop_completion
);
1681 if (cmd
->command_trb
!= xhci
->cmd_ring
->dequeue
) {
1683 "Command completion event does not match command\n");
1688 * Host aborted the command ring, check if the current command was
1689 * supposed to be aborted, otherwise continue normally.
1690 * The command ring is stopped now, but the xHC will issue a Command
1691 * Ring Stopped event which will cause us to restart it.
1693 if (cmd_comp_code
== COMP_COMMAND_ABORTED
) {
1694 xhci
->cmd_ring_state
= CMD_RING_STATE_STOPPED
;
1695 if (cmd
->status
== COMP_COMMAND_ABORTED
) {
1696 if (xhci
->current_cmd
== cmd
)
1697 xhci
->current_cmd
= NULL
;
1702 cmd_type
= TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb
->generic
.field
[3]));
1704 case TRB_ENABLE_SLOT
:
1705 xhci_handle_cmd_enable_slot(xhci
, slot_id
, cmd
, cmd_comp_code
);
1707 case TRB_DISABLE_SLOT
:
1708 xhci_handle_cmd_disable_slot(xhci
, slot_id
);
1711 if (!cmd
->completion
)
1712 xhci_handle_cmd_config_ep(xhci
, slot_id
, cmd_comp_code
);
1714 case TRB_EVAL_CONTEXT
:
1717 xhci_handle_cmd_addr_dev(xhci
, slot_id
);
1720 WARN_ON(slot_id
!= TRB_TO_SLOT_ID(
1721 le32_to_cpu(cmd_trb
->generic
.field
[3])));
1722 if (!cmd
->completion
)
1723 xhci_handle_cmd_stop_ep(xhci
, slot_id
, cmd_trb
,
1727 WARN_ON(slot_id
!= TRB_TO_SLOT_ID(
1728 le32_to_cpu(cmd_trb
->generic
.field
[3])));
1729 xhci_handle_cmd_set_deq(xhci
, slot_id
, cmd_trb
, cmd_comp_code
);
1732 /* Is this an aborted command turned to NO-OP? */
1733 if (cmd
->status
== COMP_COMMAND_RING_STOPPED
)
1734 cmd_comp_code
= COMP_COMMAND_RING_STOPPED
;
1737 WARN_ON(slot_id
!= TRB_TO_SLOT_ID(
1738 le32_to_cpu(cmd_trb
->generic
.field
[3])));
1739 xhci_handle_cmd_reset_ep(xhci
, slot_id
, cmd_trb
, cmd_comp_code
);
1742 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1743 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1745 slot_id
= TRB_TO_SLOT_ID(
1746 le32_to_cpu(cmd_trb
->generic
.field
[3]));
1747 xhci_handle_cmd_reset_dev(xhci
, slot_id
);
1749 case TRB_NEC_GET_FW
:
1750 xhci_handle_cmd_nec_get_fw(xhci
, event
);
1753 /* Skip over unknown commands on the event ring */
1754 xhci_info(xhci
, "INFO unknown command type %d\n", cmd_type
);
1758 /* restart timer if this wasn't the last command */
1759 if (!list_is_singular(&xhci
->cmd_list
)) {
1760 xhci
->current_cmd
= list_first_entry(&cmd
->cmd_list
,
1761 struct xhci_command
, cmd_list
);
1762 xhci_mod_cmd_timer(xhci
, XHCI_CMD_DEFAULT_TIMEOUT
);
1763 } else if (xhci
->current_cmd
== cmd
) {
1764 xhci
->current_cmd
= NULL
;
1768 xhci_complete_del_and_free_cmd(cmd
, cmd_comp_code
);
1770 inc_deq(xhci
, xhci
->cmd_ring
);
1773 static void handle_vendor_event(struct xhci_hcd
*xhci
,
1774 union xhci_trb
*event
, u32 trb_type
)
1776 xhci_dbg(xhci
, "Vendor specific event TRB type = %u\n", trb_type
);
1777 if (trb_type
== TRB_NEC_CMD_COMP
&& (xhci
->quirks
& XHCI_NEC_HOST
))
1778 handle_cmd_completion(xhci
, &event
->event_cmd
);
1781 static void handle_device_notification(struct xhci_hcd
*xhci
,
1782 union xhci_trb
*event
)
1785 struct usb_device
*udev
;
1787 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->generic
.field
[3]));
1788 if (!xhci
->devs
[slot_id
]) {
1789 xhci_warn(xhci
, "Device Notification event for "
1790 "unused slot %u\n", slot_id
);
1794 xhci_dbg(xhci
, "Device Wake Notification event for slot ID %u\n",
1796 udev
= xhci
->devs
[slot_id
]->udev
;
1797 if (udev
&& udev
->parent
)
1798 usb_wakeup_notification(udev
->parent
, udev
->portnum
);
1802 * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI
1804 * As per ThunderX2errata-129 USB 2 device may come up as USB 1
1805 * If a connection to a USB 1 device is followed by another connection
1806 * to a USB 2 device.
1808 * Reset the PHY after the USB device is disconnected if device speed
1809 * is less than HCD_USB3.
1810 * Retry the reset sequence max of 4 times checking the PLL lock status.
1813 static void xhci_cavium_reset_phy_quirk(struct xhci_hcd
*xhci
)
1815 struct usb_hcd
*hcd
= xhci_to_hcd(xhci
);
1817 u32 retry_count
= 4;
1820 /* Assert PHY reset */
1821 writel(0x6F, hcd
->regs
+ 0x1048);
1823 /* De-assert the PHY reset */
1824 writel(0x7F, hcd
->regs
+ 0x1048);
1826 pll_lock_check
= readl(hcd
->regs
+ 0x1070);
1827 } while (!(pll_lock_check
& 0x1) && --retry_count
);
1830 static void handle_port_status(struct xhci_hcd
*xhci
,
1831 union xhci_trb
*event
)
1833 struct usb_hcd
*hcd
;
1835 u32 portsc
, cmd_reg
;
1838 unsigned int hcd_portnum
;
1839 struct xhci_bus_state
*bus_state
;
1840 bool bogus_port_status
= false;
1841 struct xhci_port
*port
;
1843 /* Port status change events always have a successful completion code */
1844 if (GET_COMP_CODE(le32_to_cpu(event
->generic
.field
[2])) != COMP_SUCCESS
)
1846 "WARN: xHC returned failed port status event\n");
1848 port_id
= GET_PORT_ID(le32_to_cpu(event
->generic
.field
[0]));
1849 max_ports
= HCS_MAX_PORTS(xhci
->hcs_params1
);
1851 if ((port_id
<= 0) || (port_id
> max_ports
)) {
1852 xhci_warn(xhci
, "Port change event with invalid port ID %d\n",
1854 inc_deq(xhci
, xhci
->event_ring
);
1858 port
= &xhci
->hw_ports
[port_id
- 1];
1859 if (!port
|| !port
->rhub
|| port
->hcd_portnum
== DUPLICATE_ENTRY
) {
1860 xhci_warn(xhci
, "Port change event, no port for port ID %u\n",
1862 bogus_port_status
= true;
1866 /* We might get interrupts after shared_hcd is removed */
1867 if (port
->rhub
== &xhci
->usb3_rhub
&& xhci
->shared_hcd
== NULL
) {
1868 xhci_dbg(xhci
, "ignore port event for removed USB3 hcd\n");
1869 bogus_port_status
= true;
1873 hcd
= port
->rhub
->hcd
;
1874 bus_state
= &port
->rhub
->bus_state
;
1875 hcd_portnum
= port
->hcd_portnum
;
1876 portsc
= readl(port
->addr
);
1878 xhci_dbg(xhci
, "Port change event, %d-%d, id %d, portsc: 0x%x\n",
1879 hcd
->self
.busnum
, hcd_portnum
+ 1, port_id
, portsc
);
1881 trace_xhci_handle_port_status(hcd_portnum
, portsc
);
1883 if (hcd
->state
== HC_STATE_SUSPENDED
) {
1884 xhci_dbg(xhci
, "resume root hub\n");
1885 usb_hcd_resume_root_hub(hcd
);
1888 if (hcd
->speed
>= HCD_USB3
&&
1889 (portsc
& PORT_PLS_MASK
) == XDEV_INACTIVE
) {
1890 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
, hcd_portnum
+ 1);
1891 if (slot_id
&& xhci
->devs
[slot_id
])
1892 xhci
->devs
[slot_id
]->flags
|= VDEV_PORT_ERROR
;
1895 if ((portsc
& PORT_PLC
) && (portsc
& PORT_PLS_MASK
) == XDEV_RESUME
) {
1896 xhci_dbg(xhci
, "port resume event for port %d\n", port_id
);
1898 cmd_reg
= readl(&xhci
->op_regs
->command
);
1899 if (!(cmd_reg
& CMD_RUN
)) {
1900 xhci_warn(xhci
, "xHC is not running.\n");
1904 if (DEV_SUPERSPEED_ANY(portsc
)) {
1905 xhci_dbg(xhci
, "remote wake SS port %d\n", port_id
);
1906 /* Set a flag to say the port signaled remote wakeup,
1907 * so we can tell the difference between the end of
1908 * device and host initiated resume.
1910 bus_state
->port_remote_wakeup
|= 1 << hcd_portnum
;
1911 xhci_test_and_clear_bit(xhci
, port
, PORT_PLC
);
1912 usb_hcd_start_port_resume(&hcd
->self
, hcd_portnum
);
1913 xhci_set_link_state(xhci
, port
, XDEV_U0
);
1914 /* Need to wait until the next link state change
1915 * indicates the device is actually in U0.
1917 bogus_port_status
= true;
1919 } else if (!test_bit(hcd_portnum
, &bus_state
->resuming_ports
)) {
1920 xhci_dbg(xhci
, "resume HS port %d\n", port_id
);
1921 bus_state
->resume_done
[hcd_portnum
] = jiffies
+
1922 msecs_to_jiffies(USB_RESUME_TIMEOUT
);
1923 set_bit(hcd_portnum
, &bus_state
->resuming_ports
);
1924 /* Do the rest in GetPortStatus after resume time delay.
1925 * Avoid polling roothub status before that so that a
1926 * usb device auto-resume latency around ~40ms.
1928 set_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
1929 mod_timer(&hcd
->rh_timer
,
1930 bus_state
->resume_done
[hcd_portnum
]);
1931 usb_hcd_start_port_resume(&hcd
->self
, hcd_portnum
);
1932 bogus_port_status
= true;
1936 if ((portsc
& PORT_PLC
) &&
1937 DEV_SUPERSPEED_ANY(portsc
) &&
1938 ((portsc
& PORT_PLS_MASK
) == XDEV_U0
||
1939 (portsc
& PORT_PLS_MASK
) == XDEV_U1
||
1940 (portsc
& PORT_PLS_MASK
) == XDEV_U2
)) {
1941 xhci_dbg(xhci
, "resume SS port %d finished\n", port_id
);
1942 complete(&bus_state
->u3exit_done
[hcd_portnum
]);
1943 /* We've just brought the device into U0/1/2 through either the
1944 * Resume state after a device remote wakeup, or through the
1945 * U3Exit state after a host-initiated resume. If it's a device
1946 * initiated remote wake, don't pass up the link state change,
1947 * so the roothub behavior is consistent with external
1948 * USB 3.0 hub behavior.
1950 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
, hcd_portnum
+ 1);
1951 if (slot_id
&& xhci
->devs
[slot_id
])
1952 xhci_ring_device(xhci
, slot_id
);
1953 if (bus_state
->port_remote_wakeup
& (1 << hcd_portnum
)) {
1954 xhci_test_and_clear_bit(xhci
, port
, PORT_PLC
);
1955 usb_wakeup_notification(hcd
->self
.root_hub
,
1957 bogus_port_status
= true;
1963 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1964 * RExit to a disconnect state). If so, let the the driver know it's
1965 * out of the RExit state.
1967 if (!DEV_SUPERSPEED_ANY(portsc
) && hcd
->speed
< HCD_USB3
&&
1968 test_and_clear_bit(hcd_portnum
,
1969 &bus_state
->rexit_ports
)) {
1970 complete(&bus_state
->rexit_done
[hcd_portnum
]);
1971 bogus_port_status
= true;
1975 if (hcd
->speed
< HCD_USB3
) {
1976 xhci_test_and_clear_bit(xhci
, port
, PORT_PLC
);
1977 if ((xhci
->quirks
& XHCI_RESET_PLL_ON_DISCONNECT
) &&
1978 (portsc
& PORT_CSC
) && !(portsc
& PORT_CONNECT
))
1979 xhci_cavium_reset_phy_quirk(xhci
);
1983 /* Update event ring dequeue pointer before dropping the lock */
1984 inc_deq(xhci
, xhci
->event_ring
);
1986 /* Don't make the USB core poll the roothub if we got a bad port status
1987 * change event. Besides, at that point we can't tell which roothub
1988 * (USB 2.0 or USB 3.0) to kick.
1990 if (bogus_port_status
)
1994 * xHCI port-status-change events occur when the "or" of all the
1995 * status-change bits in the portsc register changes from 0 to 1.
1996 * New status changes won't cause an event if any other change
1997 * bits are still set. When an event occurs, switch over to
1998 * polling to avoid losing status changes.
2000 xhci_dbg(xhci
, "%s: starting port polling.\n", __func__
);
2001 set_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
2002 spin_unlock(&xhci
->lock
);
2003 /* Pass this up to the core */
2004 usb_hcd_poll_rh_status(hcd
);
2005 spin_lock(&xhci
->lock
);
2009 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
2010 * at end_trb, which may be in another segment. If the suspect DMA address is a
2011 * TRB in this TD, this function returns that TRB's segment. Otherwise it
2014 struct xhci_segment
*trb_in_td(struct xhci_hcd
*xhci
,
2015 struct xhci_segment
*start_seg
,
2016 union xhci_trb
*start_trb
,
2017 union xhci_trb
*end_trb
,
2018 dma_addr_t suspect_dma
,
2021 dma_addr_t start_dma
;
2022 dma_addr_t end_seg_dma
;
2023 dma_addr_t end_trb_dma
;
2024 struct xhci_segment
*cur_seg
;
2026 start_dma
= xhci_trb_virt_to_dma(start_seg
, start_trb
);
2027 cur_seg
= start_seg
;
2032 /* We may get an event for a Link TRB in the middle of a TD */
2033 end_seg_dma
= xhci_trb_virt_to_dma(cur_seg
,
2034 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1]);
2035 /* If the end TRB isn't in this segment, this is set to 0 */
2036 end_trb_dma
= xhci_trb_virt_to_dma(cur_seg
, end_trb
);
2040 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
2041 (unsigned long long)suspect_dma
,
2042 (unsigned long long)start_dma
,
2043 (unsigned long long)end_trb_dma
,
2044 (unsigned long long)cur_seg
->dma
,
2045 (unsigned long long)end_seg_dma
);
2047 if (end_trb_dma
> 0) {
2048 /* The end TRB is in this segment, so suspect should be here */
2049 if (start_dma
<= end_trb_dma
) {
2050 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_trb_dma
)
2053 /* Case for one segment with
2054 * a TD wrapped around to the top
2056 if ((suspect_dma
>= start_dma
&&
2057 suspect_dma
<= end_seg_dma
) ||
2058 (suspect_dma
>= cur_seg
->dma
&&
2059 suspect_dma
<= end_trb_dma
))
2064 /* Might still be somewhere in this segment */
2065 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_seg_dma
)
2068 cur_seg
= cur_seg
->next
;
2069 start_dma
= xhci_trb_virt_to_dma(cur_seg
, &cur_seg
->trbs
[0]);
2070 } while (cur_seg
!= start_seg
);
2075 static void xhci_clear_hub_tt_buffer(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
2076 struct xhci_virt_ep
*ep
)
2079 * As part of low/full-speed endpoint-halt processing
2080 * we must clear the TT buffer (USB 2.0 specification 11.17.5).
2082 if (td
->urb
->dev
->tt
&& !usb_pipeint(td
->urb
->pipe
) &&
2083 (td
->urb
->dev
->tt
->hub
!= xhci_to_hcd(xhci
)->self
.root_hub
) &&
2084 !(ep
->ep_state
& EP_CLEARING_TT
)) {
2085 ep
->ep_state
|= EP_CLEARING_TT
;
2086 td
->urb
->ep
->hcpriv
= td
->urb
->dev
;
2087 if (usb_hub_clear_tt_buffer(td
->urb
))
2088 ep
->ep_state
&= ~EP_CLEARING_TT
;
2092 /* Check if an error has halted the endpoint ring. The class driver will
2093 * cleanup the halt for a non-default control endpoint if we indicate a stall.
2094 * However, a babble and other errors also halt the endpoint ring, and the class
2095 * driver won't clear the halt in that case, so we need to issue a Set Transfer
2096 * Ring Dequeue Pointer command manually.
2098 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd
*xhci
,
2099 struct xhci_ep_ctx
*ep_ctx
,
2100 unsigned int trb_comp_code
)
2102 /* TRB completion codes that may require a manual halt cleanup */
2103 if (trb_comp_code
== COMP_USB_TRANSACTION_ERROR
||
2104 trb_comp_code
== COMP_BABBLE_DETECTED_ERROR
||
2105 trb_comp_code
== COMP_SPLIT_TRANSACTION_ERROR
)
2106 /* The 0.95 spec says a babbling control endpoint
2107 * is not halted. The 0.96 spec says it is. Some HW
2108 * claims to be 0.95 compliant, but it halts the control
2109 * endpoint anyway. Check if a babble halted the
2112 if (GET_EP_CTX_STATE(ep_ctx
) == EP_STATE_HALTED
)
2118 int xhci_is_vendor_info_code(struct xhci_hcd
*xhci
, unsigned int trb_comp_code
)
2120 if (trb_comp_code
>= 224 && trb_comp_code
<= 255) {
2121 /* Vendor defined "informational" completion code,
2122 * treat as not-an-error.
2124 xhci_dbg(xhci
, "Vendor defined info completion code %u\n",
2126 xhci_dbg(xhci
, "Treating code as success.\n");
2132 static int finish_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
2133 struct xhci_transfer_event
*event
, struct xhci_virt_ep
*ep
)
2135 struct xhci_ep_ctx
*ep_ctx
;
2136 struct xhci_ring
*ep_ring
;
2139 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
2140 ep_ctx
= xhci_get_ep_ctx(xhci
, ep
->vdev
->out_ctx
, ep
->ep_index
);
2141 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
2143 switch (trb_comp_code
) {
2144 case COMP_STOPPED_LENGTH_INVALID
:
2145 case COMP_STOPPED_SHORT_PACKET
:
2148 * The "Stop Endpoint" completion will take care of any
2149 * stopped TDs. A stopped TD may be restarted, so don't update
2150 * the ring dequeue pointer or take this TD off any lists yet.
2153 case COMP_USB_TRANSACTION_ERROR
:
2154 case COMP_BABBLE_DETECTED_ERROR
:
2155 case COMP_SPLIT_TRANSACTION_ERROR
:
2157 * If endpoint context state is not halted we might be
2158 * racing with a reset endpoint command issued by a unsuccessful
2159 * stop endpoint completion (context error). In that case the
2160 * td should be on the cancelled list, and EP_HALTED flag set.
2162 * Or then it's not halted due to the 0.95 spec stating that a
2163 * babbling control endpoint should not halt. The 0.96 spec
2164 * again says it should. Some HW claims to be 0.95 compliant,
2165 * but it halts the control endpoint anyway.
2167 if (GET_EP_CTX_STATE(ep_ctx
) != EP_STATE_HALTED
) {
2169 * If EP_HALTED is set and TD is on the cancelled list
2170 * the TD and dequeue pointer will be handled by reset
2171 * ep command completion
2173 if ((ep
->ep_state
& EP_HALTED
) &&
2174 !list_empty(&td
->cancelled_td_list
)) {
2175 xhci_dbg(xhci
, "Already resolving halted ep for 0x%llx\n",
2176 (unsigned long long)xhci_trb_virt_to_dma(
2177 td
->start_seg
, td
->first_trb
));
2180 /* endpoint not halted, don't reset it */
2183 /* Almost same procedure as for STALL_ERROR below */
2184 xhci_clear_hub_tt_buffer(xhci
, td
, ep
);
2185 xhci_handle_halted_endpoint(xhci
, ep
, ep_ring
->stream_id
, td
,
2188 case COMP_STALL_ERROR
:
2190 * xhci internal endpoint state will go to a "halt" state for
2191 * any stall, including default control pipe protocol stall.
2192 * To clear the host side halt we need to issue a reset endpoint
2193 * command, followed by a set dequeue command to move past the
2195 * Class drivers clear the device side halt from a functional
2196 * stall later. Hub TT buffer should only be cleared for FS/LS
2197 * devices behind HS hubs for functional stalls.
2199 if (ep
->ep_index
!= 0)
2200 xhci_clear_hub_tt_buffer(xhci
, td
, ep
);
2202 xhci_handle_halted_endpoint(xhci
, ep
, ep_ring
->stream_id
, td
,
2205 return 0; /* xhci_handle_halted_endpoint marked td cancelled */
2210 /* Update ring dequeue pointer */
2211 ep_ring
->dequeue
= td
->last_trb
;
2212 ep_ring
->deq_seg
= td
->last_trb_seg
;
2213 ep_ring
->num_trbs_free
+= td
->num_trbs
- 1;
2214 inc_deq(xhci
, ep_ring
);
2216 return xhci_td_cleanup(xhci
, td
, ep_ring
, td
->status
);
2219 /* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */
2220 static int sum_trb_lengths(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
2221 union xhci_trb
*stop_trb
)
2224 union xhci_trb
*trb
= ring
->dequeue
;
2225 struct xhci_segment
*seg
= ring
->deq_seg
;
2227 for (sum
= 0; trb
!= stop_trb
; next_trb(xhci
, ring
, &seg
, &trb
)) {
2228 if (!trb_is_noop(trb
) && !trb_is_link(trb
))
2229 sum
+= TRB_LEN(le32_to_cpu(trb
->generic
.field
[2]));
2235 * Process control tds, update urb status and actual_length.
2237 static int process_ctrl_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
2238 union xhci_trb
*ep_trb
, struct xhci_transfer_event
*event
,
2239 struct xhci_virt_ep
*ep
)
2241 struct xhci_ep_ctx
*ep_ctx
;
2243 u32 remaining
, requested
;
2246 trb_type
= TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb
->generic
.field
[3]));
2247 ep_ctx
= xhci_get_ep_ctx(xhci
, ep
->vdev
->out_ctx
, ep
->ep_index
);
2248 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
2249 requested
= td
->urb
->transfer_buffer_length
;
2250 remaining
= EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
2252 switch (trb_comp_code
) {
2254 if (trb_type
!= TRB_STATUS
) {
2255 xhci_warn(xhci
, "WARN: Success on ctrl %s TRB without IOC set?\n",
2256 (trb_type
== TRB_DATA
) ? "data" : "setup");
2257 td
->status
= -ESHUTDOWN
;
2262 case COMP_SHORT_PACKET
:
2265 case COMP_STOPPED_SHORT_PACKET
:
2266 if (trb_type
== TRB_DATA
|| trb_type
== TRB_NORMAL
)
2267 td
->urb
->actual_length
= remaining
;
2269 xhci_warn(xhci
, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
2274 td
->urb
->actual_length
= 0;
2278 td
->urb
->actual_length
= requested
- remaining
;
2281 td
->urb
->actual_length
= requested
;
2284 xhci_warn(xhci
, "WARN: unexpected TRB Type %d\n",
2288 case COMP_STOPPED_LENGTH_INVALID
:
2291 if (!xhci_requires_manual_halt_cleanup(xhci
,
2292 ep_ctx
, trb_comp_code
))
2294 xhci_dbg(xhci
, "TRB error %u, halted endpoint index = %u\n",
2295 trb_comp_code
, ep
->ep_index
);
2297 case COMP_STALL_ERROR
:
2298 /* Did we transfer part of the data (middle) phase? */
2299 if (trb_type
== TRB_DATA
|| trb_type
== TRB_NORMAL
)
2300 td
->urb
->actual_length
= requested
- remaining
;
2301 else if (!td
->urb_length_set
)
2302 td
->urb
->actual_length
= 0;
2306 /* stopped at setup stage, no data transferred */
2307 if (trb_type
== TRB_SETUP
)
2311 * if on data stage then update the actual_length of the URB and flag it
2312 * as set, so it won't be overwritten in the event for the last TRB.
2314 if (trb_type
== TRB_DATA
||
2315 trb_type
== TRB_NORMAL
) {
2316 td
->urb_length_set
= true;
2317 td
->urb
->actual_length
= requested
- remaining
;
2318 xhci_dbg(xhci
, "Waiting for status stage event\n");
2322 /* at status stage */
2323 if (!td
->urb_length_set
)
2324 td
->urb
->actual_length
= requested
;
2327 return finish_td(xhci
, td
, event
, ep
);
2331 * Process isochronous tds, update urb packet status and actual_length.
2333 static int process_isoc_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
2334 union xhci_trb
*ep_trb
, struct xhci_transfer_event
*event
,
2335 struct xhci_virt_ep
*ep
)
2337 struct urb_priv
*urb_priv
;
2339 struct usb_iso_packet_descriptor
*frame
;
2341 bool sum_trbs_for_length
= false;
2342 u32 remaining
, requested
, ep_trb_len
;
2343 int short_framestatus
;
2345 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
2346 urb_priv
= td
->urb
->hcpriv
;
2347 idx
= urb_priv
->num_tds_done
;
2348 frame
= &td
->urb
->iso_frame_desc
[idx
];
2349 requested
= frame
->length
;
2350 remaining
= EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
2351 ep_trb_len
= TRB_LEN(le32_to_cpu(ep_trb
->generic
.field
[2]));
2352 short_framestatus
= td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
?
2355 /* handle completion code */
2356 switch (trb_comp_code
) {
2359 frame
->status
= short_framestatus
;
2360 if (xhci
->quirks
& XHCI_TRUST_TX_LENGTH
)
2361 sum_trbs_for_length
= true;
2366 case COMP_SHORT_PACKET
:
2367 frame
->status
= short_framestatus
;
2368 sum_trbs_for_length
= true;
2370 case COMP_BANDWIDTH_OVERRUN_ERROR
:
2371 frame
->status
= -ECOMM
;
2373 case COMP_ISOCH_BUFFER_OVERRUN
:
2374 case COMP_BABBLE_DETECTED_ERROR
:
2375 frame
->status
= -EOVERFLOW
;
2377 case COMP_INCOMPATIBLE_DEVICE_ERROR
:
2378 case COMP_STALL_ERROR
:
2379 frame
->status
= -EPROTO
;
2381 case COMP_USB_TRANSACTION_ERROR
:
2382 frame
->status
= -EPROTO
;
2383 if (ep_trb
!= td
->last_trb
)
2387 sum_trbs_for_length
= true;
2389 case COMP_STOPPED_SHORT_PACKET
:
2390 /* field normally containing residue now contains tranferred */
2391 frame
->status
= short_framestatus
;
2392 requested
= remaining
;
2394 case COMP_STOPPED_LENGTH_INVALID
:
2399 sum_trbs_for_length
= true;
2404 if (sum_trbs_for_length
)
2405 frame
->actual_length
= sum_trb_lengths(xhci
, ep
->ring
, ep_trb
) +
2406 ep_trb_len
- remaining
;
2408 frame
->actual_length
= requested
;
2410 td
->urb
->actual_length
+= frame
->actual_length
;
2412 return finish_td(xhci
, td
, event
, ep
);
2415 static int skip_isoc_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
2416 struct xhci_virt_ep
*ep
, int status
)
2418 struct urb_priv
*urb_priv
;
2419 struct usb_iso_packet_descriptor
*frame
;
2422 urb_priv
= td
->urb
->hcpriv
;
2423 idx
= urb_priv
->num_tds_done
;
2424 frame
= &td
->urb
->iso_frame_desc
[idx
];
2426 /* The transfer is partly done. */
2427 frame
->status
= -EXDEV
;
2429 /* calc actual length */
2430 frame
->actual_length
= 0;
2432 /* Update ring dequeue pointer */
2433 ep
->ring
->dequeue
= td
->last_trb
;
2434 ep
->ring
->deq_seg
= td
->last_trb_seg
;
2435 ep
->ring
->num_trbs_free
+= td
->num_trbs
- 1;
2436 inc_deq(xhci
, ep
->ring
);
2438 return xhci_td_cleanup(xhci
, td
, ep
->ring
, status
);
2442 * Process bulk and interrupt tds, update urb status and actual_length.
2444 static int process_bulk_intr_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
2445 union xhci_trb
*ep_trb
, struct xhci_transfer_event
*event
,
2446 struct xhci_virt_ep
*ep
)
2448 struct xhci_slot_ctx
*slot_ctx
;
2449 struct xhci_ring
*ep_ring
;
2451 u32 remaining
, requested
, ep_trb_len
;
2453 slot_ctx
= xhci_get_slot_ctx(xhci
, ep
->vdev
->out_ctx
);
2454 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
2455 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
2456 remaining
= EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
2457 ep_trb_len
= TRB_LEN(le32_to_cpu(ep_trb
->generic
.field
[2]));
2458 requested
= td
->urb
->transfer_buffer_length
;
2460 switch (trb_comp_code
) {
2462 ep_ring
->err_count
= 0;
2463 /* handle success with untransferred data as short packet */
2464 if (ep_trb
!= td
->last_trb
|| remaining
) {
2465 xhci_warn(xhci
, "WARN Successful completion on short TX\n");
2466 xhci_dbg(xhci
, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2467 td
->urb
->ep
->desc
.bEndpointAddress
,
2468 requested
, remaining
);
2472 case COMP_SHORT_PACKET
:
2473 xhci_dbg(xhci
, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2474 td
->urb
->ep
->desc
.bEndpointAddress
,
2475 requested
, remaining
);
2478 case COMP_STOPPED_SHORT_PACKET
:
2479 td
->urb
->actual_length
= remaining
;
2481 case COMP_STOPPED_LENGTH_INVALID
:
2482 /* stopped on ep trb with invalid length, exclude it */
2486 case COMP_USB_TRANSACTION_ERROR
:
2487 if (xhci
->quirks
& XHCI_NO_SOFT_RETRY
||
2488 (ep_ring
->err_count
++ > MAX_SOFT_RETRY
) ||
2489 le32_to_cpu(slot_ctx
->tt_info
) & TT_SLOT
)
2494 xhci_handle_halted_endpoint(xhci
, ep
, ep_ring
->stream_id
, td
,
2502 if (ep_trb
== td
->last_trb
)
2503 td
->urb
->actual_length
= requested
- remaining
;
2505 td
->urb
->actual_length
=
2506 sum_trb_lengths(xhci
, ep_ring
, ep_trb
) +
2507 ep_trb_len
- remaining
;
2509 if (remaining
> requested
) {
2510 xhci_warn(xhci
, "bad transfer trb length %d in event trb\n",
2512 td
->urb
->actual_length
= 0;
2514 return finish_td(xhci
, td
, event
, ep
);
2518 * If this function returns an error condition, it means it got a Transfer
2519 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2520 * At this point, the host controller is probably hosed and should be reset.
2522 static int handle_tx_event(struct xhci_hcd
*xhci
,
2523 struct xhci_transfer_event
*event
)
2525 struct xhci_virt_ep
*ep
;
2526 struct xhci_ring
*ep_ring
;
2527 unsigned int slot_id
;
2529 struct xhci_td
*td
= NULL
;
2530 dma_addr_t ep_trb_dma
;
2531 struct xhci_segment
*ep_seg
;
2532 union xhci_trb
*ep_trb
;
2533 int status
= -EINPROGRESS
;
2534 struct xhci_ep_ctx
*ep_ctx
;
2535 struct list_head
*tmp
;
2538 bool handling_skipped_tds
= false;
2540 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
2541 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
2542 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
2543 ep_trb_dma
= le64_to_cpu(event
->buffer
);
2545 ep
= xhci_get_virt_ep(xhci
, slot_id
, ep_index
);
2547 xhci_err(xhci
, "ERROR Invalid Transfer event\n");
2551 ep_ring
= xhci_dma_to_transfer_ring(ep
, ep_trb_dma
);
2552 ep_ctx
= xhci_get_ep_ctx(xhci
, ep
->vdev
->out_ctx
, ep_index
);
2554 if (GET_EP_CTX_STATE(ep_ctx
) == EP_STATE_DISABLED
) {
2556 "ERROR Transfer event for disabled endpoint slot %u ep %u\n",
2561 /* Some transfer events don't always point to a trb, see xhci 4.17.4 */
2563 switch (trb_comp_code
) {
2564 case COMP_STALL_ERROR
:
2565 case COMP_USB_TRANSACTION_ERROR
:
2566 case COMP_INVALID_STREAM_TYPE_ERROR
:
2567 case COMP_INVALID_STREAM_ID_ERROR
:
2568 xhci_handle_halted_endpoint(xhci
, ep
, 0, NULL
,
2571 case COMP_RING_UNDERRUN
:
2572 case COMP_RING_OVERRUN
:
2573 case COMP_STOPPED_LENGTH_INVALID
:
2576 xhci_err(xhci
, "ERROR Transfer event for unknown stream ring slot %u ep %u\n",
2582 /* Count current td numbers if ep->skip is set */
2584 list_for_each(tmp
, &ep_ring
->td_list
)
2588 /* Look for common error cases */
2589 switch (trb_comp_code
) {
2590 /* Skip codes that require special handling depending on
2594 if (EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)) == 0)
2596 if (xhci
->quirks
& XHCI_TRUST_TX_LENGTH
||
2597 ep_ring
->last_td_was_short
)
2598 trb_comp_code
= COMP_SHORT_PACKET
;
2600 xhci_warn_ratelimited(xhci
,
2601 "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n",
2604 case COMP_SHORT_PACKET
:
2606 /* Completion codes for endpoint stopped state */
2608 xhci_dbg(xhci
, "Stopped on Transfer TRB for slot %u ep %u\n",
2611 case COMP_STOPPED_LENGTH_INVALID
:
2613 "Stopped on No-op or Link TRB for slot %u ep %u\n",
2616 case COMP_STOPPED_SHORT_PACKET
:
2618 "Stopped with short packet transfer detected for slot %u ep %u\n",
2621 /* Completion codes for endpoint halted state */
2622 case COMP_STALL_ERROR
:
2623 xhci_dbg(xhci
, "Stalled endpoint for slot %u ep %u\n", slot_id
,
2627 case COMP_SPLIT_TRANSACTION_ERROR
:
2628 xhci_dbg(xhci
, "Split transaction error for slot %u ep %u\n",
2632 case COMP_USB_TRANSACTION_ERROR
:
2633 xhci_dbg(xhci
, "Transfer error for slot %u ep %u on endpoint\n",
2637 case COMP_BABBLE_DETECTED_ERROR
:
2638 xhci_dbg(xhci
, "Babble error for slot %u ep %u on endpoint\n",
2640 status
= -EOVERFLOW
;
2642 /* Completion codes for endpoint error state */
2643 case COMP_TRB_ERROR
:
2645 "WARN: TRB error for slot %u ep %u on endpoint\n",
2649 /* completion codes not indicating endpoint state change */
2650 case COMP_DATA_BUFFER_ERROR
:
2652 "WARN: HC couldn't access mem fast enough for slot %u ep %u\n",
2656 case COMP_BANDWIDTH_OVERRUN_ERROR
:
2658 "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n",
2661 case COMP_ISOCH_BUFFER_OVERRUN
:
2663 "WARN: buffer overrun event for slot %u ep %u on endpoint",
2666 case COMP_RING_UNDERRUN
:
2668 * When the Isoch ring is empty, the xHC will generate
2669 * a Ring Overrun Event for IN Isoch endpoint or Ring
2670 * Underrun Event for OUT Isoch endpoint.
2672 xhci_dbg(xhci
, "underrun event on endpoint\n");
2673 if (!list_empty(&ep_ring
->td_list
))
2674 xhci_dbg(xhci
, "Underrun Event for slot %d ep %d "
2675 "still with TDs queued?\n",
2676 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2679 case COMP_RING_OVERRUN
:
2680 xhci_dbg(xhci
, "overrun event on endpoint\n");
2681 if (!list_empty(&ep_ring
->td_list
))
2682 xhci_dbg(xhci
, "Overrun Event for slot %d ep %d "
2683 "still with TDs queued?\n",
2684 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2687 case COMP_MISSED_SERVICE_ERROR
:
2689 * When encounter missed service error, one or more isoc tds
2690 * may be missed by xHC.
2691 * Set skip flag of the ep_ring; Complete the missed tds as
2692 * short transfer when process the ep_ring next time.
2696 "Miss service interval error for slot %u ep %u, set skip flag\n",
2699 case COMP_NO_PING_RESPONSE_ERROR
:
2702 "No Ping response error for slot %u ep %u, Skip one Isoc TD\n",
2706 case COMP_INCOMPATIBLE_DEVICE_ERROR
:
2707 /* needs disable slot command to recover */
2709 "WARN: detect an incompatible device for slot %u ep %u",
2714 if (xhci_is_vendor_info_code(xhci
, trb_comp_code
)) {
2719 "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n",
2720 trb_comp_code
, slot_id
, ep_index
);
2725 /* This TRB should be in the TD at the head of this ring's
2728 if (list_empty(&ep_ring
->td_list
)) {
2730 * Don't print wanings if it's due to a stopped endpoint
2731 * generating an extra completion event if the device
2732 * was suspended. Or, a event for the last TRB of a
2733 * short TD we already got a short event for.
2734 * The short TD is already removed from the TD list.
2737 if (!(trb_comp_code
== COMP_STOPPED
||
2738 trb_comp_code
== COMP_STOPPED_LENGTH_INVALID
||
2739 ep_ring
->last_td_was_short
)) {
2740 xhci_warn(xhci
, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2741 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2746 xhci_dbg(xhci
, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n",
2749 if (trb_comp_code
== COMP_STALL_ERROR
||
2750 xhci_requires_manual_halt_cleanup(xhci
, ep_ctx
,
2752 xhci_handle_halted_endpoint(xhci
, ep
,
2760 /* We've skipped all the TDs on the ep ring when ep->skip set */
2761 if (ep
->skip
&& td_num
== 0) {
2763 xhci_dbg(xhci
, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n",
2768 td
= list_first_entry(&ep_ring
->td_list
, struct xhci_td
,
2773 /* Is this a TRB in the currently executing TD? */
2774 ep_seg
= trb_in_td(xhci
, ep_ring
->deq_seg
, ep_ring
->dequeue
,
2775 td
->last_trb
, ep_trb_dma
, false);
2778 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2779 * is not in the current TD pointed by ep_ring->dequeue because
2780 * that the hardware dequeue pointer still at the previous TRB
2781 * of the current TD. The previous TRB maybe a Link TD or the
2782 * last TRB of the previous TD. The command completion handle
2783 * will take care the rest.
2785 if (!ep_seg
&& (trb_comp_code
== COMP_STOPPED
||
2786 trb_comp_code
== COMP_STOPPED_LENGTH_INVALID
)) {
2792 !usb_endpoint_xfer_isoc(&td
->urb
->ep
->desc
)) {
2793 /* Some host controllers give a spurious
2794 * successful event after a short transfer.
2797 if ((xhci
->quirks
& XHCI_SPURIOUS_SUCCESS
) &&
2798 ep_ring
->last_td_was_short
) {
2799 ep_ring
->last_td_was_short
= false;
2802 /* HC is busted, give up! */
2804 "ERROR Transfer event TRB DMA ptr not "
2805 "part of current TD ep_index %d "
2806 "comp_code %u\n", ep_index
,
2808 trb_in_td(xhci
, ep_ring
->deq_seg
,
2809 ep_ring
->dequeue
, td
->last_trb
,
2814 skip_isoc_td(xhci
, td
, ep
, status
);
2817 if (trb_comp_code
== COMP_SHORT_PACKET
)
2818 ep_ring
->last_td_was_short
= true;
2820 ep_ring
->last_td_was_short
= false;
2824 "Found td. Clear skip flag for slot %u ep %u.\n",
2829 ep_trb
= &ep_seg
->trbs
[(ep_trb_dma
- ep_seg
->dma
) /
2832 trace_xhci_handle_transfer(ep_ring
,
2833 (struct xhci_generic_trb
*) ep_trb
);
2836 * No-op TRB could trigger interrupts in a case where
2837 * a URB was killed and a STALL_ERROR happens right
2838 * after the endpoint ring stopped. Reset the halted
2839 * endpoint. Otherwise, the endpoint remains stalled
2843 if (trb_is_noop(ep_trb
)) {
2844 if (trb_comp_code
== COMP_STALL_ERROR
||
2845 xhci_requires_manual_halt_cleanup(xhci
, ep_ctx
,
2847 xhci_handle_halted_endpoint(xhci
, ep
,
2853 td
->status
= status
;
2855 /* update the urb's actual_length and give back to the core */
2856 if (usb_endpoint_xfer_control(&td
->urb
->ep
->desc
))
2857 process_ctrl_td(xhci
, td
, ep_trb
, event
, ep
);
2858 else if (usb_endpoint_xfer_isoc(&td
->urb
->ep
->desc
))
2859 process_isoc_td(xhci
, td
, ep_trb
, event
, ep
);
2861 process_bulk_intr_td(xhci
, td
, ep_trb
, event
, ep
);
2863 handling_skipped_tds
= ep
->skip
&&
2864 trb_comp_code
!= COMP_MISSED_SERVICE_ERROR
&&
2865 trb_comp_code
!= COMP_NO_PING_RESPONSE_ERROR
;
2868 * Do not update event ring dequeue pointer if we're in a loop
2869 * processing missed tds.
2871 if (!handling_skipped_tds
)
2872 inc_deq(xhci
, xhci
->event_ring
);
2875 * If ep->skip is set, it means there are missed tds on the
2876 * endpoint ring need to take care of.
2877 * Process them as short transfer until reach the td pointed by
2880 } while (handling_skipped_tds
);
2885 xhci_err(xhci
, "@%016llx %08x %08x %08x %08x\n",
2886 (unsigned long long) xhci_trb_virt_to_dma(
2887 xhci
->event_ring
->deq_seg
,
2888 xhci
->event_ring
->dequeue
),
2889 lower_32_bits(le64_to_cpu(event
->buffer
)),
2890 upper_32_bits(le64_to_cpu(event
->buffer
)),
2891 le32_to_cpu(event
->transfer_len
),
2892 le32_to_cpu(event
->flags
));
2897 * This function handles all OS-owned events on the event ring. It may drop
2898 * xhci->lock between event processing (e.g. to pass up port status changes).
2899 * Returns >0 for "possibly more events to process" (caller should call again),
2900 * otherwise 0 if done. In future, <0 returns should indicate error code.
2902 static int xhci_handle_event(struct xhci_hcd
*xhci
)
2904 union xhci_trb
*event
;
2905 int update_ptrs
= 1;
2909 /* Event ring hasn't been allocated yet. */
2910 if (!xhci
->event_ring
|| !xhci
->event_ring
->dequeue
) {
2911 xhci_err(xhci
, "ERROR event ring not ready\n");
2915 event
= xhci
->event_ring
->dequeue
;
2916 /* Does the HC or OS own the TRB? */
2917 if ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_CYCLE
) !=
2918 xhci
->event_ring
->cycle_state
)
2921 trace_xhci_handle_event(xhci
->event_ring
, &event
->generic
);
2924 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2925 * speculative reads of the event's flags/data below.
2928 trb_type
= TRB_FIELD_TO_TYPE(le32_to_cpu(event
->event_cmd
.flags
));
2929 /* FIXME: Handle more event types. */
2932 case TRB_COMPLETION
:
2933 handle_cmd_completion(xhci
, &event
->event_cmd
);
2935 case TRB_PORT_STATUS
:
2936 handle_port_status(xhci
, event
);
2940 ret
= handle_tx_event(xhci
, &event
->trans_event
);
2945 handle_device_notification(xhci
, event
);
2948 if (trb_type
>= TRB_VENDOR_DEFINED_LOW
)
2949 handle_vendor_event(xhci
, event
, trb_type
);
2951 xhci_warn(xhci
, "ERROR unknown event type %d\n", trb_type
);
2953 /* Any of the above functions may drop and re-acquire the lock, so check
2954 * to make sure a watchdog timer didn't mark the host as non-responsive.
2956 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
2957 xhci_dbg(xhci
, "xHCI host dying, returning from "
2958 "event handler.\n");
2963 /* Update SW event ring dequeue pointer */
2964 inc_deq(xhci
, xhci
->event_ring
);
2966 /* Are there more items on the event ring? Caller will call us again to
2973 * Update Event Ring Dequeue Pointer:
2974 * - When all events have finished
2975 * - To avoid "Event Ring Full Error" condition
2977 static void xhci_update_erst_dequeue(struct xhci_hcd
*xhci
,
2978 union xhci_trb
*event_ring_deq
)
2983 temp_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
2984 /* If necessary, update the HW's version of the event ring deq ptr. */
2985 if (event_ring_deq
!= xhci
->event_ring
->dequeue
) {
2986 deq
= xhci_trb_virt_to_dma(xhci
->event_ring
->deq_seg
,
2987 xhci
->event_ring
->dequeue
);
2989 xhci_warn(xhci
, "WARN something wrong with SW event ring dequeue ptr\n");
2991 * Per 4.9.4, Software writes to the ERDP register shall
2992 * always advance the Event Ring Dequeue Pointer value.
2994 if ((temp_64
& (u64
) ~ERST_PTR_MASK
) ==
2995 ((u64
) deq
& (u64
) ~ERST_PTR_MASK
))
2998 /* Update HC event ring dequeue pointer */
2999 temp_64
&= ERST_PTR_MASK
;
3000 temp_64
|= ((u64
) deq
& (u64
) ~ERST_PTR_MASK
);
3003 /* Clear the event handler busy flag (RW1C) */
3004 temp_64
|= ERST_EHB
;
3005 xhci_write_64(xhci
, temp_64
, &xhci
->ir_set
->erst_dequeue
);
3009 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
3010 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
3011 * indicators of an event TRB error, but we check the status *first* to be safe.
3013 irqreturn_t
xhci_irq(struct usb_hcd
*hcd
)
3015 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
3016 union xhci_trb
*event_ring_deq
;
3017 irqreturn_t ret
= IRQ_NONE
;
3018 unsigned long flags
;
3023 spin_lock_irqsave(&xhci
->lock
, flags
);
3024 /* Check if the xHC generated the interrupt, or the irq is shared */
3025 status
= readl(&xhci
->op_regs
->status
);
3026 if (status
== ~(u32
)0) {
3032 if (!(status
& STS_EINT
))
3035 if (status
& STS_FATAL
) {
3036 xhci_warn(xhci
, "WARNING: Host System Error\n");
3043 * Clear the op reg interrupt status first,
3044 * so we can receive interrupts from other MSI-X interrupters.
3045 * Write 1 to clear the interrupt status.
3048 writel(status
, &xhci
->op_regs
->status
);
3050 if (!hcd
->msi_enabled
) {
3052 irq_pending
= readl(&xhci
->ir_set
->irq_pending
);
3053 irq_pending
|= IMAN_IP
;
3054 writel(irq_pending
, &xhci
->ir_set
->irq_pending
);
3057 if (xhci
->xhc_state
& XHCI_STATE_DYING
||
3058 xhci
->xhc_state
& XHCI_STATE_HALTED
) {
3059 xhci_dbg(xhci
, "xHCI dying, ignoring interrupt. "
3060 "Shouldn't IRQs be disabled?\n");
3061 /* Clear the event handler busy flag (RW1C);
3062 * the event ring should be empty.
3064 temp_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
3065 xhci_write_64(xhci
, temp_64
| ERST_EHB
,
3066 &xhci
->ir_set
->erst_dequeue
);
3071 event_ring_deq
= xhci
->event_ring
->dequeue
;
3072 /* FIXME this should be a delayed service routine
3073 * that clears the EHB.
3075 while (xhci_handle_event(xhci
) > 0) {
3076 if (event_loop
++ < TRBS_PER_SEGMENT
/ 2)
3078 xhci_update_erst_dequeue(xhci
, event_ring_deq
);
3082 xhci_update_erst_dequeue(xhci
, event_ring_deq
);
3086 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3091 irqreturn_t
xhci_msi_irq(int irq
, void *hcd
)
3093 return xhci_irq(hcd
);
3096 /**** Endpoint Ring Operations ****/
3099 * Generic function for queueing a TRB on a ring.
3100 * The caller must have checked to make sure there's room on the ring.
3102 * @more_trbs_coming: Will you enqueue more TRBs before calling
3103 * prepare_transfer()?
3105 static void queue_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
3106 bool more_trbs_coming
,
3107 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
3109 struct xhci_generic_trb
*trb
;
3111 trb
= &ring
->enqueue
->generic
;
3112 trb
->field
[0] = cpu_to_le32(field1
);
3113 trb
->field
[1] = cpu_to_le32(field2
);
3114 trb
->field
[2] = cpu_to_le32(field3
);
3115 /* make sure TRB is fully written before giving it to the controller */
3117 trb
->field
[3] = cpu_to_le32(field4
);
3119 trace_xhci_queue_trb(ring
, trb
);
3121 inc_enq(xhci
, ring
, more_trbs_coming
);
3125 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
3126 * FIXME allocate segments if the ring is full.
3128 static int prepare_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
3129 u32 ep_state
, unsigned int num_trbs
, gfp_t mem_flags
)
3131 unsigned int num_trbs_needed
;
3132 unsigned int link_trb_count
= 0;
3134 /* Make sure the endpoint has been added to xHC schedule */
3136 case EP_STATE_DISABLED
:
3138 * USB core changed config/interfaces without notifying us,
3139 * or hardware is reporting the wrong state.
3141 xhci_warn(xhci
, "WARN urb submitted to disabled ep\n");
3143 case EP_STATE_ERROR
:
3144 xhci_warn(xhci
, "WARN waiting for error on ep to be cleared\n");
3145 /* FIXME event handling code for error needs to clear it */
3146 /* XXX not sure if this should be -ENOENT or not */
3148 case EP_STATE_HALTED
:
3149 xhci_dbg(xhci
, "WARN halted endpoint, queueing URB anyway.\n");
3151 case EP_STATE_STOPPED
:
3152 case EP_STATE_RUNNING
:
3155 xhci_err(xhci
, "ERROR unknown endpoint state for ep\n");
3157 * FIXME issue Configure Endpoint command to try to get the HC
3158 * back into a known state.
3164 if (room_on_ring(xhci
, ep_ring
, num_trbs
))
3167 if (ep_ring
== xhci
->cmd_ring
) {
3168 xhci_err(xhci
, "Do not support expand command ring\n");
3172 xhci_dbg_trace(xhci
, trace_xhci_dbg_ring_expansion
,
3173 "ERROR no room on ep ring, try ring expansion");
3174 num_trbs_needed
= num_trbs
- ep_ring
->num_trbs_free
;
3175 if (xhci_ring_expansion(xhci
, ep_ring
, num_trbs_needed
,
3177 xhci_err(xhci
, "Ring expansion failed\n");
3182 while (trb_is_link(ep_ring
->enqueue
)) {
3183 /* If we're not dealing with 0.95 hardware or isoc rings
3184 * on AMD 0.96 host, clear the chain bit.
3186 if (!xhci_link_trb_quirk(xhci
) &&
3187 !(ep_ring
->type
== TYPE_ISOC
&&
3188 (xhci
->quirks
& XHCI_AMD_0x96_HOST
)))
3189 ep_ring
->enqueue
->link
.control
&=
3190 cpu_to_le32(~TRB_CHAIN
);
3192 ep_ring
->enqueue
->link
.control
|=
3193 cpu_to_le32(TRB_CHAIN
);
3196 ep_ring
->enqueue
->link
.control
^= cpu_to_le32(TRB_CYCLE
);
3198 /* Toggle the cycle bit after the last ring segment. */
3199 if (link_trb_toggles_cycle(ep_ring
->enqueue
))
3200 ep_ring
->cycle_state
^= 1;
3202 ep_ring
->enq_seg
= ep_ring
->enq_seg
->next
;
3203 ep_ring
->enqueue
= ep_ring
->enq_seg
->trbs
;
3205 /* prevent infinite loop if all first trbs are link trbs */
3206 if (link_trb_count
++ > ep_ring
->num_segs
) {
3207 xhci_warn(xhci
, "Ring is an endless link TRB loop\n");
3212 if (last_trb_on_seg(ep_ring
->enq_seg
, ep_ring
->enqueue
)) {
3213 xhci_warn(xhci
, "Missing link TRB at end of ring segment\n");
3220 static int prepare_transfer(struct xhci_hcd
*xhci
,
3221 struct xhci_virt_device
*xdev
,
3222 unsigned int ep_index
,
3223 unsigned int stream_id
,
3224 unsigned int num_trbs
,
3226 unsigned int td_index
,
3230 struct urb_priv
*urb_priv
;
3232 struct xhci_ring
*ep_ring
;
3233 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
3235 ep_ring
= xhci_triad_to_transfer_ring(xhci
, xdev
->slot_id
, ep_index
,
3238 xhci_dbg(xhci
, "Can't prepare ring for bad stream ID %u\n",
3243 ret
= prepare_ring(xhci
, ep_ring
, GET_EP_CTX_STATE(ep_ctx
),
3244 num_trbs
, mem_flags
);
3248 urb_priv
= urb
->hcpriv
;
3249 td
= &urb_priv
->td
[td_index
];
3251 INIT_LIST_HEAD(&td
->td_list
);
3252 INIT_LIST_HEAD(&td
->cancelled_td_list
);
3254 if (td_index
== 0) {
3255 ret
= usb_hcd_link_urb_to_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
3261 /* Add this TD to the tail of the endpoint ring's TD list */
3262 list_add_tail(&td
->td_list
, &ep_ring
->td_list
);
3263 td
->start_seg
= ep_ring
->enq_seg
;
3264 td
->first_trb
= ep_ring
->enqueue
;
3269 unsigned int count_trbs(u64 addr
, u64 len
)
3271 unsigned int num_trbs
;
3273 num_trbs
= DIV_ROUND_UP(len
+ (addr
& (TRB_MAX_BUFF_SIZE
- 1)),
3281 static inline unsigned int count_trbs_needed(struct urb
*urb
)
3283 return count_trbs(urb
->transfer_dma
, urb
->transfer_buffer_length
);
3286 static unsigned int count_sg_trbs_needed(struct urb
*urb
)
3288 struct scatterlist
*sg
;
3289 unsigned int i
, len
, full_len
, num_trbs
= 0;
3291 full_len
= urb
->transfer_buffer_length
;
3293 for_each_sg(urb
->sg
, sg
, urb
->num_mapped_sgs
, i
) {
3294 len
= sg_dma_len(sg
);
3295 num_trbs
+= count_trbs(sg_dma_address(sg
), len
);
3296 len
= min_t(unsigned int, len
, full_len
);
3305 static unsigned int count_isoc_trbs_needed(struct urb
*urb
, int i
)
3309 addr
= (u64
) (urb
->transfer_dma
+ urb
->iso_frame_desc
[i
].offset
);
3310 len
= urb
->iso_frame_desc
[i
].length
;
3312 return count_trbs(addr
, len
);
3315 static void check_trb_math(struct urb
*urb
, int running_total
)
3317 if (unlikely(running_total
!= urb
->transfer_buffer_length
))
3318 dev_err(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated tx length, "
3319 "queued %#x (%d), asked for %#x (%d)\n",
3321 urb
->ep
->desc
.bEndpointAddress
,
3322 running_total
, running_total
,
3323 urb
->transfer_buffer_length
,
3324 urb
->transfer_buffer_length
);
3327 static void giveback_first_trb(struct xhci_hcd
*xhci
, int slot_id
,
3328 unsigned int ep_index
, unsigned int stream_id
, int start_cycle
,
3329 struct xhci_generic_trb
*start_trb
)
3332 * Pass all the TRBs to the hardware at once and make sure this write
3337 start_trb
->field
[3] |= cpu_to_le32(start_cycle
);
3339 start_trb
->field
[3] &= cpu_to_le32(~TRB_CYCLE
);
3340 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
, stream_id
);
3343 static void check_interval(struct xhci_hcd
*xhci
, struct urb
*urb
,
3344 struct xhci_ep_ctx
*ep_ctx
)
3349 xhci_interval
= EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx
->ep_info
));
3350 ep_interval
= urb
->interval
;
3352 /* Convert to microframes */
3353 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3354 urb
->dev
->speed
== USB_SPEED_FULL
)
3357 /* FIXME change this to a warning and a suggestion to use the new API
3358 * to set the polling interval (once the API is added).
3360 if (xhci_interval
!= ep_interval
) {
3361 dev_dbg_ratelimited(&urb
->dev
->dev
,
3362 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3363 ep_interval
, ep_interval
== 1 ? "" : "s",
3364 xhci_interval
, xhci_interval
== 1 ? "" : "s");
3365 urb
->interval
= xhci_interval
;
3366 /* Convert back to frames for LS/FS devices */
3367 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3368 urb
->dev
->speed
== USB_SPEED_FULL
)
3374 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3375 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3376 * (comprised of sg list entries) can take several service intervals to
3379 int xhci_queue_intr_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3380 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3382 struct xhci_ep_ctx
*ep_ctx
;
3384 ep_ctx
= xhci_get_ep_ctx(xhci
, xhci
->devs
[slot_id
]->out_ctx
, ep_index
);
3385 check_interval(xhci
, urb
, ep_ctx
);
3387 return xhci_queue_bulk_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
3391 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3392 * packets remaining in the TD (*not* including this TRB).
3394 * Total TD packet count = total_packet_count =
3395 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3397 * Packets transferred up to and including this TRB = packets_transferred =
3398 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3400 * TD size = total_packet_count - packets_transferred
3402 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3403 * including this TRB, right shifted by 10
3405 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3406 * This is taken care of in the TRB_TD_SIZE() macro
3408 * The last TRB in a TD must have the TD size set to zero.
3410 static u32
xhci_td_remainder(struct xhci_hcd
*xhci
, int transferred
,
3411 int trb_buff_len
, unsigned int td_total_len
,
3412 struct urb
*urb
, bool more_trbs_coming
)
3414 u32 maxp
, total_packet_count
;
3416 /* MTK xHCI 0.96 contains some features from 1.0 */
3417 if (xhci
->hci_version
< 0x100 && !(xhci
->quirks
& XHCI_MTK_HOST
))
3418 return ((td_total_len
- transferred
) >> 10);
3420 /* One TRB with a zero-length data packet. */
3421 if (!more_trbs_coming
|| (transferred
== 0 && trb_buff_len
== 0) ||
3422 trb_buff_len
== td_total_len
)
3425 /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */
3426 if ((xhci
->quirks
& XHCI_MTK_HOST
) && (xhci
->hci_version
< 0x100))
3429 maxp
= usb_endpoint_maxp(&urb
->ep
->desc
);
3430 total_packet_count
= DIV_ROUND_UP(td_total_len
, maxp
);
3432 /* Queueing functions don't count the current TRB into transferred */
3433 return (total_packet_count
- ((transferred
+ trb_buff_len
) / maxp
));
3437 static int xhci_align_td(struct xhci_hcd
*xhci
, struct urb
*urb
, u32 enqd_len
,
3438 u32
*trb_buff_len
, struct xhci_segment
*seg
)
3440 struct device
*dev
= xhci_to_hcd(xhci
)->self
.controller
;
3441 unsigned int unalign
;
3442 unsigned int max_pkt
;
3446 max_pkt
= usb_endpoint_maxp(&urb
->ep
->desc
);
3447 unalign
= (enqd_len
+ *trb_buff_len
) % max_pkt
;
3449 /* we got lucky, last normal TRB data on segment is packet aligned */
3453 xhci_dbg(xhci
, "Unaligned %d bytes, buff len %d\n",
3454 unalign
, *trb_buff_len
);
3456 /* is the last nornal TRB alignable by splitting it */
3457 if (*trb_buff_len
> unalign
) {
3458 *trb_buff_len
-= unalign
;
3459 xhci_dbg(xhci
, "split align, new buff len %d\n", *trb_buff_len
);
3464 * We want enqd_len + trb_buff_len to sum up to a number aligned to
3465 * number which is divisible by the endpoint's wMaxPacketSize. IOW:
3466 * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0.
3468 new_buff_len
= max_pkt
- (enqd_len
% max_pkt
);
3470 if (new_buff_len
> (urb
->transfer_buffer_length
- enqd_len
))
3471 new_buff_len
= (urb
->transfer_buffer_length
- enqd_len
);
3473 /* create a max max_pkt sized bounce buffer pointed to by last trb */
3474 if (usb_urb_dir_out(urb
)) {
3476 len
= sg_pcopy_to_buffer(urb
->sg
, urb
->num_sgs
,
3477 seg
->bounce_buf
, new_buff_len
, enqd_len
);
3478 if (len
!= new_buff_len
)
3479 xhci_warn(xhci
, "WARN Wrong bounce buffer write length: %zu != %d\n",
3482 memcpy(seg
->bounce_buf
, urb
->transfer_buffer
+ enqd_len
, new_buff_len
);
3485 seg
->bounce_dma
= dma_map_single(dev
, seg
->bounce_buf
,
3486 max_pkt
, DMA_TO_DEVICE
);
3488 seg
->bounce_dma
= dma_map_single(dev
, seg
->bounce_buf
,
3489 max_pkt
, DMA_FROM_DEVICE
);
3492 if (dma_mapping_error(dev
, seg
->bounce_dma
)) {
3493 /* try without aligning. Some host controllers survive */
3494 xhci_warn(xhci
, "Failed mapping bounce buffer, not aligning\n");
3497 *trb_buff_len
= new_buff_len
;
3498 seg
->bounce_len
= new_buff_len
;
3499 seg
->bounce_offs
= enqd_len
;
3501 xhci_dbg(xhci
, "Bounce align, new buff len %d\n", *trb_buff_len
);
3506 /* This is very similar to what ehci-q.c qtd_fill() does */
3507 int xhci_queue_bulk_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3508 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3510 struct xhci_ring
*ring
;
3511 struct urb_priv
*urb_priv
;
3513 struct xhci_generic_trb
*start_trb
;
3514 struct scatterlist
*sg
= NULL
;
3515 bool more_trbs_coming
= true;
3516 bool need_zero_pkt
= false;
3517 bool first_trb
= true;
3518 unsigned int num_trbs
;
3519 unsigned int start_cycle
, num_sgs
= 0;
3520 unsigned int enqd_len
, block_len
, trb_buff_len
, full_len
;
3522 u32 field
, length_field
, remainder
;
3523 u64 addr
, send_addr
;
3525 ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
3529 full_len
= urb
->transfer_buffer_length
;
3530 /* If we have scatter/gather list, we use it. */
3531 if (urb
->num_sgs
&& !(urb
->transfer_flags
& URB_DMA_MAP_SINGLE
)) {
3532 num_sgs
= urb
->num_mapped_sgs
;
3534 addr
= (u64
) sg_dma_address(sg
);
3535 block_len
= sg_dma_len(sg
);
3536 num_trbs
= count_sg_trbs_needed(urb
);
3538 num_trbs
= count_trbs_needed(urb
);
3539 addr
= (u64
) urb
->transfer_dma
;
3540 block_len
= full_len
;
3542 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
3543 ep_index
, urb
->stream_id
,
3544 num_trbs
, urb
, 0, mem_flags
);
3545 if (unlikely(ret
< 0))
3548 urb_priv
= urb
->hcpriv
;
3550 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3551 if (urb
->transfer_flags
& URB_ZERO_PACKET
&& urb_priv
->num_tds
> 1)
3552 need_zero_pkt
= true;
3554 td
= &urb_priv
->td
[0];
3557 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3558 * until we've finished creating all the other TRBs. The ring's cycle
3559 * state may change as we enqueue the other TRBs, so save it too.
3561 start_trb
= &ring
->enqueue
->generic
;
3562 start_cycle
= ring
->cycle_state
;
3565 /* Queue the TRBs, even if they are zero-length */
3566 for (enqd_len
= 0; first_trb
|| enqd_len
< full_len
;
3567 enqd_len
+= trb_buff_len
) {
3568 field
= TRB_TYPE(TRB_NORMAL
);
3570 /* TRB buffer should not cross 64KB boundaries */
3571 trb_buff_len
= TRB_BUFF_LEN_UP_TO_BOUNDARY(addr
);
3572 trb_buff_len
= min_t(unsigned int, trb_buff_len
, block_len
);
3574 if (enqd_len
+ trb_buff_len
> full_len
)
3575 trb_buff_len
= full_len
- enqd_len
;
3577 /* Don't change the cycle bit of the first TRB until later */
3580 if (start_cycle
== 0)
3583 field
|= ring
->cycle_state
;
3585 /* Chain all the TRBs together; clear the chain bit in the last
3586 * TRB to indicate it's the last TRB in the chain.
3588 if (enqd_len
+ trb_buff_len
< full_len
) {
3590 if (trb_is_link(ring
->enqueue
+ 1)) {
3591 if (xhci_align_td(xhci
, urb
, enqd_len
,
3594 send_addr
= ring
->enq_seg
->bounce_dma
;
3595 /* assuming TD won't span 2 segs */
3596 td
->bounce_seg
= ring
->enq_seg
;
3600 if (enqd_len
+ trb_buff_len
>= full_len
) {
3601 field
&= ~TRB_CHAIN
;
3603 more_trbs_coming
= false;
3604 td
->last_trb
= ring
->enqueue
;
3605 td
->last_trb_seg
= ring
->enq_seg
;
3606 if (xhci_urb_suitable_for_idt(urb
)) {
3607 memcpy(&send_addr
, urb
->transfer_buffer
,
3609 le64_to_cpus(&send_addr
);
3614 /* Only set interrupt on short packet for IN endpoints */
3615 if (usb_urb_dir_in(urb
))
3618 /* Set the TRB length, TD size, and interrupter fields. */
3619 remainder
= xhci_td_remainder(xhci
, enqd_len
, trb_buff_len
,
3620 full_len
, urb
, more_trbs_coming
);
3622 length_field
= TRB_LEN(trb_buff_len
) |
3623 TRB_TD_SIZE(remainder
) |
3626 queue_trb(xhci
, ring
, more_trbs_coming
| need_zero_pkt
,
3627 lower_32_bits(send_addr
),
3628 upper_32_bits(send_addr
),
3632 addr
+= trb_buff_len
;
3633 sent_len
= trb_buff_len
;
3635 while (sg
&& sent_len
>= block_len
) {
3638 sent_len
-= block_len
;
3640 if (num_sgs
!= 0 && sg
) {
3641 block_len
= sg_dma_len(sg
);
3642 addr
= (u64
) sg_dma_address(sg
);
3646 block_len
-= sent_len
;
3650 if (need_zero_pkt
) {
3651 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
3652 ep_index
, urb
->stream_id
,
3653 1, urb
, 1, mem_flags
);
3654 urb_priv
->td
[1].last_trb
= ring
->enqueue
;
3655 urb_priv
->td
[1].last_trb_seg
= ring
->enq_seg
;
3656 field
= TRB_TYPE(TRB_NORMAL
) | ring
->cycle_state
| TRB_IOC
;
3657 queue_trb(xhci
, ring
, 0, 0, 0, TRB_INTR_TARGET(0), field
);
3658 urb_priv
->td
[1].num_trbs
++;
3661 check_trb_math(urb
, enqd_len
);
3662 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
3663 start_cycle
, start_trb
);
3667 /* Caller must have locked xhci->lock */
3668 int xhci_queue_ctrl_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3669 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3671 struct xhci_ring
*ep_ring
;
3674 struct usb_ctrlrequest
*setup
;
3675 struct xhci_generic_trb
*start_trb
;
3678 struct urb_priv
*urb_priv
;
3681 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
3686 * Need to copy setup packet into setup TRB, so we can't use the setup
3689 if (!urb
->setup_packet
)
3692 /* 1 TRB for setup, 1 for status */
3695 * Don't need to check if we need additional event data and normal TRBs,
3696 * since data in control transfers will never get bigger than 16MB
3697 * XXX: can we get a buffer that crosses 64KB boundaries?
3699 if (urb
->transfer_buffer_length
> 0)
3701 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
3702 ep_index
, urb
->stream_id
,
3703 num_trbs
, urb
, 0, mem_flags
);
3707 urb_priv
= urb
->hcpriv
;
3708 td
= &urb_priv
->td
[0];
3709 td
->num_trbs
= num_trbs
;
3712 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3713 * until we've finished creating all the other TRBs. The ring's cycle
3714 * state may change as we enqueue the other TRBs, so save it too.
3716 start_trb
= &ep_ring
->enqueue
->generic
;
3717 start_cycle
= ep_ring
->cycle_state
;
3719 /* Queue setup TRB - see section 6.4.1.2.1 */
3720 /* FIXME better way to translate setup_packet into two u32 fields? */
3721 setup
= (struct usb_ctrlrequest
*) urb
->setup_packet
;
3723 field
|= TRB_IDT
| TRB_TYPE(TRB_SETUP
);
3724 if (start_cycle
== 0)
3727 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3728 if ((xhci
->hci_version
>= 0x100) || (xhci
->quirks
& XHCI_MTK_HOST
)) {
3729 if (urb
->transfer_buffer_length
> 0) {
3730 if (setup
->bRequestType
& USB_DIR_IN
)
3731 field
|= TRB_TX_TYPE(TRB_DATA_IN
);
3733 field
|= TRB_TX_TYPE(TRB_DATA_OUT
);
3737 queue_trb(xhci
, ep_ring
, true,
3738 setup
->bRequestType
| setup
->bRequest
<< 8 | le16_to_cpu(setup
->wValue
) << 16,
3739 le16_to_cpu(setup
->wIndex
) | le16_to_cpu(setup
->wLength
) << 16,
3740 TRB_LEN(8) | TRB_INTR_TARGET(0),
3741 /* Immediate data in pointer */
3744 /* If there's data, queue data TRBs */
3745 /* Only set interrupt on short packet for IN endpoints */
3746 if (usb_urb_dir_in(urb
))
3747 field
= TRB_ISP
| TRB_TYPE(TRB_DATA
);
3749 field
= TRB_TYPE(TRB_DATA
);
3751 if (urb
->transfer_buffer_length
> 0) {
3752 u32 length_field
, remainder
;
3755 if (xhci_urb_suitable_for_idt(urb
)) {
3756 memcpy(&addr
, urb
->transfer_buffer
,
3757 urb
->transfer_buffer_length
);
3758 le64_to_cpus(&addr
);
3761 addr
= (u64
) urb
->transfer_dma
;
3764 remainder
= xhci_td_remainder(xhci
, 0,
3765 urb
->transfer_buffer_length
,
3766 urb
->transfer_buffer_length
,
3768 length_field
= TRB_LEN(urb
->transfer_buffer_length
) |
3769 TRB_TD_SIZE(remainder
) |
3771 if (setup
->bRequestType
& USB_DIR_IN
)
3772 field
|= TRB_DIR_IN
;
3773 queue_trb(xhci
, ep_ring
, true,
3774 lower_32_bits(addr
),
3775 upper_32_bits(addr
),
3777 field
| ep_ring
->cycle_state
);
3780 /* Save the DMA address of the last TRB in the TD */
3781 td
->last_trb
= ep_ring
->enqueue
;
3782 td
->last_trb_seg
= ep_ring
->enq_seg
;
3784 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3785 /* If the device sent data, the status stage is an OUT transfer */
3786 if (urb
->transfer_buffer_length
> 0 && setup
->bRequestType
& USB_DIR_IN
)
3790 queue_trb(xhci
, ep_ring
, false,
3794 /* Event on completion */
3795 field
| TRB_IOC
| TRB_TYPE(TRB_STATUS
) | ep_ring
->cycle_state
);
3797 giveback_first_trb(xhci
, slot_id
, ep_index
, 0,
3798 start_cycle
, start_trb
);
3803 * The transfer burst count field of the isochronous TRB defines the number of
3804 * bursts that are required to move all packets in this TD. Only SuperSpeed
3805 * devices can burst up to bMaxBurst number of packets per service interval.
3806 * This field is zero based, meaning a value of zero in the field means one
3807 * burst. Basically, for everything but SuperSpeed devices, this field will be
3808 * zero. Only xHCI 1.0 host controllers support this field.
3810 static unsigned int xhci_get_burst_count(struct xhci_hcd
*xhci
,
3811 struct urb
*urb
, unsigned int total_packet_count
)
3813 unsigned int max_burst
;
3815 if (xhci
->hci_version
< 0x100 || urb
->dev
->speed
< USB_SPEED_SUPER
)
3818 max_burst
= urb
->ep
->ss_ep_comp
.bMaxBurst
;
3819 return DIV_ROUND_UP(total_packet_count
, max_burst
+ 1) - 1;
3823 * Returns the number of packets in the last "burst" of packets. This field is
3824 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3825 * the last burst packet count is equal to the total number of packets in the
3826 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3827 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3828 * contain 1 to (bMaxBurst + 1) packets.
3830 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd
*xhci
,
3831 struct urb
*urb
, unsigned int total_packet_count
)
3833 unsigned int max_burst
;
3834 unsigned int residue
;
3836 if (xhci
->hci_version
< 0x100)
3839 if (urb
->dev
->speed
>= USB_SPEED_SUPER
) {
3840 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3841 max_burst
= urb
->ep
->ss_ep_comp
.bMaxBurst
;
3842 residue
= total_packet_count
% (max_burst
+ 1);
3843 /* If residue is zero, the last burst contains (max_burst + 1)
3844 * number of packets, but the TLBPC field is zero-based.
3850 if (total_packet_count
== 0)
3852 return total_packet_count
- 1;
3856 * Calculates Frame ID field of the isochronous TRB identifies the
3857 * target frame that the Interval associated with this Isochronous
3858 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3860 * Returns actual frame id on success, negative value on error.
3862 static int xhci_get_isoc_frame_id(struct xhci_hcd
*xhci
,
3863 struct urb
*urb
, int index
)
3865 int start_frame
, ist
, ret
= 0;
3866 int start_frame_id
, end_frame_id
, current_frame_id
;
3868 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3869 urb
->dev
->speed
== USB_SPEED_FULL
)
3870 start_frame
= urb
->start_frame
+ index
* urb
->interval
;
3872 start_frame
= (urb
->start_frame
+ index
* urb
->interval
) >> 3;
3874 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3876 * If bit [3] of IST is cleared to '0', software can add a TRB no
3877 * later than IST[2:0] Microframes before that TRB is scheduled to
3879 * If bit [3] of IST is set to '1', software can add a TRB no later
3880 * than IST[2:0] Frames before that TRB is scheduled to be executed.
3882 ist
= HCS_IST(xhci
->hcs_params2
) & 0x7;
3883 if (HCS_IST(xhci
->hcs_params2
) & (1 << 3))
3886 /* Software shall not schedule an Isoch TD with a Frame ID value that
3887 * is less than the Start Frame ID or greater than the End Frame ID,
3890 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3891 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3893 * Both the End Frame ID and Start Frame ID values are calculated
3894 * in microframes. When software determines the valid Frame ID value;
3895 * The End Frame ID value should be rounded down to the nearest Frame
3896 * boundary, and the Start Frame ID value should be rounded up to the
3897 * nearest Frame boundary.
3899 current_frame_id
= readl(&xhci
->run_regs
->microframe_index
);
3900 start_frame_id
= roundup(current_frame_id
+ ist
+ 1, 8);
3901 end_frame_id
= rounddown(current_frame_id
+ 895 * 8, 8);
3903 start_frame
&= 0x7ff;
3904 start_frame_id
= (start_frame_id
>> 3) & 0x7ff;
3905 end_frame_id
= (end_frame_id
>> 3) & 0x7ff;
3907 xhci_dbg(xhci
, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3908 __func__
, index
, readl(&xhci
->run_regs
->microframe_index
),
3909 start_frame_id
, end_frame_id
, start_frame
);
3911 if (start_frame_id
< end_frame_id
) {
3912 if (start_frame
> end_frame_id
||
3913 start_frame
< start_frame_id
)
3915 } else if (start_frame_id
> end_frame_id
) {
3916 if ((start_frame
> end_frame_id
&&
3917 start_frame
< start_frame_id
))
3924 if (ret
== -EINVAL
|| start_frame
== start_frame_id
) {
3925 start_frame
= start_frame_id
+ 1;
3926 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3927 urb
->dev
->speed
== USB_SPEED_FULL
)
3928 urb
->start_frame
= start_frame
;
3930 urb
->start_frame
= start_frame
<< 3;
3936 xhci_warn(xhci
, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
3937 start_frame
, current_frame_id
, index
,
3938 start_frame_id
, end_frame_id
);
3939 xhci_warn(xhci
, "Ignore frame ID field, use SIA bit instead\n");
3946 /* Check if we should generate event interrupt for a TD in an isoc URB */
3947 static bool trb_block_event_intr(struct xhci_hcd
*xhci
, int num_tds
, int i
)
3949 if (xhci
->hci_version
< 0x100)
3951 /* always generate an event interrupt for the last TD */
3952 if (i
== num_tds
- 1)
3955 * If AVOID_BEI is set the host handles full event rings poorly,
3956 * generate an event at least every 8th TD to clear the event ring
3958 if (i
&& xhci
->quirks
& XHCI_AVOID_BEI
)
3964 /* This is for isoc transfer */
3965 static int xhci_queue_isoc_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3966 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3968 struct xhci_ring
*ep_ring
;
3969 struct urb_priv
*urb_priv
;
3971 int num_tds
, trbs_per_td
;
3972 struct xhci_generic_trb
*start_trb
;
3975 u32 field
, length_field
;
3976 int running_total
, trb_buff_len
, td_len
, td_remain_len
, ret
;
3977 u64 start_addr
, addr
;
3979 bool more_trbs_coming
;
3980 struct xhci_virt_ep
*xep
;
3983 xep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
3984 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
3986 num_tds
= urb
->number_of_packets
;
3988 xhci_dbg(xhci
, "Isoc URB with zero packets?\n");
3991 start_addr
= (u64
) urb
->transfer_dma
;
3992 start_trb
= &ep_ring
->enqueue
->generic
;
3993 start_cycle
= ep_ring
->cycle_state
;
3995 urb_priv
= urb
->hcpriv
;
3996 /* Queue the TRBs for each TD, even if they are zero-length */
3997 for (i
= 0; i
< num_tds
; i
++) {
3998 unsigned int total_pkt_count
, max_pkt
;
3999 unsigned int burst_count
, last_burst_pkt_count
;
4004 addr
= start_addr
+ urb
->iso_frame_desc
[i
].offset
;
4005 td_len
= urb
->iso_frame_desc
[i
].length
;
4006 td_remain_len
= td_len
;
4007 max_pkt
= usb_endpoint_maxp(&urb
->ep
->desc
);
4008 total_pkt_count
= DIV_ROUND_UP(td_len
, max_pkt
);
4010 /* A zero-length transfer still involves at least one packet. */
4011 if (total_pkt_count
== 0)
4013 burst_count
= xhci_get_burst_count(xhci
, urb
, total_pkt_count
);
4014 last_burst_pkt_count
= xhci_get_last_burst_packet_count(xhci
,
4015 urb
, total_pkt_count
);
4017 trbs_per_td
= count_isoc_trbs_needed(urb
, i
);
4019 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
], ep_index
,
4020 urb
->stream_id
, trbs_per_td
, urb
, i
, mem_flags
);
4026 td
= &urb_priv
->td
[i
];
4027 td
->num_trbs
= trbs_per_td
;
4028 /* use SIA as default, if frame id is used overwrite it */
4029 sia_frame_id
= TRB_SIA
;
4030 if (!(urb
->transfer_flags
& URB_ISO_ASAP
) &&
4031 HCC_CFC(xhci
->hcc_params
)) {
4032 frame_id
= xhci_get_isoc_frame_id(xhci
, urb
, i
);
4034 sia_frame_id
= TRB_FRAME_ID(frame_id
);
4037 * Set isoc specific data for the first TRB in a TD.
4038 * Prevent HW from getting the TRBs by keeping the cycle state
4039 * inverted in the first TDs isoc TRB.
4041 field
= TRB_TYPE(TRB_ISOC
) |
4042 TRB_TLBPC(last_burst_pkt_count
) |
4044 (i
? ep_ring
->cycle_state
: !start_cycle
);
4046 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
4047 if (!xep
->use_extended_tbc
)
4048 field
|= TRB_TBC(burst_count
);
4050 /* fill the rest of the TRB fields, and remaining normal TRBs */
4051 for (j
= 0; j
< trbs_per_td
; j
++) {
4054 /* only first TRB is isoc, overwrite otherwise */
4056 field
= TRB_TYPE(TRB_NORMAL
) |
4057 ep_ring
->cycle_state
;
4059 /* Only set interrupt on short packet for IN EPs */
4060 if (usb_urb_dir_in(urb
))
4063 /* Set the chain bit for all except the last TRB */
4064 if (j
< trbs_per_td
- 1) {
4065 more_trbs_coming
= true;
4068 more_trbs_coming
= false;
4069 td
->last_trb
= ep_ring
->enqueue
;
4070 td
->last_trb_seg
= ep_ring
->enq_seg
;
4072 if (trb_block_event_intr(xhci
, num_tds
, i
))
4075 /* Calculate TRB length */
4076 trb_buff_len
= TRB_BUFF_LEN_UP_TO_BOUNDARY(addr
);
4077 if (trb_buff_len
> td_remain_len
)
4078 trb_buff_len
= td_remain_len
;
4080 /* Set the TRB length, TD size, & interrupter fields. */
4081 remainder
= xhci_td_remainder(xhci
, running_total
,
4082 trb_buff_len
, td_len
,
4083 urb
, more_trbs_coming
);
4085 length_field
= TRB_LEN(trb_buff_len
) |
4088 /* xhci 1.1 with ETE uses TD Size field for TBC */
4089 if (first_trb
&& xep
->use_extended_tbc
)
4090 length_field
|= TRB_TD_SIZE_TBC(burst_count
);
4092 length_field
|= TRB_TD_SIZE(remainder
);
4095 queue_trb(xhci
, ep_ring
, more_trbs_coming
,
4096 lower_32_bits(addr
),
4097 upper_32_bits(addr
),
4100 running_total
+= trb_buff_len
;
4102 addr
+= trb_buff_len
;
4103 td_remain_len
-= trb_buff_len
;
4106 /* Check TD length */
4107 if (running_total
!= td_len
) {
4108 xhci_err(xhci
, "ISOC TD length unmatch\n");
4114 /* store the next frame id */
4115 if (HCC_CFC(xhci
->hcc_params
))
4116 xep
->next_frame_id
= urb
->start_frame
+ num_tds
* urb
->interval
;
4118 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
== 0) {
4119 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
4120 usb_amd_quirk_pll_disable();
4122 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
++;
4124 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
4125 start_cycle
, start_trb
);
4128 /* Clean up a partially enqueued isoc transfer. */
4130 for (i
--; i
>= 0; i
--)
4131 list_del_init(&urb_priv
->td
[i
].td_list
);
4133 /* Use the first TD as a temporary variable to turn the TDs we've queued
4134 * into No-ops with a software-owned cycle bit. That way the hardware
4135 * won't accidentally start executing bogus TDs when we partially
4136 * overwrite them. td->first_trb and td->start_seg are already set.
4138 urb_priv
->td
[0].last_trb
= ep_ring
->enqueue
;
4139 /* Every TRB except the first & last will have its cycle bit flipped. */
4140 td_to_noop(xhci
, ep_ring
, &urb_priv
->td
[0], true);
4142 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
4143 ep_ring
->enqueue
= urb_priv
->td
[0].first_trb
;
4144 ep_ring
->enq_seg
= urb_priv
->td
[0].start_seg
;
4145 ep_ring
->cycle_state
= start_cycle
;
4146 ep_ring
->num_trbs_free
= ep_ring
->num_trbs_free_temp
;
4147 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
4152 * Check transfer ring to guarantee there is enough room for the urb.
4153 * Update ISO URB start_frame and interval.
4154 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
4155 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
4156 * Contiguous Frame ID is not supported by HC.
4158 int xhci_queue_isoc_tx_prepare(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
4159 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
4161 struct xhci_virt_device
*xdev
;
4162 struct xhci_ring
*ep_ring
;
4163 struct xhci_ep_ctx
*ep_ctx
;
4165 int num_tds
, num_trbs
, i
;
4167 struct xhci_virt_ep
*xep
;
4170 xdev
= xhci
->devs
[slot_id
];
4171 xep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
4172 ep_ring
= xdev
->eps
[ep_index
].ring
;
4173 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
4176 num_tds
= urb
->number_of_packets
;
4177 for (i
= 0; i
< num_tds
; i
++)
4178 num_trbs
+= count_isoc_trbs_needed(urb
, i
);
4180 /* Check the ring to guarantee there is enough room for the whole urb.
4181 * Do not insert any td of the urb to the ring if the check failed.
4183 ret
= prepare_ring(xhci
, ep_ring
, GET_EP_CTX_STATE(ep_ctx
),
4184 num_trbs
, mem_flags
);
4189 * Check interval value. This should be done before we start to
4190 * calculate the start frame value.
4192 check_interval(xhci
, urb
, ep_ctx
);
4194 /* Calculate the start frame and put it in urb->start_frame. */
4195 if (HCC_CFC(xhci
->hcc_params
) && !list_empty(&ep_ring
->td_list
)) {
4196 if (GET_EP_CTX_STATE(ep_ctx
) == EP_STATE_RUNNING
) {
4197 urb
->start_frame
= xep
->next_frame_id
;
4198 goto skip_start_over
;
4202 start_frame
= readl(&xhci
->run_regs
->microframe_index
);
4203 start_frame
&= 0x3fff;
4205 * Round up to the next frame and consider the time before trb really
4206 * gets scheduled by hardare.
4208 ist
= HCS_IST(xhci
->hcs_params2
) & 0x7;
4209 if (HCS_IST(xhci
->hcs_params2
) & (1 << 3))
4211 start_frame
+= ist
+ XHCI_CFC_DELAY
;
4212 start_frame
= roundup(start_frame
, 8);
4215 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
4216 * is greate than 8 microframes.
4218 if (urb
->dev
->speed
== USB_SPEED_LOW
||
4219 urb
->dev
->speed
== USB_SPEED_FULL
) {
4220 start_frame
= roundup(start_frame
, urb
->interval
<< 3);
4221 urb
->start_frame
= start_frame
>> 3;
4223 start_frame
= roundup(start_frame
, urb
->interval
);
4224 urb
->start_frame
= start_frame
;
4228 ep_ring
->num_trbs_free_temp
= ep_ring
->num_trbs_free
;
4230 return xhci_queue_isoc_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
4233 /**** Command Ring Operations ****/
4235 /* Generic function for queueing a command TRB on the command ring.
4236 * Check to make sure there's room on the command ring for one command TRB.
4237 * Also check that there's room reserved for commands that must not fail.
4238 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
4239 * then only check for the number of reserved spots.
4240 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
4241 * because the command event handler may want to resubmit a failed command.
4243 static int queue_command(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
4244 u32 field1
, u32 field2
,
4245 u32 field3
, u32 field4
, bool command_must_succeed
)
4247 int reserved_trbs
= xhci
->cmd_ring_reserved_trbs
;
4250 if ((xhci
->xhc_state
& XHCI_STATE_DYING
) ||
4251 (xhci
->xhc_state
& XHCI_STATE_HALTED
)) {
4252 xhci_dbg(xhci
, "xHCI dying or halted, can't queue_command\n");
4256 if (!command_must_succeed
)
4259 ret
= prepare_ring(xhci
, xhci
->cmd_ring
, EP_STATE_RUNNING
,
4260 reserved_trbs
, GFP_ATOMIC
);
4262 xhci_err(xhci
, "ERR: No room for command on command ring\n");
4263 if (command_must_succeed
)
4264 xhci_err(xhci
, "ERR: Reserved TRB counting for "
4265 "unfailable commands failed.\n");
4269 cmd
->command_trb
= xhci
->cmd_ring
->enqueue
;
4271 /* if there are no other commands queued we start the timeout timer */
4272 if (list_empty(&xhci
->cmd_list
)) {
4273 xhci
->current_cmd
= cmd
;
4274 xhci_mod_cmd_timer(xhci
, XHCI_CMD_DEFAULT_TIMEOUT
);
4277 list_add_tail(&cmd
->cmd_list
, &xhci
->cmd_list
);
4279 queue_trb(xhci
, xhci
->cmd_ring
, false, field1
, field2
, field3
,
4280 field4
| xhci
->cmd_ring
->cycle_state
);
4284 /* Queue a slot enable or disable request on the command ring */
4285 int xhci_queue_slot_control(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
4286 u32 trb_type
, u32 slot_id
)
4288 return queue_command(xhci
, cmd
, 0, 0, 0,
4289 TRB_TYPE(trb_type
) | SLOT_ID_FOR_TRB(slot_id
), false);
4292 /* Queue an address device command TRB */
4293 int xhci_queue_address_device(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
4294 dma_addr_t in_ctx_ptr
, u32 slot_id
, enum xhci_setup_dev setup
)
4296 return queue_command(xhci
, cmd
, lower_32_bits(in_ctx_ptr
),
4297 upper_32_bits(in_ctx_ptr
), 0,
4298 TRB_TYPE(TRB_ADDR_DEV
) | SLOT_ID_FOR_TRB(slot_id
)
4299 | (setup
== SETUP_CONTEXT_ONLY
? TRB_BSR
: 0), false);
4302 int xhci_queue_vendor_command(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
4303 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
4305 return queue_command(xhci
, cmd
, field1
, field2
, field3
, field4
, false);
4308 /* Queue a reset device command TRB */
4309 int xhci_queue_reset_device(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
4312 return queue_command(xhci
, cmd
, 0, 0, 0,
4313 TRB_TYPE(TRB_RESET_DEV
) | SLOT_ID_FOR_TRB(slot_id
),
4317 /* Queue a configure endpoint command TRB */
4318 int xhci_queue_configure_endpoint(struct xhci_hcd
*xhci
,
4319 struct xhci_command
*cmd
, dma_addr_t in_ctx_ptr
,
4320 u32 slot_id
, bool command_must_succeed
)
4322 return queue_command(xhci
, cmd
, lower_32_bits(in_ctx_ptr
),
4323 upper_32_bits(in_ctx_ptr
), 0,
4324 TRB_TYPE(TRB_CONFIG_EP
) | SLOT_ID_FOR_TRB(slot_id
),
4325 command_must_succeed
);
4328 /* Queue an evaluate context command TRB */
4329 int xhci_queue_evaluate_context(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
4330 dma_addr_t in_ctx_ptr
, u32 slot_id
, bool command_must_succeed
)
4332 return queue_command(xhci
, cmd
, lower_32_bits(in_ctx_ptr
),
4333 upper_32_bits(in_ctx_ptr
), 0,
4334 TRB_TYPE(TRB_EVAL_CONTEXT
) | SLOT_ID_FOR_TRB(slot_id
),
4335 command_must_succeed
);
4339 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4340 * activity on an endpoint that is about to be suspended.
4342 int xhci_queue_stop_endpoint(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
4343 int slot_id
, unsigned int ep_index
, int suspend
)
4345 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
4346 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
4347 u32 type
= TRB_TYPE(TRB_STOP_RING
);
4348 u32 trb_suspend
= SUSPEND_PORT_FOR_TRB(suspend
);
4350 return queue_command(xhci
, cmd
, 0, 0, 0,
4351 trb_slot_id
| trb_ep_index
| type
| trb_suspend
, false);
4354 int xhci_queue_reset_ep(struct xhci_hcd
*xhci
, struct xhci_command
*cmd
,
4355 int slot_id
, unsigned int ep_index
,
4356 enum xhci_ep_reset_type reset_type
)
4358 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
4359 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
4360 u32 type
= TRB_TYPE(TRB_RESET_EP
);
4362 if (reset_type
== EP_SOFT_RESET
)
4365 return queue_command(xhci
, cmd
, 0, 0, 0,
4366 trb_slot_id
| trb_ep_index
| type
, false);