2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/pci.h>
24 #include <linux/irq.h>
25 #include <linux/log2.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/slab.h>
29 #include <linux/dmi.h>
30 #include <linux/dma-mapping.h>
33 #include "xhci-trace.h"
36 #define DRIVER_AUTHOR "Sarah Sharp"
37 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
39 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
41 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
42 static int link_quirk
;
43 module_param(link_quirk
, int, S_IRUGO
| S_IWUSR
);
44 MODULE_PARM_DESC(link_quirk
, "Don't clear the chain bit on a link TRB");
46 static unsigned int quirks
;
47 module_param(quirks
, uint
, S_IRUGO
);
48 MODULE_PARM_DESC(quirks
, "Bit flags for quirks to be enabled as default");
50 /* TODO: copied from ehci-hcd.c - can this be refactored? */
52 * xhci_handshake - spin reading hc until handshake completes or fails
53 * @ptr: address of hc register to be read
54 * @mask: bits to look at in result of read
55 * @done: value of those bits when handshake succeeds
56 * @usec: timeout in microseconds
58 * Returns negative errno, or zero on success
60 * Success happens when the "mask" bits have the specified value (hardware
61 * handshake done). There are two failure modes: "usec" have passed (major
62 * hardware flakeout), or the register reads as all-ones (hardware removed).
64 int xhci_handshake(void __iomem
*ptr
, u32 mask
, u32 done
, int usec
)
70 if (result
== ~(u32
)0) /* card removed */
82 * Disable interrupts and begin the xHCI halting process.
84 void xhci_quiesce(struct xhci_hcd
*xhci
)
91 halted
= readl(&xhci
->op_regs
->status
) & STS_HALT
;
95 cmd
= readl(&xhci
->op_regs
->command
);
97 writel(cmd
, &xhci
->op_regs
->command
);
101 * Force HC into halt state.
103 * Disable any IRQs and clear the run/stop bit.
104 * HC will complete any current and actively pipelined transactions, and
105 * should halt within 16 ms of the run/stop bit being cleared.
106 * Read HC Halted bit in the status register to see when the HC is finished.
108 int xhci_halt(struct xhci_hcd
*xhci
)
111 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "// Halt the HC");
114 ret
= xhci_handshake(&xhci
->op_regs
->status
,
115 STS_HALT
, STS_HALT
, XHCI_MAX_HALT_USEC
);
117 xhci_warn(xhci
, "Host halt failed, %d\n", ret
);
120 xhci
->xhc_state
|= XHCI_STATE_HALTED
;
121 xhci
->cmd_ring_state
= CMD_RING_STATE_STOPPED
;
126 * Set the run bit and wait for the host to be running.
128 static int xhci_start(struct xhci_hcd
*xhci
)
133 temp
= readl(&xhci
->op_regs
->command
);
135 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "// Turn on HC, cmd = 0x%x.",
137 writel(temp
, &xhci
->op_regs
->command
);
140 * Wait for the HCHalted Status bit to be 0 to indicate the host is
143 ret
= xhci_handshake(&xhci
->op_regs
->status
,
144 STS_HALT
, 0, XHCI_MAX_HALT_USEC
);
145 if (ret
== -ETIMEDOUT
)
146 xhci_err(xhci
, "Host took too long to start, "
147 "waited %u microseconds.\n",
150 /* clear state flags. Including dying, halted or removing */
159 * This resets pipelines, timers, counters, state machines, etc.
160 * Transactions will be terminated immediately, and operational registers
161 * will be set to their defaults.
163 int xhci_reset(struct xhci_hcd
*xhci
)
169 state
= readl(&xhci
->op_regs
->status
);
171 if (state
== ~(u32
)0) {
172 xhci_warn(xhci
, "Host not accessible, reset failed.\n");
176 if ((state
& STS_HALT
) == 0) {
177 xhci_warn(xhci
, "Host controller not halted, aborting reset.\n");
181 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "// Reset the HC");
182 command
= readl(&xhci
->op_regs
->command
);
183 command
|= CMD_RESET
;
184 writel(command
, &xhci
->op_regs
->command
);
186 /* Existing Intel xHCI controllers require a delay of 1 mS,
187 * after setting the CMD_RESET bit, and before accessing any
188 * HC registers. This allows the HC to complete the
189 * reset operation and be ready for HC register access.
190 * Without this delay, the subsequent HC register access,
191 * may result in a system hang very rarely.
193 if (xhci
->quirks
& XHCI_INTEL_HOST
)
196 ret
= xhci_handshake(&xhci
->op_regs
->command
,
197 CMD_RESET
, 0, 10 * 1000 * 1000);
201 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
202 "Wait for controller to be ready for doorbell rings");
204 * xHCI cannot write to any doorbells or operational registers other
205 * than status until the "Controller Not Ready" flag is cleared.
207 ret
= xhci_handshake(&xhci
->op_regs
->status
,
208 STS_CNR
, 0, 10 * 1000 * 1000);
210 for (i
= 0; i
< 2; i
++) {
211 xhci
->bus_state
[i
].port_c_suspend
= 0;
212 xhci
->bus_state
[i
].suspended_ports
= 0;
213 xhci
->bus_state
[i
].resuming_ports
= 0;
220 static int xhci_free_msi(struct xhci_hcd
*xhci
)
224 if (!xhci
->msix_entries
)
227 for (i
= 0; i
< xhci
->msix_count
; i
++)
228 if (xhci
->msix_entries
[i
].vector
)
229 free_irq(xhci
->msix_entries
[i
].vector
,
237 static int xhci_setup_msi(struct xhci_hcd
*xhci
)
240 struct pci_dev
*pdev
= to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
);
242 ret
= pci_enable_msi(pdev
);
244 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
245 "failed to allocate MSI entry");
249 ret
= request_irq(pdev
->irq
, xhci_msi_irq
,
250 0, "xhci_hcd", xhci_to_hcd(xhci
));
252 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
253 "disable MSI interrupt");
254 pci_disable_msi(pdev
);
262 * free all IRQs request
264 static void xhci_free_irq(struct xhci_hcd
*xhci
)
266 struct pci_dev
*pdev
= to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
);
269 /* return if using legacy interrupt */
270 if (xhci_to_hcd(xhci
)->irq
> 0)
273 ret
= xhci_free_msi(xhci
);
277 free_irq(pdev
->irq
, xhci_to_hcd(xhci
));
285 static int xhci_setup_msix(struct xhci_hcd
*xhci
)
288 struct usb_hcd
*hcd
= xhci_to_hcd(xhci
);
289 struct pci_dev
*pdev
= to_pci_dev(hcd
->self
.controller
);
292 * calculate number of msi-x vectors supported.
293 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
294 * with max number of interrupters based on the xhci HCSPARAMS1.
295 * - num_online_cpus: maximum msi-x vectors per CPUs core.
296 * Add additional 1 vector to ensure always available interrupt.
298 xhci
->msix_count
= min(num_online_cpus() + 1,
299 HCS_MAX_INTRS(xhci
->hcs_params1
));
302 kmalloc((sizeof(struct msix_entry
))*xhci
->msix_count
,
304 if (!xhci
->msix_entries
)
307 for (i
= 0; i
< xhci
->msix_count
; i
++) {
308 xhci
->msix_entries
[i
].entry
= i
;
309 xhci
->msix_entries
[i
].vector
= 0;
312 ret
= pci_enable_msix_exact(pdev
, xhci
->msix_entries
, xhci
->msix_count
);
314 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
315 "Failed to enable MSI-X");
319 for (i
= 0; i
< xhci
->msix_count
; i
++) {
320 ret
= request_irq(xhci
->msix_entries
[i
].vector
,
322 0, "xhci_hcd", xhci_to_hcd(xhci
));
327 hcd
->msix_enabled
= 1;
331 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "disable MSI-X interrupt");
333 pci_disable_msix(pdev
);
335 kfree(xhci
->msix_entries
);
336 xhci
->msix_entries
= NULL
;
340 /* Free any IRQs and disable MSI-X */
341 static void xhci_cleanup_msix(struct xhci_hcd
*xhci
)
343 struct usb_hcd
*hcd
= xhci_to_hcd(xhci
);
344 struct pci_dev
*pdev
= to_pci_dev(hcd
->self
.controller
);
346 if (xhci
->quirks
& XHCI_PLAT
)
351 if (xhci
->msix_entries
) {
352 pci_disable_msix(pdev
);
353 kfree(xhci
->msix_entries
);
354 xhci
->msix_entries
= NULL
;
356 pci_disable_msi(pdev
);
359 hcd
->msix_enabled
= 0;
363 static void __maybe_unused
xhci_msix_sync_irqs(struct xhci_hcd
*xhci
)
367 if (xhci
->msix_entries
) {
368 for (i
= 0; i
< xhci
->msix_count
; i
++)
369 synchronize_irq(xhci
->msix_entries
[i
].vector
);
373 static int xhci_try_enable_msi(struct usb_hcd
*hcd
)
375 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
376 struct pci_dev
*pdev
;
379 /* The xhci platform device has set up IRQs through usb_add_hcd. */
380 if (xhci
->quirks
& XHCI_PLAT
)
383 pdev
= to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
);
385 * Some Fresco Logic host controllers advertise MSI, but fail to
386 * generate interrupts. Don't even try to enable MSI.
388 if (xhci
->quirks
& XHCI_BROKEN_MSI
)
391 /* unregister the legacy interrupt */
393 free_irq(hcd
->irq
, hcd
);
396 ret
= xhci_setup_msix(xhci
);
398 /* fall back to msi*/
399 ret
= xhci_setup_msi(xhci
);
402 /* hcd->irq is 0, we have MSI */
406 xhci_err(xhci
, "No msi-x/msi found and no IRQ in BIOS\n");
411 if (!strlen(hcd
->irq_descr
))
412 snprintf(hcd
->irq_descr
, sizeof(hcd
->irq_descr
), "%s:usb%d",
413 hcd
->driver
->description
, hcd
->self
.busnum
);
415 /* fall back to legacy interrupt*/
416 ret
= request_irq(pdev
->irq
, &usb_hcd_irq
, IRQF_SHARED
,
417 hcd
->irq_descr
, hcd
);
419 xhci_err(xhci
, "request interrupt %d failed\n",
423 hcd
->irq
= pdev
->irq
;
429 static inline int xhci_try_enable_msi(struct usb_hcd
*hcd
)
434 static inline void xhci_cleanup_msix(struct xhci_hcd
*xhci
)
438 static inline void xhci_msix_sync_irqs(struct xhci_hcd
*xhci
)
444 static void compliance_mode_recovery(unsigned long arg
)
446 struct xhci_hcd
*xhci
;
451 xhci
= (struct xhci_hcd
*)arg
;
453 for (i
= 0; i
< xhci
->num_usb3_ports
; i
++) {
454 temp
= readl(xhci
->usb3_ports
[i
]);
455 if ((temp
& PORT_PLS_MASK
) == USB_SS_PORT_LS_COMP_MOD
) {
457 * Compliance Mode Detected. Letting USB Core
458 * handle the Warm Reset
460 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
461 "Compliance mode detected->port %d",
463 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
464 "Attempting compliance mode recovery");
465 hcd
= xhci
->shared_hcd
;
467 if (hcd
->state
== HC_STATE_SUSPENDED
)
468 usb_hcd_resume_root_hub(hcd
);
470 usb_hcd_poll_rh_status(hcd
);
474 if (xhci
->port_status_u0
!= ((1 << xhci
->num_usb3_ports
)-1))
475 mod_timer(&xhci
->comp_mode_recovery_timer
,
476 jiffies
+ msecs_to_jiffies(COMP_MODE_RCVRY_MSECS
));
480 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
481 * that causes ports behind that hardware to enter compliance mode sometimes.
482 * The quirk creates a timer that polls every 2 seconds the link state of
483 * each host controller's port and recovers it by issuing a Warm reset
484 * if Compliance mode is detected, otherwise the port will become "dead" (no
485 * device connections or disconnections will be detected anymore). Becasue no
486 * status event is generated when entering compliance mode (per xhci spec),
487 * this quirk is needed on systems that have the failing hardware installed.
489 static void compliance_mode_recovery_timer_init(struct xhci_hcd
*xhci
)
491 xhci
->port_status_u0
= 0;
492 setup_timer(&xhci
->comp_mode_recovery_timer
,
493 compliance_mode_recovery
, (unsigned long)xhci
);
494 xhci
->comp_mode_recovery_timer
.expires
= jiffies
+
495 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS
);
497 add_timer(&xhci
->comp_mode_recovery_timer
);
498 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
499 "Compliance mode recovery timer initialized");
503 * This function identifies the systems that have installed the SN65LVPE502CP
504 * USB3.0 re-driver and that need the Compliance Mode Quirk.
506 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
508 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
510 const char *dmi_product_name
, *dmi_sys_vendor
;
512 dmi_product_name
= dmi_get_system_info(DMI_PRODUCT_NAME
);
513 dmi_sys_vendor
= dmi_get_system_info(DMI_SYS_VENDOR
);
514 if (!dmi_product_name
|| !dmi_sys_vendor
)
517 if (!(strstr(dmi_sys_vendor
, "Hewlett-Packard")))
520 if (strstr(dmi_product_name
, "Z420") ||
521 strstr(dmi_product_name
, "Z620") ||
522 strstr(dmi_product_name
, "Z820") ||
523 strstr(dmi_product_name
, "Z1 Workstation"))
529 static int xhci_all_ports_seen_u0(struct xhci_hcd
*xhci
)
531 return (xhci
->port_status_u0
== ((1 << xhci
->num_usb3_ports
)-1));
536 * Initialize memory for HCD and xHC (one-time init).
538 * Program the PAGESIZE register, initialize the device context array, create
539 * device contexts (?), set up a command ring segment (or two?), create event
540 * ring (one for now).
542 int xhci_init(struct usb_hcd
*hcd
)
544 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
547 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "xhci_init");
548 spin_lock_init(&xhci
->lock
);
549 if (xhci
->hci_version
== 0x95 && link_quirk
) {
550 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
551 "QUIRK: Not clearing Link TRB chain bits.");
552 xhci
->quirks
|= XHCI_LINK_TRB_QUIRK
;
554 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
555 "xHCI doesn't need link TRB QUIRK");
557 retval
= xhci_mem_init(xhci
, GFP_KERNEL
);
558 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "Finished xhci_init");
560 /* Initializing Compliance Mode Recovery Data If Needed */
561 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
562 xhci
->quirks
|= XHCI_COMP_MODE_QUIRK
;
563 compliance_mode_recovery_timer_init(xhci
);
569 /*-------------------------------------------------------------------------*/
572 static int xhci_run_finished(struct xhci_hcd
*xhci
)
574 if (xhci_start(xhci
)) {
578 xhci
->shared_hcd
->state
= HC_STATE_RUNNING
;
579 xhci
->cmd_ring_state
= CMD_RING_STATE_RUNNING
;
581 if (xhci
->quirks
& XHCI_NEC_HOST
)
582 xhci_ring_cmd_db(xhci
);
584 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
585 "Finished xhci_run for USB3 roothub");
590 * Start the HC after it was halted.
592 * This function is called by the USB core when the HC driver is added.
593 * Its opposite is xhci_stop().
595 * xhci_init() must be called once before this function can be called.
596 * Reset the HC, enable device slot contexts, program DCBAAP, and
597 * set command ring pointer and event ring pointer.
599 * Setup MSI-X vectors and enable interrupts.
601 int xhci_run(struct usb_hcd
*hcd
)
606 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
608 /* Start the xHCI host controller running only after the USB 2.0 roothub
612 hcd
->uses_new_polling
= 1;
613 if (!usb_hcd_is_primary_hcd(hcd
))
614 return xhci_run_finished(xhci
);
616 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "xhci_run");
618 ret
= xhci_try_enable_msi(hcd
);
622 xhci_dbg(xhci
, "Command ring memory map follows:\n");
623 xhci_debug_ring(xhci
, xhci
->cmd_ring
);
624 xhci_dbg_ring_ptrs(xhci
, xhci
->cmd_ring
);
625 xhci_dbg_cmd_ptrs(xhci
);
627 xhci_dbg(xhci
, "ERST memory map follows:\n");
628 xhci_dbg_erst(xhci
, &xhci
->erst
);
629 xhci_dbg(xhci
, "Event ring:\n");
630 xhci_debug_ring(xhci
, xhci
->event_ring
);
631 xhci_dbg_ring_ptrs(xhci
, xhci
->event_ring
);
632 temp_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
633 temp_64
&= ~ERST_PTR_MASK
;
634 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
635 "ERST deq = 64'h%0lx", (long unsigned int) temp_64
);
637 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
638 "// Set the interrupt modulation register");
639 temp
= readl(&xhci
->ir_set
->irq_control
);
640 temp
&= ~ER_IRQ_INTERVAL_MASK
;
642 * the increment interval is 8 times as much as that defined
643 * in xHCI spec on MTK's controller
645 temp
|= (u32
) ((xhci
->quirks
& XHCI_MTK_HOST
) ? 20 : 160);
646 writel(temp
, &xhci
->ir_set
->irq_control
);
648 /* Set the HCD state before we enable the irqs */
649 temp
= readl(&xhci
->op_regs
->command
);
651 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
652 "// Enable interrupts, cmd = 0x%x.", temp
);
653 writel(temp
, &xhci
->op_regs
->command
);
655 temp
= readl(&xhci
->ir_set
->irq_pending
);
656 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
657 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
658 xhci
->ir_set
, (unsigned int) ER_IRQ_ENABLE(temp
));
659 writel(ER_IRQ_ENABLE(temp
), &xhci
->ir_set
->irq_pending
);
660 xhci_print_ir_set(xhci
, 0);
662 if (xhci
->quirks
& XHCI_NEC_HOST
) {
663 struct xhci_command
*command
;
664 command
= xhci_alloc_command(xhci
, false, false, GFP_KERNEL
);
667 xhci_queue_vendor_command(xhci
, command
, 0, 0, 0,
668 TRB_TYPE(TRB_NEC_GET_FW
));
670 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
671 "Finished xhci_run for USB2 roothub");
674 EXPORT_SYMBOL_GPL(xhci_run
);
679 * This function is called by the USB core when the HC driver is removed.
680 * Its opposite is xhci_run().
682 * Disable device contexts, disable IRQs, and quiesce the HC.
683 * Reset the HC, finish any completed transactions, and cleanup memory.
685 void xhci_stop(struct usb_hcd
*hcd
)
688 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
690 mutex_lock(&xhci
->mutex
);
692 if (!(xhci
->xhc_state
& XHCI_STATE_HALTED
)) {
693 spin_lock_irq(&xhci
->lock
);
695 xhci
->xhc_state
|= XHCI_STATE_HALTED
;
696 xhci
->cmd_ring_state
= CMD_RING_STATE_STOPPED
;
699 spin_unlock_irq(&xhci
->lock
);
702 if (!usb_hcd_is_primary_hcd(hcd
)) {
703 mutex_unlock(&xhci
->mutex
);
707 xhci_cleanup_msix(xhci
);
709 /* Deleting Compliance Mode Recovery Timer */
710 if ((xhci
->quirks
& XHCI_COMP_MODE_QUIRK
) &&
711 (!(xhci_all_ports_seen_u0(xhci
)))) {
712 del_timer_sync(&xhci
->comp_mode_recovery_timer
);
713 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
714 "%s: compliance mode recovery timer deleted",
718 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
721 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
722 "// Disabling event ring interrupts");
723 temp
= readl(&xhci
->op_regs
->status
);
724 writel(temp
& ~STS_EINT
, &xhci
->op_regs
->status
);
725 temp
= readl(&xhci
->ir_set
->irq_pending
);
726 writel(ER_IRQ_DISABLE(temp
), &xhci
->ir_set
->irq_pending
);
727 xhci_print_ir_set(xhci
, 0);
729 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "cleaning up memory");
730 xhci_mem_cleanup(xhci
);
731 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
732 "xhci_stop completed - status = %x",
733 readl(&xhci
->op_regs
->status
));
734 mutex_unlock(&xhci
->mutex
);
738 * Shutdown HC (not bus-specific)
740 * This is called when the machine is rebooting or halting. We assume that the
741 * machine will be powered off, and the HC's internal state will be reset.
742 * Don't bother to free memory.
744 * This will only ever be called with the main usb_hcd (the USB3 roothub).
746 void xhci_shutdown(struct usb_hcd
*hcd
)
748 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
750 if (xhci
->quirks
& XHCI_SPURIOUS_REBOOT
)
751 usb_disable_xhci_ports(to_pci_dev(hcd
->self
.controller
));
753 spin_lock_irq(&xhci
->lock
);
755 /* Workaround for spurious wakeups at shutdown with HSW */
756 if (xhci
->quirks
& XHCI_SPURIOUS_WAKEUP
)
758 spin_unlock_irq(&xhci
->lock
);
760 xhci_cleanup_msix(xhci
);
762 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
763 "xhci_shutdown completed - status = %x",
764 readl(&xhci
->op_regs
->status
));
766 /* Yet another workaround for spurious wakeups at shutdown with HSW */
767 if (xhci
->quirks
& XHCI_SPURIOUS_WAKEUP
)
768 pci_set_power_state(to_pci_dev(hcd
->self
.controller
), PCI_D3hot
);
772 static void xhci_save_registers(struct xhci_hcd
*xhci
)
774 xhci
->s3
.command
= readl(&xhci
->op_regs
->command
);
775 xhci
->s3
.dev_nt
= readl(&xhci
->op_regs
->dev_notification
);
776 xhci
->s3
.dcbaa_ptr
= xhci_read_64(xhci
, &xhci
->op_regs
->dcbaa_ptr
);
777 xhci
->s3
.config_reg
= readl(&xhci
->op_regs
->config_reg
);
778 xhci
->s3
.erst_size
= readl(&xhci
->ir_set
->erst_size
);
779 xhci
->s3
.erst_base
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_base
);
780 xhci
->s3
.erst_dequeue
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
781 xhci
->s3
.irq_pending
= readl(&xhci
->ir_set
->irq_pending
);
782 xhci
->s3
.irq_control
= readl(&xhci
->ir_set
->irq_control
);
785 static void xhci_restore_registers(struct xhci_hcd
*xhci
)
787 writel(xhci
->s3
.command
, &xhci
->op_regs
->command
);
788 writel(xhci
->s3
.dev_nt
, &xhci
->op_regs
->dev_notification
);
789 xhci_write_64(xhci
, xhci
->s3
.dcbaa_ptr
, &xhci
->op_regs
->dcbaa_ptr
);
790 writel(xhci
->s3
.config_reg
, &xhci
->op_regs
->config_reg
);
791 writel(xhci
->s3
.erst_size
, &xhci
->ir_set
->erst_size
);
792 xhci_write_64(xhci
, xhci
->s3
.erst_base
, &xhci
->ir_set
->erst_base
);
793 xhci_write_64(xhci
, xhci
->s3
.erst_dequeue
, &xhci
->ir_set
->erst_dequeue
);
794 writel(xhci
->s3
.irq_pending
, &xhci
->ir_set
->irq_pending
);
795 writel(xhci
->s3
.irq_control
, &xhci
->ir_set
->irq_control
);
798 static void xhci_set_cmd_ring_deq(struct xhci_hcd
*xhci
)
802 /* step 2: initialize command ring buffer */
803 val_64
= xhci_read_64(xhci
, &xhci
->op_regs
->cmd_ring
);
804 val_64
= (val_64
& (u64
) CMD_RING_RSVD_BITS
) |
805 (xhci_trb_virt_to_dma(xhci
->cmd_ring
->deq_seg
,
806 xhci
->cmd_ring
->dequeue
) &
807 (u64
) ~CMD_RING_RSVD_BITS
) |
808 xhci
->cmd_ring
->cycle_state
;
809 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
810 "// Setting command ring address to 0x%llx",
811 (long unsigned long) val_64
);
812 xhci_write_64(xhci
, val_64
, &xhci
->op_regs
->cmd_ring
);
816 * The whole command ring must be cleared to zero when we suspend the host.
818 * The host doesn't save the command ring pointer in the suspend well, so we
819 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
820 * aligned, because of the reserved bits in the command ring dequeue pointer
821 * register. Therefore, we can't just set the dequeue pointer back in the
822 * middle of the ring (TRBs are 16-byte aligned).
824 static void xhci_clear_command_ring(struct xhci_hcd
*xhci
)
826 struct xhci_ring
*ring
;
827 struct xhci_segment
*seg
;
829 ring
= xhci
->cmd_ring
;
833 sizeof(union xhci_trb
) * (TRBS_PER_SEGMENT
- 1));
834 seg
->trbs
[TRBS_PER_SEGMENT
- 1].link
.control
&=
835 cpu_to_le32(~TRB_CYCLE
);
837 } while (seg
!= ring
->deq_seg
);
839 /* Reset the software enqueue and dequeue pointers */
840 ring
->deq_seg
= ring
->first_seg
;
841 ring
->dequeue
= ring
->first_seg
->trbs
;
842 ring
->enq_seg
= ring
->deq_seg
;
843 ring
->enqueue
= ring
->dequeue
;
845 ring
->num_trbs_free
= ring
->num_segs
* (TRBS_PER_SEGMENT
- 1) - 1;
847 * Ring is now zeroed, so the HW should look for change of ownership
848 * when the cycle bit is set to 1.
850 ring
->cycle_state
= 1;
853 * Reset the hardware dequeue pointer.
854 * Yes, this will need to be re-written after resume, but we're paranoid
855 * and want to make sure the hardware doesn't access bogus memory
856 * because, say, the BIOS or an SMI started the host without changing
857 * the command ring pointers.
859 xhci_set_cmd_ring_deq(xhci
);
862 static void xhci_disable_port_wake_on_bits(struct xhci_hcd
*xhci
)
865 __le32 __iomem
**port_array
;
869 spin_lock_irqsave(&xhci
->lock
, flags
);
871 /* disble usb3 ports Wake bits*/
872 port_index
= xhci
->num_usb3_ports
;
873 port_array
= xhci
->usb3_ports
;
874 while (port_index
--) {
875 t1
= readl(port_array
[port_index
]);
876 t1
= xhci_port_state_to_neutral(t1
);
877 t2
= t1
& ~PORT_WAKE_BITS
;
879 writel(t2
, port_array
[port_index
]);
882 /* disble usb2 ports Wake bits*/
883 port_index
= xhci
->num_usb2_ports
;
884 port_array
= xhci
->usb2_ports
;
885 while (port_index
--) {
886 t1
= readl(port_array
[port_index
]);
887 t1
= xhci_port_state_to_neutral(t1
);
888 t2
= t1
& ~PORT_WAKE_BITS
;
890 writel(t2
, port_array
[port_index
]);
893 spin_unlock_irqrestore(&xhci
->lock
, flags
);
897 * Stop HC (not bus-specific)
899 * This is called when the machine transition into S3/S4 mode.
902 int xhci_suspend(struct xhci_hcd
*xhci
, bool do_wakeup
)
905 unsigned int delay
= XHCI_MAX_HALT_USEC
;
906 struct usb_hcd
*hcd
= xhci_to_hcd(xhci
);
912 if (hcd
->state
!= HC_STATE_SUSPENDED
||
913 xhci
->shared_hcd
->state
!= HC_STATE_SUSPENDED
)
916 /* Clear root port wake on bits if wakeup not allowed. */
918 xhci_disable_port_wake_on_bits(xhci
);
920 /* Don't poll the roothubs on bus suspend. */
921 xhci_dbg(xhci
, "%s: stopping port polling.\n", __func__
);
922 clear_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
923 del_timer_sync(&hcd
->rh_timer
);
924 clear_bit(HCD_FLAG_POLL_RH
, &xhci
->shared_hcd
->flags
);
925 del_timer_sync(&xhci
->shared_hcd
->rh_timer
);
927 spin_lock_irq(&xhci
->lock
);
928 clear_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
929 clear_bit(HCD_FLAG_HW_ACCESSIBLE
, &xhci
->shared_hcd
->flags
);
930 /* step 1: stop endpoint */
931 /* skipped assuming that port suspend has done */
933 /* step 2: clear Run/Stop bit */
934 command
= readl(&xhci
->op_regs
->command
);
936 writel(command
, &xhci
->op_regs
->command
);
938 /* Some chips from Fresco Logic need an extraordinary delay */
939 delay
*= (xhci
->quirks
& XHCI_SLOW_SUSPEND
) ? 10 : 1;
941 if (xhci_handshake(&xhci
->op_regs
->status
,
942 STS_HALT
, STS_HALT
, delay
)) {
943 xhci_warn(xhci
, "WARN: xHC CMD_RUN timeout\n");
944 spin_unlock_irq(&xhci
->lock
);
947 xhci_clear_command_ring(xhci
);
949 /* step 3: save registers */
950 xhci_save_registers(xhci
);
952 /* step 4: set CSS flag */
953 command
= readl(&xhci
->op_regs
->command
);
955 writel(command
, &xhci
->op_regs
->command
);
956 if (xhci_handshake(&xhci
->op_regs
->status
,
957 STS_SAVE
, 0, 10 * 1000)) {
958 xhci_warn(xhci
, "WARN: xHC save state timeout\n");
959 spin_unlock_irq(&xhci
->lock
);
962 spin_unlock_irq(&xhci
->lock
);
965 * Deleting Compliance Mode Recovery Timer because the xHCI Host
966 * is about to be suspended.
968 if ((xhci
->quirks
& XHCI_COMP_MODE_QUIRK
) &&
969 (!(xhci_all_ports_seen_u0(xhci
)))) {
970 del_timer_sync(&xhci
->comp_mode_recovery_timer
);
971 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
972 "%s: compliance mode recovery timer deleted",
976 /* step 5: remove core well power */
977 /* synchronize irq when using MSI-X */
978 xhci_msix_sync_irqs(xhci
);
982 EXPORT_SYMBOL_GPL(xhci_suspend
);
985 * start xHC (not bus-specific)
987 * This is called when the machine transition from S3/S4 mode.
990 int xhci_resume(struct xhci_hcd
*xhci
, bool hibernated
)
992 u32 command
, temp
= 0, status
;
993 struct usb_hcd
*hcd
= xhci_to_hcd(xhci
);
994 struct usb_hcd
*secondary_hcd
;
996 bool comp_timer_running
= false;
1001 /* Wait a bit if either of the roothubs need to settle from the
1002 * transition into bus suspend.
1004 if (time_before(jiffies
, xhci
->bus_state
[0].next_statechange
) ||
1005 time_before(jiffies
,
1006 xhci
->bus_state
[1].next_statechange
))
1009 set_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
1010 set_bit(HCD_FLAG_HW_ACCESSIBLE
, &xhci
->shared_hcd
->flags
);
1012 spin_lock_irq(&xhci
->lock
);
1013 if (xhci
->quirks
& XHCI_RESET_ON_RESUME
)
1017 /* step 1: restore register */
1018 xhci_restore_registers(xhci
);
1019 /* step 2: initialize command ring buffer */
1020 xhci_set_cmd_ring_deq(xhci
);
1021 /* step 3: restore state and start state*/
1022 /* step 3: set CRS flag */
1023 command
= readl(&xhci
->op_regs
->command
);
1025 writel(command
, &xhci
->op_regs
->command
);
1026 if (xhci_handshake(&xhci
->op_regs
->status
,
1027 STS_RESTORE
, 0, 10 * 1000)) {
1028 xhci_warn(xhci
, "WARN: xHC restore state timeout\n");
1029 spin_unlock_irq(&xhci
->lock
);
1032 temp
= readl(&xhci
->op_regs
->status
);
1035 /* If restore operation fails, re-initialize the HC during resume */
1036 if ((temp
& STS_SRE
) || hibernated
) {
1038 if ((xhci
->quirks
& XHCI_COMP_MODE_QUIRK
) &&
1039 !(xhci_all_ports_seen_u0(xhci
))) {
1040 del_timer_sync(&xhci
->comp_mode_recovery_timer
);
1041 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
1042 "Compliance Mode Recovery Timer deleted!");
1045 /* Let the USB core know _both_ roothubs lost power. */
1046 usb_root_hub_lost_power(xhci
->main_hcd
->self
.root_hub
);
1047 usb_root_hub_lost_power(xhci
->shared_hcd
->self
.root_hub
);
1049 xhci_dbg(xhci
, "Stop HCD\n");
1052 spin_unlock_irq(&xhci
->lock
);
1053 xhci_cleanup_msix(xhci
);
1055 xhci_dbg(xhci
, "// Disabling event ring interrupts\n");
1056 temp
= readl(&xhci
->op_regs
->status
);
1057 writel(temp
& ~STS_EINT
, &xhci
->op_regs
->status
);
1058 temp
= readl(&xhci
->ir_set
->irq_pending
);
1059 writel(ER_IRQ_DISABLE(temp
), &xhci
->ir_set
->irq_pending
);
1060 xhci_print_ir_set(xhci
, 0);
1062 xhci_dbg(xhci
, "cleaning up memory\n");
1063 xhci_mem_cleanup(xhci
);
1064 xhci_dbg(xhci
, "xhci_stop completed - status = %x\n",
1065 readl(&xhci
->op_regs
->status
));
1067 /* USB core calls the PCI reinit and start functions twice:
1068 * first with the primary HCD, and then with the secondary HCD.
1069 * If we don't do the same, the host will never be started.
1071 if (!usb_hcd_is_primary_hcd(hcd
))
1072 secondary_hcd
= hcd
;
1074 secondary_hcd
= xhci
->shared_hcd
;
1076 xhci_dbg(xhci
, "Initialize the xhci_hcd\n");
1077 retval
= xhci_init(hcd
->primary_hcd
);
1080 comp_timer_running
= true;
1082 xhci_dbg(xhci
, "Start the primary HCD\n");
1083 retval
= xhci_run(hcd
->primary_hcd
);
1085 xhci_dbg(xhci
, "Start the secondary HCD\n");
1086 retval
= xhci_run(secondary_hcd
);
1088 hcd
->state
= HC_STATE_SUSPENDED
;
1089 xhci
->shared_hcd
->state
= HC_STATE_SUSPENDED
;
1093 /* step 4: set Run/Stop bit */
1094 command
= readl(&xhci
->op_regs
->command
);
1096 writel(command
, &xhci
->op_regs
->command
);
1097 xhci_handshake(&xhci
->op_regs
->status
, STS_HALT
,
1100 /* step 5: walk topology and initialize portsc,
1101 * portpmsc and portli
1103 /* this is done in bus_resume */
1105 /* step 6: restart each of the previously
1106 * Running endpoints by ringing their doorbells
1109 spin_unlock_irq(&xhci
->lock
);
1113 /* Resume root hubs only when have pending events. */
1114 status
= readl(&xhci
->op_regs
->status
);
1115 if (status
& STS_EINT
) {
1116 usb_hcd_resume_root_hub(xhci
->shared_hcd
);
1117 usb_hcd_resume_root_hub(hcd
);
1122 * If system is subject to the Quirk, Compliance Mode Timer needs to
1123 * be re-initialized Always after a system resume. Ports are subject
1124 * to suffer the Compliance Mode issue again. It doesn't matter if
1125 * ports have entered previously to U0 before system's suspension.
1127 if ((xhci
->quirks
& XHCI_COMP_MODE_QUIRK
) && !comp_timer_running
)
1128 compliance_mode_recovery_timer_init(xhci
);
1130 /* Re-enable port polling. */
1131 xhci_dbg(xhci
, "%s: starting port polling.\n", __func__
);
1132 set_bit(HCD_FLAG_POLL_RH
, &xhci
->shared_hcd
->flags
);
1133 usb_hcd_poll_rh_status(xhci
->shared_hcd
);
1134 set_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
1135 usb_hcd_poll_rh_status(hcd
);
1139 EXPORT_SYMBOL_GPL(xhci_resume
);
1140 #endif /* CONFIG_PM */
1142 /*-------------------------------------------------------------------------*/
1145 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1146 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1147 * value to right shift 1 for the bitmask.
1149 * Index = (epnum * 2) + direction - 1,
1150 * where direction = 0 for OUT, 1 for IN.
1151 * For control endpoints, the IN index is used (OUT index is unused), so
1152 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1154 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor
*desc
)
1157 if (usb_endpoint_xfer_control(desc
))
1158 index
= (unsigned int) (usb_endpoint_num(desc
)*2);
1160 index
= (unsigned int) (usb_endpoint_num(desc
)*2) +
1161 (usb_endpoint_dir_in(desc
) ? 1 : 0) - 1;
1165 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1166 * address from the XHCI endpoint index.
1168 unsigned int xhci_get_endpoint_address(unsigned int ep_index
)
1170 unsigned int number
= DIV_ROUND_UP(ep_index
, 2);
1171 unsigned int direction
= ep_index
% 2 ? USB_DIR_OUT
: USB_DIR_IN
;
1172 return direction
| number
;
1175 /* Find the flag for this endpoint (for use in the control context). Use the
1176 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1179 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor
*desc
)
1181 return 1 << (xhci_get_endpoint_index(desc
) + 1);
1184 /* Find the flag for this endpoint (for use in the control context). Use the
1185 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1188 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index
)
1190 return 1 << (ep_index
+ 1);
1193 /* Compute the last valid endpoint context index. Basically, this is the
1194 * endpoint index plus one. For slot contexts with more than valid endpoint,
1195 * we find the most significant bit set in the added contexts flags.
1196 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1197 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1199 unsigned int xhci_last_valid_endpoint(u32 added_ctxs
)
1201 return fls(added_ctxs
) - 1;
1204 /* Returns 1 if the arguments are OK;
1205 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1207 static int xhci_check_args(struct usb_hcd
*hcd
, struct usb_device
*udev
,
1208 struct usb_host_endpoint
*ep
, int check_ep
, bool check_virt_dev
,
1210 struct xhci_hcd
*xhci
;
1211 struct xhci_virt_device
*virt_dev
;
1213 if (!hcd
|| (check_ep
&& !ep
) || !udev
) {
1214 pr_debug("xHCI %s called with invalid args\n", func
);
1217 if (!udev
->parent
) {
1218 pr_debug("xHCI %s called for root hub\n", func
);
1222 xhci
= hcd_to_xhci(hcd
);
1223 if (check_virt_dev
) {
1224 if (!udev
->slot_id
|| !xhci
->devs
[udev
->slot_id
]) {
1225 xhci_dbg(xhci
, "xHCI %s called with unaddressed device\n",
1230 virt_dev
= xhci
->devs
[udev
->slot_id
];
1231 if (virt_dev
->udev
!= udev
) {
1232 xhci_dbg(xhci
, "xHCI %s called with udev and "
1233 "virt_dev does not match\n", func
);
1238 if (xhci
->xhc_state
& XHCI_STATE_HALTED
)
1244 static int xhci_configure_endpoint(struct xhci_hcd
*xhci
,
1245 struct usb_device
*udev
, struct xhci_command
*command
,
1246 bool ctx_change
, bool must_succeed
);
1249 * Full speed devices may have a max packet size greater than 8 bytes, but the
1250 * USB core doesn't know that until it reads the first 8 bytes of the
1251 * descriptor. If the usb_device's max packet size changes after that point,
1252 * we need to issue an evaluate context command and wait on it.
1254 static int xhci_check_maxpacket(struct xhci_hcd
*xhci
, unsigned int slot_id
,
1255 unsigned int ep_index
, struct urb
*urb
)
1257 struct xhci_container_ctx
*out_ctx
;
1258 struct xhci_input_control_ctx
*ctrl_ctx
;
1259 struct xhci_ep_ctx
*ep_ctx
;
1260 struct xhci_command
*command
;
1261 int max_packet_size
;
1262 int hw_max_packet_size
;
1265 out_ctx
= xhci
->devs
[slot_id
]->out_ctx
;
1266 ep_ctx
= xhci_get_ep_ctx(xhci
, out_ctx
, ep_index
);
1267 hw_max_packet_size
= MAX_PACKET_DECODED(le32_to_cpu(ep_ctx
->ep_info2
));
1268 max_packet_size
= usb_endpoint_maxp(&urb
->dev
->ep0
.desc
);
1269 if (hw_max_packet_size
!= max_packet_size
) {
1270 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
1271 "Max Packet Size for ep 0 changed.");
1272 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
1273 "Max packet size in usb_device = %d",
1275 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
1276 "Max packet size in xHCI HW = %d",
1277 hw_max_packet_size
);
1278 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
1279 "Issuing evaluate context command.");
1281 /* Set up the input context flags for the command */
1282 /* FIXME: This won't work if a non-default control endpoint
1283 * changes max packet sizes.
1286 command
= xhci_alloc_command(xhci
, false, true, GFP_KERNEL
);
1290 command
->in_ctx
= xhci
->devs
[slot_id
]->in_ctx
;
1291 ctrl_ctx
= xhci_get_input_control_ctx(command
->in_ctx
);
1293 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
1296 goto command_cleanup
;
1298 /* Set up the modified control endpoint 0 */
1299 xhci_endpoint_copy(xhci
, xhci
->devs
[slot_id
]->in_ctx
,
1300 xhci
->devs
[slot_id
]->out_ctx
, ep_index
);
1302 ep_ctx
= xhci_get_ep_ctx(xhci
, command
->in_ctx
, ep_index
);
1303 ep_ctx
->ep_info2
&= cpu_to_le32(~MAX_PACKET_MASK
);
1304 ep_ctx
->ep_info2
|= cpu_to_le32(MAX_PACKET(max_packet_size
));
1306 ctrl_ctx
->add_flags
= cpu_to_le32(EP0_FLAG
);
1307 ctrl_ctx
->drop_flags
= 0;
1309 xhci_dbg(xhci
, "Slot %d input context\n", slot_id
);
1310 xhci_dbg_ctx(xhci
, command
->in_ctx
, ep_index
);
1311 xhci_dbg(xhci
, "Slot %d output context\n", slot_id
);
1312 xhci_dbg_ctx(xhci
, out_ctx
, ep_index
);
1314 ret
= xhci_configure_endpoint(xhci
, urb
->dev
, command
,
1317 /* Clean up the input context for later use by bandwidth
1320 ctrl_ctx
->add_flags
= cpu_to_le32(SLOT_FLAG
);
1322 kfree(command
->completion
);
1329 * non-error returns are a promise to giveback() the urb later
1330 * we drop ownership so next owner (or urb unlink) can get it
1332 int xhci_urb_enqueue(struct usb_hcd
*hcd
, struct urb
*urb
, gfp_t mem_flags
)
1334 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
1335 unsigned long flags
;
1337 unsigned int slot_id
, ep_index
, ep_state
;
1338 struct urb_priv
*urb_priv
;
1341 if (!urb
|| xhci_check_args(hcd
, urb
->dev
, urb
->ep
,
1342 true, true, __func__
) <= 0)
1345 slot_id
= urb
->dev
->slot_id
;
1346 ep_index
= xhci_get_endpoint_index(&urb
->ep
->desc
);
1348 if (!HCD_HW_ACCESSIBLE(hcd
)) {
1349 if (!in_interrupt())
1350 xhci_dbg(xhci
, "urb submitted during PCI suspend\n");
1354 if (usb_endpoint_xfer_isoc(&urb
->ep
->desc
))
1355 num_tds
= urb
->number_of_packets
;
1356 else if (usb_endpoint_is_bulk_out(&urb
->ep
->desc
) &&
1357 urb
->transfer_buffer_length
> 0 &&
1358 urb
->transfer_flags
& URB_ZERO_PACKET
&&
1359 !(urb
->transfer_buffer_length
% usb_endpoint_maxp(&urb
->ep
->desc
)))
1364 urb_priv
= kzalloc(sizeof(struct urb_priv
) +
1365 num_tds
* sizeof(struct xhci_td
), mem_flags
);
1369 urb_priv
->num_tds
= num_tds
;
1370 urb_priv
->num_tds_done
= 0;
1371 urb
->hcpriv
= urb_priv
;
1373 trace_xhci_urb_enqueue(urb
);
1375 if (usb_endpoint_xfer_control(&urb
->ep
->desc
)) {
1376 /* Check to see if the max packet size for the default control
1377 * endpoint changed during FS device enumeration
1379 if (urb
->dev
->speed
== USB_SPEED_FULL
) {
1380 ret
= xhci_check_maxpacket(xhci
, slot_id
,
1383 xhci_urb_free_priv(urb_priv
);
1390 spin_lock_irqsave(&xhci
->lock
, flags
);
1392 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
1393 xhci_dbg(xhci
, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1394 urb
->ep
->desc
.bEndpointAddress
, urb
);
1399 switch (usb_endpoint_type(&urb
->ep
->desc
)) {
1401 case USB_ENDPOINT_XFER_CONTROL
:
1402 ret
= xhci_queue_ctrl_tx(xhci
, GFP_ATOMIC
, urb
,
1405 case USB_ENDPOINT_XFER_BULK
:
1406 ep_state
= xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
;
1407 if (ep_state
& (EP_GETTING_STREAMS
| EP_GETTING_NO_STREAMS
)) {
1408 xhci_warn(xhci
, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1413 ret
= xhci_queue_bulk_tx(xhci
, GFP_ATOMIC
, urb
,
1418 case USB_ENDPOINT_XFER_INT
:
1419 ret
= xhci_queue_intr_tx(xhci
, GFP_ATOMIC
, urb
,
1423 case USB_ENDPOINT_XFER_ISOC
:
1424 ret
= xhci_queue_isoc_tx_prepare(xhci
, GFP_ATOMIC
, urb
,
1430 xhci_urb_free_priv(urb_priv
);
1433 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1438 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1439 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1440 * should pick up where it left off in the TD, unless a Set Transfer Ring
1441 * Dequeue Pointer is issued.
1443 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1444 * the ring. Since the ring is a contiguous structure, they can't be physically
1445 * removed. Instead, there are two options:
1447 * 1) If the HC is in the middle of processing the URB to be canceled, we
1448 * simply move the ring's dequeue pointer past those TRBs using the Set
1449 * Transfer Ring Dequeue Pointer command. This will be the common case,
1450 * when drivers timeout on the last submitted URB and attempt to cancel.
1452 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1453 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1454 * HC will need to invalidate the any TRBs it has cached after the stop
1455 * endpoint command, as noted in the xHCI 0.95 errata.
1457 * 3) The TD may have completed by the time the Stop Endpoint Command
1458 * completes, so software needs to handle that case too.
1460 * This function should protect against the TD enqueueing code ringing the
1461 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1462 * It also needs to account for multiple cancellations on happening at the same
1463 * time for the same endpoint.
1465 * Note that this function can be called in any context, or so says
1466 * usb_hcd_unlink_urb()
1468 int xhci_urb_dequeue(struct usb_hcd
*hcd
, struct urb
*urb
, int status
)
1470 unsigned long flags
;
1473 struct xhci_hcd
*xhci
;
1474 struct urb_priv
*urb_priv
;
1476 unsigned int ep_index
;
1477 struct xhci_ring
*ep_ring
;
1478 struct xhci_virt_ep
*ep
;
1479 struct xhci_command
*command
;
1481 xhci
= hcd_to_xhci(hcd
);
1482 spin_lock_irqsave(&xhci
->lock
, flags
);
1484 trace_xhci_urb_dequeue(urb
);
1486 /* Make sure the URB hasn't completed or been unlinked already */
1487 ret
= usb_hcd_check_unlink_urb(hcd
, urb
, status
);
1488 if (ret
|| !urb
->hcpriv
)
1490 temp
= readl(&xhci
->op_regs
->status
);
1491 if (temp
== 0xffffffff || (xhci
->xhc_state
& XHCI_STATE_HALTED
)) {
1492 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
1493 "HW died, freeing TD.");
1494 urb_priv
= urb
->hcpriv
;
1495 for (i
= urb_priv
->num_tds_done
;
1496 i
< urb_priv
->num_tds
&& xhci
->devs
[urb
->dev
->slot_id
];
1498 td
= &urb_priv
->td
[i
];
1499 if (!list_empty(&td
->td_list
))
1500 list_del_init(&td
->td_list
);
1501 if (!list_empty(&td
->cancelled_td_list
))
1502 list_del_init(&td
->cancelled_td_list
);
1505 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
1506 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1507 usb_hcd_giveback_urb(hcd
, urb
, -ESHUTDOWN
);
1508 xhci_urb_free_priv(urb_priv
);
1512 ep_index
= xhci_get_endpoint_index(&urb
->ep
->desc
);
1513 ep
= &xhci
->devs
[urb
->dev
->slot_id
]->eps
[ep_index
];
1514 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
1520 urb_priv
= urb
->hcpriv
;
1521 i
= urb_priv
->num_tds_done
;
1522 if (i
< urb_priv
->num_tds
)
1523 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
1524 "Cancel URB %p, dev %s, ep 0x%x, "
1525 "starting at offset 0x%llx",
1526 urb
, urb
->dev
->devpath
,
1527 urb
->ep
->desc
.bEndpointAddress
,
1528 (unsigned long long) xhci_trb_virt_to_dma(
1529 urb_priv
->td
[i
].start_seg
,
1530 urb_priv
->td
[i
].first_trb
));
1532 for (; i
< urb_priv
->num_tds
; i
++) {
1533 td
= &urb_priv
->td
[i
];
1534 list_add_tail(&td
->cancelled_td_list
, &ep
->cancelled_td_list
);
1537 /* Queue a stop endpoint command, but only if this is
1538 * the first cancellation to be handled.
1540 if (!(ep
->ep_state
& EP_STOP_CMD_PENDING
)) {
1541 command
= xhci_alloc_command(xhci
, false, false, GFP_ATOMIC
);
1546 ep
->ep_state
|= EP_STOP_CMD_PENDING
;
1547 ep
->stop_cmd_timer
.expires
= jiffies
+
1548 XHCI_STOP_EP_CMD_TIMEOUT
* HZ
;
1549 add_timer(&ep
->stop_cmd_timer
);
1550 xhci_queue_stop_endpoint(xhci
, command
, urb
->dev
->slot_id
,
1552 xhci_ring_cmd_db(xhci
);
1555 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1559 /* Drop an endpoint from a new bandwidth configuration for this device.
1560 * Only one call to this function is allowed per endpoint before
1561 * check_bandwidth() or reset_bandwidth() must be called.
1562 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1563 * add the endpoint to the schedule with possibly new parameters denoted by a
1564 * different endpoint descriptor in usb_host_endpoint.
1565 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1568 * The USB core will not allow URBs to be queued to an endpoint that is being
1569 * disabled, so there's no need for mutual exclusion to protect
1570 * the xhci->devs[slot_id] structure.
1572 int xhci_drop_endpoint(struct usb_hcd
*hcd
, struct usb_device
*udev
,
1573 struct usb_host_endpoint
*ep
)
1575 struct xhci_hcd
*xhci
;
1576 struct xhci_container_ctx
*in_ctx
, *out_ctx
;
1577 struct xhci_input_control_ctx
*ctrl_ctx
;
1578 unsigned int ep_index
;
1579 struct xhci_ep_ctx
*ep_ctx
;
1581 u32 new_add_flags
, new_drop_flags
;
1584 ret
= xhci_check_args(hcd
, udev
, ep
, 1, true, __func__
);
1587 xhci
= hcd_to_xhci(hcd
);
1588 if (xhci
->xhc_state
& XHCI_STATE_DYING
)
1591 xhci_dbg(xhci
, "%s called for udev %p\n", __func__
, udev
);
1592 drop_flag
= xhci_get_endpoint_flag(&ep
->desc
);
1593 if (drop_flag
== SLOT_FLAG
|| drop_flag
== EP0_FLAG
) {
1594 xhci_dbg(xhci
, "xHCI %s - can't drop slot or ep 0 %#x\n",
1595 __func__
, drop_flag
);
1599 in_ctx
= xhci
->devs
[udev
->slot_id
]->in_ctx
;
1600 out_ctx
= xhci
->devs
[udev
->slot_id
]->out_ctx
;
1601 ctrl_ctx
= xhci_get_input_control_ctx(in_ctx
);
1603 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
1608 ep_index
= xhci_get_endpoint_index(&ep
->desc
);
1609 ep_ctx
= xhci_get_ep_ctx(xhci
, out_ctx
, ep_index
);
1610 /* If the HC already knows the endpoint is disabled,
1611 * or the HCD has noted it is disabled, ignore this request
1613 if ((GET_EP_CTX_STATE(ep_ctx
) == EP_STATE_DISABLED
) ||
1614 le32_to_cpu(ctrl_ctx
->drop_flags
) &
1615 xhci_get_endpoint_flag(&ep
->desc
)) {
1616 /* Do not warn when called after a usb_device_reset */
1617 if (xhci
->devs
[udev
->slot_id
]->eps
[ep_index
].ring
!= NULL
)
1618 xhci_warn(xhci
, "xHCI %s called with disabled ep %p\n",
1623 ctrl_ctx
->drop_flags
|= cpu_to_le32(drop_flag
);
1624 new_drop_flags
= le32_to_cpu(ctrl_ctx
->drop_flags
);
1626 ctrl_ctx
->add_flags
&= cpu_to_le32(~drop_flag
);
1627 new_add_flags
= le32_to_cpu(ctrl_ctx
->add_flags
);
1629 xhci_endpoint_zero(xhci
, xhci
->devs
[udev
->slot_id
], ep
);
1631 if (xhci
->quirks
& XHCI_MTK_HOST
)
1632 xhci_mtk_drop_ep_quirk(hcd
, udev
, ep
);
1634 xhci_dbg(xhci
, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1635 (unsigned int) ep
->desc
.bEndpointAddress
,
1637 (unsigned int) new_drop_flags
,
1638 (unsigned int) new_add_flags
);
1642 /* Add an endpoint to a new possible bandwidth configuration for this device.
1643 * Only one call to this function is allowed per endpoint before
1644 * check_bandwidth() or reset_bandwidth() must be called.
1645 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1646 * add the endpoint to the schedule with possibly new parameters denoted by a
1647 * different endpoint descriptor in usb_host_endpoint.
1648 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1651 * The USB core will not allow URBs to be queued to an endpoint until the
1652 * configuration or alt setting is installed in the device, so there's no need
1653 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1655 int xhci_add_endpoint(struct usb_hcd
*hcd
, struct usb_device
*udev
,
1656 struct usb_host_endpoint
*ep
)
1658 struct xhci_hcd
*xhci
;
1659 struct xhci_container_ctx
*in_ctx
;
1660 unsigned int ep_index
;
1661 struct xhci_input_control_ctx
*ctrl_ctx
;
1663 u32 new_add_flags
, new_drop_flags
;
1664 struct xhci_virt_device
*virt_dev
;
1667 ret
= xhci_check_args(hcd
, udev
, ep
, 1, true, __func__
);
1669 /* So we won't queue a reset ep command for a root hub */
1673 xhci
= hcd_to_xhci(hcd
);
1674 if (xhci
->xhc_state
& XHCI_STATE_DYING
)
1677 added_ctxs
= xhci_get_endpoint_flag(&ep
->desc
);
1678 if (added_ctxs
== SLOT_FLAG
|| added_ctxs
== EP0_FLAG
) {
1679 /* FIXME when we have to issue an evaluate endpoint command to
1680 * deal with ep0 max packet size changing once we get the
1683 xhci_dbg(xhci
, "xHCI %s - can't add slot or ep 0 %#x\n",
1684 __func__
, added_ctxs
);
1688 virt_dev
= xhci
->devs
[udev
->slot_id
];
1689 in_ctx
= virt_dev
->in_ctx
;
1690 ctrl_ctx
= xhci_get_input_control_ctx(in_ctx
);
1692 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
1697 ep_index
= xhci_get_endpoint_index(&ep
->desc
);
1698 /* If this endpoint is already in use, and the upper layers are trying
1699 * to add it again without dropping it, reject the addition.
1701 if (virt_dev
->eps
[ep_index
].ring
&&
1702 !(le32_to_cpu(ctrl_ctx
->drop_flags
) & added_ctxs
)) {
1703 xhci_warn(xhci
, "Trying to add endpoint 0x%x "
1704 "without dropping it.\n",
1705 (unsigned int) ep
->desc
.bEndpointAddress
);
1709 /* If the HCD has already noted the endpoint is enabled,
1710 * ignore this request.
1712 if (le32_to_cpu(ctrl_ctx
->add_flags
) & added_ctxs
) {
1713 xhci_warn(xhci
, "xHCI %s called with enabled ep %p\n",
1719 * Configuration and alternate setting changes must be done in
1720 * process context, not interrupt context (or so documenation
1721 * for usb_set_interface() and usb_set_configuration() claim).
1723 if (xhci_endpoint_init(xhci
, virt_dev
, udev
, ep
, GFP_NOIO
) < 0) {
1724 dev_dbg(&udev
->dev
, "%s - could not initialize ep %#x\n",
1725 __func__
, ep
->desc
.bEndpointAddress
);
1729 if (xhci
->quirks
& XHCI_MTK_HOST
) {
1730 ret
= xhci_mtk_add_ep_quirk(hcd
, udev
, ep
);
1732 xhci_free_or_cache_endpoint_ring(xhci
,
1733 virt_dev
, ep_index
);
1738 ctrl_ctx
->add_flags
|= cpu_to_le32(added_ctxs
);
1739 new_add_flags
= le32_to_cpu(ctrl_ctx
->add_flags
);
1741 /* If xhci_endpoint_disable() was called for this endpoint, but the
1742 * xHC hasn't been notified yet through the check_bandwidth() call,
1743 * this re-adds a new state for the endpoint from the new endpoint
1744 * descriptors. We must drop and re-add this endpoint, so we leave the
1747 new_drop_flags
= le32_to_cpu(ctrl_ctx
->drop_flags
);
1749 /* Store the usb_device pointer for later use */
1752 xhci_dbg(xhci
, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1753 (unsigned int) ep
->desc
.bEndpointAddress
,
1755 (unsigned int) new_drop_flags
,
1756 (unsigned int) new_add_flags
);
1760 static void xhci_zero_in_ctx(struct xhci_hcd
*xhci
, struct xhci_virt_device
*virt_dev
)
1762 struct xhci_input_control_ctx
*ctrl_ctx
;
1763 struct xhci_ep_ctx
*ep_ctx
;
1764 struct xhci_slot_ctx
*slot_ctx
;
1767 ctrl_ctx
= xhci_get_input_control_ctx(virt_dev
->in_ctx
);
1769 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
1774 /* When a device's add flag and drop flag are zero, any subsequent
1775 * configure endpoint command will leave that endpoint's state
1776 * untouched. Make sure we don't leave any old state in the input
1777 * endpoint contexts.
1779 ctrl_ctx
->drop_flags
= 0;
1780 ctrl_ctx
->add_flags
= 0;
1781 slot_ctx
= xhci_get_slot_ctx(xhci
, virt_dev
->in_ctx
);
1782 slot_ctx
->dev_info
&= cpu_to_le32(~LAST_CTX_MASK
);
1783 /* Endpoint 0 is always valid */
1784 slot_ctx
->dev_info
|= cpu_to_le32(LAST_CTX(1));
1785 for (i
= 1; i
< 31; i
++) {
1786 ep_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->in_ctx
, i
);
1787 ep_ctx
->ep_info
= 0;
1788 ep_ctx
->ep_info2
= 0;
1790 ep_ctx
->tx_info
= 0;
1794 static int xhci_configure_endpoint_result(struct xhci_hcd
*xhci
,
1795 struct usb_device
*udev
, u32
*cmd_status
)
1799 switch (*cmd_status
) {
1800 case COMP_COMMAND_ABORTED
:
1802 xhci_warn(xhci
, "Timeout while waiting for configure endpoint command\n");
1805 case COMP_RESOURCE_ERROR
:
1806 dev_warn(&udev
->dev
,
1807 "Not enough host controller resources for new device state.\n");
1809 /* FIXME: can we allocate more resources for the HC? */
1811 case COMP_BANDWIDTH_ERROR
:
1812 case COMP_SECONDARY_BANDWIDTH_ERROR
:
1813 dev_warn(&udev
->dev
,
1814 "Not enough bandwidth for new device state.\n");
1816 /* FIXME: can we go back to the old state? */
1818 case COMP_TRB_ERROR
:
1819 /* the HCD set up something wrong */
1820 dev_warn(&udev
->dev
, "ERROR: Endpoint drop flag = 0, "
1822 "and endpoint is not disabled.\n");
1825 case COMP_INCOMPATIBLE_DEVICE_ERROR
:
1826 dev_warn(&udev
->dev
,
1827 "ERROR: Incompatible device for endpoint configure command.\n");
1831 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
1832 "Successful Endpoint Configure command");
1836 xhci_err(xhci
, "ERROR: unexpected command completion code 0x%x.\n",
1844 static int xhci_evaluate_context_result(struct xhci_hcd
*xhci
,
1845 struct usb_device
*udev
, u32
*cmd_status
)
1848 struct xhci_virt_device
*virt_dev
= xhci
->devs
[udev
->slot_id
];
1850 switch (*cmd_status
) {
1851 case COMP_COMMAND_ABORTED
:
1853 xhci_warn(xhci
, "Timeout while waiting for evaluate context command\n");
1856 case COMP_PARAMETER_ERROR
:
1857 dev_warn(&udev
->dev
,
1858 "WARN: xHCI driver setup invalid evaluate context command.\n");
1861 case COMP_SLOT_NOT_ENABLED_ERROR
:
1862 dev_warn(&udev
->dev
,
1863 "WARN: slot not enabled for evaluate context command.\n");
1866 case COMP_CONTEXT_STATE_ERROR
:
1867 dev_warn(&udev
->dev
,
1868 "WARN: invalid context state for evaluate context command.\n");
1869 xhci_dbg_ctx(xhci
, virt_dev
->out_ctx
, 1);
1872 case COMP_INCOMPATIBLE_DEVICE_ERROR
:
1873 dev_warn(&udev
->dev
,
1874 "ERROR: Incompatible device for evaluate context command.\n");
1877 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR
:
1878 /* Max Exit Latency too large error */
1879 dev_warn(&udev
->dev
, "WARN: Max Exit Latency too large\n");
1883 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
1884 "Successful evaluate context command");
1888 xhci_err(xhci
, "ERROR: unexpected command completion code 0x%x.\n",
1896 static u32
xhci_count_num_new_endpoints(struct xhci_hcd
*xhci
,
1897 struct xhci_input_control_ctx
*ctrl_ctx
)
1899 u32 valid_add_flags
;
1900 u32 valid_drop_flags
;
1902 /* Ignore the slot flag (bit 0), and the default control endpoint flag
1903 * (bit 1). The default control endpoint is added during the Address
1904 * Device command and is never removed until the slot is disabled.
1906 valid_add_flags
= le32_to_cpu(ctrl_ctx
->add_flags
) >> 2;
1907 valid_drop_flags
= le32_to_cpu(ctrl_ctx
->drop_flags
) >> 2;
1909 /* Use hweight32 to count the number of ones in the add flags, or
1910 * number of endpoints added. Don't count endpoints that are changed
1911 * (both added and dropped).
1913 return hweight32(valid_add_flags
) -
1914 hweight32(valid_add_flags
& valid_drop_flags
);
1917 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd
*xhci
,
1918 struct xhci_input_control_ctx
*ctrl_ctx
)
1920 u32 valid_add_flags
;
1921 u32 valid_drop_flags
;
1923 valid_add_flags
= le32_to_cpu(ctrl_ctx
->add_flags
) >> 2;
1924 valid_drop_flags
= le32_to_cpu(ctrl_ctx
->drop_flags
) >> 2;
1926 return hweight32(valid_drop_flags
) -
1927 hweight32(valid_add_flags
& valid_drop_flags
);
1931 * We need to reserve the new number of endpoints before the configure endpoint
1932 * command completes. We can't subtract the dropped endpoints from the number
1933 * of active endpoints until the command completes because we can oversubscribe
1934 * the host in this case:
1936 * - the first configure endpoint command drops more endpoints than it adds
1937 * - a second configure endpoint command that adds more endpoints is queued
1938 * - the first configure endpoint command fails, so the config is unchanged
1939 * - the second command may succeed, even though there isn't enough resources
1941 * Must be called with xhci->lock held.
1943 static int xhci_reserve_host_resources(struct xhci_hcd
*xhci
,
1944 struct xhci_input_control_ctx
*ctrl_ctx
)
1948 added_eps
= xhci_count_num_new_endpoints(xhci
, ctrl_ctx
);
1949 if (xhci
->num_active_eps
+ added_eps
> xhci
->limit_active_eps
) {
1950 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
1951 "Not enough ep ctxs: "
1952 "%u active, need to add %u, limit is %u.",
1953 xhci
->num_active_eps
, added_eps
,
1954 xhci
->limit_active_eps
);
1957 xhci
->num_active_eps
+= added_eps
;
1958 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
1959 "Adding %u ep ctxs, %u now active.", added_eps
,
1960 xhci
->num_active_eps
);
1965 * The configure endpoint was failed by the xHC for some other reason, so we
1966 * need to revert the resources that failed configuration would have used.
1968 * Must be called with xhci->lock held.
1970 static void xhci_free_host_resources(struct xhci_hcd
*xhci
,
1971 struct xhci_input_control_ctx
*ctrl_ctx
)
1975 num_failed_eps
= xhci_count_num_new_endpoints(xhci
, ctrl_ctx
);
1976 xhci
->num_active_eps
-= num_failed_eps
;
1977 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
1978 "Removing %u failed ep ctxs, %u now active.",
1980 xhci
->num_active_eps
);
1984 * Now that the command has completed, clean up the active endpoint count by
1985 * subtracting out the endpoints that were dropped (but not changed).
1987 * Must be called with xhci->lock held.
1989 static void xhci_finish_resource_reservation(struct xhci_hcd
*xhci
,
1990 struct xhci_input_control_ctx
*ctrl_ctx
)
1992 u32 num_dropped_eps
;
1994 num_dropped_eps
= xhci_count_num_dropped_endpoints(xhci
, ctrl_ctx
);
1995 xhci
->num_active_eps
-= num_dropped_eps
;
1996 if (num_dropped_eps
)
1997 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
1998 "Removing %u dropped ep ctxs, %u now active.",
2000 xhci
->num_active_eps
);
2003 static unsigned int xhci_get_block_size(struct usb_device
*udev
)
2005 switch (udev
->speed
) {
2007 case USB_SPEED_FULL
:
2009 case USB_SPEED_HIGH
:
2011 case USB_SPEED_SUPER
:
2012 case USB_SPEED_SUPER_PLUS
:
2014 case USB_SPEED_UNKNOWN
:
2015 case USB_SPEED_WIRELESS
:
2017 /* Should never happen */
2023 xhci_get_largest_overhead(struct xhci_interval_bw
*interval_bw
)
2025 if (interval_bw
->overhead
[LS_OVERHEAD_TYPE
])
2027 if (interval_bw
->overhead
[FS_OVERHEAD_TYPE
])
2032 /* If we are changing a LS/FS device under a HS hub,
2033 * make sure (if we are activating a new TT) that the HS bus has enough
2034 * bandwidth for this new TT.
2036 static int xhci_check_tt_bw_table(struct xhci_hcd
*xhci
,
2037 struct xhci_virt_device
*virt_dev
,
2040 struct xhci_interval_bw_table
*bw_table
;
2041 struct xhci_tt_bw_info
*tt_info
;
2043 /* Find the bandwidth table for the root port this TT is attached to. */
2044 bw_table
= &xhci
->rh_bw
[virt_dev
->real_port
- 1].bw_table
;
2045 tt_info
= virt_dev
->tt_info
;
2046 /* If this TT already had active endpoints, the bandwidth for this TT
2047 * has already been added. Removing all periodic endpoints (and thus
2048 * making the TT enactive) will only decrease the bandwidth used.
2052 if (old_active_eps
== 0 && tt_info
->active_eps
!= 0) {
2053 if (bw_table
->bw_used
+ TT_HS_OVERHEAD
> HS_BW_LIMIT
)
2057 /* Not sure why we would have no new active endpoints...
2059 * Maybe because of an Evaluate Context change for a hub update or a
2060 * control endpoint 0 max packet size change?
2061 * FIXME: skip the bandwidth calculation in that case.
2066 static int xhci_check_ss_bw(struct xhci_hcd
*xhci
,
2067 struct xhci_virt_device
*virt_dev
)
2069 unsigned int bw_reserved
;
2071 bw_reserved
= DIV_ROUND_UP(SS_BW_RESERVED
*SS_BW_LIMIT_IN
, 100);
2072 if (virt_dev
->bw_table
->ss_bw_in
> (SS_BW_LIMIT_IN
- bw_reserved
))
2075 bw_reserved
= DIV_ROUND_UP(SS_BW_RESERVED
*SS_BW_LIMIT_OUT
, 100);
2076 if (virt_dev
->bw_table
->ss_bw_out
> (SS_BW_LIMIT_OUT
- bw_reserved
))
2083 * This algorithm is a very conservative estimate of the worst-case scheduling
2084 * scenario for any one interval. The hardware dynamically schedules the
2085 * packets, so we can't tell which microframe could be the limiting factor in
2086 * the bandwidth scheduling. This only takes into account periodic endpoints.
2088 * Obviously, we can't solve an NP complete problem to find the minimum worst
2089 * case scenario. Instead, we come up with an estimate that is no less than
2090 * the worst case bandwidth used for any one microframe, but may be an
2093 * We walk the requirements for each endpoint by interval, starting with the
2094 * smallest interval, and place packets in the schedule where there is only one
2095 * possible way to schedule packets for that interval. In order to simplify
2096 * this algorithm, we record the largest max packet size for each interval, and
2097 * assume all packets will be that size.
2099 * For interval 0, we obviously must schedule all packets for each interval.
2100 * The bandwidth for interval 0 is just the amount of data to be transmitted
2101 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2102 * the number of packets).
2104 * For interval 1, we have two possible microframes to schedule those packets
2105 * in. For this algorithm, if we can schedule the same number of packets for
2106 * each possible scheduling opportunity (each microframe), we will do so. The
2107 * remaining number of packets will be saved to be transmitted in the gaps in
2108 * the next interval's scheduling sequence.
2110 * As we move those remaining packets to be scheduled with interval 2 packets,
2111 * we have to double the number of remaining packets to transmit. This is
2112 * because the intervals are actually powers of 2, and we would be transmitting
2113 * the previous interval's packets twice in this interval. We also have to be
2114 * sure that when we look at the largest max packet size for this interval, we
2115 * also look at the largest max packet size for the remaining packets and take
2116 * the greater of the two.
2118 * The algorithm continues to evenly distribute packets in each scheduling
2119 * opportunity, and push the remaining packets out, until we get to the last
2120 * interval. Then those packets and their associated overhead are just added
2121 * to the bandwidth used.
2123 static int xhci_check_bw_table(struct xhci_hcd
*xhci
,
2124 struct xhci_virt_device
*virt_dev
,
2127 unsigned int bw_reserved
;
2128 unsigned int max_bandwidth
;
2129 unsigned int bw_used
;
2130 unsigned int block_size
;
2131 struct xhci_interval_bw_table
*bw_table
;
2132 unsigned int packet_size
= 0;
2133 unsigned int overhead
= 0;
2134 unsigned int packets_transmitted
= 0;
2135 unsigned int packets_remaining
= 0;
2138 if (virt_dev
->udev
->speed
>= USB_SPEED_SUPER
)
2139 return xhci_check_ss_bw(xhci
, virt_dev
);
2141 if (virt_dev
->udev
->speed
== USB_SPEED_HIGH
) {
2142 max_bandwidth
= HS_BW_LIMIT
;
2143 /* Convert percent of bus BW reserved to blocks reserved */
2144 bw_reserved
= DIV_ROUND_UP(HS_BW_RESERVED
* max_bandwidth
, 100);
2146 max_bandwidth
= FS_BW_LIMIT
;
2147 bw_reserved
= DIV_ROUND_UP(FS_BW_RESERVED
* max_bandwidth
, 100);
2150 bw_table
= virt_dev
->bw_table
;
2151 /* We need to translate the max packet size and max ESIT payloads into
2152 * the units the hardware uses.
2154 block_size
= xhci_get_block_size(virt_dev
->udev
);
2156 /* If we are manipulating a LS/FS device under a HS hub, double check
2157 * that the HS bus has enough bandwidth if we are activing a new TT.
2159 if (virt_dev
->tt_info
) {
2160 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
2161 "Recalculating BW for rootport %u",
2162 virt_dev
->real_port
);
2163 if (xhci_check_tt_bw_table(xhci
, virt_dev
, old_active_eps
)) {
2164 xhci_warn(xhci
, "Not enough bandwidth on HS bus for "
2165 "newly activated TT.\n");
2168 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
2169 "Recalculating BW for TT slot %u port %u",
2170 virt_dev
->tt_info
->slot_id
,
2171 virt_dev
->tt_info
->ttport
);
2173 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
2174 "Recalculating BW for rootport %u",
2175 virt_dev
->real_port
);
2178 /* Add in how much bandwidth will be used for interval zero, or the
2179 * rounded max ESIT payload + number of packets * largest overhead.
2181 bw_used
= DIV_ROUND_UP(bw_table
->interval0_esit_payload
, block_size
) +
2182 bw_table
->interval_bw
[0].num_packets
*
2183 xhci_get_largest_overhead(&bw_table
->interval_bw
[0]);
2185 for (i
= 1; i
< XHCI_MAX_INTERVAL
; i
++) {
2186 unsigned int bw_added
;
2187 unsigned int largest_mps
;
2188 unsigned int interval_overhead
;
2191 * How many packets could we transmit in this interval?
2192 * If packets didn't fit in the previous interval, we will need
2193 * to transmit that many packets twice within this interval.
2195 packets_remaining
= 2 * packets_remaining
+
2196 bw_table
->interval_bw
[i
].num_packets
;
2198 /* Find the largest max packet size of this or the previous
2201 if (list_empty(&bw_table
->interval_bw
[i
].endpoints
))
2204 struct xhci_virt_ep
*virt_ep
;
2205 struct list_head
*ep_entry
;
2207 ep_entry
= bw_table
->interval_bw
[i
].endpoints
.next
;
2208 virt_ep
= list_entry(ep_entry
,
2209 struct xhci_virt_ep
, bw_endpoint_list
);
2210 /* Convert to blocks, rounding up */
2211 largest_mps
= DIV_ROUND_UP(
2212 virt_ep
->bw_info
.max_packet_size
,
2215 if (largest_mps
> packet_size
)
2216 packet_size
= largest_mps
;
2218 /* Use the larger overhead of this or the previous interval. */
2219 interval_overhead
= xhci_get_largest_overhead(
2220 &bw_table
->interval_bw
[i
]);
2221 if (interval_overhead
> overhead
)
2222 overhead
= interval_overhead
;
2224 /* How many packets can we evenly distribute across
2225 * (1 << (i + 1)) possible scheduling opportunities?
2227 packets_transmitted
= packets_remaining
>> (i
+ 1);
2229 /* Add in the bandwidth used for those scheduled packets */
2230 bw_added
= packets_transmitted
* (overhead
+ packet_size
);
2232 /* How many packets do we have remaining to transmit? */
2233 packets_remaining
= packets_remaining
% (1 << (i
+ 1));
2235 /* What largest max packet size should those packets have? */
2236 /* If we've transmitted all packets, don't carry over the
2237 * largest packet size.
2239 if (packets_remaining
== 0) {
2242 } else if (packets_transmitted
> 0) {
2243 /* Otherwise if we do have remaining packets, and we've
2244 * scheduled some packets in this interval, take the
2245 * largest max packet size from endpoints with this
2248 packet_size
= largest_mps
;
2249 overhead
= interval_overhead
;
2251 /* Otherwise carry over packet_size and overhead from the last
2252 * time we had a remainder.
2254 bw_used
+= bw_added
;
2255 if (bw_used
> max_bandwidth
) {
2256 xhci_warn(xhci
, "Not enough bandwidth. "
2257 "Proposed: %u, Max: %u\n",
2258 bw_used
, max_bandwidth
);
2263 * Ok, we know we have some packets left over after even-handedly
2264 * scheduling interval 15. We don't know which microframes they will
2265 * fit into, so we over-schedule and say they will be scheduled every
2268 if (packets_remaining
> 0)
2269 bw_used
+= overhead
+ packet_size
;
2271 if (!virt_dev
->tt_info
&& virt_dev
->udev
->speed
== USB_SPEED_HIGH
) {
2272 unsigned int port_index
= virt_dev
->real_port
- 1;
2274 /* OK, we're manipulating a HS device attached to a
2275 * root port bandwidth domain. Include the number of active TTs
2276 * in the bandwidth used.
2278 bw_used
+= TT_HS_OVERHEAD
*
2279 xhci
->rh_bw
[port_index
].num_active_tts
;
2282 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
2283 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2284 "Available: %u " "percent",
2285 bw_used
, max_bandwidth
, bw_reserved
,
2286 (max_bandwidth
- bw_used
- bw_reserved
) * 100 /
2289 bw_used
+= bw_reserved
;
2290 if (bw_used
> max_bandwidth
) {
2291 xhci_warn(xhci
, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2292 bw_used
, max_bandwidth
);
2296 bw_table
->bw_used
= bw_used
;
2300 static bool xhci_is_async_ep(unsigned int ep_type
)
2302 return (ep_type
!= ISOC_OUT_EP
&& ep_type
!= INT_OUT_EP
&&
2303 ep_type
!= ISOC_IN_EP
&&
2304 ep_type
!= INT_IN_EP
);
2307 static bool xhci_is_sync_in_ep(unsigned int ep_type
)
2309 return (ep_type
== ISOC_IN_EP
|| ep_type
== INT_IN_EP
);
2312 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info
*ep_bw
)
2314 unsigned int mps
= DIV_ROUND_UP(ep_bw
->max_packet_size
, SS_BLOCK
);
2316 if (ep_bw
->ep_interval
== 0)
2317 return SS_OVERHEAD_BURST
+
2318 (ep_bw
->mult
* ep_bw
->num_packets
*
2319 (SS_OVERHEAD
+ mps
));
2320 return DIV_ROUND_UP(ep_bw
->mult
* ep_bw
->num_packets
*
2321 (SS_OVERHEAD
+ mps
+ SS_OVERHEAD_BURST
),
2322 1 << ep_bw
->ep_interval
);
2326 void xhci_drop_ep_from_interval_table(struct xhci_hcd
*xhci
,
2327 struct xhci_bw_info
*ep_bw
,
2328 struct xhci_interval_bw_table
*bw_table
,
2329 struct usb_device
*udev
,
2330 struct xhci_virt_ep
*virt_ep
,
2331 struct xhci_tt_bw_info
*tt_info
)
2333 struct xhci_interval_bw
*interval_bw
;
2334 int normalized_interval
;
2336 if (xhci_is_async_ep(ep_bw
->type
))
2339 if (udev
->speed
>= USB_SPEED_SUPER
) {
2340 if (xhci_is_sync_in_ep(ep_bw
->type
))
2341 xhci
->devs
[udev
->slot_id
]->bw_table
->ss_bw_in
-=
2342 xhci_get_ss_bw_consumed(ep_bw
);
2344 xhci
->devs
[udev
->slot_id
]->bw_table
->ss_bw_out
-=
2345 xhci_get_ss_bw_consumed(ep_bw
);
2349 /* SuperSpeed endpoints never get added to intervals in the table, so
2350 * this check is only valid for HS/FS/LS devices.
2352 if (list_empty(&virt_ep
->bw_endpoint_list
))
2354 /* For LS/FS devices, we need to translate the interval expressed in
2355 * microframes to frames.
2357 if (udev
->speed
== USB_SPEED_HIGH
)
2358 normalized_interval
= ep_bw
->ep_interval
;
2360 normalized_interval
= ep_bw
->ep_interval
- 3;
2362 if (normalized_interval
== 0)
2363 bw_table
->interval0_esit_payload
-= ep_bw
->max_esit_payload
;
2364 interval_bw
= &bw_table
->interval_bw
[normalized_interval
];
2365 interval_bw
->num_packets
-= ep_bw
->num_packets
;
2366 switch (udev
->speed
) {
2368 interval_bw
->overhead
[LS_OVERHEAD_TYPE
] -= 1;
2370 case USB_SPEED_FULL
:
2371 interval_bw
->overhead
[FS_OVERHEAD_TYPE
] -= 1;
2373 case USB_SPEED_HIGH
:
2374 interval_bw
->overhead
[HS_OVERHEAD_TYPE
] -= 1;
2376 case USB_SPEED_SUPER
:
2377 case USB_SPEED_SUPER_PLUS
:
2378 case USB_SPEED_UNKNOWN
:
2379 case USB_SPEED_WIRELESS
:
2380 /* Should never happen because only LS/FS/HS endpoints will get
2381 * added to the endpoint list.
2386 tt_info
->active_eps
-= 1;
2387 list_del_init(&virt_ep
->bw_endpoint_list
);
2390 static void xhci_add_ep_to_interval_table(struct xhci_hcd
*xhci
,
2391 struct xhci_bw_info
*ep_bw
,
2392 struct xhci_interval_bw_table
*bw_table
,
2393 struct usb_device
*udev
,
2394 struct xhci_virt_ep
*virt_ep
,
2395 struct xhci_tt_bw_info
*tt_info
)
2397 struct xhci_interval_bw
*interval_bw
;
2398 struct xhci_virt_ep
*smaller_ep
;
2399 int normalized_interval
;
2401 if (xhci_is_async_ep(ep_bw
->type
))
2404 if (udev
->speed
== USB_SPEED_SUPER
) {
2405 if (xhci_is_sync_in_ep(ep_bw
->type
))
2406 xhci
->devs
[udev
->slot_id
]->bw_table
->ss_bw_in
+=
2407 xhci_get_ss_bw_consumed(ep_bw
);
2409 xhci
->devs
[udev
->slot_id
]->bw_table
->ss_bw_out
+=
2410 xhci_get_ss_bw_consumed(ep_bw
);
2414 /* For LS/FS devices, we need to translate the interval expressed in
2415 * microframes to frames.
2417 if (udev
->speed
== USB_SPEED_HIGH
)
2418 normalized_interval
= ep_bw
->ep_interval
;
2420 normalized_interval
= ep_bw
->ep_interval
- 3;
2422 if (normalized_interval
== 0)
2423 bw_table
->interval0_esit_payload
+= ep_bw
->max_esit_payload
;
2424 interval_bw
= &bw_table
->interval_bw
[normalized_interval
];
2425 interval_bw
->num_packets
+= ep_bw
->num_packets
;
2426 switch (udev
->speed
) {
2428 interval_bw
->overhead
[LS_OVERHEAD_TYPE
] += 1;
2430 case USB_SPEED_FULL
:
2431 interval_bw
->overhead
[FS_OVERHEAD_TYPE
] += 1;
2433 case USB_SPEED_HIGH
:
2434 interval_bw
->overhead
[HS_OVERHEAD_TYPE
] += 1;
2436 case USB_SPEED_SUPER
:
2437 case USB_SPEED_SUPER_PLUS
:
2438 case USB_SPEED_UNKNOWN
:
2439 case USB_SPEED_WIRELESS
:
2440 /* Should never happen because only LS/FS/HS endpoints will get
2441 * added to the endpoint list.
2447 tt_info
->active_eps
+= 1;
2448 /* Insert the endpoint into the list, largest max packet size first. */
2449 list_for_each_entry(smaller_ep
, &interval_bw
->endpoints
,
2451 if (ep_bw
->max_packet_size
>=
2452 smaller_ep
->bw_info
.max_packet_size
) {
2453 /* Add the new ep before the smaller endpoint */
2454 list_add_tail(&virt_ep
->bw_endpoint_list
,
2455 &smaller_ep
->bw_endpoint_list
);
2459 /* Add the new endpoint at the end of the list. */
2460 list_add_tail(&virt_ep
->bw_endpoint_list
,
2461 &interval_bw
->endpoints
);
2464 void xhci_update_tt_active_eps(struct xhci_hcd
*xhci
,
2465 struct xhci_virt_device
*virt_dev
,
2468 struct xhci_root_port_bw_info
*rh_bw_info
;
2469 if (!virt_dev
->tt_info
)
2472 rh_bw_info
= &xhci
->rh_bw
[virt_dev
->real_port
- 1];
2473 if (old_active_eps
== 0 &&
2474 virt_dev
->tt_info
->active_eps
!= 0) {
2475 rh_bw_info
->num_active_tts
+= 1;
2476 rh_bw_info
->bw_table
.bw_used
+= TT_HS_OVERHEAD
;
2477 } else if (old_active_eps
!= 0 &&
2478 virt_dev
->tt_info
->active_eps
== 0) {
2479 rh_bw_info
->num_active_tts
-= 1;
2480 rh_bw_info
->bw_table
.bw_used
-= TT_HS_OVERHEAD
;
2484 static int xhci_reserve_bandwidth(struct xhci_hcd
*xhci
,
2485 struct xhci_virt_device
*virt_dev
,
2486 struct xhci_container_ctx
*in_ctx
)
2488 struct xhci_bw_info ep_bw_info
[31];
2490 struct xhci_input_control_ctx
*ctrl_ctx
;
2491 int old_active_eps
= 0;
2493 if (virt_dev
->tt_info
)
2494 old_active_eps
= virt_dev
->tt_info
->active_eps
;
2496 ctrl_ctx
= xhci_get_input_control_ctx(in_ctx
);
2498 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
2503 for (i
= 0; i
< 31; i
++) {
2504 if (!EP_IS_ADDED(ctrl_ctx
, i
) && !EP_IS_DROPPED(ctrl_ctx
, i
))
2507 /* Make a copy of the BW info in case we need to revert this */
2508 memcpy(&ep_bw_info
[i
], &virt_dev
->eps
[i
].bw_info
,
2509 sizeof(ep_bw_info
[i
]));
2510 /* Drop the endpoint from the interval table if the endpoint is
2511 * being dropped or changed.
2513 if (EP_IS_DROPPED(ctrl_ctx
, i
))
2514 xhci_drop_ep_from_interval_table(xhci
,
2515 &virt_dev
->eps
[i
].bw_info
,
2521 /* Overwrite the information stored in the endpoints' bw_info */
2522 xhci_update_bw_info(xhci
, virt_dev
->in_ctx
, ctrl_ctx
, virt_dev
);
2523 for (i
= 0; i
< 31; i
++) {
2524 /* Add any changed or added endpoints to the interval table */
2525 if (EP_IS_ADDED(ctrl_ctx
, i
))
2526 xhci_add_ep_to_interval_table(xhci
,
2527 &virt_dev
->eps
[i
].bw_info
,
2534 if (!xhci_check_bw_table(xhci
, virt_dev
, old_active_eps
)) {
2535 /* Ok, this fits in the bandwidth we have.
2536 * Update the number of active TTs.
2538 xhci_update_tt_active_eps(xhci
, virt_dev
, old_active_eps
);
2542 /* We don't have enough bandwidth for this, revert the stored info. */
2543 for (i
= 0; i
< 31; i
++) {
2544 if (!EP_IS_ADDED(ctrl_ctx
, i
) && !EP_IS_DROPPED(ctrl_ctx
, i
))
2547 /* Drop the new copies of any added or changed endpoints from
2548 * the interval table.
2550 if (EP_IS_ADDED(ctrl_ctx
, i
)) {
2551 xhci_drop_ep_from_interval_table(xhci
,
2552 &virt_dev
->eps
[i
].bw_info
,
2558 /* Revert the endpoint back to its old information */
2559 memcpy(&virt_dev
->eps
[i
].bw_info
, &ep_bw_info
[i
],
2560 sizeof(ep_bw_info
[i
]));
2561 /* Add any changed or dropped endpoints back into the table */
2562 if (EP_IS_DROPPED(ctrl_ctx
, i
))
2563 xhci_add_ep_to_interval_table(xhci
,
2564 &virt_dev
->eps
[i
].bw_info
,
2574 /* Issue a configure endpoint command or evaluate context command
2575 * and wait for it to finish.
2577 static int xhci_configure_endpoint(struct xhci_hcd
*xhci
,
2578 struct usb_device
*udev
,
2579 struct xhci_command
*command
,
2580 bool ctx_change
, bool must_succeed
)
2583 unsigned long flags
;
2584 struct xhci_input_control_ctx
*ctrl_ctx
;
2585 struct xhci_virt_device
*virt_dev
;
2590 spin_lock_irqsave(&xhci
->lock
, flags
);
2591 virt_dev
= xhci
->devs
[udev
->slot_id
];
2593 ctrl_ctx
= xhci_get_input_control_ctx(command
->in_ctx
);
2595 spin_unlock_irqrestore(&xhci
->lock
, flags
);
2596 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
2601 if ((xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
) &&
2602 xhci_reserve_host_resources(xhci
, ctrl_ctx
)) {
2603 spin_unlock_irqrestore(&xhci
->lock
, flags
);
2604 xhci_warn(xhci
, "Not enough host resources, "
2605 "active endpoint contexts = %u\n",
2606 xhci
->num_active_eps
);
2609 if ((xhci
->quirks
& XHCI_SW_BW_CHECKING
) &&
2610 xhci_reserve_bandwidth(xhci
, virt_dev
, command
->in_ctx
)) {
2611 if ((xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
))
2612 xhci_free_host_resources(xhci
, ctrl_ctx
);
2613 spin_unlock_irqrestore(&xhci
->lock
, flags
);
2614 xhci_warn(xhci
, "Not enough bandwidth\n");
2619 ret
= xhci_queue_configure_endpoint(xhci
, command
,
2620 command
->in_ctx
->dma
,
2621 udev
->slot_id
, must_succeed
);
2623 ret
= xhci_queue_evaluate_context(xhci
, command
,
2624 command
->in_ctx
->dma
,
2625 udev
->slot_id
, must_succeed
);
2627 if ((xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
))
2628 xhci_free_host_resources(xhci
, ctrl_ctx
);
2629 spin_unlock_irqrestore(&xhci
->lock
, flags
);
2630 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
2631 "FIXME allocate a new ring segment");
2634 xhci_ring_cmd_db(xhci
);
2635 spin_unlock_irqrestore(&xhci
->lock
, flags
);
2637 /* Wait for the configure endpoint command to complete */
2638 wait_for_completion(command
->completion
);
2641 ret
= xhci_configure_endpoint_result(xhci
, udev
,
2644 ret
= xhci_evaluate_context_result(xhci
, udev
,
2647 if ((xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
)) {
2648 spin_lock_irqsave(&xhci
->lock
, flags
);
2649 /* If the command failed, remove the reserved resources.
2650 * Otherwise, clean up the estimate to include dropped eps.
2653 xhci_free_host_resources(xhci
, ctrl_ctx
);
2655 xhci_finish_resource_reservation(xhci
, ctrl_ctx
);
2656 spin_unlock_irqrestore(&xhci
->lock
, flags
);
2661 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd
*xhci
,
2662 struct xhci_virt_device
*vdev
, int i
)
2664 struct xhci_virt_ep
*ep
= &vdev
->eps
[i
];
2666 if (ep
->ep_state
& EP_HAS_STREAMS
) {
2667 xhci_warn(xhci
, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2668 xhci_get_endpoint_address(i
));
2669 xhci_free_stream_info(xhci
, ep
->stream_info
);
2670 ep
->stream_info
= NULL
;
2671 ep
->ep_state
&= ~EP_HAS_STREAMS
;
2675 /* Called after one or more calls to xhci_add_endpoint() or
2676 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2677 * to call xhci_reset_bandwidth().
2679 * Since we are in the middle of changing either configuration or
2680 * installing a new alt setting, the USB core won't allow URBs to be
2681 * enqueued for any endpoint on the old config or interface. Nothing
2682 * else should be touching the xhci->devs[slot_id] structure, so we
2683 * don't need to take the xhci->lock for manipulating that.
2685 int xhci_check_bandwidth(struct usb_hcd
*hcd
, struct usb_device
*udev
)
2689 struct xhci_hcd
*xhci
;
2690 struct xhci_virt_device
*virt_dev
;
2691 struct xhci_input_control_ctx
*ctrl_ctx
;
2692 struct xhci_slot_ctx
*slot_ctx
;
2693 struct xhci_command
*command
;
2695 ret
= xhci_check_args(hcd
, udev
, NULL
, 0, true, __func__
);
2698 xhci
= hcd_to_xhci(hcd
);
2699 if ((xhci
->xhc_state
& XHCI_STATE_DYING
) ||
2700 (xhci
->xhc_state
& XHCI_STATE_REMOVING
))
2703 xhci_dbg(xhci
, "%s called for udev %p\n", __func__
, udev
);
2704 virt_dev
= xhci
->devs
[udev
->slot_id
];
2706 command
= xhci_alloc_command(xhci
, false, true, GFP_KERNEL
);
2710 command
->in_ctx
= virt_dev
->in_ctx
;
2712 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2713 ctrl_ctx
= xhci_get_input_control_ctx(command
->in_ctx
);
2715 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
2718 goto command_cleanup
;
2720 ctrl_ctx
->add_flags
|= cpu_to_le32(SLOT_FLAG
);
2721 ctrl_ctx
->add_flags
&= cpu_to_le32(~EP0_FLAG
);
2722 ctrl_ctx
->drop_flags
&= cpu_to_le32(~(SLOT_FLAG
| EP0_FLAG
));
2724 /* Don't issue the command if there's no endpoints to update. */
2725 if (ctrl_ctx
->add_flags
== cpu_to_le32(SLOT_FLAG
) &&
2726 ctrl_ctx
->drop_flags
== 0) {
2728 goto command_cleanup
;
2730 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
2731 slot_ctx
= xhci_get_slot_ctx(xhci
, virt_dev
->in_ctx
);
2732 for (i
= 31; i
>= 1; i
--) {
2733 __le32 le32
= cpu_to_le32(BIT(i
));
2735 if ((virt_dev
->eps
[i
-1].ring
&& !(ctrl_ctx
->drop_flags
& le32
))
2736 || (ctrl_ctx
->add_flags
& le32
) || i
== 1) {
2737 slot_ctx
->dev_info
&= cpu_to_le32(~LAST_CTX_MASK
);
2738 slot_ctx
->dev_info
|= cpu_to_le32(LAST_CTX(i
));
2742 xhci_dbg(xhci
, "New Input Control Context:\n");
2743 xhci_dbg_ctx(xhci
, virt_dev
->in_ctx
,
2744 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx
->dev_info
)));
2746 ret
= xhci_configure_endpoint(xhci
, udev
, command
,
2749 /* Callee should call reset_bandwidth() */
2750 goto command_cleanup
;
2752 xhci_dbg(xhci
, "Output context after successful config ep cmd:\n");
2753 xhci_dbg_ctx(xhci
, virt_dev
->out_ctx
,
2754 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx
->dev_info
)));
2756 /* Free any rings that were dropped, but not changed. */
2757 for (i
= 1; i
< 31; i
++) {
2758 if ((le32_to_cpu(ctrl_ctx
->drop_flags
) & (1 << (i
+ 1))) &&
2759 !(le32_to_cpu(ctrl_ctx
->add_flags
) & (1 << (i
+ 1)))) {
2760 xhci_free_or_cache_endpoint_ring(xhci
, virt_dev
, i
);
2761 xhci_check_bw_drop_ep_streams(xhci
, virt_dev
, i
);
2764 xhci_zero_in_ctx(xhci
, virt_dev
);
2766 * Install any rings for completely new endpoints or changed endpoints,
2767 * and free or cache any old rings from changed endpoints.
2769 for (i
= 1; i
< 31; i
++) {
2770 if (!virt_dev
->eps
[i
].new_ring
)
2772 /* Only cache or free the old ring if it exists.
2773 * It may not if this is the first add of an endpoint.
2775 if (virt_dev
->eps
[i
].ring
) {
2776 xhci_free_or_cache_endpoint_ring(xhci
, virt_dev
, i
);
2778 xhci_check_bw_drop_ep_streams(xhci
, virt_dev
, i
);
2779 virt_dev
->eps
[i
].ring
= virt_dev
->eps
[i
].new_ring
;
2780 virt_dev
->eps
[i
].new_ring
= NULL
;
2783 kfree(command
->completion
);
2789 void xhci_reset_bandwidth(struct usb_hcd
*hcd
, struct usb_device
*udev
)
2791 struct xhci_hcd
*xhci
;
2792 struct xhci_virt_device
*virt_dev
;
2795 ret
= xhci_check_args(hcd
, udev
, NULL
, 0, true, __func__
);
2798 xhci
= hcd_to_xhci(hcd
);
2800 xhci_dbg(xhci
, "%s called for udev %p\n", __func__
, udev
);
2801 virt_dev
= xhci
->devs
[udev
->slot_id
];
2802 /* Free any rings allocated for added endpoints */
2803 for (i
= 0; i
< 31; i
++) {
2804 if (virt_dev
->eps
[i
].new_ring
) {
2805 xhci_ring_free(xhci
, virt_dev
->eps
[i
].new_ring
);
2806 virt_dev
->eps
[i
].new_ring
= NULL
;
2809 xhci_zero_in_ctx(xhci
, virt_dev
);
2812 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd
*xhci
,
2813 struct xhci_container_ctx
*in_ctx
,
2814 struct xhci_container_ctx
*out_ctx
,
2815 struct xhci_input_control_ctx
*ctrl_ctx
,
2816 u32 add_flags
, u32 drop_flags
)
2818 ctrl_ctx
->add_flags
= cpu_to_le32(add_flags
);
2819 ctrl_ctx
->drop_flags
= cpu_to_le32(drop_flags
);
2820 xhci_slot_copy(xhci
, in_ctx
, out_ctx
);
2821 ctrl_ctx
->add_flags
|= cpu_to_le32(SLOT_FLAG
);
2823 xhci_dbg(xhci
, "Input Context:\n");
2824 xhci_dbg_ctx(xhci
, in_ctx
, xhci_last_valid_endpoint(add_flags
));
2827 static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd
*xhci
,
2828 unsigned int slot_id
, unsigned int ep_index
,
2829 struct xhci_dequeue_state
*deq_state
)
2831 struct xhci_input_control_ctx
*ctrl_ctx
;
2832 struct xhci_container_ctx
*in_ctx
;
2833 struct xhci_ep_ctx
*ep_ctx
;
2837 in_ctx
= xhci
->devs
[slot_id
]->in_ctx
;
2838 ctrl_ctx
= xhci_get_input_control_ctx(in_ctx
);
2840 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
2845 xhci_endpoint_copy(xhci
, xhci
->devs
[slot_id
]->in_ctx
,
2846 xhci
->devs
[slot_id
]->out_ctx
, ep_index
);
2847 ep_ctx
= xhci_get_ep_ctx(xhci
, in_ctx
, ep_index
);
2848 addr
= xhci_trb_virt_to_dma(deq_state
->new_deq_seg
,
2849 deq_state
->new_deq_ptr
);
2851 xhci_warn(xhci
, "WARN Cannot submit config ep after "
2852 "reset ep command\n");
2853 xhci_warn(xhci
, "WARN deq seg = %p, deq ptr = %p\n",
2854 deq_state
->new_deq_seg
,
2855 deq_state
->new_deq_ptr
);
2858 ep_ctx
->deq
= cpu_to_le64(addr
| deq_state
->new_cycle_state
);
2860 added_ctxs
= xhci_get_endpoint_flag_from_index(ep_index
);
2861 xhci_setup_input_ctx_for_config_ep(xhci
, xhci
->devs
[slot_id
]->in_ctx
,
2862 xhci
->devs
[slot_id
]->out_ctx
, ctrl_ctx
,
2863 added_ctxs
, added_ctxs
);
2866 void xhci_cleanup_stalled_ring(struct xhci_hcd
*xhci
,
2867 unsigned int ep_index
, struct xhci_td
*td
)
2869 struct xhci_dequeue_state deq_state
;
2870 struct xhci_virt_ep
*ep
;
2871 struct usb_device
*udev
= td
->urb
->dev
;
2873 xhci_dbg_trace(xhci
, trace_xhci_dbg_reset_ep
,
2874 "Cleaning up stalled endpoint ring");
2875 ep
= &xhci
->devs
[udev
->slot_id
]->eps
[ep_index
];
2876 /* We need to move the HW's dequeue pointer past this TD,
2877 * or it will attempt to resend it on the next doorbell ring.
2879 xhci_find_new_dequeue_state(xhci
, udev
->slot_id
,
2880 ep_index
, ep
->stopped_stream
, td
, &deq_state
);
2882 if (!deq_state
.new_deq_ptr
|| !deq_state
.new_deq_seg
)
2885 /* HW with the reset endpoint quirk will use the saved dequeue state to
2886 * issue a configure endpoint command later.
2888 if (!(xhci
->quirks
& XHCI_RESET_EP_QUIRK
)) {
2889 xhci_dbg_trace(xhci
, trace_xhci_dbg_reset_ep
,
2890 "Queueing new dequeue state");
2891 xhci_queue_new_dequeue_state(xhci
, udev
->slot_id
,
2892 ep_index
, ep
->stopped_stream
, &deq_state
);
2894 /* Better hope no one uses the input context between now and the
2895 * reset endpoint completion!
2896 * XXX: No idea how this hardware will react when stream rings
2899 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
2900 "Setting up input context for "
2901 "configure endpoint command");
2902 xhci_setup_input_ctx_for_quirk(xhci
, udev
->slot_id
,
2903 ep_index
, &deq_state
);
2907 /* Called when clearing halted device. The core should have sent the control
2908 * message to clear the device halt condition. The host side of the halt should
2909 * already be cleared with a reset endpoint command issued when the STALL tx
2910 * event was received.
2912 * Context: in_interrupt
2915 void xhci_endpoint_reset(struct usb_hcd
*hcd
,
2916 struct usb_host_endpoint
*ep
)
2918 struct xhci_hcd
*xhci
;
2920 xhci
= hcd_to_xhci(hcd
);
2923 * We might need to implement the config ep cmd in xhci 4.8.1 note:
2924 * The Reset Endpoint Command may only be issued to endpoints in the
2925 * Halted state. If software wishes reset the Data Toggle or Sequence
2926 * Number of an endpoint that isn't in the Halted state, then software
2927 * may issue a Configure Endpoint Command with the Drop and Add bits set
2928 * for the target endpoint. that is in the Stopped state.
2931 /* For now just print debug to follow the situation */
2932 xhci_dbg(xhci
, "Endpoint 0x%x ep reset callback called\n",
2933 ep
->desc
.bEndpointAddress
);
2936 static int xhci_check_streams_endpoint(struct xhci_hcd
*xhci
,
2937 struct usb_device
*udev
, struct usb_host_endpoint
*ep
,
2938 unsigned int slot_id
)
2941 unsigned int ep_index
;
2942 unsigned int ep_state
;
2946 ret
= xhci_check_args(xhci_to_hcd(xhci
), udev
, ep
, 1, true, __func__
);
2949 if (usb_ss_max_streams(&ep
->ss_ep_comp
) == 0) {
2950 xhci_warn(xhci
, "WARN: SuperSpeed Endpoint Companion"
2951 " descriptor for ep 0x%x does not support streams\n",
2952 ep
->desc
.bEndpointAddress
);
2956 ep_index
= xhci_get_endpoint_index(&ep
->desc
);
2957 ep_state
= xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
;
2958 if (ep_state
& EP_HAS_STREAMS
||
2959 ep_state
& EP_GETTING_STREAMS
) {
2960 xhci_warn(xhci
, "WARN: SuperSpeed bulk endpoint 0x%x "
2961 "already has streams set up.\n",
2962 ep
->desc
.bEndpointAddress
);
2963 xhci_warn(xhci
, "Send email to xHCI maintainer and ask for "
2964 "dynamic stream context array reallocation.\n");
2967 if (!list_empty(&xhci
->devs
[slot_id
]->eps
[ep_index
].ring
->td_list
)) {
2968 xhci_warn(xhci
, "Cannot setup streams for SuperSpeed bulk "
2969 "endpoint 0x%x; URBs are pending.\n",
2970 ep
->desc
.bEndpointAddress
);
2976 static void xhci_calculate_streams_entries(struct xhci_hcd
*xhci
,
2977 unsigned int *num_streams
, unsigned int *num_stream_ctxs
)
2979 unsigned int max_streams
;
2981 /* The stream context array size must be a power of two */
2982 *num_stream_ctxs
= roundup_pow_of_two(*num_streams
);
2984 * Find out how many primary stream array entries the host controller
2985 * supports. Later we may use secondary stream arrays (similar to 2nd
2986 * level page entries), but that's an optional feature for xHCI host
2987 * controllers. xHCs must support at least 4 stream IDs.
2989 max_streams
= HCC_MAX_PSA(xhci
->hcc_params
);
2990 if (*num_stream_ctxs
> max_streams
) {
2991 xhci_dbg(xhci
, "xHCI HW only supports %u stream ctx entries.\n",
2993 *num_stream_ctxs
= max_streams
;
2994 *num_streams
= max_streams
;
2998 /* Returns an error code if one of the endpoint already has streams.
2999 * This does not change any data structures, it only checks and gathers
3002 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd
*xhci
,
3003 struct usb_device
*udev
,
3004 struct usb_host_endpoint
**eps
, unsigned int num_eps
,
3005 unsigned int *num_streams
, u32
*changed_ep_bitmask
)
3007 unsigned int max_streams
;
3008 unsigned int endpoint_flag
;
3012 for (i
= 0; i
< num_eps
; i
++) {
3013 ret
= xhci_check_streams_endpoint(xhci
, udev
,
3014 eps
[i
], udev
->slot_id
);
3018 max_streams
= usb_ss_max_streams(&eps
[i
]->ss_ep_comp
);
3019 if (max_streams
< (*num_streams
- 1)) {
3020 xhci_dbg(xhci
, "Ep 0x%x only supports %u stream IDs.\n",
3021 eps
[i
]->desc
.bEndpointAddress
,
3023 *num_streams
= max_streams
+1;
3026 endpoint_flag
= xhci_get_endpoint_flag(&eps
[i
]->desc
);
3027 if (*changed_ep_bitmask
& endpoint_flag
)
3029 *changed_ep_bitmask
|= endpoint_flag
;
3034 static u32
xhci_calculate_no_streams_bitmask(struct xhci_hcd
*xhci
,
3035 struct usb_device
*udev
,
3036 struct usb_host_endpoint
**eps
, unsigned int num_eps
)
3038 u32 changed_ep_bitmask
= 0;
3039 unsigned int slot_id
;
3040 unsigned int ep_index
;
3041 unsigned int ep_state
;
3044 slot_id
= udev
->slot_id
;
3045 if (!xhci
->devs
[slot_id
])
3048 for (i
= 0; i
< num_eps
; i
++) {
3049 ep_index
= xhci_get_endpoint_index(&eps
[i
]->desc
);
3050 ep_state
= xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
;
3051 /* Are streams already being freed for the endpoint? */
3052 if (ep_state
& EP_GETTING_NO_STREAMS
) {
3053 xhci_warn(xhci
, "WARN Can't disable streams for "
3055 "streams are being disabled already\n",
3056 eps
[i
]->desc
.bEndpointAddress
);
3059 /* Are there actually any streams to free? */
3060 if (!(ep_state
& EP_HAS_STREAMS
) &&
3061 !(ep_state
& EP_GETTING_STREAMS
)) {
3062 xhci_warn(xhci
, "WARN Can't disable streams for "
3064 "streams are already disabled!\n",
3065 eps
[i
]->desc
.bEndpointAddress
);
3066 xhci_warn(xhci
, "WARN xhci_free_streams() called "
3067 "with non-streams endpoint\n");
3070 changed_ep_bitmask
|= xhci_get_endpoint_flag(&eps
[i
]->desc
);
3072 return changed_ep_bitmask
;
3076 * The USB device drivers use this function (through the HCD interface in USB
3077 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3078 * coordinate mass storage command queueing across multiple endpoints (basically
3079 * a stream ID == a task ID).
3081 * Setting up streams involves allocating the same size stream context array
3082 * for each endpoint and issuing a configure endpoint command for all endpoints.
3084 * Don't allow the call to succeed if one endpoint only supports one stream
3085 * (which means it doesn't support streams at all).
3087 * Drivers may get less stream IDs than they asked for, if the host controller
3088 * hardware or endpoints claim they can't support the number of requested
3091 int xhci_alloc_streams(struct usb_hcd
*hcd
, struct usb_device
*udev
,
3092 struct usb_host_endpoint
**eps
, unsigned int num_eps
,
3093 unsigned int num_streams
, gfp_t mem_flags
)
3096 struct xhci_hcd
*xhci
;
3097 struct xhci_virt_device
*vdev
;
3098 struct xhci_command
*config_cmd
;
3099 struct xhci_input_control_ctx
*ctrl_ctx
;
3100 unsigned int ep_index
;
3101 unsigned int num_stream_ctxs
;
3102 unsigned int max_packet
;
3103 unsigned long flags
;
3104 u32 changed_ep_bitmask
= 0;
3109 /* Add one to the number of streams requested to account for
3110 * stream 0 that is reserved for xHCI usage.
3113 xhci
= hcd_to_xhci(hcd
);
3114 xhci_dbg(xhci
, "Driver wants %u stream IDs (including stream 0).\n",
3117 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3118 if ((xhci
->quirks
& XHCI_BROKEN_STREAMS
) ||
3119 HCC_MAX_PSA(xhci
->hcc_params
) < 4) {
3120 xhci_dbg(xhci
, "xHCI controller does not support streams.\n");
3124 config_cmd
= xhci_alloc_command(xhci
, true, true, mem_flags
);
3126 xhci_dbg(xhci
, "Could not allocate xHCI command structure.\n");
3129 ctrl_ctx
= xhci_get_input_control_ctx(config_cmd
->in_ctx
);
3131 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
3133 xhci_free_command(xhci
, config_cmd
);
3137 /* Check to make sure all endpoints are not already configured for
3138 * streams. While we're at it, find the maximum number of streams that
3139 * all the endpoints will support and check for duplicate endpoints.
3141 spin_lock_irqsave(&xhci
->lock
, flags
);
3142 ret
= xhci_calculate_streams_and_bitmask(xhci
, udev
, eps
,
3143 num_eps
, &num_streams
, &changed_ep_bitmask
);
3145 xhci_free_command(xhci
, config_cmd
);
3146 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3149 if (num_streams
<= 1) {
3150 xhci_warn(xhci
, "WARN: endpoints can't handle "
3151 "more than one stream.\n");
3152 xhci_free_command(xhci
, config_cmd
);
3153 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3156 vdev
= xhci
->devs
[udev
->slot_id
];
3157 /* Mark each endpoint as being in transition, so
3158 * xhci_urb_enqueue() will reject all URBs.
3160 for (i
= 0; i
< num_eps
; i
++) {
3161 ep_index
= xhci_get_endpoint_index(&eps
[i
]->desc
);
3162 vdev
->eps
[ep_index
].ep_state
|= EP_GETTING_STREAMS
;
3164 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3166 /* Setup internal data structures and allocate HW data structures for
3167 * streams (but don't install the HW structures in the input context
3168 * until we're sure all memory allocation succeeded).
3170 xhci_calculate_streams_entries(xhci
, &num_streams
, &num_stream_ctxs
);
3171 xhci_dbg(xhci
, "Need %u stream ctx entries for %u stream IDs.\n",
3172 num_stream_ctxs
, num_streams
);
3174 for (i
= 0; i
< num_eps
; i
++) {
3175 ep_index
= xhci_get_endpoint_index(&eps
[i
]->desc
);
3176 max_packet
= usb_endpoint_maxp(&eps
[i
]->desc
);
3177 vdev
->eps
[ep_index
].stream_info
= xhci_alloc_stream_info(xhci
,
3180 max_packet
, mem_flags
);
3181 if (!vdev
->eps
[ep_index
].stream_info
)
3183 /* Set maxPstreams in endpoint context and update deq ptr to
3184 * point to stream context array. FIXME
3188 /* Set up the input context for a configure endpoint command. */
3189 for (i
= 0; i
< num_eps
; i
++) {
3190 struct xhci_ep_ctx
*ep_ctx
;
3192 ep_index
= xhci_get_endpoint_index(&eps
[i
]->desc
);
3193 ep_ctx
= xhci_get_ep_ctx(xhci
, config_cmd
->in_ctx
, ep_index
);
3195 xhci_endpoint_copy(xhci
, config_cmd
->in_ctx
,
3196 vdev
->out_ctx
, ep_index
);
3197 xhci_setup_streams_ep_input_ctx(xhci
, ep_ctx
,
3198 vdev
->eps
[ep_index
].stream_info
);
3200 /* Tell the HW to drop its old copy of the endpoint context info
3201 * and add the updated copy from the input context.
3203 xhci_setup_input_ctx_for_config_ep(xhci
, config_cmd
->in_ctx
,
3204 vdev
->out_ctx
, ctrl_ctx
,
3205 changed_ep_bitmask
, changed_ep_bitmask
);
3207 /* Issue and wait for the configure endpoint command */
3208 ret
= xhci_configure_endpoint(xhci
, udev
, config_cmd
,
3211 /* xHC rejected the configure endpoint command for some reason, so we
3212 * leave the old ring intact and free our internal streams data
3218 spin_lock_irqsave(&xhci
->lock
, flags
);
3219 for (i
= 0; i
< num_eps
; i
++) {
3220 ep_index
= xhci_get_endpoint_index(&eps
[i
]->desc
);
3221 vdev
->eps
[ep_index
].ep_state
&= ~EP_GETTING_STREAMS
;
3222 xhci_dbg(xhci
, "Slot %u ep ctx %u now has streams.\n",
3223 udev
->slot_id
, ep_index
);
3224 vdev
->eps
[ep_index
].ep_state
|= EP_HAS_STREAMS
;
3226 xhci_free_command(xhci
, config_cmd
);
3227 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3229 /* Subtract 1 for stream 0, which drivers can't use */
3230 return num_streams
- 1;
3233 /* If it didn't work, free the streams! */
3234 for (i
= 0; i
< num_eps
; i
++) {
3235 ep_index
= xhci_get_endpoint_index(&eps
[i
]->desc
);
3236 xhci_free_stream_info(xhci
, vdev
->eps
[ep_index
].stream_info
);
3237 vdev
->eps
[ep_index
].stream_info
= NULL
;
3238 /* FIXME Unset maxPstreams in endpoint context and
3239 * update deq ptr to point to normal string ring.
3241 vdev
->eps
[ep_index
].ep_state
&= ~EP_GETTING_STREAMS
;
3242 vdev
->eps
[ep_index
].ep_state
&= ~EP_HAS_STREAMS
;
3243 xhci_endpoint_zero(xhci
, vdev
, eps
[i
]);
3245 xhci_free_command(xhci
, config_cmd
);
3249 /* Transition the endpoint from using streams to being a "normal" endpoint
3252 * Modify the endpoint context state, submit a configure endpoint command,
3253 * and free all endpoint rings for streams if that completes successfully.
3255 int xhci_free_streams(struct usb_hcd
*hcd
, struct usb_device
*udev
,
3256 struct usb_host_endpoint
**eps
, unsigned int num_eps
,
3260 struct xhci_hcd
*xhci
;
3261 struct xhci_virt_device
*vdev
;
3262 struct xhci_command
*command
;
3263 struct xhci_input_control_ctx
*ctrl_ctx
;
3264 unsigned int ep_index
;
3265 unsigned long flags
;
3266 u32 changed_ep_bitmask
;
3268 xhci
= hcd_to_xhci(hcd
);
3269 vdev
= xhci
->devs
[udev
->slot_id
];
3271 /* Set up a configure endpoint command to remove the streams rings */
3272 spin_lock_irqsave(&xhci
->lock
, flags
);
3273 changed_ep_bitmask
= xhci_calculate_no_streams_bitmask(xhci
,
3274 udev
, eps
, num_eps
);
3275 if (changed_ep_bitmask
== 0) {
3276 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3280 /* Use the xhci_command structure from the first endpoint. We may have
3281 * allocated too many, but the driver may call xhci_free_streams() for
3282 * each endpoint it grouped into one call to xhci_alloc_streams().
3284 ep_index
= xhci_get_endpoint_index(&eps
[0]->desc
);
3285 command
= vdev
->eps
[ep_index
].stream_info
->free_streams_command
;
3286 ctrl_ctx
= xhci_get_input_control_ctx(command
->in_ctx
);
3288 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3289 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
3294 for (i
= 0; i
< num_eps
; i
++) {
3295 struct xhci_ep_ctx
*ep_ctx
;
3297 ep_index
= xhci_get_endpoint_index(&eps
[i
]->desc
);
3298 ep_ctx
= xhci_get_ep_ctx(xhci
, command
->in_ctx
, ep_index
);
3299 xhci
->devs
[udev
->slot_id
]->eps
[ep_index
].ep_state
|=
3300 EP_GETTING_NO_STREAMS
;
3302 xhci_endpoint_copy(xhci
, command
->in_ctx
,
3303 vdev
->out_ctx
, ep_index
);
3304 xhci_setup_no_streams_ep_input_ctx(ep_ctx
,
3305 &vdev
->eps
[ep_index
]);
3307 xhci_setup_input_ctx_for_config_ep(xhci
, command
->in_ctx
,
3308 vdev
->out_ctx
, ctrl_ctx
,
3309 changed_ep_bitmask
, changed_ep_bitmask
);
3310 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3312 /* Issue and wait for the configure endpoint command,
3313 * which must succeed.
3315 ret
= xhci_configure_endpoint(xhci
, udev
, command
,
3318 /* xHC rejected the configure endpoint command for some reason, so we
3319 * leave the streams rings intact.
3324 spin_lock_irqsave(&xhci
->lock
, flags
);
3325 for (i
= 0; i
< num_eps
; i
++) {
3326 ep_index
= xhci_get_endpoint_index(&eps
[i
]->desc
);
3327 xhci_free_stream_info(xhci
, vdev
->eps
[ep_index
].stream_info
);
3328 vdev
->eps
[ep_index
].stream_info
= NULL
;
3329 /* FIXME Unset maxPstreams in endpoint context and
3330 * update deq ptr to point to normal string ring.
3332 vdev
->eps
[ep_index
].ep_state
&= ~EP_GETTING_NO_STREAMS
;
3333 vdev
->eps
[ep_index
].ep_state
&= ~EP_HAS_STREAMS
;
3335 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3341 * Deletes endpoint resources for endpoints that were active before a Reset
3342 * Device command, or a Disable Slot command. The Reset Device command leaves
3343 * the control endpoint intact, whereas the Disable Slot command deletes it.
3345 * Must be called with xhci->lock held.
3347 void xhci_free_device_endpoint_resources(struct xhci_hcd
*xhci
,
3348 struct xhci_virt_device
*virt_dev
, bool drop_control_ep
)
3351 unsigned int num_dropped_eps
= 0;
3352 unsigned int drop_flags
= 0;
3354 for (i
= (drop_control_ep
? 0 : 1); i
< 31; i
++) {
3355 if (virt_dev
->eps
[i
].ring
) {
3356 drop_flags
|= 1 << i
;
3360 xhci
->num_active_eps
-= num_dropped_eps
;
3361 if (num_dropped_eps
)
3362 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
3363 "Dropped %u ep ctxs, flags = 0x%x, "
3365 num_dropped_eps
, drop_flags
,
3366 xhci
->num_active_eps
);
3370 * This submits a Reset Device Command, which will set the device state to 0,
3371 * set the device address to 0, and disable all the endpoints except the default
3372 * control endpoint. The USB core should come back and call
3373 * xhci_address_device(), and then re-set up the configuration. If this is
3374 * called because of a usb_reset_and_verify_device(), then the old alternate
3375 * settings will be re-installed through the normal bandwidth allocation
3378 * Wait for the Reset Device command to finish. Remove all structures
3379 * associated with the endpoints that were disabled. Clear the input device
3380 * structure? Cache the rings? Reset the control endpoint 0 max packet size?
3382 * If the virt_dev to be reset does not exist or does not match the udev,
3383 * it means the device is lost, possibly due to the xHC restore error and
3384 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3385 * re-allocate the device.
3387 int xhci_discover_or_reset_device(struct usb_hcd
*hcd
, struct usb_device
*udev
)
3390 unsigned long flags
;
3391 struct xhci_hcd
*xhci
;
3392 unsigned int slot_id
;
3393 struct xhci_virt_device
*virt_dev
;
3394 struct xhci_command
*reset_device_cmd
;
3395 int last_freed_endpoint
;
3396 struct xhci_slot_ctx
*slot_ctx
;
3397 int old_active_eps
= 0;
3399 ret
= xhci_check_args(hcd
, udev
, NULL
, 0, false, __func__
);
3402 xhci
= hcd_to_xhci(hcd
);
3403 slot_id
= udev
->slot_id
;
3404 virt_dev
= xhci
->devs
[slot_id
];
3406 xhci_dbg(xhci
, "The device to be reset with slot ID %u does "
3407 "not exist. Re-allocate the device\n", slot_id
);
3408 ret
= xhci_alloc_dev(hcd
, udev
);
3415 if (virt_dev
->tt_info
)
3416 old_active_eps
= virt_dev
->tt_info
->active_eps
;
3418 if (virt_dev
->udev
!= udev
) {
3419 /* If the virt_dev and the udev does not match, this virt_dev
3420 * may belong to another udev.
3421 * Re-allocate the device.
3423 xhci_dbg(xhci
, "The device to be reset with slot ID %u does "
3424 "not match the udev. Re-allocate the device\n",
3426 ret
= xhci_alloc_dev(hcd
, udev
);
3433 /* If device is not setup, there is no point in resetting it */
3434 slot_ctx
= xhci_get_slot_ctx(xhci
, virt_dev
->out_ctx
);
3435 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx
->dev_state
)) ==
3436 SLOT_STATE_DISABLED
)
3439 xhci_dbg(xhci
, "Resetting device with slot ID %u\n", slot_id
);
3440 /* Allocate the command structure that holds the struct completion.
3441 * Assume we're in process context, since the normal device reset
3442 * process has to wait for the device anyway. Storage devices are
3443 * reset as part of error handling, so use GFP_NOIO instead of
3446 reset_device_cmd
= xhci_alloc_command(xhci
, false, true, GFP_NOIO
);
3447 if (!reset_device_cmd
) {
3448 xhci_dbg(xhci
, "Couldn't allocate command structure.\n");
3452 /* Attempt to submit the Reset Device command to the command ring */
3453 spin_lock_irqsave(&xhci
->lock
, flags
);
3455 ret
= xhci_queue_reset_device(xhci
, reset_device_cmd
, slot_id
);
3457 xhci_dbg(xhci
, "FIXME: allocate a command ring segment\n");
3458 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3459 goto command_cleanup
;
3461 xhci_ring_cmd_db(xhci
);
3462 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3464 /* Wait for the Reset Device command to finish */
3465 wait_for_completion(reset_device_cmd
->completion
);
3467 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3468 * unless we tried to reset a slot ID that wasn't enabled,
3469 * or the device wasn't in the addressed or configured state.
3471 ret
= reset_device_cmd
->status
;
3473 case COMP_COMMAND_ABORTED
:
3475 xhci_warn(xhci
, "Timeout waiting for reset device command\n");
3477 goto command_cleanup
;
3478 case COMP_SLOT_NOT_ENABLED_ERROR
: /* 0.95 completion for bad slot ID */
3479 case COMP_CONTEXT_STATE_ERROR
: /* 0.96 completion code for same thing */
3480 xhci_dbg(xhci
, "Can't reset device (slot ID %u) in %s state\n",
3482 xhci_get_slot_state(xhci
, virt_dev
->out_ctx
));
3483 xhci_dbg(xhci
, "Not freeing device rings.\n");
3484 /* Don't treat this as an error. May change my mind later. */
3486 goto command_cleanup
;
3488 xhci_dbg(xhci
, "Successful reset device command.\n");
3491 if (xhci_is_vendor_info_code(xhci
, ret
))
3493 xhci_warn(xhci
, "Unknown completion code %u for "
3494 "reset device command.\n", ret
);
3496 goto command_cleanup
;
3499 /* Free up host controller endpoint resources */
3500 if ((xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
)) {
3501 spin_lock_irqsave(&xhci
->lock
, flags
);
3502 /* Don't delete the default control endpoint resources */
3503 xhci_free_device_endpoint_resources(xhci
, virt_dev
, false);
3504 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3507 /* Everything but endpoint 0 is disabled, so free or cache the rings. */
3508 last_freed_endpoint
= 1;
3509 for (i
= 1; i
< 31; i
++) {
3510 struct xhci_virt_ep
*ep
= &virt_dev
->eps
[i
];
3512 if (ep
->ep_state
& EP_HAS_STREAMS
) {
3513 xhci_warn(xhci
, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3514 xhci_get_endpoint_address(i
));
3515 xhci_free_stream_info(xhci
, ep
->stream_info
);
3516 ep
->stream_info
= NULL
;
3517 ep
->ep_state
&= ~EP_HAS_STREAMS
;
3521 xhci_free_or_cache_endpoint_ring(xhci
, virt_dev
, i
);
3522 last_freed_endpoint
= i
;
3524 if (!list_empty(&virt_dev
->eps
[i
].bw_endpoint_list
))
3525 xhci_drop_ep_from_interval_table(xhci
,
3526 &virt_dev
->eps
[i
].bw_info
,
3531 xhci_clear_endpoint_bw_info(&virt_dev
->eps
[i
].bw_info
);
3533 /* If necessary, update the number of active TTs on this root port */
3534 xhci_update_tt_active_eps(xhci
, virt_dev
, old_active_eps
);
3536 xhci_dbg(xhci
, "Output context after successful reset device cmd:\n");
3537 xhci_dbg_ctx(xhci
, virt_dev
->out_ctx
, last_freed_endpoint
);
3541 xhci_free_command(xhci
, reset_device_cmd
);
3546 * At this point, the struct usb_device is about to go away, the device has
3547 * disconnected, and all traffic has been stopped and the endpoints have been
3548 * disabled. Free any HC data structures associated with that device.
3550 void xhci_free_dev(struct usb_hcd
*hcd
, struct usb_device
*udev
)
3552 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
3553 struct xhci_virt_device
*virt_dev
;
3554 unsigned long flags
;
3557 struct xhci_command
*command
;
3559 command
= xhci_alloc_command(xhci
, false, false, GFP_KERNEL
);
3563 #ifndef CONFIG_USB_DEFAULT_PERSIST
3565 * We called pm_runtime_get_noresume when the device was attached.
3566 * Decrement the counter here to allow controller to runtime suspend
3567 * if no devices remain.
3569 if (xhci
->quirks
& XHCI_RESET_ON_RESUME
)
3570 pm_runtime_put_noidle(hcd
->self
.controller
);
3573 ret
= xhci_check_args(hcd
, udev
, NULL
, 0, true, __func__
);
3574 /* If the host is halted due to driver unload, we still need to free the
3577 if (ret
<= 0 && ret
!= -ENODEV
) {
3582 virt_dev
= xhci
->devs
[udev
->slot_id
];
3584 /* Stop any wayward timer functions (which may grab the lock) */
3585 for (i
= 0; i
< 31; i
++) {
3586 virt_dev
->eps
[i
].ep_state
&= ~EP_STOP_CMD_PENDING
;
3587 del_timer_sync(&virt_dev
->eps
[i
].stop_cmd_timer
);
3590 spin_lock_irqsave(&xhci
->lock
, flags
);
3591 /* Don't disable the slot if the host controller is dead. */
3592 state
= readl(&xhci
->op_regs
->status
);
3593 if (state
== 0xffffffff || (xhci
->xhc_state
& XHCI_STATE_DYING
) ||
3594 (xhci
->xhc_state
& XHCI_STATE_HALTED
)) {
3595 xhci_free_virt_device(xhci
, udev
->slot_id
);
3596 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3601 if (xhci_queue_slot_control(xhci
, command
, TRB_DISABLE_SLOT
,
3603 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3604 xhci_dbg(xhci
, "FIXME: allocate a command ring segment\n");
3607 xhci_ring_cmd_db(xhci
);
3608 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3611 * Event command completion handler will free any data structures
3612 * associated with the slot. XXX Can free sleep?
3617 * Checks if we have enough host controller resources for the default control
3620 * Must be called with xhci->lock held.
3622 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd
*xhci
)
3624 if (xhci
->num_active_eps
+ 1 > xhci
->limit_active_eps
) {
3625 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
3626 "Not enough ep ctxs: "
3627 "%u active, need to add 1, limit is %u.",
3628 xhci
->num_active_eps
, xhci
->limit_active_eps
);
3631 xhci
->num_active_eps
+= 1;
3632 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
3633 "Adding 1 ep ctx, %u now active.",
3634 xhci
->num_active_eps
);
3640 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3641 * timed out, or allocating memory failed. Returns 1 on success.
3643 int xhci_alloc_dev(struct usb_hcd
*hcd
, struct usb_device
*udev
)
3645 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
3646 unsigned long flags
;
3648 struct xhci_command
*command
;
3650 command
= xhci_alloc_command(xhci
, false, true, GFP_KERNEL
);
3654 /* xhci->slot_id and xhci->addr_dev are not thread-safe */
3655 mutex_lock(&xhci
->mutex
);
3656 spin_lock_irqsave(&xhci
->lock
, flags
);
3657 ret
= xhci_queue_slot_control(xhci
, command
, TRB_ENABLE_SLOT
, 0);
3659 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3660 mutex_unlock(&xhci
->mutex
);
3661 xhci_dbg(xhci
, "FIXME: allocate a command ring segment\n");
3662 xhci_free_command(xhci
, command
);
3665 xhci_ring_cmd_db(xhci
);
3666 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3668 wait_for_completion(command
->completion
);
3669 slot_id
= command
->slot_id
;
3670 mutex_unlock(&xhci
->mutex
);
3672 if (!slot_id
|| command
->status
!= COMP_SUCCESS
) {
3673 xhci_err(xhci
, "Error while assigning device slot ID\n");
3674 xhci_err(xhci
, "Max number of devices this xHCI host supports is %u.\n",
3676 readl(&xhci
->cap_regs
->hcs_params1
)));
3677 xhci_free_command(xhci
, command
);
3681 if ((xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
)) {
3682 spin_lock_irqsave(&xhci
->lock
, flags
);
3683 ret
= xhci_reserve_host_control_ep_resources(xhci
);
3685 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3686 xhci_warn(xhci
, "Not enough host resources, "
3687 "active endpoint contexts = %u\n",
3688 xhci
->num_active_eps
);
3691 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3693 /* Use GFP_NOIO, since this function can be called from
3694 * xhci_discover_or_reset_device(), which may be called as part of
3695 * mass storage driver error handling.
3697 if (!xhci_alloc_virt_device(xhci
, slot_id
, udev
, GFP_NOIO
)) {
3698 xhci_warn(xhci
, "Could not allocate xHCI USB device data structures\n");
3701 udev
->slot_id
= slot_id
;
3703 #ifndef CONFIG_USB_DEFAULT_PERSIST
3705 * If resetting upon resume, we can't put the controller into runtime
3706 * suspend if there is a device attached.
3708 if (xhci
->quirks
& XHCI_RESET_ON_RESUME
)
3709 pm_runtime_get_noresume(hcd
->self
.controller
);
3713 xhci_free_command(xhci
, command
);
3714 /* Is this a LS or FS device under a HS hub? */
3715 /* Hub or peripherial? */
3719 /* Disable slot, if we can do it without mem alloc */
3720 spin_lock_irqsave(&xhci
->lock
, flags
);
3721 kfree(command
->completion
);
3722 command
->completion
= NULL
;
3723 command
->status
= 0;
3724 if (!xhci_queue_slot_control(xhci
, command
, TRB_DISABLE_SLOT
,
3726 xhci_ring_cmd_db(xhci
);
3727 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3732 * Issue an Address Device command and optionally send a corresponding
3733 * SetAddress request to the device.
3735 static int xhci_setup_device(struct usb_hcd
*hcd
, struct usb_device
*udev
,
3736 enum xhci_setup_dev setup
)
3738 const char *act
= setup
== SETUP_CONTEXT_ONLY
? "context" : "address";
3739 unsigned long flags
;
3740 struct xhci_virt_device
*virt_dev
;
3742 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
3743 struct xhci_slot_ctx
*slot_ctx
;
3744 struct xhci_input_control_ctx
*ctrl_ctx
;
3746 struct xhci_command
*command
= NULL
;
3748 mutex_lock(&xhci
->mutex
);
3750 if (xhci
->xhc_state
) { /* dying, removing or halted */
3755 if (!udev
->slot_id
) {
3756 xhci_dbg_trace(xhci
, trace_xhci_dbg_address
,
3757 "Bad Slot ID %d", udev
->slot_id
);
3762 virt_dev
= xhci
->devs
[udev
->slot_id
];
3764 if (WARN_ON(!virt_dev
)) {
3766 * In plug/unplug torture test with an NEC controller,
3767 * a zero-dereference was observed once due to virt_dev = 0.
3768 * Print useful debug rather than crash if it is observed again!
3770 xhci_warn(xhci
, "Virt dev invalid for slot_id 0x%x!\n",
3776 if (setup
== SETUP_CONTEXT_ONLY
) {
3777 slot_ctx
= xhci_get_slot_ctx(xhci
, virt_dev
->out_ctx
);
3778 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx
->dev_state
)) ==
3779 SLOT_STATE_DEFAULT
) {
3780 xhci_dbg(xhci
, "Slot already in default state\n");
3785 command
= xhci_alloc_command(xhci
, false, true, GFP_KERNEL
);
3791 command
->in_ctx
= virt_dev
->in_ctx
;
3793 slot_ctx
= xhci_get_slot_ctx(xhci
, virt_dev
->in_ctx
);
3794 ctrl_ctx
= xhci_get_input_control_ctx(virt_dev
->in_ctx
);
3796 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
3802 * If this is the first Set Address since device plug-in or
3803 * virt_device realloaction after a resume with an xHCI power loss,
3804 * then set up the slot context.
3806 if (!slot_ctx
->dev_info
)
3807 xhci_setup_addressable_virt_dev(xhci
, udev
);
3808 /* Otherwise, update the control endpoint ring enqueue pointer. */
3810 xhci_copy_ep0_dequeue_into_input_ctx(xhci
, udev
);
3811 ctrl_ctx
->add_flags
= cpu_to_le32(SLOT_FLAG
| EP0_FLAG
);
3812 ctrl_ctx
->drop_flags
= 0;
3814 xhci_dbg(xhci
, "Slot ID %d Input Context:\n", udev
->slot_id
);
3815 xhci_dbg_ctx(xhci
, virt_dev
->in_ctx
, 2);
3816 trace_xhci_address_ctx(xhci
, virt_dev
->in_ctx
,
3817 le32_to_cpu(slot_ctx
->dev_info
) >> 27);
3819 spin_lock_irqsave(&xhci
->lock
, flags
);
3820 trace_xhci_setup_device(virt_dev
);
3821 ret
= xhci_queue_address_device(xhci
, command
, virt_dev
->in_ctx
->dma
,
3822 udev
->slot_id
, setup
);
3824 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3825 xhci_dbg_trace(xhci
, trace_xhci_dbg_address
,
3826 "FIXME: allocate a command ring segment");
3829 xhci_ring_cmd_db(xhci
);
3830 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3832 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
3833 wait_for_completion(command
->completion
);
3835 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
3836 * the SetAddress() "recovery interval" required by USB and aborting the
3837 * command on a timeout.
3839 switch (command
->status
) {
3840 case COMP_COMMAND_ABORTED
:
3842 xhci_warn(xhci
, "Timeout while waiting for setup device command\n");
3845 case COMP_CONTEXT_STATE_ERROR
:
3846 case COMP_SLOT_NOT_ENABLED_ERROR
:
3847 xhci_err(xhci
, "Setup ERROR: setup %s command for slot %d.\n",
3848 act
, udev
->slot_id
);
3851 case COMP_USB_TRANSACTION_ERROR
:
3852 dev_warn(&udev
->dev
, "Device not responding to setup %s.\n", act
);
3855 case COMP_INCOMPATIBLE_DEVICE_ERROR
:
3856 dev_warn(&udev
->dev
,
3857 "ERROR: Incompatible device for setup %s command\n", act
);
3861 xhci_dbg_trace(xhci
, trace_xhci_dbg_address
,
3862 "Successful setup %s command", act
);
3866 "ERROR: unexpected setup %s command completion code 0x%x.\n",
3867 act
, command
->status
);
3868 xhci_dbg(xhci
, "Slot ID %d Output Context:\n", udev
->slot_id
);
3869 xhci_dbg_ctx(xhci
, virt_dev
->out_ctx
, 2);
3870 trace_xhci_address_ctx(xhci
, virt_dev
->out_ctx
, 1);
3876 temp_64
= xhci_read_64(xhci
, &xhci
->op_regs
->dcbaa_ptr
);
3877 xhci_dbg_trace(xhci
, trace_xhci_dbg_address
,
3878 "Op regs DCBAA ptr = %#016llx", temp_64
);
3879 xhci_dbg_trace(xhci
, trace_xhci_dbg_address
,
3880 "Slot ID %d dcbaa entry @%p = %#016llx",
3882 &xhci
->dcbaa
->dev_context_ptrs
[udev
->slot_id
],
3883 (unsigned long long)
3884 le64_to_cpu(xhci
->dcbaa
->dev_context_ptrs
[udev
->slot_id
]));
3885 xhci_dbg_trace(xhci
, trace_xhci_dbg_address
,
3886 "Output Context DMA address = %#08llx",
3887 (unsigned long long)virt_dev
->out_ctx
->dma
);
3888 xhci_dbg(xhci
, "Slot ID %d Input Context:\n", udev
->slot_id
);
3889 xhci_dbg_ctx(xhci
, virt_dev
->in_ctx
, 2);
3890 trace_xhci_address_ctx(xhci
, virt_dev
->in_ctx
,
3891 le32_to_cpu(slot_ctx
->dev_info
) >> 27);
3892 xhci_dbg(xhci
, "Slot ID %d Output Context:\n", udev
->slot_id
);
3893 xhci_dbg_ctx(xhci
, virt_dev
->out_ctx
, 2);
3895 * USB core uses address 1 for the roothubs, so we add one to the
3896 * address given back to us by the HC.
3898 slot_ctx
= xhci_get_slot_ctx(xhci
, virt_dev
->out_ctx
);
3899 trace_xhci_address_ctx(xhci
, virt_dev
->out_ctx
,
3900 le32_to_cpu(slot_ctx
->dev_info
) >> 27);
3901 /* Zero the input context control for later use */
3902 ctrl_ctx
->add_flags
= 0;
3903 ctrl_ctx
->drop_flags
= 0;
3905 xhci_dbg_trace(xhci
, trace_xhci_dbg_address
,
3906 "Internal device address = %d",
3907 le32_to_cpu(slot_ctx
->dev_state
) & DEV_ADDR_MASK
);
3909 mutex_unlock(&xhci
->mutex
);
3911 kfree(command
->completion
);
3917 int xhci_address_device(struct usb_hcd
*hcd
, struct usb_device
*udev
)
3919 return xhci_setup_device(hcd
, udev
, SETUP_CONTEXT_ADDRESS
);
3922 int xhci_enable_device(struct usb_hcd
*hcd
, struct usb_device
*udev
)
3924 return xhci_setup_device(hcd
, udev
, SETUP_CONTEXT_ONLY
);
3928 * Transfer the port index into real index in the HW port status
3929 * registers. Caculate offset between the port's PORTSC register
3930 * and port status base. Divide the number of per port register
3931 * to get the real index. The raw port number bases 1.
3933 int xhci_find_raw_port_number(struct usb_hcd
*hcd
, int port1
)
3935 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
3936 __le32 __iomem
*base_addr
= &xhci
->op_regs
->port_status_base
;
3937 __le32 __iomem
*addr
;
3940 if (hcd
->speed
< HCD_USB3
)
3941 addr
= xhci
->usb2_ports
[port1
- 1];
3943 addr
= xhci
->usb3_ports
[port1
- 1];
3945 raw_port
= (addr
- base_addr
)/NUM_PORT_REGS
+ 1;
3950 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
3951 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
3953 static int __maybe_unused
xhci_change_max_exit_latency(struct xhci_hcd
*xhci
,
3954 struct usb_device
*udev
, u16 max_exit_latency
)
3956 struct xhci_virt_device
*virt_dev
;
3957 struct xhci_command
*command
;
3958 struct xhci_input_control_ctx
*ctrl_ctx
;
3959 struct xhci_slot_ctx
*slot_ctx
;
3960 unsigned long flags
;
3963 spin_lock_irqsave(&xhci
->lock
, flags
);
3965 virt_dev
= xhci
->devs
[udev
->slot_id
];
3968 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
3969 * xHC was re-initialized. Exit latency will be set later after
3970 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
3973 if (!virt_dev
|| max_exit_latency
== virt_dev
->current_mel
) {
3974 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3978 /* Attempt to issue an Evaluate Context command to change the MEL. */
3979 command
= xhci
->lpm_command
;
3980 ctrl_ctx
= xhci_get_input_control_ctx(command
->in_ctx
);
3982 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3983 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
3988 xhci_slot_copy(xhci
, command
->in_ctx
, virt_dev
->out_ctx
);
3989 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3991 ctrl_ctx
->add_flags
|= cpu_to_le32(SLOT_FLAG
);
3992 slot_ctx
= xhci_get_slot_ctx(xhci
, command
->in_ctx
);
3993 slot_ctx
->dev_info2
&= cpu_to_le32(~((u32
) MAX_EXIT
));
3994 slot_ctx
->dev_info2
|= cpu_to_le32(max_exit_latency
);
3995 slot_ctx
->dev_state
= 0;
3997 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
3998 "Set up evaluate context for LPM MEL change.");
3999 xhci_dbg(xhci
, "Slot %u Input Context:\n", udev
->slot_id
);
4000 xhci_dbg_ctx(xhci
, command
->in_ctx
, 0);
4002 /* Issue and wait for the evaluate context command. */
4003 ret
= xhci_configure_endpoint(xhci
, udev
, command
,
4005 xhci_dbg(xhci
, "Slot %u Output Context:\n", udev
->slot_id
);
4006 xhci_dbg_ctx(xhci
, virt_dev
->out_ctx
, 0);
4009 spin_lock_irqsave(&xhci
->lock
, flags
);
4010 virt_dev
->current_mel
= max_exit_latency
;
4011 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4018 /* BESL to HIRD Encoding array for USB2 LPM */
4019 static int xhci_besl_encoding
[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4020 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4022 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4023 static int xhci_calculate_hird_besl(struct xhci_hcd
*xhci
,
4024 struct usb_device
*udev
)
4026 int u2del
, besl
, besl_host
;
4027 int besl_device
= 0;
4030 u2del
= HCS_U2_LATENCY(xhci
->hcs_params3
);
4031 field
= le32_to_cpu(udev
->bos
->ext_cap
->bmAttributes
);
4033 if (field
& USB_BESL_SUPPORT
) {
4034 for (besl_host
= 0; besl_host
< 16; besl_host
++) {
4035 if (xhci_besl_encoding
[besl_host
] >= u2del
)
4038 /* Use baseline BESL value as default */
4039 if (field
& USB_BESL_BASELINE_VALID
)
4040 besl_device
= USB_GET_BESL_BASELINE(field
);
4041 else if (field
& USB_BESL_DEEP_VALID
)
4042 besl_device
= USB_GET_BESL_DEEP(field
);
4047 besl_host
= (u2del
- 51) / 75 + 1;
4050 besl
= besl_host
+ besl_device
;
4057 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4058 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device
*udev
)
4065 field
= le32_to_cpu(udev
->bos
->ext_cap
->bmAttributes
);
4067 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4068 l1
= udev
->l1_params
.timeout
/ 256;
4070 /* device has preferred BESLD */
4071 if (field
& USB_BESL_DEEP_VALID
) {
4072 besld
= USB_GET_BESL_DEEP(field
);
4076 return PORT_BESLD(besld
) | PORT_L1_TIMEOUT(l1
) | PORT_HIRDM(hirdm
);
4079 int xhci_set_usb2_hardware_lpm(struct usb_hcd
*hcd
,
4080 struct usb_device
*udev
, int enable
)
4082 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
4083 __le32 __iomem
**port_array
;
4084 __le32 __iomem
*pm_addr
, *hlpm_addr
;
4085 u32 pm_val
, hlpm_val
, field
;
4086 unsigned int port_num
;
4087 unsigned long flags
;
4088 int hird
, exit_latency
;
4091 if (hcd
->speed
>= HCD_USB3
|| !xhci
->hw_lpm_support
||
4095 if (!udev
->parent
|| udev
->parent
->parent
||
4096 udev
->descriptor
.bDeviceClass
== USB_CLASS_HUB
)
4099 if (udev
->usb2_hw_lpm_capable
!= 1)
4102 spin_lock_irqsave(&xhci
->lock
, flags
);
4104 port_array
= xhci
->usb2_ports
;
4105 port_num
= udev
->portnum
- 1;
4106 pm_addr
= port_array
[port_num
] + PORTPMSC
;
4107 pm_val
= readl(pm_addr
);
4108 hlpm_addr
= port_array
[port_num
] + PORTHLPMC
;
4109 field
= le32_to_cpu(udev
->bos
->ext_cap
->bmAttributes
);
4111 xhci_dbg(xhci
, "%s port %d USB2 hardware LPM\n",
4112 enable
? "enable" : "disable", port_num
+ 1);
4115 /* Host supports BESL timeout instead of HIRD */
4116 if (udev
->usb2_hw_lpm_besl_capable
) {
4117 /* if device doesn't have a preferred BESL value use a
4118 * default one which works with mixed HIRD and BESL
4119 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4121 if ((field
& USB_BESL_SUPPORT
) &&
4122 (field
& USB_BESL_BASELINE_VALID
))
4123 hird
= USB_GET_BESL_BASELINE(field
);
4125 hird
= udev
->l1_params
.besl
;
4127 exit_latency
= xhci_besl_encoding
[hird
];
4128 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4130 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4131 * input context for link powermanagement evaluate
4132 * context commands. It is protected by hcd->bandwidth
4133 * mutex and is shared by all devices. We need to set
4134 * the max ext latency in USB 2 BESL LPM as well, so
4135 * use the same mutex and xhci_change_max_exit_latency()
4137 mutex_lock(hcd
->bandwidth_mutex
);
4138 ret
= xhci_change_max_exit_latency(xhci
, udev
,
4140 mutex_unlock(hcd
->bandwidth_mutex
);
4144 spin_lock_irqsave(&xhci
->lock
, flags
);
4146 hlpm_val
= xhci_calculate_usb2_hw_lpm_params(udev
);
4147 writel(hlpm_val
, hlpm_addr
);
4151 hird
= xhci_calculate_hird_besl(xhci
, udev
);
4154 pm_val
&= ~PORT_HIRD_MASK
;
4155 pm_val
|= PORT_HIRD(hird
) | PORT_RWE
| PORT_L1DS(udev
->slot_id
);
4156 writel(pm_val
, pm_addr
);
4157 pm_val
= readl(pm_addr
);
4159 writel(pm_val
, pm_addr
);
4163 pm_val
&= ~(PORT_HLE
| PORT_RWE
| PORT_HIRD_MASK
| PORT_L1DS_MASK
);
4164 writel(pm_val
, pm_addr
);
4167 if (udev
->usb2_hw_lpm_besl_capable
) {
4168 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4169 mutex_lock(hcd
->bandwidth_mutex
);
4170 xhci_change_max_exit_latency(xhci
, udev
, 0);
4171 mutex_unlock(hcd
->bandwidth_mutex
);
4176 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4180 /* check if a usb2 port supports a given extened capability protocol
4181 * only USB2 ports extended protocol capability values are cached.
4182 * Return 1 if capability is supported
4184 static int xhci_check_usb2_port_capability(struct xhci_hcd
*xhci
, int port
,
4185 unsigned capability
)
4187 u32 port_offset
, port_count
;
4190 for (i
= 0; i
< xhci
->num_ext_caps
; i
++) {
4191 if (xhci
->ext_caps
[i
] & capability
) {
4192 /* port offsets starts at 1 */
4193 port_offset
= XHCI_EXT_PORT_OFF(xhci
->ext_caps
[i
]) - 1;
4194 port_count
= XHCI_EXT_PORT_COUNT(xhci
->ext_caps
[i
]);
4195 if (port
>= port_offset
&&
4196 port
< port_offset
+ port_count
)
4203 int xhci_update_device(struct usb_hcd
*hcd
, struct usb_device
*udev
)
4205 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
4206 int portnum
= udev
->portnum
- 1;
4208 if (hcd
->speed
>= HCD_USB3
|| !xhci
->sw_lpm_support
||
4212 /* we only support lpm for non-hub device connected to root hub yet */
4213 if (!udev
->parent
|| udev
->parent
->parent
||
4214 udev
->descriptor
.bDeviceClass
== USB_CLASS_HUB
)
4217 if (xhci
->hw_lpm_support
== 1 &&
4218 xhci_check_usb2_port_capability(
4219 xhci
, portnum
, XHCI_HLC
)) {
4220 udev
->usb2_hw_lpm_capable
= 1;
4221 udev
->l1_params
.timeout
= XHCI_L1_TIMEOUT
;
4222 udev
->l1_params
.besl
= XHCI_DEFAULT_BESL
;
4223 if (xhci_check_usb2_port_capability(xhci
, portnum
,
4225 udev
->usb2_hw_lpm_besl_capable
= 1;
4231 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4233 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4234 static unsigned long long xhci_service_interval_to_ns(
4235 struct usb_endpoint_descriptor
*desc
)
4237 return (1ULL << (desc
->bInterval
- 1)) * 125 * 1000;
4240 static u16
xhci_get_timeout_no_hub_lpm(struct usb_device
*udev
,
4241 enum usb3_link_state state
)
4243 unsigned long long sel
;
4244 unsigned long long pel
;
4245 unsigned int max_sel_pel
;
4250 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4251 sel
= DIV_ROUND_UP(udev
->u1_params
.sel
, 1000);
4252 pel
= DIV_ROUND_UP(udev
->u1_params
.pel
, 1000);
4253 max_sel_pel
= USB3_LPM_MAX_U1_SEL_PEL
;
4257 sel
= DIV_ROUND_UP(udev
->u2_params
.sel
, 1000);
4258 pel
= DIV_ROUND_UP(udev
->u2_params
.pel
, 1000);
4259 max_sel_pel
= USB3_LPM_MAX_U2_SEL_PEL
;
4263 dev_warn(&udev
->dev
, "%s: Can't get timeout for non-U1 or U2 state.\n",
4265 return USB3_LPM_DISABLED
;
4268 if (sel
<= max_sel_pel
&& pel
<= max_sel_pel
)
4269 return USB3_LPM_DEVICE_INITIATED
;
4271 if (sel
> max_sel_pel
)
4272 dev_dbg(&udev
->dev
, "Device-initiated %s disabled "
4273 "due to long SEL %llu ms\n",
4276 dev_dbg(&udev
->dev
, "Device-initiated %s disabled "
4277 "due to long PEL %llu ms\n",
4279 return USB3_LPM_DISABLED
;
4282 /* The U1 timeout should be the maximum of the following values:
4283 * - For control endpoints, U1 system exit latency (SEL) * 3
4284 * - For bulk endpoints, U1 SEL * 5
4285 * - For interrupt endpoints:
4286 * - Notification EPs, U1 SEL * 3
4287 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4288 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4290 static unsigned long long xhci_calculate_intel_u1_timeout(
4291 struct usb_device
*udev
,
4292 struct usb_endpoint_descriptor
*desc
)
4294 unsigned long long timeout_ns
;
4298 ep_type
= usb_endpoint_type(desc
);
4300 case USB_ENDPOINT_XFER_CONTROL
:
4301 timeout_ns
= udev
->u1_params
.sel
* 3;
4303 case USB_ENDPOINT_XFER_BULK
:
4304 timeout_ns
= udev
->u1_params
.sel
* 5;
4306 case USB_ENDPOINT_XFER_INT
:
4307 intr_type
= usb_endpoint_interrupt_type(desc
);
4308 if (intr_type
== USB_ENDPOINT_INTR_NOTIFICATION
) {
4309 timeout_ns
= udev
->u1_params
.sel
* 3;
4312 /* Otherwise the calculation is the same as isoc eps */
4313 case USB_ENDPOINT_XFER_ISOC
:
4314 timeout_ns
= xhci_service_interval_to_ns(desc
);
4315 timeout_ns
= DIV_ROUND_UP_ULL(timeout_ns
* 105, 100);
4316 if (timeout_ns
< udev
->u1_params
.sel
* 2)
4317 timeout_ns
= udev
->u1_params
.sel
* 2;
4326 /* Returns the hub-encoded U1 timeout value. */
4327 static u16
xhci_calculate_u1_timeout(struct xhci_hcd
*xhci
,
4328 struct usb_device
*udev
,
4329 struct usb_endpoint_descriptor
*desc
)
4331 unsigned long long timeout_ns
;
4333 if (xhci
->quirks
& XHCI_INTEL_HOST
)
4334 timeout_ns
= xhci_calculate_intel_u1_timeout(udev
, desc
);
4336 timeout_ns
= udev
->u1_params
.sel
;
4338 /* The U1 timeout is encoded in 1us intervals.
4339 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4341 if (timeout_ns
== USB3_LPM_DISABLED
)
4344 timeout_ns
= DIV_ROUND_UP_ULL(timeout_ns
, 1000);
4346 /* If the necessary timeout value is bigger than what we can set in the
4347 * USB 3.0 hub, we have to disable hub-initiated U1.
4349 if (timeout_ns
<= USB3_LPM_U1_MAX_TIMEOUT
)
4351 dev_dbg(&udev
->dev
, "Hub-initiated U1 disabled "
4352 "due to long timeout %llu ms\n", timeout_ns
);
4353 return xhci_get_timeout_no_hub_lpm(udev
, USB3_LPM_U1
);
4356 /* The U2 timeout should be the maximum of:
4357 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4358 * - largest bInterval of any active periodic endpoint (to avoid going
4359 * into lower power link states between intervals).
4360 * - the U2 Exit Latency of the device
4362 static unsigned long long xhci_calculate_intel_u2_timeout(
4363 struct usb_device
*udev
,
4364 struct usb_endpoint_descriptor
*desc
)
4366 unsigned long long timeout_ns
;
4367 unsigned long long u2_del_ns
;
4369 timeout_ns
= 10 * 1000 * 1000;
4371 if ((usb_endpoint_xfer_int(desc
) || usb_endpoint_xfer_isoc(desc
)) &&
4372 (xhci_service_interval_to_ns(desc
) > timeout_ns
))
4373 timeout_ns
= xhci_service_interval_to_ns(desc
);
4375 u2_del_ns
= le16_to_cpu(udev
->bos
->ss_cap
->bU2DevExitLat
) * 1000ULL;
4376 if (u2_del_ns
> timeout_ns
)
4377 timeout_ns
= u2_del_ns
;
4382 /* Returns the hub-encoded U2 timeout value. */
4383 static u16
xhci_calculate_u2_timeout(struct xhci_hcd
*xhci
,
4384 struct usb_device
*udev
,
4385 struct usb_endpoint_descriptor
*desc
)
4387 unsigned long long timeout_ns
;
4389 if (xhci
->quirks
& XHCI_INTEL_HOST
)
4390 timeout_ns
= xhci_calculate_intel_u2_timeout(udev
, desc
);
4392 timeout_ns
= udev
->u2_params
.sel
;
4394 /* The U2 timeout is encoded in 256us intervals */
4395 timeout_ns
= DIV_ROUND_UP_ULL(timeout_ns
, 256 * 1000);
4396 /* If the necessary timeout value is bigger than what we can set in the
4397 * USB 3.0 hub, we have to disable hub-initiated U2.
4399 if (timeout_ns
<= USB3_LPM_U2_MAX_TIMEOUT
)
4401 dev_dbg(&udev
->dev
, "Hub-initiated U2 disabled "
4402 "due to long timeout %llu ms\n", timeout_ns
);
4403 return xhci_get_timeout_no_hub_lpm(udev
, USB3_LPM_U2
);
4406 static u16
xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd
*xhci
,
4407 struct usb_device
*udev
,
4408 struct usb_endpoint_descriptor
*desc
,
4409 enum usb3_link_state state
,
4412 if (state
== USB3_LPM_U1
)
4413 return xhci_calculate_u1_timeout(xhci
, udev
, desc
);
4414 else if (state
== USB3_LPM_U2
)
4415 return xhci_calculate_u2_timeout(xhci
, udev
, desc
);
4417 return USB3_LPM_DISABLED
;
4420 static int xhci_update_timeout_for_endpoint(struct xhci_hcd
*xhci
,
4421 struct usb_device
*udev
,
4422 struct usb_endpoint_descriptor
*desc
,
4423 enum usb3_link_state state
,
4428 alt_timeout
= xhci_call_host_update_timeout_for_endpoint(xhci
, udev
,
4429 desc
, state
, timeout
);
4431 /* If we found we can't enable hub-initiated LPM, or
4432 * the U1 or U2 exit latency was too high to allow
4433 * device-initiated LPM as well, just stop searching.
4435 if (alt_timeout
== USB3_LPM_DISABLED
||
4436 alt_timeout
== USB3_LPM_DEVICE_INITIATED
) {
4437 *timeout
= alt_timeout
;
4440 if (alt_timeout
> *timeout
)
4441 *timeout
= alt_timeout
;
4445 static int xhci_update_timeout_for_interface(struct xhci_hcd
*xhci
,
4446 struct usb_device
*udev
,
4447 struct usb_host_interface
*alt
,
4448 enum usb3_link_state state
,
4453 for (j
= 0; j
< alt
->desc
.bNumEndpoints
; j
++) {
4454 if (xhci_update_timeout_for_endpoint(xhci
, udev
,
4455 &alt
->endpoint
[j
].desc
, state
, timeout
))
4462 static int xhci_check_intel_tier_policy(struct usb_device
*udev
,
4463 enum usb3_link_state state
)
4465 struct usb_device
*parent
;
4466 unsigned int num_hubs
;
4468 if (state
== USB3_LPM_U2
)
4471 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4472 for (parent
= udev
->parent
, num_hubs
= 0; parent
->parent
;
4473 parent
= parent
->parent
)
4479 dev_dbg(&udev
->dev
, "Disabling U1 link state for device"
4480 " below second-tier hub.\n");
4481 dev_dbg(&udev
->dev
, "Plug device into first-tier hub "
4482 "to decrease power consumption.\n");
4486 static int xhci_check_tier_policy(struct xhci_hcd
*xhci
,
4487 struct usb_device
*udev
,
4488 enum usb3_link_state state
)
4490 if (xhci
->quirks
& XHCI_INTEL_HOST
)
4491 return xhci_check_intel_tier_policy(udev
, state
);
4496 /* Returns the U1 or U2 timeout that should be enabled.
4497 * If the tier check or timeout setting functions return with a non-zero exit
4498 * code, that means the timeout value has been finalized and we shouldn't look
4499 * at any more endpoints.
4501 static u16
xhci_calculate_lpm_timeout(struct usb_hcd
*hcd
,
4502 struct usb_device
*udev
, enum usb3_link_state state
)
4504 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
4505 struct usb_host_config
*config
;
4508 u16 timeout
= USB3_LPM_DISABLED
;
4510 if (state
== USB3_LPM_U1
)
4512 else if (state
== USB3_LPM_U2
)
4515 dev_warn(&udev
->dev
, "Can't enable unknown link state %i\n",
4520 if (xhci_check_tier_policy(xhci
, udev
, state
) < 0)
4523 /* Gather some information about the currently installed configuration
4524 * and alternate interface settings.
4526 if (xhci_update_timeout_for_endpoint(xhci
, udev
, &udev
->ep0
.desc
,
4530 config
= udev
->actconfig
;
4534 for (i
= 0; i
< config
->desc
.bNumInterfaces
; i
++) {
4535 struct usb_driver
*driver
;
4536 struct usb_interface
*intf
= config
->interface
[i
];
4541 /* Check if any currently bound drivers want hub-initiated LPM
4544 if (intf
->dev
.driver
) {
4545 driver
= to_usb_driver(intf
->dev
.driver
);
4546 if (driver
&& driver
->disable_hub_initiated_lpm
) {
4547 dev_dbg(&udev
->dev
, "Hub-initiated %s disabled "
4548 "at request of driver %s\n",
4549 state_name
, driver
->name
);
4550 return xhci_get_timeout_no_hub_lpm(udev
, state
);
4554 /* Not sure how this could happen... */
4555 if (!intf
->cur_altsetting
)
4558 if (xhci_update_timeout_for_interface(xhci
, udev
,
4559 intf
->cur_altsetting
,
4566 static int calculate_max_exit_latency(struct usb_device
*udev
,
4567 enum usb3_link_state state_changed
,
4568 u16 hub_encoded_timeout
)
4570 unsigned long long u1_mel_us
= 0;
4571 unsigned long long u2_mel_us
= 0;
4572 unsigned long long mel_us
= 0;
4578 disabling_u1
= (state_changed
== USB3_LPM_U1
&&
4579 hub_encoded_timeout
== USB3_LPM_DISABLED
);
4580 disabling_u2
= (state_changed
== USB3_LPM_U2
&&
4581 hub_encoded_timeout
== USB3_LPM_DISABLED
);
4583 enabling_u1
= (state_changed
== USB3_LPM_U1
&&
4584 hub_encoded_timeout
!= USB3_LPM_DISABLED
);
4585 enabling_u2
= (state_changed
== USB3_LPM_U2
&&
4586 hub_encoded_timeout
!= USB3_LPM_DISABLED
);
4588 /* If U1 was already enabled and we're not disabling it,
4589 * or we're going to enable U1, account for the U1 max exit latency.
4591 if ((udev
->u1_params
.timeout
!= USB3_LPM_DISABLED
&& !disabling_u1
) ||
4593 u1_mel_us
= DIV_ROUND_UP(udev
->u1_params
.mel
, 1000);
4594 if ((udev
->u2_params
.timeout
!= USB3_LPM_DISABLED
&& !disabling_u2
) ||
4596 u2_mel_us
= DIV_ROUND_UP(udev
->u2_params
.mel
, 1000);
4598 if (u1_mel_us
> u2_mel_us
)
4602 /* xHCI host controller max exit latency field is only 16 bits wide. */
4603 if (mel_us
> MAX_EXIT
) {
4604 dev_warn(&udev
->dev
, "Link PM max exit latency of %lluus "
4605 "is too big.\n", mel_us
);
4611 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4612 int xhci_enable_usb3_lpm_timeout(struct usb_hcd
*hcd
,
4613 struct usb_device
*udev
, enum usb3_link_state state
)
4615 struct xhci_hcd
*xhci
;
4616 u16 hub_encoded_timeout
;
4620 xhci
= hcd_to_xhci(hcd
);
4621 /* The LPM timeout values are pretty host-controller specific, so don't
4622 * enable hub-initiated timeouts unless the vendor has provided
4623 * information about their timeout algorithm.
4625 if (!xhci
|| !(xhci
->quirks
& XHCI_LPM_SUPPORT
) ||
4626 !xhci
->devs
[udev
->slot_id
])
4627 return USB3_LPM_DISABLED
;
4629 hub_encoded_timeout
= xhci_calculate_lpm_timeout(hcd
, udev
, state
);
4630 mel
= calculate_max_exit_latency(udev
, state
, hub_encoded_timeout
);
4632 /* Max Exit Latency is too big, disable LPM. */
4633 hub_encoded_timeout
= USB3_LPM_DISABLED
;
4637 ret
= xhci_change_max_exit_latency(xhci
, udev
, mel
);
4640 return hub_encoded_timeout
;
4643 int xhci_disable_usb3_lpm_timeout(struct usb_hcd
*hcd
,
4644 struct usb_device
*udev
, enum usb3_link_state state
)
4646 struct xhci_hcd
*xhci
;
4649 xhci
= hcd_to_xhci(hcd
);
4650 if (!xhci
|| !(xhci
->quirks
& XHCI_LPM_SUPPORT
) ||
4651 !xhci
->devs
[udev
->slot_id
])
4654 mel
= calculate_max_exit_latency(udev
, state
, USB3_LPM_DISABLED
);
4655 return xhci_change_max_exit_latency(xhci
, udev
, mel
);
4657 #else /* CONFIG_PM */
4659 int xhci_set_usb2_hardware_lpm(struct usb_hcd
*hcd
,
4660 struct usb_device
*udev
, int enable
)
4665 int xhci_update_device(struct usb_hcd
*hcd
, struct usb_device
*udev
)
4670 int xhci_enable_usb3_lpm_timeout(struct usb_hcd
*hcd
,
4671 struct usb_device
*udev
, enum usb3_link_state state
)
4673 return USB3_LPM_DISABLED
;
4676 int xhci_disable_usb3_lpm_timeout(struct usb_hcd
*hcd
,
4677 struct usb_device
*udev
, enum usb3_link_state state
)
4681 #endif /* CONFIG_PM */
4683 /*-------------------------------------------------------------------------*/
4685 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
4686 * internal data structures for the device.
4688 int xhci_update_hub_device(struct usb_hcd
*hcd
, struct usb_device
*hdev
,
4689 struct usb_tt
*tt
, gfp_t mem_flags
)
4691 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
4692 struct xhci_virt_device
*vdev
;
4693 struct xhci_command
*config_cmd
;
4694 struct xhci_input_control_ctx
*ctrl_ctx
;
4695 struct xhci_slot_ctx
*slot_ctx
;
4696 unsigned long flags
;
4697 unsigned think_time
;
4700 /* Ignore root hubs */
4704 vdev
= xhci
->devs
[hdev
->slot_id
];
4706 xhci_warn(xhci
, "Cannot update hub desc for unknown device.\n");
4709 config_cmd
= xhci_alloc_command(xhci
, true, true, mem_flags
);
4711 xhci_dbg(xhci
, "Could not allocate xHCI command structure.\n");
4714 ctrl_ctx
= xhci_get_input_control_ctx(config_cmd
->in_ctx
);
4716 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
4718 xhci_free_command(xhci
, config_cmd
);
4722 spin_lock_irqsave(&xhci
->lock
, flags
);
4723 if (hdev
->speed
== USB_SPEED_HIGH
&&
4724 xhci_alloc_tt_info(xhci
, vdev
, hdev
, tt
, GFP_ATOMIC
)) {
4725 xhci_dbg(xhci
, "Could not allocate xHCI TT structure.\n");
4726 xhci_free_command(xhci
, config_cmd
);
4727 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4731 xhci_slot_copy(xhci
, config_cmd
->in_ctx
, vdev
->out_ctx
);
4732 ctrl_ctx
->add_flags
|= cpu_to_le32(SLOT_FLAG
);
4733 slot_ctx
= xhci_get_slot_ctx(xhci
, config_cmd
->in_ctx
);
4734 slot_ctx
->dev_info
|= cpu_to_le32(DEV_HUB
);
4736 * refer to section 6.2.2: MTT should be 0 for full speed hub,
4737 * but it may be already set to 1 when setup an xHCI virtual
4738 * device, so clear it anyway.
4741 slot_ctx
->dev_info
|= cpu_to_le32(DEV_MTT
);
4742 else if (hdev
->speed
== USB_SPEED_FULL
)
4743 slot_ctx
->dev_info
&= cpu_to_le32(~DEV_MTT
);
4745 if (xhci
->hci_version
> 0x95) {
4746 xhci_dbg(xhci
, "xHCI version %x needs hub "
4747 "TT think time and number of ports\n",
4748 (unsigned int) xhci
->hci_version
);
4749 slot_ctx
->dev_info2
|= cpu_to_le32(XHCI_MAX_PORTS(hdev
->maxchild
));
4750 /* Set TT think time - convert from ns to FS bit times.
4751 * 0 = 8 FS bit times, 1 = 16 FS bit times,
4752 * 2 = 24 FS bit times, 3 = 32 FS bit times.
4754 * xHCI 1.0: this field shall be 0 if the device is not a
4757 think_time
= tt
->think_time
;
4758 if (think_time
!= 0)
4759 think_time
= (think_time
/ 666) - 1;
4760 if (xhci
->hci_version
< 0x100 || hdev
->speed
== USB_SPEED_HIGH
)
4761 slot_ctx
->tt_info
|=
4762 cpu_to_le32(TT_THINK_TIME(think_time
));
4764 xhci_dbg(xhci
, "xHCI version %x doesn't need hub "
4765 "TT think time or number of ports\n",
4766 (unsigned int) xhci
->hci_version
);
4768 slot_ctx
->dev_state
= 0;
4769 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4771 xhci_dbg(xhci
, "Set up %s for hub device.\n",
4772 (xhci
->hci_version
> 0x95) ?
4773 "configure endpoint" : "evaluate context");
4774 xhci_dbg(xhci
, "Slot %u Input Context:\n", hdev
->slot_id
);
4775 xhci_dbg_ctx(xhci
, config_cmd
->in_ctx
, 0);
4777 /* Issue and wait for the configure endpoint or
4778 * evaluate context command.
4780 if (xhci
->hci_version
> 0x95)
4781 ret
= xhci_configure_endpoint(xhci
, hdev
, config_cmd
,
4784 ret
= xhci_configure_endpoint(xhci
, hdev
, config_cmd
,
4787 xhci_dbg(xhci
, "Slot %u Output Context:\n", hdev
->slot_id
);
4788 xhci_dbg_ctx(xhci
, vdev
->out_ctx
, 0);
4790 xhci_free_command(xhci
, config_cmd
);
4794 int xhci_get_frame(struct usb_hcd
*hcd
)
4796 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
4797 /* EHCI mods by the periodic size. Why? */
4798 return readl(&xhci
->run_regs
->microframe_index
) >> 3;
4801 int xhci_gen_setup(struct usb_hcd
*hcd
, xhci_get_quirks_t get_quirks
)
4803 struct xhci_hcd
*xhci
;
4804 struct device
*dev
= hcd
->self
.controller
;
4807 /* Accept arbitrarily long scatter-gather lists */
4808 hcd
->self
.sg_tablesize
= ~0;
4810 /* support to build packet from discontinuous buffers */
4811 hcd
->self
.no_sg_constraint
= 1;
4813 /* XHCI controllers don't stop the ep queue on short packets :| */
4814 hcd
->self
.no_stop_on_short
= 1;
4816 xhci
= hcd_to_xhci(hcd
);
4818 if (usb_hcd_is_primary_hcd(hcd
)) {
4819 xhci
->main_hcd
= hcd
;
4820 /* Mark the first roothub as being USB 2.0.
4821 * The xHCI driver will register the USB 3.0 roothub.
4823 hcd
->speed
= HCD_USB2
;
4824 hcd
->self
.root_hub
->speed
= USB_SPEED_HIGH
;
4826 * USB 2.0 roothub under xHCI has an integrated TT,
4827 * (rate matching hub) as opposed to having an OHCI/UHCI
4828 * companion controller.
4832 if (xhci
->sbrn
== 0x31) {
4833 xhci_info(xhci
, "Host supports USB 3.1 Enhanced SuperSpeed\n");
4834 hcd
->speed
= HCD_USB31
;
4835 hcd
->self
.root_hub
->speed
= USB_SPEED_SUPER_PLUS
;
4837 /* xHCI private pointer was set in xhci_pci_probe for the second
4838 * registered roothub.
4843 mutex_init(&xhci
->mutex
);
4844 xhci
->cap_regs
= hcd
->regs
;
4845 xhci
->op_regs
= hcd
->regs
+
4846 HC_LENGTH(readl(&xhci
->cap_regs
->hc_capbase
));
4847 xhci
->run_regs
= hcd
->regs
+
4848 (readl(&xhci
->cap_regs
->run_regs_off
) & RTSOFF_MASK
);
4849 /* Cache read-only capability registers */
4850 xhci
->hcs_params1
= readl(&xhci
->cap_regs
->hcs_params1
);
4851 xhci
->hcs_params2
= readl(&xhci
->cap_regs
->hcs_params2
);
4852 xhci
->hcs_params3
= readl(&xhci
->cap_regs
->hcs_params3
);
4853 xhci
->hcc_params
= readl(&xhci
->cap_regs
->hc_capbase
);
4854 xhci
->hci_version
= HC_VERSION(xhci
->hcc_params
);
4855 xhci
->hcc_params
= readl(&xhci
->cap_regs
->hcc_params
);
4856 if (xhci
->hci_version
> 0x100)
4857 xhci
->hcc_params2
= readl(&xhci
->cap_regs
->hcc_params2
);
4858 xhci_print_registers(xhci
);
4860 xhci
->quirks
|= quirks
;
4862 get_quirks(dev
, xhci
);
4864 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
4865 * success event after a short transfer. This quirk will ignore such
4868 if (xhci
->hci_version
> 0x96)
4869 xhci
->quirks
|= XHCI_SPURIOUS_SUCCESS
;
4871 /* Make sure the HC is halted. */
4872 retval
= xhci_halt(xhci
);
4876 xhci_dbg(xhci
, "Resetting HCD\n");
4877 /* Reset the internal HC memory state and registers. */
4878 retval
= xhci_reset(xhci
);
4881 xhci_dbg(xhci
, "Reset complete\n");
4884 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
4885 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
4886 * address memory pointers actually. So, this driver clears the AC64
4887 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
4888 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
4890 if (xhci
->quirks
& XHCI_NO_64BIT_SUPPORT
)
4891 xhci
->hcc_params
&= ~BIT(0);
4893 /* Set dma_mask and coherent_dma_mask to 64-bits,
4894 * if xHC supports 64-bit addressing */
4895 if (HCC_64BIT_ADDR(xhci
->hcc_params
) &&
4896 !dma_set_mask(dev
, DMA_BIT_MASK(64))) {
4897 xhci_dbg(xhci
, "Enabling 64-bit DMA addresses.\n");
4898 dma_set_coherent_mask(dev
, DMA_BIT_MASK(64));
4901 * This is to avoid error in cases where a 32-bit USB
4902 * controller is used on a 64-bit capable system.
4904 retval
= dma_set_mask(dev
, DMA_BIT_MASK(32));
4907 xhci_dbg(xhci
, "Enabling 32-bit DMA addresses.\n");
4908 dma_set_coherent_mask(dev
, DMA_BIT_MASK(32));
4911 xhci_dbg(xhci
, "Calling HCD init\n");
4912 /* Initialize HCD and host controller data structures. */
4913 retval
= xhci_init(hcd
);
4916 xhci_dbg(xhci
, "Called HCD init\n");
4918 xhci_info(xhci
, "hcc params 0x%08x hci version 0x%x quirks 0x%08x\n",
4919 xhci
->hcc_params
, xhci
->hci_version
, xhci
->quirks
);
4923 EXPORT_SYMBOL_GPL(xhci_gen_setup
);
4925 static const struct hc_driver xhci_hc_driver
= {
4926 .description
= "xhci-hcd",
4927 .product_desc
= "xHCI Host Controller",
4928 .hcd_priv_size
= sizeof(struct xhci_hcd
),
4931 * generic hardware linkage
4934 .flags
= HCD_MEMORY
| HCD_USB3
| HCD_SHARED
,
4937 * basic lifecycle operations
4939 .reset
= NULL
, /* set in xhci_init_driver() */
4942 .shutdown
= xhci_shutdown
,
4945 * managing i/o requests and associated device resources
4947 .urb_enqueue
= xhci_urb_enqueue
,
4948 .urb_dequeue
= xhci_urb_dequeue
,
4949 .alloc_dev
= xhci_alloc_dev
,
4950 .free_dev
= xhci_free_dev
,
4951 .alloc_streams
= xhci_alloc_streams
,
4952 .free_streams
= xhci_free_streams
,
4953 .add_endpoint
= xhci_add_endpoint
,
4954 .drop_endpoint
= xhci_drop_endpoint
,
4955 .endpoint_reset
= xhci_endpoint_reset
,
4956 .check_bandwidth
= xhci_check_bandwidth
,
4957 .reset_bandwidth
= xhci_reset_bandwidth
,
4958 .address_device
= xhci_address_device
,
4959 .enable_device
= xhci_enable_device
,
4960 .update_hub_device
= xhci_update_hub_device
,
4961 .reset_device
= xhci_discover_or_reset_device
,
4964 * scheduling support
4966 .get_frame_number
= xhci_get_frame
,
4971 .hub_control
= xhci_hub_control
,
4972 .hub_status_data
= xhci_hub_status_data
,
4973 .bus_suspend
= xhci_bus_suspend
,
4974 .bus_resume
= xhci_bus_resume
,
4977 * call back when device connected and addressed
4979 .update_device
= xhci_update_device
,
4980 .set_usb2_hw_lpm
= xhci_set_usb2_hardware_lpm
,
4981 .enable_usb3_lpm_timeout
= xhci_enable_usb3_lpm_timeout
,
4982 .disable_usb3_lpm_timeout
= xhci_disable_usb3_lpm_timeout
,
4983 .find_raw_port_number
= xhci_find_raw_port_number
,
4986 void xhci_init_driver(struct hc_driver
*drv
,
4987 const struct xhci_driver_overrides
*over
)
4991 /* Copy the generic table to drv then apply the overrides */
4992 *drv
= xhci_hc_driver
;
4995 drv
->hcd_priv_size
+= over
->extra_priv_size
;
4997 drv
->reset
= over
->reset
;
4999 drv
->start
= over
->start
;
5002 EXPORT_SYMBOL_GPL(xhci_init_driver
);
5004 MODULE_DESCRIPTION(DRIVER_DESC
);
5005 MODULE_AUTHOR(DRIVER_AUTHOR
);
5006 MODULE_LICENSE("GPL");
5008 static int __init
xhci_hcd_init(void)
5011 * Check the compiler generated sizes of structures that must be laid
5012 * out in specific ways for hardware access.
5014 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array
) != 256*32/8);
5015 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx
) != 8*32/8);
5016 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx
) != 8*32/8);
5017 /* xhci_device_control has eight fields, and also
5018 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5020 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx
) != 4*32/8);
5021 BUILD_BUG_ON(sizeof(union xhci_trb
) != 4*32/8);
5022 BUILD_BUG_ON(sizeof(struct xhci_erst_entry
) != 4*32/8);
5023 BUILD_BUG_ON(sizeof(struct xhci_cap_regs
) != 8*32/8);
5024 BUILD_BUG_ON(sizeof(struct xhci_intr_reg
) != 8*32/8);
5025 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5026 BUILD_BUG_ON(sizeof(struct xhci_run_regs
) != (8+8*128)*32/8);
5035 * If an init function is provided, an exit function must also be provided
5036 * to allow module unload.
5038 static void __exit
xhci_hcd_fini(void) { }
5040 module_init(xhci_hcd_init
);
5041 module_exit(xhci_hcd_fini
);