1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
11 #include <linux/pci.h>
12 #include <linux/irq.h>
13 #include <linux/log2.h>
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/slab.h>
17 #include <linux/dmi.h>
18 #include <linux/dma-mapping.h>
21 #include "xhci-trace.h"
23 #include "xhci-debugfs.h"
24 #include "xhci-dbgcap.h"
26 #define DRIVER_AUTHOR "Sarah Sharp"
27 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
29 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
31 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
32 static int link_quirk
;
33 module_param(link_quirk
, int, S_IRUGO
| S_IWUSR
);
34 MODULE_PARM_DESC(link_quirk
, "Don't clear the chain bit on a link TRB");
36 static unsigned long long quirks
;
37 module_param(quirks
, ullong
, S_IRUGO
);
38 MODULE_PARM_DESC(quirks
, "Bit flags for quirks to be enabled as default");
40 /* TODO: copied from ehci-hcd.c - can this be refactored? */
42 * xhci_handshake - spin reading hc until handshake completes or fails
43 * @ptr: address of hc register to be read
44 * @mask: bits to look at in result of read
45 * @done: value of those bits when handshake succeeds
46 * @usec: timeout in microseconds
48 * Returns negative errno, or zero on success
50 * Success happens when the "mask" bits have the specified value (hardware
51 * handshake done). There are two failure modes: "usec" have passed (major
52 * hardware flakeout), or the register reads as all-ones (hardware removed).
54 int xhci_handshake(void __iomem
*ptr
, u32 mask
, u32 done
, int usec
)
60 if (result
== ~(u32
)0) /* card removed */
72 * Disable interrupts and begin the xHCI halting process.
74 void xhci_quiesce(struct xhci_hcd
*xhci
)
81 halted
= readl(&xhci
->op_regs
->status
) & STS_HALT
;
85 cmd
= readl(&xhci
->op_regs
->command
);
87 writel(cmd
, &xhci
->op_regs
->command
);
91 * Force HC into halt state.
93 * Disable any IRQs and clear the run/stop bit.
94 * HC will complete any current and actively pipelined transactions, and
95 * should halt within 16 ms of the run/stop bit being cleared.
96 * Read HC Halted bit in the status register to see when the HC is finished.
98 int xhci_halt(struct xhci_hcd
*xhci
)
101 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "// Halt the HC");
104 ret
= xhci_handshake(&xhci
->op_regs
->status
,
105 STS_HALT
, STS_HALT
, XHCI_MAX_HALT_USEC
);
107 xhci_warn(xhci
, "Host halt failed, %d\n", ret
);
110 xhci
->xhc_state
|= XHCI_STATE_HALTED
;
111 xhci
->cmd_ring_state
= CMD_RING_STATE_STOPPED
;
116 * Set the run bit and wait for the host to be running.
118 int xhci_start(struct xhci_hcd
*xhci
)
123 temp
= readl(&xhci
->op_regs
->command
);
125 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "// Turn on HC, cmd = 0x%x.",
127 writel(temp
, &xhci
->op_regs
->command
);
130 * Wait for the HCHalted Status bit to be 0 to indicate the host is
133 ret
= xhci_handshake(&xhci
->op_regs
->status
,
134 STS_HALT
, 0, XHCI_MAX_HALT_USEC
);
135 if (ret
== -ETIMEDOUT
)
136 xhci_err(xhci
, "Host took too long to start, "
137 "waited %u microseconds.\n",
140 /* clear state flags. Including dying, halted or removing */
149 * This resets pipelines, timers, counters, state machines, etc.
150 * Transactions will be terminated immediately, and operational registers
151 * will be set to their defaults.
153 int xhci_reset(struct xhci_hcd
*xhci
)
159 state
= readl(&xhci
->op_regs
->status
);
161 if (state
== ~(u32
)0) {
162 xhci_warn(xhci
, "Host not accessible, reset failed.\n");
166 if ((state
& STS_HALT
) == 0) {
167 xhci_warn(xhci
, "Host controller not halted, aborting reset.\n");
171 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "// Reset the HC");
172 command
= readl(&xhci
->op_regs
->command
);
173 command
|= CMD_RESET
;
174 writel(command
, &xhci
->op_regs
->command
);
176 /* Existing Intel xHCI controllers require a delay of 1 mS,
177 * after setting the CMD_RESET bit, and before accessing any
178 * HC registers. This allows the HC to complete the
179 * reset operation and be ready for HC register access.
180 * Without this delay, the subsequent HC register access,
181 * may result in a system hang very rarely.
183 if (xhci
->quirks
& XHCI_INTEL_HOST
)
186 ret
= xhci_handshake(&xhci
->op_regs
->command
,
187 CMD_RESET
, 0, 10 * 1000 * 1000);
191 if (xhci
->quirks
& XHCI_ASMEDIA_MODIFY_FLOWCONTROL
)
192 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
));
194 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
195 "Wait for controller to be ready for doorbell rings");
197 * xHCI cannot write to any doorbells or operational registers other
198 * than status until the "Controller Not Ready" flag is cleared.
200 ret
= xhci_handshake(&xhci
->op_regs
->status
,
201 STS_CNR
, 0, 10 * 1000 * 1000);
203 for (i
= 0; i
< 2; i
++) {
204 xhci
->bus_state
[i
].port_c_suspend
= 0;
205 xhci
->bus_state
[i
].suspended_ports
= 0;
206 xhci
->bus_state
[i
].resuming_ports
= 0;
213 #ifdef CONFIG_USB_PCI
217 static int xhci_setup_msi(struct xhci_hcd
*xhci
)
221 * TODO:Check with MSI Soc for sysdev
223 struct pci_dev
*pdev
= to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
);
225 ret
= pci_alloc_irq_vectors(pdev
, 1, 1, PCI_IRQ_MSI
);
227 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
228 "failed to allocate MSI entry");
232 ret
= request_irq(pdev
->irq
, xhci_msi_irq
,
233 0, "xhci_hcd", xhci_to_hcd(xhci
));
235 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
236 "disable MSI interrupt");
237 pci_free_irq_vectors(pdev
);
246 static int xhci_setup_msix(struct xhci_hcd
*xhci
)
249 struct usb_hcd
*hcd
= xhci_to_hcd(xhci
);
250 struct pci_dev
*pdev
= to_pci_dev(hcd
->self
.controller
);
253 * calculate number of msi-x vectors supported.
254 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
255 * with max number of interrupters based on the xhci HCSPARAMS1.
256 * - num_online_cpus: maximum msi-x vectors per CPUs core.
257 * Add additional 1 vector to ensure always available interrupt.
259 xhci
->msix_count
= min(num_online_cpus() + 1,
260 HCS_MAX_INTRS(xhci
->hcs_params1
));
262 ret
= pci_alloc_irq_vectors(pdev
, xhci
->msix_count
, xhci
->msix_count
,
265 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
266 "Failed to enable MSI-X");
270 for (i
= 0; i
< xhci
->msix_count
; i
++) {
271 ret
= request_irq(pci_irq_vector(pdev
, i
), xhci_msi_irq
, 0,
272 "xhci_hcd", xhci_to_hcd(xhci
));
277 hcd
->msix_enabled
= 1;
281 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "disable MSI-X interrupt");
283 free_irq(pci_irq_vector(pdev
, i
), xhci_to_hcd(xhci
));
284 pci_free_irq_vectors(pdev
);
288 /* Free any IRQs and disable MSI-X */
289 static void xhci_cleanup_msix(struct xhci_hcd
*xhci
)
291 struct usb_hcd
*hcd
= xhci_to_hcd(xhci
);
292 struct pci_dev
*pdev
= to_pci_dev(hcd
->self
.controller
);
294 if (xhci
->quirks
& XHCI_PLAT
)
297 /* return if using legacy interrupt */
301 if (hcd
->msix_enabled
) {
304 for (i
= 0; i
< xhci
->msix_count
; i
++)
305 free_irq(pci_irq_vector(pdev
, i
), xhci_to_hcd(xhci
));
307 free_irq(pci_irq_vector(pdev
, 0), xhci_to_hcd(xhci
));
310 pci_free_irq_vectors(pdev
);
311 hcd
->msix_enabled
= 0;
314 static void __maybe_unused
xhci_msix_sync_irqs(struct xhci_hcd
*xhci
)
316 struct usb_hcd
*hcd
= xhci_to_hcd(xhci
);
318 if (hcd
->msix_enabled
) {
319 struct pci_dev
*pdev
= to_pci_dev(hcd
->self
.controller
);
322 for (i
= 0; i
< xhci
->msix_count
; i
++)
323 synchronize_irq(pci_irq_vector(pdev
, i
));
327 static int xhci_try_enable_msi(struct usb_hcd
*hcd
)
329 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
330 struct pci_dev
*pdev
;
333 /* The xhci platform device has set up IRQs through usb_add_hcd. */
334 if (xhci
->quirks
& XHCI_PLAT
)
337 pdev
= to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
);
339 * Some Fresco Logic host controllers advertise MSI, but fail to
340 * generate interrupts. Don't even try to enable MSI.
342 if (xhci
->quirks
& XHCI_BROKEN_MSI
)
345 /* unregister the legacy interrupt */
347 free_irq(hcd
->irq
, hcd
);
350 ret
= xhci_setup_msix(xhci
);
352 /* fall back to msi*/
353 ret
= xhci_setup_msi(xhci
);
356 hcd
->msi_enabled
= 1;
361 xhci_err(xhci
, "No msi-x/msi found and no IRQ in BIOS\n");
366 if (!strlen(hcd
->irq_descr
))
367 snprintf(hcd
->irq_descr
, sizeof(hcd
->irq_descr
), "%s:usb%d",
368 hcd
->driver
->description
, hcd
->self
.busnum
);
370 /* fall back to legacy interrupt*/
371 ret
= request_irq(pdev
->irq
, &usb_hcd_irq
, IRQF_SHARED
,
372 hcd
->irq_descr
, hcd
);
374 xhci_err(xhci
, "request interrupt %d failed\n",
378 hcd
->irq
= pdev
->irq
;
384 static inline int xhci_try_enable_msi(struct usb_hcd
*hcd
)
389 static inline void xhci_cleanup_msix(struct xhci_hcd
*xhci
)
393 static inline void xhci_msix_sync_irqs(struct xhci_hcd
*xhci
)
399 static void compliance_mode_recovery(struct timer_list
*t
)
401 struct xhci_hcd
*xhci
;
406 xhci
= from_timer(xhci
, t
, comp_mode_recovery_timer
);
408 for (i
= 0; i
< xhci
->num_usb3_ports
; i
++) {
409 temp
= readl(xhci
->usb3_ports
[i
]);
410 if ((temp
& PORT_PLS_MASK
) == USB_SS_PORT_LS_COMP_MOD
) {
412 * Compliance Mode Detected. Letting USB Core
413 * handle the Warm Reset
415 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
416 "Compliance mode detected->port %d",
418 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
419 "Attempting compliance mode recovery");
420 hcd
= xhci
->shared_hcd
;
422 if (hcd
->state
== HC_STATE_SUSPENDED
)
423 usb_hcd_resume_root_hub(hcd
);
425 usb_hcd_poll_rh_status(hcd
);
429 if (xhci
->port_status_u0
!= ((1 << xhci
->num_usb3_ports
)-1))
430 mod_timer(&xhci
->comp_mode_recovery_timer
,
431 jiffies
+ msecs_to_jiffies(COMP_MODE_RCVRY_MSECS
));
435 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
436 * that causes ports behind that hardware to enter compliance mode sometimes.
437 * The quirk creates a timer that polls every 2 seconds the link state of
438 * each host controller's port and recovers it by issuing a Warm reset
439 * if Compliance mode is detected, otherwise the port will become "dead" (no
440 * device connections or disconnections will be detected anymore). Becasue no
441 * status event is generated when entering compliance mode (per xhci spec),
442 * this quirk is needed on systems that have the failing hardware installed.
444 static void compliance_mode_recovery_timer_init(struct xhci_hcd
*xhci
)
446 xhci
->port_status_u0
= 0;
447 timer_setup(&xhci
->comp_mode_recovery_timer
, compliance_mode_recovery
,
449 xhci
->comp_mode_recovery_timer
.expires
= jiffies
+
450 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS
);
452 add_timer(&xhci
->comp_mode_recovery_timer
);
453 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
454 "Compliance mode recovery timer initialized");
458 * This function identifies the systems that have installed the SN65LVPE502CP
459 * USB3.0 re-driver and that need the Compliance Mode Quirk.
461 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
463 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
465 const char *dmi_product_name
, *dmi_sys_vendor
;
467 dmi_product_name
= dmi_get_system_info(DMI_PRODUCT_NAME
);
468 dmi_sys_vendor
= dmi_get_system_info(DMI_SYS_VENDOR
);
469 if (!dmi_product_name
|| !dmi_sys_vendor
)
472 if (!(strstr(dmi_sys_vendor
, "Hewlett-Packard")))
475 if (strstr(dmi_product_name
, "Z420") ||
476 strstr(dmi_product_name
, "Z620") ||
477 strstr(dmi_product_name
, "Z820") ||
478 strstr(dmi_product_name
, "Z1 Workstation"))
484 static int xhci_all_ports_seen_u0(struct xhci_hcd
*xhci
)
486 return (xhci
->port_status_u0
== ((1 << xhci
->num_usb3_ports
)-1));
491 * Initialize memory for HCD and xHC (one-time init).
493 * Program the PAGESIZE register, initialize the device context array, create
494 * device contexts (?), set up a command ring segment (or two?), create event
495 * ring (one for now).
497 static int xhci_init(struct usb_hcd
*hcd
)
499 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
502 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "xhci_init");
503 spin_lock_init(&xhci
->lock
);
504 if (xhci
->hci_version
== 0x95 && link_quirk
) {
505 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
506 "QUIRK: Not clearing Link TRB chain bits.");
507 xhci
->quirks
|= XHCI_LINK_TRB_QUIRK
;
509 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
510 "xHCI doesn't need link TRB QUIRK");
512 retval
= xhci_mem_init(xhci
, GFP_KERNEL
);
513 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "Finished xhci_init");
515 /* Initializing Compliance Mode Recovery Data If Needed */
516 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
517 xhci
->quirks
|= XHCI_COMP_MODE_QUIRK
;
518 compliance_mode_recovery_timer_init(xhci
);
524 /*-------------------------------------------------------------------------*/
527 static int xhci_run_finished(struct xhci_hcd
*xhci
)
529 if (xhci_start(xhci
)) {
533 xhci
->shared_hcd
->state
= HC_STATE_RUNNING
;
534 xhci
->cmd_ring_state
= CMD_RING_STATE_RUNNING
;
536 if (xhci
->quirks
& XHCI_NEC_HOST
)
537 xhci_ring_cmd_db(xhci
);
539 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
540 "Finished xhci_run for USB3 roothub");
545 * Start the HC after it was halted.
547 * This function is called by the USB core when the HC driver is added.
548 * Its opposite is xhci_stop().
550 * xhci_init() must be called once before this function can be called.
551 * Reset the HC, enable device slot contexts, program DCBAAP, and
552 * set command ring pointer and event ring pointer.
554 * Setup MSI-X vectors and enable interrupts.
556 int xhci_run(struct usb_hcd
*hcd
)
561 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
563 /* Start the xHCI host controller running only after the USB 2.0 roothub
567 hcd
->uses_new_polling
= 1;
568 if (!usb_hcd_is_primary_hcd(hcd
))
569 return xhci_run_finished(xhci
);
571 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "xhci_run");
573 ret
= xhci_try_enable_msi(hcd
);
577 xhci_dbg_cmd_ptrs(xhci
);
579 xhci_dbg(xhci
, "ERST memory map follows:\n");
580 xhci_dbg_erst(xhci
, &xhci
->erst
);
581 temp_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
582 temp_64
&= ~ERST_PTR_MASK
;
583 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
584 "ERST deq = 64'h%0lx", (long unsigned int) temp_64
);
586 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
587 "// Set the interrupt modulation register");
588 temp
= readl(&xhci
->ir_set
->irq_control
);
589 temp
&= ~ER_IRQ_INTERVAL_MASK
;
591 * the increment interval is 8 times as much as that defined
592 * in xHCI spec on MTK's controller
594 temp
|= (u32
) ((xhci
->quirks
& XHCI_MTK_HOST
) ? 20 : 160);
595 writel(temp
, &xhci
->ir_set
->irq_control
);
597 /* Set the HCD state before we enable the irqs */
598 temp
= readl(&xhci
->op_regs
->command
);
600 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
601 "// Enable interrupts, cmd = 0x%x.", temp
);
602 writel(temp
, &xhci
->op_regs
->command
);
604 temp
= readl(&xhci
->ir_set
->irq_pending
);
605 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
606 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
607 xhci
->ir_set
, (unsigned int) ER_IRQ_ENABLE(temp
));
608 writel(ER_IRQ_ENABLE(temp
), &xhci
->ir_set
->irq_pending
);
609 xhci_print_ir_set(xhci
, 0);
611 if (xhci
->quirks
& XHCI_NEC_HOST
) {
612 struct xhci_command
*command
;
614 command
= xhci_alloc_command(xhci
, false, false, GFP_KERNEL
);
618 ret
= xhci_queue_vendor_command(xhci
, command
, 0, 0, 0,
619 TRB_TYPE(TRB_NEC_GET_FW
));
621 xhci_free_command(xhci
, command
);
623 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
624 "Finished xhci_run for USB2 roothub");
628 xhci_debugfs_init(xhci
);
632 EXPORT_SYMBOL_GPL(xhci_run
);
637 * This function is called by the USB core when the HC driver is removed.
638 * Its opposite is xhci_run().
640 * Disable device contexts, disable IRQs, and quiesce the HC.
641 * Reset the HC, finish any completed transactions, and cleanup memory.
643 static void xhci_stop(struct usb_hcd
*hcd
)
646 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
648 mutex_lock(&xhci
->mutex
);
650 /* Only halt host and free memory after both hcds are removed */
651 if (!usb_hcd_is_primary_hcd(hcd
)) {
652 /* usb core will free this hcd shortly, unset pointer */
653 xhci
->shared_hcd
= NULL
;
654 mutex_unlock(&xhci
->mutex
);
660 spin_lock_irq(&xhci
->lock
);
661 xhci
->xhc_state
|= XHCI_STATE_HALTED
;
662 xhci
->cmd_ring_state
= CMD_RING_STATE_STOPPED
;
665 spin_unlock_irq(&xhci
->lock
);
667 xhci_cleanup_msix(xhci
);
669 /* Deleting Compliance Mode Recovery Timer */
670 if ((xhci
->quirks
& XHCI_COMP_MODE_QUIRK
) &&
671 (!(xhci_all_ports_seen_u0(xhci
)))) {
672 del_timer_sync(&xhci
->comp_mode_recovery_timer
);
673 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
674 "%s: compliance mode recovery timer deleted",
678 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
681 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
682 "// Disabling event ring interrupts");
683 temp
= readl(&xhci
->op_regs
->status
);
684 writel((temp
& ~0x1fff) | STS_EINT
, &xhci
->op_regs
->status
);
685 temp
= readl(&xhci
->ir_set
->irq_pending
);
686 writel(ER_IRQ_DISABLE(temp
), &xhci
->ir_set
->irq_pending
);
687 xhci_print_ir_set(xhci
, 0);
689 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "cleaning up memory");
690 xhci_mem_cleanup(xhci
);
691 xhci_debugfs_exit(xhci
);
692 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
693 "xhci_stop completed - status = %x",
694 readl(&xhci
->op_regs
->status
));
695 mutex_unlock(&xhci
->mutex
);
699 * Shutdown HC (not bus-specific)
701 * This is called when the machine is rebooting or halting. We assume that the
702 * machine will be powered off, and the HC's internal state will be reset.
703 * Don't bother to free memory.
705 * This will only ever be called with the main usb_hcd (the USB3 roothub).
707 static void xhci_shutdown(struct usb_hcd
*hcd
)
709 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
711 if (xhci
->quirks
& XHCI_SPURIOUS_REBOOT
)
712 usb_disable_xhci_ports(to_pci_dev(hcd
->self
.sysdev
));
714 spin_lock_irq(&xhci
->lock
);
716 /* Workaround for spurious wakeups at shutdown with HSW */
717 if (xhci
->quirks
& XHCI_SPURIOUS_WAKEUP
)
719 spin_unlock_irq(&xhci
->lock
);
721 xhci_cleanup_msix(xhci
);
723 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
724 "xhci_shutdown completed - status = %x",
725 readl(&xhci
->op_regs
->status
));
727 /* Yet another workaround for spurious wakeups at shutdown with HSW */
728 if (xhci
->quirks
& XHCI_SPURIOUS_WAKEUP
)
729 pci_set_power_state(to_pci_dev(hcd
->self
.sysdev
), PCI_D3hot
);
733 static void xhci_save_registers(struct xhci_hcd
*xhci
)
735 xhci
->s3
.command
= readl(&xhci
->op_regs
->command
);
736 xhci
->s3
.dev_nt
= readl(&xhci
->op_regs
->dev_notification
);
737 xhci
->s3
.dcbaa_ptr
= xhci_read_64(xhci
, &xhci
->op_regs
->dcbaa_ptr
);
738 xhci
->s3
.config_reg
= readl(&xhci
->op_regs
->config_reg
);
739 xhci
->s3
.erst_size
= readl(&xhci
->ir_set
->erst_size
);
740 xhci
->s3
.erst_base
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_base
);
741 xhci
->s3
.erst_dequeue
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
742 xhci
->s3
.irq_pending
= readl(&xhci
->ir_set
->irq_pending
);
743 xhci
->s3
.irq_control
= readl(&xhci
->ir_set
->irq_control
);
746 static void xhci_restore_registers(struct xhci_hcd
*xhci
)
748 writel(xhci
->s3
.command
, &xhci
->op_regs
->command
);
749 writel(xhci
->s3
.dev_nt
, &xhci
->op_regs
->dev_notification
);
750 xhci_write_64(xhci
, xhci
->s3
.dcbaa_ptr
, &xhci
->op_regs
->dcbaa_ptr
);
751 writel(xhci
->s3
.config_reg
, &xhci
->op_regs
->config_reg
);
752 writel(xhci
->s3
.erst_size
, &xhci
->ir_set
->erst_size
);
753 xhci_write_64(xhci
, xhci
->s3
.erst_base
, &xhci
->ir_set
->erst_base
);
754 xhci_write_64(xhci
, xhci
->s3
.erst_dequeue
, &xhci
->ir_set
->erst_dequeue
);
755 writel(xhci
->s3
.irq_pending
, &xhci
->ir_set
->irq_pending
);
756 writel(xhci
->s3
.irq_control
, &xhci
->ir_set
->irq_control
);
759 static void xhci_set_cmd_ring_deq(struct xhci_hcd
*xhci
)
763 /* step 2: initialize command ring buffer */
764 val_64
= xhci_read_64(xhci
, &xhci
->op_regs
->cmd_ring
);
765 val_64
= (val_64
& (u64
) CMD_RING_RSVD_BITS
) |
766 (xhci_trb_virt_to_dma(xhci
->cmd_ring
->deq_seg
,
767 xhci
->cmd_ring
->dequeue
) &
768 (u64
) ~CMD_RING_RSVD_BITS
) |
769 xhci
->cmd_ring
->cycle_state
;
770 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
771 "// Setting command ring address to 0x%llx",
772 (long unsigned long) val_64
);
773 xhci_write_64(xhci
, val_64
, &xhci
->op_regs
->cmd_ring
);
777 * The whole command ring must be cleared to zero when we suspend the host.
779 * The host doesn't save the command ring pointer in the suspend well, so we
780 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
781 * aligned, because of the reserved bits in the command ring dequeue pointer
782 * register. Therefore, we can't just set the dequeue pointer back in the
783 * middle of the ring (TRBs are 16-byte aligned).
785 static void xhci_clear_command_ring(struct xhci_hcd
*xhci
)
787 struct xhci_ring
*ring
;
788 struct xhci_segment
*seg
;
790 ring
= xhci
->cmd_ring
;
794 sizeof(union xhci_trb
) * (TRBS_PER_SEGMENT
- 1));
795 seg
->trbs
[TRBS_PER_SEGMENT
- 1].link
.control
&=
796 cpu_to_le32(~TRB_CYCLE
);
798 } while (seg
!= ring
->deq_seg
);
800 /* Reset the software enqueue and dequeue pointers */
801 ring
->deq_seg
= ring
->first_seg
;
802 ring
->dequeue
= ring
->first_seg
->trbs
;
803 ring
->enq_seg
= ring
->deq_seg
;
804 ring
->enqueue
= ring
->dequeue
;
806 ring
->num_trbs_free
= ring
->num_segs
* (TRBS_PER_SEGMENT
- 1) - 1;
808 * Ring is now zeroed, so the HW should look for change of ownership
809 * when the cycle bit is set to 1.
811 ring
->cycle_state
= 1;
814 * Reset the hardware dequeue pointer.
815 * Yes, this will need to be re-written after resume, but we're paranoid
816 * and want to make sure the hardware doesn't access bogus memory
817 * because, say, the BIOS or an SMI started the host without changing
818 * the command ring pointers.
820 xhci_set_cmd_ring_deq(xhci
);
823 static void xhci_disable_port_wake_on_bits(struct xhci_hcd
*xhci
)
826 __le32 __iomem
**port_array
;
830 spin_lock_irqsave(&xhci
->lock
, flags
);
832 /* disable usb3 ports Wake bits */
833 port_index
= xhci
->num_usb3_ports
;
834 port_array
= xhci
->usb3_ports
;
835 while (port_index
--) {
836 t1
= readl(port_array
[port_index
]);
837 t1
= xhci_port_state_to_neutral(t1
);
838 t2
= t1
& ~PORT_WAKE_BITS
;
840 writel(t2
, port_array
[port_index
]);
843 /* disable usb2 ports Wake bits */
844 port_index
= xhci
->num_usb2_ports
;
845 port_array
= xhci
->usb2_ports
;
846 while (port_index
--) {
847 t1
= readl(port_array
[port_index
]);
848 t1
= xhci_port_state_to_neutral(t1
);
849 t2
= t1
& ~PORT_WAKE_BITS
;
851 writel(t2
, port_array
[port_index
]);
854 spin_unlock_irqrestore(&xhci
->lock
, flags
);
857 static bool xhci_pending_portevent(struct xhci_hcd
*xhci
)
859 __le32 __iomem
**port_array
;
864 status
= readl(&xhci
->op_regs
->status
);
865 if (status
& STS_EINT
)
868 * Checking STS_EINT is not enough as there is a lag between a change
869 * bit being set and the Port Status Change Event that it generated
870 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
873 port_index
= xhci
->num_usb2_ports
;
874 port_array
= xhci
->usb2_ports
;
875 while (port_index
--) {
876 portsc
= readl(port_array
[port_index
]);
877 if (portsc
& PORT_CHANGE_MASK
||
878 (portsc
& PORT_PLS_MASK
) == XDEV_RESUME
)
881 port_index
= xhci
->num_usb3_ports
;
882 port_array
= xhci
->usb3_ports
;
883 while (port_index
--) {
884 portsc
= readl(port_array
[port_index
]);
885 if (portsc
& PORT_CHANGE_MASK
||
886 (portsc
& PORT_PLS_MASK
) == XDEV_RESUME
)
893 * Stop HC (not bus-specific)
895 * This is called when the machine transition into S3/S4 mode.
898 int xhci_suspend(struct xhci_hcd
*xhci
, bool do_wakeup
)
901 unsigned int delay
= XHCI_MAX_HALT_USEC
;
902 struct usb_hcd
*hcd
= xhci_to_hcd(xhci
);
909 if (hcd
->state
!= HC_STATE_SUSPENDED
||
910 xhci
->shared_hcd
->state
!= HC_STATE_SUSPENDED
)
913 xhci_dbc_suspend(xhci
);
915 /* Clear root port wake on bits if wakeup not allowed. */
917 xhci_disable_port_wake_on_bits(xhci
);
919 /* Don't poll the roothubs on bus suspend. */
920 xhci_dbg(xhci
, "%s: stopping port polling.\n", __func__
);
921 clear_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
922 del_timer_sync(&hcd
->rh_timer
);
923 clear_bit(HCD_FLAG_POLL_RH
, &xhci
->shared_hcd
->flags
);
924 del_timer_sync(&xhci
->shared_hcd
->rh_timer
);
926 if (xhci
->quirks
& XHCI_SUSPEND_DELAY
)
927 usleep_range(1000, 1500);
929 spin_lock_irq(&xhci
->lock
);
930 clear_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
931 clear_bit(HCD_FLAG_HW_ACCESSIBLE
, &xhci
->shared_hcd
->flags
);
932 /* step 1: stop endpoint */
933 /* skipped assuming that port suspend has done */
935 /* step 2: clear Run/Stop bit */
936 command
= readl(&xhci
->op_regs
->command
);
938 writel(command
, &xhci
->op_regs
->command
);
940 /* Some chips from Fresco Logic need an extraordinary delay */
941 delay
*= (xhci
->quirks
& XHCI_SLOW_SUSPEND
) ? 10 : 1;
943 if (xhci_handshake(&xhci
->op_regs
->status
,
944 STS_HALT
, STS_HALT
, delay
)) {
945 xhci_warn(xhci
, "WARN: xHC CMD_RUN timeout\n");
946 spin_unlock_irq(&xhci
->lock
);
949 xhci_clear_command_ring(xhci
);
951 /* step 3: save registers */
952 xhci_save_registers(xhci
);
954 /* step 4: set CSS flag */
955 command
= readl(&xhci
->op_regs
->command
);
957 writel(command
, &xhci
->op_regs
->command
);
958 xhci
->broken_suspend
= 0;
959 if (xhci_handshake(&xhci
->op_regs
->status
,
960 STS_SAVE
, 0, 10 * 1000)) {
962 * AMD SNPS xHC 3.0 occasionally does not clear the
963 * SSS bit of USBSTS and when driver tries to poll
964 * to see if the xHC clears BIT(8) which never happens
965 * and driver assumes that controller is not responding
966 * and times out. To workaround this, its good to check
967 * if SRE and HCE bits are not set (as per xhci
968 * Section 5.4.2) and bypass the timeout.
970 res
= readl(&xhci
->op_regs
->status
);
971 if ((xhci
->quirks
& XHCI_SNPS_BROKEN_SUSPEND
) &&
972 (((res
& STS_SRE
) == 0) &&
973 ((res
& STS_HCE
) == 0))) {
974 xhci
->broken_suspend
= 1;
976 xhci_warn(xhci
, "WARN: xHC save state timeout\n");
977 spin_unlock_irq(&xhci
->lock
);
981 spin_unlock_irq(&xhci
->lock
);
984 * Deleting Compliance Mode Recovery Timer because the xHCI Host
985 * is about to be suspended.
987 if ((xhci
->quirks
& XHCI_COMP_MODE_QUIRK
) &&
988 (!(xhci_all_ports_seen_u0(xhci
)))) {
989 del_timer_sync(&xhci
->comp_mode_recovery_timer
);
990 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
991 "%s: compliance mode recovery timer deleted",
995 /* step 5: remove core well power */
996 /* synchronize irq when using MSI-X */
997 xhci_msix_sync_irqs(xhci
);
1001 EXPORT_SYMBOL_GPL(xhci_suspend
);
1004 * start xHC (not bus-specific)
1006 * This is called when the machine transition from S3/S4 mode.
1009 int xhci_resume(struct xhci_hcd
*xhci
, bool hibernated
)
1011 u32 command
, temp
= 0;
1012 struct usb_hcd
*hcd
= xhci_to_hcd(xhci
);
1013 struct usb_hcd
*secondary_hcd
;
1015 bool comp_timer_running
= false;
1020 /* Wait a bit if either of the roothubs need to settle from the
1021 * transition into bus suspend.
1023 if (time_before(jiffies
, xhci
->bus_state
[0].next_statechange
) ||
1024 time_before(jiffies
,
1025 xhci
->bus_state
[1].next_statechange
))
1028 set_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
1029 set_bit(HCD_FLAG_HW_ACCESSIBLE
, &xhci
->shared_hcd
->flags
);
1031 spin_lock_irq(&xhci
->lock
);
1032 if ((xhci
->quirks
& XHCI_RESET_ON_RESUME
) || xhci
->broken_suspend
)
1036 /* step 1: restore register */
1037 xhci_restore_registers(xhci
);
1038 /* step 2: initialize command ring buffer */
1039 xhci_set_cmd_ring_deq(xhci
);
1040 /* step 3: restore state and start state*/
1041 /* step 3: set CRS flag */
1042 command
= readl(&xhci
->op_regs
->command
);
1044 writel(command
, &xhci
->op_regs
->command
);
1045 if (xhci_handshake(&xhci
->op_regs
->status
,
1046 STS_RESTORE
, 0, 10 * 1000)) {
1047 xhci_warn(xhci
, "WARN: xHC restore state timeout\n");
1048 spin_unlock_irq(&xhci
->lock
);
1051 temp
= readl(&xhci
->op_regs
->status
);
1054 /* If restore operation fails, re-initialize the HC during resume */
1055 if ((temp
& STS_SRE
) || hibernated
) {
1057 if ((xhci
->quirks
& XHCI_COMP_MODE_QUIRK
) &&
1058 !(xhci_all_ports_seen_u0(xhci
))) {
1059 del_timer_sync(&xhci
->comp_mode_recovery_timer
);
1060 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
1061 "Compliance Mode Recovery Timer deleted!");
1064 /* Let the USB core know _both_ roothubs lost power. */
1065 usb_root_hub_lost_power(xhci
->main_hcd
->self
.root_hub
);
1066 usb_root_hub_lost_power(xhci
->shared_hcd
->self
.root_hub
);
1068 xhci_dbg(xhci
, "Stop HCD\n");
1071 spin_unlock_irq(&xhci
->lock
);
1072 xhci_cleanup_msix(xhci
);
1074 xhci_dbg(xhci
, "// Disabling event ring interrupts\n");
1075 temp
= readl(&xhci
->op_regs
->status
);
1076 writel((temp
& ~0x1fff) | STS_EINT
, &xhci
->op_regs
->status
);
1077 temp
= readl(&xhci
->ir_set
->irq_pending
);
1078 writel(ER_IRQ_DISABLE(temp
), &xhci
->ir_set
->irq_pending
);
1079 xhci_print_ir_set(xhci
, 0);
1081 xhci_dbg(xhci
, "cleaning up memory\n");
1082 xhci_mem_cleanup(xhci
);
1083 xhci_debugfs_exit(xhci
);
1084 xhci_dbg(xhci
, "xhci_stop completed - status = %x\n",
1085 readl(&xhci
->op_regs
->status
));
1087 /* USB core calls the PCI reinit and start functions twice:
1088 * first with the primary HCD, and then with the secondary HCD.
1089 * If we don't do the same, the host will never be started.
1091 if (!usb_hcd_is_primary_hcd(hcd
))
1092 secondary_hcd
= hcd
;
1094 secondary_hcd
= xhci
->shared_hcd
;
1096 xhci_dbg(xhci
, "Initialize the xhci_hcd\n");
1097 retval
= xhci_init(hcd
->primary_hcd
);
1100 comp_timer_running
= true;
1102 xhci_dbg(xhci
, "Start the primary HCD\n");
1103 retval
= xhci_run(hcd
->primary_hcd
);
1105 xhci_dbg(xhci
, "Start the secondary HCD\n");
1106 retval
= xhci_run(secondary_hcd
);
1108 hcd
->state
= HC_STATE_SUSPENDED
;
1109 xhci
->shared_hcd
->state
= HC_STATE_SUSPENDED
;
1113 /* step 4: set Run/Stop bit */
1114 command
= readl(&xhci
->op_regs
->command
);
1116 writel(command
, &xhci
->op_regs
->command
);
1117 xhci_handshake(&xhci
->op_regs
->status
, STS_HALT
,
1120 /* step 5: walk topology and initialize portsc,
1121 * portpmsc and portli
1123 /* this is done in bus_resume */
1125 /* step 6: restart each of the previously
1126 * Running endpoints by ringing their doorbells
1129 spin_unlock_irq(&xhci
->lock
);
1131 xhci_dbc_resume(xhci
);
1135 /* Resume root hubs only when have pending events. */
1136 if (xhci_pending_portevent(xhci
)) {
1137 usb_hcd_resume_root_hub(xhci
->shared_hcd
);
1138 usb_hcd_resume_root_hub(hcd
);
1143 * If system is subject to the Quirk, Compliance Mode Timer needs to
1144 * be re-initialized Always after a system resume. Ports are subject
1145 * to suffer the Compliance Mode issue again. It doesn't matter if
1146 * ports have entered previously to U0 before system's suspension.
1148 if ((xhci
->quirks
& XHCI_COMP_MODE_QUIRK
) && !comp_timer_running
)
1149 compliance_mode_recovery_timer_init(xhci
);
1151 if (xhci
->quirks
& XHCI_ASMEDIA_MODIFY_FLOWCONTROL
)
1152 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd
->self
.controller
));
1154 /* Re-enable port polling. */
1155 xhci_dbg(xhci
, "%s: starting port polling.\n", __func__
);
1156 set_bit(HCD_FLAG_POLL_RH
, &xhci
->shared_hcd
->flags
);
1157 usb_hcd_poll_rh_status(xhci
->shared_hcd
);
1158 set_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
1159 usb_hcd_poll_rh_status(hcd
);
1163 EXPORT_SYMBOL_GPL(xhci_resume
);
1164 #endif /* CONFIG_PM */
1166 /*-------------------------------------------------------------------------*/
1169 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1170 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1171 * value to right shift 1 for the bitmask.
1173 * Index = (epnum * 2) + direction - 1,
1174 * where direction = 0 for OUT, 1 for IN.
1175 * For control endpoints, the IN index is used (OUT index is unused), so
1176 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1178 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor
*desc
)
1181 if (usb_endpoint_xfer_control(desc
))
1182 index
= (unsigned int) (usb_endpoint_num(desc
)*2);
1184 index
= (unsigned int) (usb_endpoint_num(desc
)*2) +
1185 (usb_endpoint_dir_in(desc
) ? 1 : 0) - 1;
1189 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1190 * address from the XHCI endpoint index.
1192 unsigned int xhci_get_endpoint_address(unsigned int ep_index
)
1194 unsigned int number
= DIV_ROUND_UP(ep_index
, 2);
1195 unsigned int direction
= ep_index
% 2 ? USB_DIR_OUT
: USB_DIR_IN
;
1196 return direction
| number
;
1199 /* Find the flag for this endpoint (for use in the control context). Use the
1200 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1203 static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor
*desc
)
1205 return 1 << (xhci_get_endpoint_index(desc
) + 1);
1208 /* Find the flag for this endpoint (for use in the control context). Use the
1209 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1212 static unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index
)
1214 return 1 << (ep_index
+ 1);
1217 /* Compute the last valid endpoint context index. Basically, this is the
1218 * endpoint index plus one. For slot contexts with more than valid endpoint,
1219 * we find the most significant bit set in the added contexts flags.
1220 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1221 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1223 unsigned int xhci_last_valid_endpoint(u32 added_ctxs
)
1225 return fls(added_ctxs
) - 1;
1228 /* Returns 1 if the arguments are OK;
1229 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1231 static int xhci_check_args(struct usb_hcd
*hcd
, struct usb_device
*udev
,
1232 struct usb_host_endpoint
*ep
, int check_ep
, bool check_virt_dev
,
1234 struct xhci_hcd
*xhci
;
1235 struct xhci_virt_device
*virt_dev
;
1237 if (!hcd
|| (check_ep
&& !ep
) || !udev
) {
1238 pr_debug("xHCI %s called with invalid args\n", func
);
1241 if (!udev
->parent
) {
1242 pr_debug("xHCI %s called for root hub\n", func
);
1246 xhci
= hcd_to_xhci(hcd
);
1247 if (check_virt_dev
) {
1248 if (!udev
->slot_id
|| !xhci
->devs
[udev
->slot_id
]) {
1249 xhci_dbg(xhci
, "xHCI %s called with unaddressed device\n",
1254 virt_dev
= xhci
->devs
[udev
->slot_id
];
1255 if (virt_dev
->udev
!= udev
) {
1256 xhci_dbg(xhci
, "xHCI %s called with udev and "
1257 "virt_dev does not match\n", func
);
1262 if (xhci
->xhc_state
& XHCI_STATE_HALTED
)
1268 static int xhci_configure_endpoint(struct xhci_hcd
*xhci
,
1269 struct usb_device
*udev
, struct xhci_command
*command
,
1270 bool ctx_change
, bool must_succeed
);
1273 * Full speed devices may have a max packet size greater than 8 bytes, but the
1274 * USB core doesn't know that until it reads the first 8 bytes of the
1275 * descriptor. If the usb_device's max packet size changes after that point,
1276 * we need to issue an evaluate context command and wait on it.
1278 static int xhci_check_maxpacket(struct xhci_hcd
*xhci
, unsigned int slot_id
,
1279 unsigned int ep_index
, struct urb
*urb
)
1281 struct xhci_container_ctx
*out_ctx
;
1282 struct xhci_input_control_ctx
*ctrl_ctx
;
1283 struct xhci_ep_ctx
*ep_ctx
;
1284 struct xhci_command
*command
;
1285 int max_packet_size
;
1286 int hw_max_packet_size
;
1289 out_ctx
= xhci
->devs
[slot_id
]->out_ctx
;
1290 ep_ctx
= xhci_get_ep_ctx(xhci
, out_ctx
, ep_index
);
1291 hw_max_packet_size
= MAX_PACKET_DECODED(le32_to_cpu(ep_ctx
->ep_info2
));
1292 max_packet_size
= usb_endpoint_maxp(&urb
->dev
->ep0
.desc
);
1293 if (hw_max_packet_size
!= max_packet_size
) {
1294 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
1295 "Max Packet Size for ep 0 changed.");
1296 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
1297 "Max packet size in usb_device = %d",
1299 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
1300 "Max packet size in xHCI HW = %d",
1301 hw_max_packet_size
);
1302 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
1303 "Issuing evaluate context command.");
1305 /* Set up the input context flags for the command */
1306 /* FIXME: This won't work if a non-default control endpoint
1307 * changes max packet sizes.
1310 command
= xhci_alloc_command(xhci
, false, true, GFP_KERNEL
);
1314 command
->in_ctx
= xhci
->devs
[slot_id
]->in_ctx
;
1315 ctrl_ctx
= xhci_get_input_control_ctx(command
->in_ctx
);
1317 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
1320 goto command_cleanup
;
1322 /* Set up the modified control endpoint 0 */
1323 xhci_endpoint_copy(xhci
, xhci
->devs
[slot_id
]->in_ctx
,
1324 xhci
->devs
[slot_id
]->out_ctx
, ep_index
);
1326 ep_ctx
= xhci_get_ep_ctx(xhci
, command
->in_ctx
, ep_index
);
1327 ep_ctx
->ep_info2
&= cpu_to_le32(~MAX_PACKET_MASK
);
1328 ep_ctx
->ep_info2
|= cpu_to_le32(MAX_PACKET(max_packet_size
));
1330 ctrl_ctx
->add_flags
= cpu_to_le32(EP0_FLAG
);
1331 ctrl_ctx
->drop_flags
= 0;
1333 ret
= xhci_configure_endpoint(xhci
, urb
->dev
, command
,
1336 /* Clean up the input context for later use by bandwidth
1339 ctrl_ctx
->add_flags
= cpu_to_le32(SLOT_FLAG
);
1341 kfree(command
->completion
);
1348 * non-error returns are a promise to giveback() the urb later
1349 * we drop ownership so next owner (or urb unlink) can get it
1351 static int xhci_urb_enqueue(struct usb_hcd
*hcd
, struct urb
*urb
, gfp_t mem_flags
)
1353 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
1354 unsigned long flags
;
1356 unsigned int slot_id
, ep_index
, ep_state
;
1357 struct urb_priv
*urb_priv
;
1360 if (!urb
|| xhci_check_args(hcd
, urb
->dev
, urb
->ep
,
1361 true, true, __func__
) <= 0)
1364 slot_id
= urb
->dev
->slot_id
;
1365 ep_index
= xhci_get_endpoint_index(&urb
->ep
->desc
);
1367 if (!HCD_HW_ACCESSIBLE(hcd
)) {
1368 if (!in_interrupt())
1369 xhci_dbg(xhci
, "urb submitted during PCI suspend\n");
1373 if (usb_endpoint_xfer_isoc(&urb
->ep
->desc
))
1374 num_tds
= urb
->number_of_packets
;
1375 else if (usb_endpoint_is_bulk_out(&urb
->ep
->desc
) &&
1376 urb
->transfer_buffer_length
> 0 &&
1377 urb
->transfer_flags
& URB_ZERO_PACKET
&&
1378 !(urb
->transfer_buffer_length
% usb_endpoint_maxp(&urb
->ep
->desc
)))
1383 urb_priv
= kzalloc(sizeof(struct urb_priv
) +
1384 num_tds
* sizeof(struct xhci_td
), mem_flags
);
1388 urb_priv
->num_tds
= num_tds
;
1389 urb_priv
->num_tds_done
= 0;
1390 urb
->hcpriv
= urb_priv
;
1392 trace_xhci_urb_enqueue(urb
);
1394 if (usb_endpoint_xfer_control(&urb
->ep
->desc
)) {
1395 /* Check to see if the max packet size for the default control
1396 * endpoint changed during FS device enumeration
1398 if (urb
->dev
->speed
== USB_SPEED_FULL
) {
1399 ret
= xhci_check_maxpacket(xhci
, slot_id
,
1402 xhci_urb_free_priv(urb_priv
);
1409 spin_lock_irqsave(&xhci
->lock
, flags
);
1411 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
1412 xhci_dbg(xhci
, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1413 urb
->ep
->desc
.bEndpointAddress
, urb
);
1418 switch (usb_endpoint_type(&urb
->ep
->desc
)) {
1420 case USB_ENDPOINT_XFER_CONTROL
:
1421 ret
= xhci_queue_ctrl_tx(xhci
, GFP_ATOMIC
, urb
,
1424 case USB_ENDPOINT_XFER_BULK
:
1425 ep_state
= xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
;
1426 if (ep_state
& (EP_GETTING_STREAMS
| EP_GETTING_NO_STREAMS
)) {
1427 xhci_warn(xhci
, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1432 ret
= xhci_queue_bulk_tx(xhci
, GFP_ATOMIC
, urb
,
1437 case USB_ENDPOINT_XFER_INT
:
1438 ret
= xhci_queue_intr_tx(xhci
, GFP_ATOMIC
, urb
,
1442 case USB_ENDPOINT_XFER_ISOC
:
1443 ret
= xhci_queue_isoc_tx_prepare(xhci
, GFP_ATOMIC
, urb
,
1449 xhci_urb_free_priv(urb_priv
);
1452 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1457 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1458 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1459 * should pick up where it left off in the TD, unless a Set Transfer Ring
1460 * Dequeue Pointer is issued.
1462 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1463 * the ring. Since the ring is a contiguous structure, they can't be physically
1464 * removed. Instead, there are two options:
1466 * 1) If the HC is in the middle of processing the URB to be canceled, we
1467 * simply move the ring's dequeue pointer past those TRBs using the Set
1468 * Transfer Ring Dequeue Pointer command. This will be the common case,
1469 * when drivers timeout on the last submitted URB and attempt to cancel.
1471 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1472 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1473 * HC will need to invalidate the any TRBs it has cached after the stop
1474 * endpoint command, as noted in the xHCI 0.95 errata.
1476 * 3) The TD may have completed by the time the Stop Endpoint Command
1477 * completes, so software needs to handle that case too.
1479 * This function should protect against the TD enqueueing code ringing the
1480 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1481 * It also needs to account for multiple cancellations on happening at the same
1482 * time for the same endpoint.
1484 * Note that this function can be called in any context, or so says
1485 * usb_hcd_unlink_urb()
1487 static int xhci_urb_dequeue(struct usb_hcd
*hcd
, struct urb
*urb
, int status
)
1489 unsigned long flags
;
1492 struct xhci_hcd
*xhci
;
1493 struct urb_priv
*urb_priv
;
1495 unsigned int ep_index
;
1496 struct xhci_ring
*ep_ring
;
1497 struct xhci_virt_ep
*ep
;
1498 struct xhci_command
*command
;
1499 struct xhci_virt_device
*vdev
;
1501 xhci
= hcd_to_xhci(hcd
);
1502 spin_lock_irqsave(&xhci
->lock
, flags
);
1504 trace_xhci_urb_dequeue(urb
);
1506 /* Make sure the URB hasn't completed or been unlinked already */
1507 ret
= usb_hcd_check_unlink_urb(hcd
, urb
, status
);
1511 /* give back URB now if we can't queue it for cancel */
1512 vdev
= xhci
->devs
[urb
->dev
->slot_id
];
1513 urb_priv
= urb
->hcpriv
;
1514 if (!vdev
|| !urb_priv
)
1517 ep_index
= xhci_get_endpoint_index(&urb
->ep
->desc
);
1518 ep
= &vdev
->eps
[ep_index
];
1519 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
1520 if (!ep
|| !ep_ring
)
1523 /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1524 temp
= readl(&xhci
->op_regs
->status
);
1525 if (temp
== ~(u32
)0 || xhci
->xhc_state
& XHCI_STATE_DYING
) {
1530 if (xhci
->xhc_state
& XHCI_STATE_HALTED
) {
1531 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
1532 "HC halted, freeing TD manually.");
1533 for (i
= urb_priv
->num_tds_done
;
1534 i
< urb_priv
->num_tds
;
1536 td
= &urb_priv
->td
[i
];
1537 if (!list_empty(&td
->td_list
))
1538 list_del_init(&td
->td_list
);
1539 if (!list_empty(&td
->cancelled_td_list
))
1540 list_del_init(&td
->cancelled_td_list
);
1545 i
= urb_priv
->num_tds_done
;
1546 if (i
< urb_priv
->num_tds
)
1547 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
1548 "Cancel URB %p, dev %s, ep 0x%x, "
1549 "starting at offset 0x%llx",
1550 urb
, urb
->dev
->devpath
,
1551 urb
->ep
->desc
.bEndpointAddress
,
1552 (unsigned long long) xhci_trb_virt_to_dma(
1553 urb_priv
->td
[i
].start_seg
,
1554 urb_priv
->td
[i
].first_trb
));
1556 for (; i
< urb_priv
->num_tds
; i
++) {
1557 td
= &urb_priv
->td
[i
];
1558 list_add_tail(&td
->cancelled_td_list
, &ep
->cancelled_td_list
);
1561 /* Queue a stop endpoint command, but only if this is
1562 * the first cancellation to be handled.
1564 if (!(ep
->ep_state
& EP_STOP_CMD_PENDING
)) {
1565 command
= xhci_alloc_command(xhci
, false, false, GFP_ATOMIC
);
1570 ep
->ep_state
|= EP_STOP_CMD_PENDING
;
1571 ep
->stop_cmd_timer
.expires
= jiffies
+
1572 XHCI_STOP_EP_CMD_TIMEOUT
* HZ
;
1573 add_timer(&ep
->stop_cmd_timer
);
1574 xhci_queue_stop_endpoint(xhci
, command
, urb
->dev
->slot_id
,
1576 xhci_ring_cmd_db(xhci
);
1579 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1584 xhci_urb_free_priv(urb_priv
);
1585 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
1586 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1587 usb_hcd_giveback_urb(hcd
, urb
, -ESHUTDOWN
);
1591 /* Drop an endpoint from a new bandwidth configuration for this device.
1592 * Only one call to this function is allowed per endpoint before
1593 * check_bandwidth() or reset_bandwidth() must be called.
1594 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1595 * add the endpoint to the schedule with possibly new parameters denoted by a
1596 * different endpoint descriptor in usb_host_endpoint.
1597 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1600 * The USB core will not allow URBs to be queued to an endpoint that is being
1601 * disabled, so there's no need for mutual exclusion to protect
1602 * the xhci->devs[slot_id] structure.
1604 static int xhci_drop_endpoint(struct usb_hcd
*hcd
, struct usb_device
*udev
,
1605 struct usb_host_endpoint
*ep
)
1607 struct xhci_hcd
*xhci
;
1608 struct xhci_container_ctx
*in_ctx
, *out_ctx
;
1609 struct xhci_input_control_ctx
*ctrl_ctx
;
1610 unsigned int ep_index
;
1611 struct xhci_ep_ctx
*ep_ctx
;
1613 u32 new_add_flags
, new_drop_flags
;
1616 ret
= xhci_check_args(hcd
, udev
, ep
, 1, true, __func__
);
1619 xhci
= hcd_to_xhci(hcd
);
1620 if (xhci
->xhc_state
& XHCI_STATE_DYING
)
1623 xhci_dbg(xhci
, "%s called for udev %p\n", __func__
, udev
);
1624 drop_flag
= xhci_get_endpoint_flag(&ep
->desc
);
1625 if (drop_flag
== SLOT_FLAG
|| drop_flag
== EP0_FLAG
) {
1626 xhci_dbg(xhci
, "xHCI %s - can't drop slot or ep 0 %#x\n",
1627 __func__
, drop_flag
);
1631 in_ctx
= xhci
->devs
[udev
->slot_id
]->in_ctx
;
1632 out_ctx
= xhci
->devs
[udev
->slot_id
]->out_ctx
;
1633 ctrl_ctx
= xhci_get_input_control_ctx(in_ctx
);
1635 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
1640 ep_index
= xhci_get_endpoint_index(&ep
->desc
);
1641 ep_ctx
= xhci_get_ep_ctx(xhci
, out_ctx
, ep_index
);
1642 /* If the HC already knows the endpoint is disabled,
1643 * or the HCD has noted it is disabled, ignore this request
1645 if ((GET_EP_CTX_STATE(ep_ctx
) == EP_STATE_DISABLED
) ||
1646 le32_to_cpu(ctrl_ctx
->drop_flags
) &
1647 xhci_get_endpoint_flag(&ep
->desc
)) {
1648 /* Do not warn when called after a usb_device_reset */
1649 if (xhci
->devs
[udev
->slot_id
]->eps
[ep_index
].ring
!= NULL
)
1650 xhci_warn(xhci
, "xHCI %s called with disabled ep %p\n",
1655 ctrl_ctx
->drop_flags
|= cpu_to_le32(drop_flag
);
1656 new_drop_flags
= le32_to_cpu(ctrl_ctx
->drop_flags
);
1658 ctrl_ctx
->add_flags
&= cpu_to_le32(~drop_flag
);
1659 new_add_flags
= le32_to_cpu(ctrl_ctx
->add_flags
);
1661 xhci_debugfs_remove_endpoint(xhci
, xhci
->devs
[udev
->slot_id
], ep_index
);
1663 xhci_endpoint_zero(xhci
, xhci
->devs
[udev
->slot_id
], ep
);
1665 if (xhci
->quirks
& XHCI_MTK_HOST
)
1666 xhci_mtk_drop_ep_quirk(hcd
, udev
, ep
);
1668 xhci_dbg(xhci
, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1669 (unsigned int) ep
->desc
.bEndpointAddress
,
1671 (unsigned int) new_drop_flags
,
1672 (unsigned int) new_add_flags
);
1676 /* Add an endpoint to a new possible bandwidth configuration for this device.
1677 * Only one call to this function is allowed per endpoint before
1678 * check_bandwidth() or reset_bandwidth() must be called.
1679 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1680 * add the endpoint to the schedule with possibly new parameters denoted by a
1681 * different endpoint descriptor in usb_host_endpoint.
1682 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1685 * The USB core will not allow URBs to be queued to an endpoint until the
1686 * configuration or alt setting is installed in the device, so there's no need
1687 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1689 static int xhci_add_endpoint(struct usb_hcd
*hcd
, struct usb_device
*udev
,
1690 struct usb_host_endpoint
*ep
)
1692 struct xhci_hcd
*xhci
;
1693 struct xhci_container_ctx
*in_ctx
;
1694 unsigned int ep_index
;
1695 struct xhci_input_control_ctx
*ctrl_ctx
;
1697 u32 new_add_flags
, new_drop_flags
;
1698 struct xhci_virt_device
*virt_dev
;
1701 ret
= xhci_check_args(hcd
, udev
, ep
, 1, true, __func__
);
1703 /* So we won't queue a reset ep command for a root hub */
1707 xhci
= hcd_to_xhci(hcd
);
1708 if (xhci
->xhc_state
& XHCI_STATE_DYING
)
1711 added_ctxs
= xhci_get_endpoint_flag(&ep
->desc
);
1712 if (added_ctxs
== SLOT_FLAG
|| added_ctxs
== EP0_FLAG
) {
1713 /* FIXME when we have to issue an evaluate endpoint command to
1714 * deal with ep0 max packet size changing once we get the
1717 xhci_dbg(xhci
, "xHCI %s - can't add slot or ep 0 %#x\n",
1718 __func__
, added_ctxs
);
1722 virt_dev
= xhci
->devs
[udev
->slot_id
];
1723 in_ctx
= virt_dev
->in_ctx
;
1724 ctrl_ctx
= xhci_get_input_control_ctx(in_ctx
);
1726 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
1731 ep_index
= xhci_get_endpoint_index(&ep
->desc
);
1732 /* If this endpoint is already in use, and the upper layers are trying
1733 * to add it again without dropping it, reject the addition.
1735 if (virt_dev
->eps
[ep_index
].ring
&&
1736 !(le32_to_cpu(ctrl_ctx
->drop_flags
) & added_ctxs
)) {
1737 xhci_warn(xhci
, "Trying to add endpoint 0x%x "
1738 "without dropping it.\n",
1739 (unsigned int) ep
->desc
.bEndpointAddress
);
1743 /* If the HCD has already noted the endpoint is enabled,
1744 * ignore this request.
1746 if (le32_to_cpu(ctrl_ctx
->add_flags
) & added_ctxs
) {
1747 xhci_warn(xhci
, "xHCI %s called with enabled ep %p\n",
1753 * Configuration and alternate setting changes must be done in
1754 * process context, not interrupt context (or so documenation
1755 * for usb_set_interface() and usb_set_configuration() claim).
1757 if (xhci_endpoint_init(xhci
, virt_dev
, udev
, ep
, GFP_NOIO
) < 0) {
1758 dev_dbg(&udev
->dev
, "%s - could not initialize ep %#x\n",
1759 __func__
, ep
->desc
.bEndpointAddress
);
1763 if (xhci
->quirks
& XHCI_MTK_HOST
) {
1764 ret
= xhci_mtk_add_ep_quirk(hcd
, udev
, ep
);
1766 xhci_ring_free(xhci
, virt_dev
->eps
[ep_index
].new_ring
);
1767 virt_dev
->eps
[ep_index
].new_ring
= NULL
;
1772 ctrl_ctx
->add_flags
|= cpu_to_le32(added_ctxs
);
1773 new_add_flags
= le32_to_cpu(ctrl_ctx
->add_flags
);
1775 /* If xhci_endpoint_disable() was called for this endpoint, but the
1776 * xHC hasn't been notified yet through the check_bandwidth() call,
1777 * this re-adds a new state for the endpoint from the new endpoint
1778 * descriptors. We must drop and re-add this endpoint, so we leave the
1781 new_drop_flags
= le32_to_cpu(ctrl_ctx
->drop_flags
);
1783 /* Store the usb_device pointer for later use */
1786 xhci_debugfs_create_endpoint(xhci
, virt_dev
, ep_index
);
1788 xhci_dbg(xhci
, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1789 (unsigned int) ep
->desc
.bEndpointAddress
,
1791 (unsigned int) new_drop_flags
,
1792 (unsigned int) new_add_flags
);
1796 static void xhci_zero_in_ctx(struct xhci_hcd
*xhci
, struct xhci_virt_device
*virt_dev
)
1798 struct xhci_input_control_ctx
*ctrl_ctx
;
1799 struct xhci_ep_ctx
*ep_ctx
;
1800 struct xhci_slot_ctx
*slot_ctx
;
1803 ctrl_ctx
= xhci_get_input_control_ctx(virt_dev
->in_ctx
);
1805 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
1810 /* When a device's add flag and drop flag are zero, any subsequent
1811 * configure endpoint command will leave that endpoint's state
1812 * untouched. Make sure we don't leave any old state in the input
1813 * endpoint contexts.
1815 ctrl_ctx
->drop_flags
= 0;
1816 ctrl_ctx
->add_flags
= 0;
1817 slot_ctx
= xhci_get_slot_ctx(xhci
, virt_dev
->in_ctx
);
1818 slot_ctx
->dev_info
&= cpu_to_le32(~LAST_CTX_MASK
);
1819 /* Endpoint 0 is always valid */
1820 slot_ctx
->dev_info
|= cpu_to_le32(LAST_CTX(1));
1821 for (i
= 1; i
< 31; i
++) {
1822 ep_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->in_ctx
, i
);
1823 ep_ctx
->ep_info
= 0;
1824 ep_ctx
->ep_info2
= 0;
1826 ep_ctx
->tx_info
= 0;
1830 static int xhci_configure_endpoint_result(struct xhci_hcd
*xhci
,
1831 struct usb_device
*udev
, u32
*cmd_status
)
1835 switch (*cmd_status
) {
1836 case COMP_COMMAND_ABORTED
:
1837 case COMP_COMMAND_RING_STOPPED
:
1838 xhci_warn(xhci
, "Timeout while waiting for configure endpoint command\n");
1841 case COMP_RESOURCE_ERROR
:
1842 dev_warn(&udev
->dev
,
1843 "Not enough host controller resources for new device state.\n");
1845 /* FIXME: can we allocate more resources for the HC? */
1847 case COMP_BANDWIDTH_ERROR
:
1848 case COMP_SECONDARY_BANDWIDTH_ERROR
:
1849 dev_warn(&udev
->dev
,
1850 "Not enough bandwidth for new device state.\n");
1852 /* FIXME: can we go back to the old state? */
1854 case COMP_TRB_ERROR
:
1855 /* the HCD set up something wrong */
1856 dev_warn(&udev
->dev
, "ERROR: Endpoint drop flag = 0, "
1858 "and endpoint is not disabled.\n");
1861 case COMP_INCOMPATIBLE_DEVICE_ERROR
:
1862 dev_warn(&udev
->dev
,
1863 "ERROR: Incompatible device for endpoint configure command.\n");
1867 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
1868 "Successful Endpoint Configure command");
1872 xhci_err(xhci
, "ERROR: unexpected command completion code 0x%x.\n",
1880 static int xhci_evaluate_context_result(struct xhci_hcd
*xhci
,
1881 struct usb_device
*udev
, u32
*cmd_status
)
1885 switch (*cmd_status
) {
1886 case COMP_COMMAND_ABORTED
:
1887 case COMP_COMMAND_RING_STOPPED
:
1888 xhci_warn(xhci
, "Timeout while waiting for evaluate context command\n");
1891 case COMP_PARAMETER_ERROR
:
1892 dev_warn(&udev
->dev
,
1893 "WARN: xHCI driver setup invalid evaluate context command.\n");
1896 case COMP_SLOT_NOT_ENABLED_ERROR
:
1897 dev_warn(&udev
->dev
,
1898 "WARN: slot not enabled for evaluate context command.\n");
1901 case COMP_CONTEXT_STATE_ERROR
:
1902 dev_warn(&udev
->dev
,
1903 "WARN: invalid context state for evaluate context command.\n");
1906 case COMP_INCOMPATIBLE_DEVICE_ERROR
:
1907 dev_warn(&udev
->dev
,
1908 "ERROR: Incompatible device for evaluate context command.\n");
1911 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR
:
1912 /* Max Exit Latency too large error */
1913 dev_warn(&udev
->dev
, "WARN: Max Exit Latency too large\n");
1917 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
1918 "Successful evaluate context command");
1922 xhci_err(xhci
, "ERROR: unexpected command completion code 0x%x.\n",
1930 static u32
xhci_count_num_new_endpoints(struct xhci_hcd
*xhci
,
1931 struct xhci_input_control_ctx
*ctrl_ctx
)
1933 u32 valid_add_flags
;
1934 u32 valid_drop_flags
;
1936 /* Ignore the slot flag (bit 0), and the default control endpoint flag
1937 * (bit 1). The default control endpoint is added during the Address
1938 * Device command and is never removed until the slot is disabled.
1940 valid_add_flags
= le32_to_cpu(ctrl_ctx
->add_flags
) >> 2;
1941 valid_drop_flags
= le32_to_cpu(ctrl_ctx
->drop_flags
) >> 2;
1943 /* Use hweight32 to count the number of ones in the add flags, or
1944 * number of endpoints added. Don't count endpoints that are changed
1945 * (both added and dropped).
1947 return hweight32(valid_add_flags
) -
1948 hweight32(valid_add_flags
& valid_drop_flags
);
1951 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd
*xhci
,
1952 struct xhci_input_control_ctx
*ctrl_ctx
)
1954 u32 valid_add_flags
;
1955 u32 valid_drop_flags
;
1957 valid_add_flags
= le32_to_cpu(ctrl_ctx
->add_flags
) >> 2;
1958 valid_drop_flags
= le32_to_cpu(ctrl_ctx
->drop_flags
) >> 2;
1960 return hweight32(valid_drop_flags
) -
1961 hweight32(valid_add_flags
& valid_drop_flags
);
1965 * We need to reserve the new number of endpoints before the configure endpoint
1966 * command completes. We can't subtract the dropped endpoints from the number
1967 * of active endpoints until the command completes because we can oversubscribe
1968 * the host in this case:
1970 * - the first configure endpoint command drops more endpoints than it adds
1971 * - a second configure endpoint command that adds more endpoints is queued
1972 * - the first configure endpoint command fails, so the config is unchanged
1973 * - the second command may succeed, even though there isn't enough resources
1975 * Must be called with xhci->lock held.
1977 static int xhci_reserve_host_resources(struct xhci_hcd
*xhci
,
1978 struct xhci_input_control_ctx
*ctrl_ctx
)
1982 added_eps
= xhci_count_num_new_endpoints(xhci
, ctrl_ctx
);
1983 if (xhci
->num_active_eps
+ added_eps
> xhci
->limit_active_eps
) {
1984 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
1985 "Not enough ep ctxs: "
1986 "%u active, need to add %u, limit is %u.",
1987 xhci
->num_active_eps
, added_eps
,
1988 xhci
->limit_active_eps
);
1991 xhci
->num_active_eps
+= added_eps
;
1992 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
1993 "Adding %u ep ctxs, %u now active.", added_eps
,
1994 xhci
->num_active_eps
);
1999 * The configure endpoint was failed by the xHC for some other reason, so we
2000 * need to revert the resources that failed configuration would have used.
2002 * Must be called with xhci->lock held.
2004 static void xhci_free_host_resources(struct xhci_hcd
*xhci
,
2005 struct xhci_input_control_ctx
*ctrl_ctx
)
2009 num_failed_eps
= xhci_count_num_new_endpoints(xhci
, ctrl_ctx
);
2010 xhci
->num_active_eps
-= num_failed_eps
;
2011 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
2012 "Removing %u failed ep ctxs, %u now active.",
2014 xhci
->num_active_eps
);
2018 * Now that the command has completed, clean up the active endpoint count by
2019 * subtracting out the endpoints that were dropped (but not changed).
2021 * Must be called with xhci->lock held.
2023 static void xhci_finish_resource_reservation(struct xhci_hcd
*xhci
,
2024 struct xhci_input_control_ctx
*ctrl_ctx
)
2026 u32 num_dropped_eps
;
2028 num_dropped_eps
= xhci_count_num_dropped_endpoints(xhci
, ctrl_ctx
);
2029 xhci
->num_active_eps
-= num_dropped_eps
;
2030 if (num_dropped_eps
)
2031 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
2032 "Removing %u dropped ep ctxs, %u now active.",
2034 xhci
->num_active_eps
);
2037 static unsigned int xhci_get_block_size(struct usb_device
*udev
)
2039 switch (udev
->speed
) {
2041 case USB_SPEED_FULL
:
2043 case USB_SPEED_HIGH
:
2045 case USB_SPEED_SUPER
:
2046 case USB_SPEED_SUPER_PLUS
:
2048 case USB_SPEED_UNKNOWN
:
2049 case USB_SPEED_WIRELESS
:
2051 /* Should never happen */
2057 xhci_get_largest_overhead(struct xhci_interval_bw
*interval_bw
)
2059 if (interval_bw
->overhead
[LS_OVERHEAD_TYPE
])
2061 if (interval_bw
->overhead
[FS_OVERHEAD_TYPE
])
2066 /* If we are changing a LS/FS device under a HS hub,
2067 * make sure (if we are activating a new TT) that the HS bus has enough
2068 * bandwidth for this new TT.
2070 static int xhci_check_tt_bw_table(struct xhci_hcd
*xhci
,
2071 struct xhci_virt_device
*virt_dev
,
2074 struct xhci_interval_bw_table
*bw_table
;
2075 struct xhci_tt_bw_info
*tt_info
;
2077 /* Find the bandwidth table for the root port this TT is attached to. */
2078 bw_table
= &xhci
->rh_bw
[virt_dev
->real_port
- 1].bw_table
;
2079 tt_info
= virt_dev
->tt_info
;
2080 /* If this TT already had active endpoints, the bandwidth for this TT
2081 * has already been added. Removing all periodic endpoints (and thus
2082 * making the TT enactive) will only decrease the bandwidth used.
2086 if (old_active_eps
== 0 && tt_info
->active_eps
!= 0) {
2087 if (bw_table
->bw_used
+ TT_HS_OVERHEAD
> HS_BW_LIMIT
)
2091 /* Not sure why we would have no new active endpoints...
2093 * Maybe because of an Evaluate Context change for a hub update or a
2094 * control endpoint 0 max packet size change?
2095 * FIXME: skip the bandwidth calculation in that case.
2100 static int xhci_check_ss_bw(struct xhci_hcd
*xhci
,
2101 struct xhci_virt_device
*virt_dev
)
2103 unsigned int bw_reserved
;
2105 bw_reserved
= DIV_ROUND_UP(SS_BW_RESERVED
*SS_BW_LIMIT_IN
, 100);
2106 if (virt_dev
->bw_table
->ss_bw_in
> (SS_BW_LIMIT_IN
- bw_reserved
))
2109 bw_reserved
= DIV_ROUND_UP(SS_BW_RESERVED
*SS_BW_LIMIT_OUT
, 100);
2110 if (virt_dev
->bw_table
->ss_bw_out
> (SS_BW_LIMIT_OUT
- bw_reserved
))
2117 * This algorithm is a very conservative estimate of the worst-case scheduling
2118 * scenario for any one interval. The hardware dynamically schedules the
2119 * packets, so we can't tell which microframe could be the limiting factor in
2120 * the bandwidth scheduling. This only takes into account periodic endpoints.
2122 * Obviously, we can't solve an NP complete problem to find the minimum worst
2123 * case scenario. Instead, we come up with an estimate that is no less than
2124 * the worst case bandwidth used for any one microframe, but may be an
2127 * We walk the requirements for each endpoint by interval, starting with the
2128 * smallest interval, and place packets in the schedule where there is only one
2129 * possible way to schedule packets for that interval. In order to simplify
2130 * this algorithm, we record the largest max packet size for each interval, and
2131 * assume all packets will be that size.
2133 * For interval 0, we obviously must schedule all packets for each interval.
2134 * The bandwidth for interval 0 is just the amount of data to be transmitted
2135 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2136 * the number of packets).
2138 * For interval 1, we have two possible microframes to schedule those packets
2139 * in. For this algorithm, if we can schedule the same number of packets for
2140 * each possible scheduling opportunity (each microframe), we will do so. The
2141 * remaining number of packets will be saved to be transmitted in the gaps in
2142 * the next interval's scheduling sequence.
2144 * As we move those remaining packets to be scheduled with interval 2 packets,
2145 * we have to double the number of remaining packets to transmit. This is
2146 * because the intervals are actually powers of 2, and we would be transmitting
2147 * the previous interval's packets twice in this interval. We also have to be
2148 * sure that when we look at the largest max packet size for this interval, we
2149 * also look at the largest max packet size for the remaining packets and take
2150 * the greater of the two.
2152 * The algorithm continues to evenly distribute packets in each scheduling
2153 * opportunity, and push the remaining packets out, until we get to the last
2154 * interval. Then those packets and their associated overhead are just added
2155 * to the bandwidth used.
2157 static int xhci_check_bw_table(struct xhci_hcd
*xhci
,
2158 struct xhci_virt_device
*virt_dev
,
2161 unsigned int bw_reserved
;
2162 unsigned int max_bandwidth
;
2163 unsigned int bw_used
;
2164 unsigned int block_size
;
2165 struct xhci_interval_bw_table
*bw_table
;
2166 unsigned int packet_size
= 0;
2167 unsigned int overhead
= 0;
2168 unsigned int packets_transmitted
= 0;
2169 unsigned int packets_remaining
= 0;
2172 if (virt_dev
->udev
->speed
>= USB_SPEED_SUPER
)
2173 return xhci_check_ss_bw(xhci
, virt_dev
);
2175 if (virt_dev
->udev
->speed
== USB_SPEED_HIGH
) {
2176 max_bandwidth
= HS_BW_LIMIT
;
2177 /* Convert percent of bus BW reserved to blocks reserved */
2178 bw_reserved
= DIV_ROUND_UP(HS_BW_RESERVED
* max_bandwidth
, 100);
2180 max_bandwidth
= FS_BW_LIMIT
;
2181 bw_reserved
= DIV_ROUND_UP(FS_BW_RESERVED
* max_bandwidth
, 100);
2184 bw_table
= virt_dev
->bw_table
;
2185 /* We need to translate the max packet size and max ESIT payloads into
2186 * the units the hardware uses.
2188 block_size
= xhci_get_block_size(virt_dev
->udev
);
2190 /* If we are manipulating a LS/FS device under a HS hub, double check
2191 * that the HS bus has enough bandwidth if we are activing a new TT.
2193 if (virt_dev
->tt_info
) {
2194 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
2195 "Recalculating BW for rootport %u",
2196 virt_dev
->real_port
);
2197 if (xhci_check_tt_bw_table(xhci
, virt_dev
, old_active_eps
)) {
2198 xhci_warn(xhci
, "Not enough bandwidth on HS bus for "
2199 "newly activated TT.\n");
2202 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
2203 "Recalculating BW for TT slot %u port %u",
2204 virt_dev
->tt_info
->slot_id
,
2205 virt_dev
->tt_info
->ttport
);
2207 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
2208 "Recalculating BW for rootport %u",
2209 virt_dev
->real_port
);
2212 /* Add in how much bandwidth will be used for interval zero, or the
2213 * rounded max ESIT payload + number of packets * largest overhead.
2215 bw_used
= DIV_ROUND_UP(bw_table
->interval0_esit_payload
, block_size
) +
2216 bw_table
->interval_bw
[0].num_packets
*
2217 xhci_get_largest_overhead(&bw_table
->interval_bw
[0]);
2219 for (i
= 1; i
< XHCI_MAX_INTERVAL
; i
++) {
2220 unsigned int bw_added
;
2221 unsigned int largest_mps
;
2222 unsigned int interval_overhead
;
2225 * How many packets could we transmit in this interval?
2226 * If packets didn't fit in the previous interval, we will need
2227 * to transmit that many packets twice within this interval.
2229 packets_remaining
= 2 * packets_remaining
+
2230 bw_table
->interval_bw
[i
].num_packets
;
2232 /* Find the largest max packet size of this or the previous
2235 if (list_empty(&bw_table
->interval_bw
[i
].endpoints
))
2238 struct xhci_virt_ep
*virt_ep
;
2239 struct list_head
*ep_entry
;
2241 ep_entry
= bw_table
->interval_bw
[i
].endpoints
.next
;
2242 virt_ep
= list_entry(ep_entry
,
2243 struct xhci_virt_ep
, bw_endpoint_list
);
2244 /* Convert to blocks, rounding up */
2245 largest_mps
= DIV_ROUND_UP(
2246 virt_ep
->bw_info
.max_packet_size
,
2249 if (largest_mps
> packet_size
)
2250 packet_size
= largest_mps
;
2252 /* Use the larger overhead of this or the previous interval. */
2253 interval_overhead
= xhci_get_largest_overhead(
2254 &bw_table
->interval_bw
[i
]);
2255 if (interval_overhead
> overhead
)
2256 overhead
= interval_overhead
;
2258 /* How many packets can we evenly distribute across
2259 * (1 << (i + 1)) possible scheduling opportunities?
2261 packets_transmitted
= packets_remaining
>> (i
+ 1);
2263 /* Add in the bandwidth used for those scheduled packets */
2264 bw_added
= packets_transmitted
* (overhead
+ packet_size
);
2266 /* How many packets do we have remaining to transmit? */
2267 packets_remaining
= packets_remaining
% (1 << (i
+ 1));
2269 /* What largest max packet size should those packets have? */
2270 /* If we've transmitted all packets, don't carry over the
2271 * largest packet size.
2273 if (packets_remaining
== 0) {
2276 } else if (packets_transmitted
> 0) {
2277 /* Otherwise if we do have remaining packets, and we've
2278 * scheduled some packets in this interval, take the
2279 * largest max packet size from endpoints with this
2282 packet_size
= largest_mps
;
2283 overhead
= interval_overhead
;
2285 /* Otherwise carry over packet_size and overhead from the last
2286 * time we had a remainder.
2288 bw_used
+= bw_added
;
2289 if (bw_used
> max_bandwidth
) {
2290 xhci_warn(xhci
, "Not enough bandwidth. "
2291 "Proposed: %u, Max: %u\n",
2292 bw_used
, max_bandwidth
);
2297 * Ok, we know we have some packets left over after even-handedly
2298 * scheduling interval 15. We don't know which microframes they will
2299 * fit into, so we over-schedule and say they will be scheduled every
2302 if (packets_remaining
> 0)
2303 bw_used
+= overhead
+ packet_size
;
2305 if (!virt_dev
->tt_info
&& virt_dev
->udev
->speed
== USB_SPEED_HIGH
) {
2306 unsigned int port_index
= virt_dev
->real_port
- 1;
2308 /* OK, we're manipulating a HS device attached to a
2309 * root port bandwidth domain. Include the number of active TTs
2310 * in the bandwidth used.
2312 bw_used
+= TT_HS_OVERHEAD
*
2313 xhci
->rh_bw
[port_index
].num_active_tts
;
2316 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
2317 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2318 "Available: %u " "percent",
2319 bw_used
, max_bandwidth
, bw_reserved
,
2320 (max_bandwidth
- bw_used
- bw_reserved
) * 100 /
2323 bw_used
+= bw_reserved
;
2324 if (bw_used
> max_bandwidth
) {
2325 xhci_warn(xhci
, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2326 bw_used
, max_bandwidth
);
2330 bw_table
->bw_used
= bw_used
;
2334 static bool xhci_is_async_ep(unsigned int ep_type
)
2336 return (ep_type
!= ISOC_OUT_EP
&& ep_type
!= INT_OUT_EP
&&
2337 ep_type
!= ISOC_IN_EP
&&
2338 ep_type
!= INT_IN_EP
);
2341 static bool xhci_is_sync_in_ep(unsigned int ep_type
)
2343 return (ep_type
== ISOC_IN_EP
|| ep_type
== INT_IN_EP
);
2346 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info
*ep_bw
)
2348 unsigned int mps
= DIV_ROUND_UP(ep_bw
->max_packet_size
, SS_BLOCK
);
2350 if (ep_bw
->ep_interval
== 0)
2351 return SS_OVERHEAD_BURST
+
2352 (ep_bw
->mult
* ep_bw
->num_packets
*
2353 (SS_OVERHEAD
+ mps
));
2354 return DIV_ROUND_UP(ep_bw
->mult
* ep_bw
->num_packets
*
2355 (SS_OVERHEAD
+ mps
+ SS_OVERHEAD_BURST
),
2356 1 << ep_bw
->ep_interval
);
2360 static void xhci_drop_ep_from_interval_table(struct xhci_hcd
*xhci
,
2361 struct xhci_bw_info
*ep_bw
,
2362 struct xhci_interval_bw_table
*bw_table
,
2363 struct usb_device
*udev
,
2364 struct xhci_virt_ep
*virt_ep
,
2365 struct xhci_tt_bw_info
*tt_info
)
2367 struct xhci_interval_bw
*interval_bw
;
2368 int normalized_interval
;
2370 if (xhci_is_async_ep(ep_bw
->type
))
2373 if (udev
->speed
>= USB_SPEED_SUPER
) {
2374 if (xhci_is_sync_in_ep(ep_bw
->type
))
2375 xhci
->devs
[udev
->slot_id
]->bw_table
->ss_bw_in
-=
2376 xhci_get_ss_bw_consumed(ep_bw
);
2378 xhci
->devs
[udev
->slot_id
]->bw_table
->ss_bw_out
-=
2379 xhci_get_ss_bw_consumed(ep_bw
);
2383 /* SuperSpeed endpoints never get added to intervals in the table, so
2384 * this check is only valid for HS/FS/LS devices.
2386 if (list_empty(&virt_ep
->bw_endpoint_list
))
2388 /* For LS/FS devices, we need to translate the interval expressed in
2389 * microframes to frames.
2391 if (udev
->speed
== USB_SPEED_HIGH
)
2392 normalized_interval
= ep_bw
->ep_interval
;
2394 normalized_interval
= ep_bw
->ep_interval
- 3;
2396 if (normalized_interval
== 0)
2397 bw_table
->interval0_esit_payload
-= ep_bw
->max_esit_payload
;
2398 interval_bw
= &bw_table
->interval_bw
[normalized_interval
];
2399 interval_bw
->num_packets
-= ep_bw
->num_packets
;
2400 switch (udev
->speed
) {
2402 interval_bw
->overhead
[LS_OVERHEAD_TYPE
] -= 1;
2404 case USB_SPEED_FULL
:
2405 interval_bw
->overhead
[FS_OVERHEAD_TYPE
] -= 1;
2407 case USB_SPEED_HIGH
:
2408 interval_bw
->overhead
[HS_OVERHEAD_TYPE
] -= 1;
2410 case USB_SPEED_SUPER
:
2411 case USB_SPEED_SUPER_PLUS
:
2412 case USB_SPEED_UNKNOWN
:
2413 case USB_SPEED_WIRELESS
:
2414 /* Should never happen because only LS/FS/HS endpoints will get
2415 * added to the endpoint list.
2420 tt_info
->active_eps
-= 1;
2421 list_del_init(&virt_ep
->bw_endpoint_list
);
2424 static void xhci_add_ep_to_interval_table(struct xhci_hcd
*xhci
,
2425 struct xhci_bw_info
*ep_bw
,
2426 struct xhci_interval_bw_table
*bw_table
,
2427 struct usb_device
*udev
,
2428 struct xhci_virt_ep
*virt_ep
,
2429 struct xhci_tt_bw_info
*tt_info
)
2431 struct xhci_interval_bw
*interval_bw
;
2432 struct xhci_virt_ep
*smaller_ep
;
2433 int normalized_interval
;
2435 if (xhci_is_async_ep(ep_bw
->type
))
2438 if (udev
->speed
== USB_SPEED_SUPER
) {
2439 if (xhci_is_sync_in_ep(ep_bw
->type
))
2440 xhci
->devs
[udev
->slot_id
]->bw_table
->ss_bw_in
+=
2441 xhci_get_ss_bw_consumed(ep_bw
);
2443 xhci
->devs
[udev
->slot_id
]->bw_table
->ss_bw_out
+=
2444 xhci_get_ss_bw_consumed(ep_bw
);
2448 /* For LS/FS devices, we need to translate the interval expressed in
2449 * microframes to frames.
2451 if (udev
->speed
== USB_SPEED_HIGH
)
2452 normalized_interval
= ep_bw
->ep_interval
;
2454 normalized_interval
= ep_bw
->ep_interval
- 3;
2456 if (normalized_interval
== 0)
2457 bw_table
->interval0_esit_payload
+= ep_bw
->max_esit_payload
;
2458 interval_bw
= &bw_table
->interval_bw
[normalized_interval
];
2459 interval_bw
->num_packets
+= ep_bw
->num_packets
;
2460 switch (udev
->speed
) {
2462 interval_bw
->overhead
[LS_OVERHEAD_TYPE
] += 1;
2464 case USB_SPEED_FULL
:
2465 interval_bw
->overhead
[FS_OVERHEAD_TYPE
] += 1;
2467 case USB_SPEED_HIGH
:
2468 interval_bw
->overhead
[HS_OVERHEAD_TYPE
] += 1;
2470 case USB_SPEED_SUPER
:
2471 case USB_SPEED_SUPER_PLUS
:
2472 case USB_SPEED_UNKNOWN
:
2473 case USB_SPEED_WIRELESS
:
2474 /* Should never happen because only LS/FS/HS endpoints will get
2475 * added to the endpoint list.
2481 tt_info
->active_eps
+= 1;
2482 /* Insert the endpoint into the list, largest max packet size first. */
2483 list_for_each_entry(smaller_ep
, &interval_bw
->endpoints
,
2485 if (ep_bw
->max_packet_size
>=
2486 smaller_ep
->bw_info
.max_packet_size
) {
2487 /* Add the new ep before the smaller endpoint */
2488 list_add_tail(&virt_ep
->bw_endpoint_list
,
2489 &smaller_ep
->bw_endpoint_list
);
2493 /* Add the new endpoint at the end of the list. */
2494 list_add_tail(&virt_ep
->bw_endpoint_list
,
2495 &interval_bw
->endpoints
);
2498 void xhci_update_tt_active_eps(struct xhci_hcd
*xhci
,
2499 struct xhci_virt_device
*virt_dev
,
2502 struct xhci_root_port_bw_info
*rh_bw_info
;
2503 if (!virt_dev
->tt_info
)
2506 rh_bw_info
= &xhci
->rh_bw
[virt_dev
->real_port
- 1];
2507 if (old_active_eps
== 0 &&
2508 virt_dev
->tt_info
->active_eps
!= 0) {
2509 rh_bw_info
->num_active_tts
+= 1;
2510 rh_bw_info
->bw_table
.bw_used
+= TT_HS_OVERHEAD
;
2511 } else if (old_active_eps
!= 0 &&
2512 virt_dev
->tt_info
->active_eps
== 0) {
2513 rh_bw_info
->num_active_tts
-= 1;
2514 rh_bw_info
->bw_table
.bw_used
-= TT_HS_OVERHEAD
;
2518 static int xhci_reserve_bandwidth(struct xhci_hcd
*xhci
,
2519 struct xhci_virt_device
*virt_dev
,
2520 struct xhci_container_ctx
*in_ctx
)
2522 struct xhci_bw_info ep_bw_info
[31];
2524 struct xhci_input_control_ctx
*ctrl_ctx
;
2525 int old_active_eps
= 0;
2527 if (virt_dev
->tt_info
)
2528 old_active_eps
= virt_dev
->tt_info
->active_eps
;
2530 ctrl_ctx
= xhci_get_input_control_ctx(in_ctx
);
2532 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
2537 for (i
= 0; i
< 31; i
++) {
2538 if (!EP_IS_ADDED(ctrl_ctx
, i
) && !EP_IS_DROPPED(ctrl_ctx
, i
))
2541 /* Make a copy of the BW info in case we need to revert this */
2542 memcpy(&ep_bw_info
[i
], &virt_dev
->eps
[i
].bw_info
,
2543 sizeof(ep_bw_info
[i
]));
2544 /* Drop the endpoint from the interval table if the endpoint is
2545 * being dropped or changed.
2547 if (EP_IS_DROPPED(ctrl_ctx
, i
))
2548 xhci_drop_ep_from_interval_table(xhci
,
2549 &virt_dev
->eps
[i
].bw_info
,
2555 /* Overwrite the information stored in the endpoints' bw_info */
2556 xhci_update_bw_info(xhci
, virt_dev
->in_ctx
, ctrl_ctx
, virt_dev
);
2557 for (i
= 0; i
< 31; i
++) {
2558 /* Add any changed or added endpoints to the interval table */
2559 if (EP_IS_ADDED(ctrl_ctx
, i
))
2560 xhci_add_ep_to_interval_table(xhci
,
2561 &virt_dev
->eps
[i
].bw_info
,
2568 if (!xhci_check_bw_table(xhci
, virt_dev
, old_active_eps
)) {
2569 /* Ok, this fits in the bandwidth we have.
2570 * Update the number of active TTs.
2572 xhci_update_tt_active_eps(xhci
, virt_dev
, old_active_eps
);
2576 /* We don't have enough bandwidth for this, revert the stored info. */
2577 for (i
= 0; i
< 31; i
++) {
2578 if (!EP_IS_ADDED(ctrl_ctx
, i
) && !EP_IS_DROPPED(ctrl_ctx
, i
))
2581 /* Drop the new copies of any added or changed endpoints from
2582 * the interval table.
2584 if (EP_IS_ADDED(ctrl_ctx
, i
)) {
2585 xhci_drop_ep_from_interval_table(xhci
,
2586 &virt_dev
->eps
[i
].bw_info
,
2592 /* Revert the endpoint back to its old information */
2593 memcpy(&virt_dev
->eps
[i
].bw_info
, &ep_bw_info
[i
],
2594 sizeof(ep_bw_info
[i
]));
2595 /* Add any changed or dropped endpoints back into the table */
2596 if (EP_IS_DROPPED(ctrl_ctx
, i
))
2597 xhci_add_ep_to_interval_table(xhci
,
2598 &virt_dev
->eps
[i
].bw_info
,
2608 /* Issue a configure endpoint command or evaluate context command
2609 * and wait for it to finish.
2611 static int xhci_configure_endpoint(struct xhci_hcd
*xhci
,
2612 struct usb_device
*udev
,
2613 struct xhci_command
*command
,
2614 bool ctx_change
, bool must_succeed
)
2617 unsigned long flags
;
2618 struct xhci_input_control_ctx
*ctrl_ctx
;
2619 struct xhci_virt_device
*virt_dev
;
2620 struct xhci_slot_ctx
*slot_ctx
;
2625 spin_lock_irqsave(&xhci
->lock
, flags
);
2627 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
2628 spin_unlock_irqrestore(&xhci
->lock
, flags
);
2632 virt_dev
= xhci
->devs
[udev
->slot_id
];
2634 ctrl_ctx
= xhci_get_input_control_ctx(command
->in_ctx
);
2636 spin_unlock_irqrestore(&xhci
->lock
, flags
);
2637 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
2642 if ((xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
) &&
2643 xhci_reserve_host_resources(xhci
, ctrl_ctx
)) {
2644 spin_unlock_irqrestore(&xhci
->lock
, flags
);
2645 xhci_warn(xhci
, "Not enough host resources, "
2646 "active endpoint contexts = %u\n",
2647 xhci
->num_active_eps
);
2650 if ((xhci
->quirks
& XHCI_SW_BW_CHECKING
) &&
2651 xhci_reserve_bandwidth(xhci
, virt_dev
, command
->in_ctx
)) {
2652 if ((xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
))
2653 xhci_free_host_resources(xhci
, ctrl_ctx
);
2654 spin_unlock_irqrestore(&xhci
->lock
, flags
);
2655 xhci_warn(xhci
, "Not enough bandwidth\n");
2659 slot_ctx
= xhci_get_slot_ctx(xhci
, command
->in_ctx
);
2660 trace_xhci_configure_endpoint(slot_ctx
);
2663 ret
= xhci_queue_configure_endpoint(xhci
, command
,
2664 command
->in_ctx
->dma
,
2665 udev
->slot_id
, must_succeed
);
2667 ret
= xhci_queue_evaluate_context(xhci
, command
,
2668 command
->in_ctx
->dma
,
2669 udev
->slot_id
, must_succeed
);
2671 if ((xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
))
2672 xhci_free_host_resources(xhci
, ctrl_ctx
);
2673 spin_unlock_irqrestore(&xhci
->lock
, flags
);
2674 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
2675 "FIXME allocate a new ring segment");
2678 xhci_ring_cmd_db(xhci
);
2679 spin_unlock_irqrestore(&xhci
->lock
, flags
);
2681 /* Wait for the configure endpoint command to complete */
2682 wait_for_completion(command
->completion
);
2685 ret
= xhci_configure_endpoint_result(xhci
, udev
,
2688 ret
= xhci_evaluate_context_result(xhci
, udev
,
2691 if ((xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
)) {
2692 spin_lock_irqsave(&xhci
->lock
, flags
);
2693 /* If the command failed, remove the reserved resources.
2694 * Otherwise, clean up the estimate to include dropped eps.
2697 xhci_free_host_resources(xhci
, ctrl_ctx
);
2699 xhci_finish_resource_reservation(xhci
, ctrl_ctx
);
2700 spin_unlock_irqrestore(&xhci
->lock
, flags
);
2705 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd
*xhci
,
2706 struct xhci_virt_device
*vdev
, int i
)
2708 struct xhci_virt_ep
*ep
= &vdev
->eps
[i
];
2710 if (ep
->ep_state
& EP_HAS_STREAMS
) {
2711 xhci_warn(xhci
, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2712 xhci_get_endpoint_address(i
));
2713 xhci_free_stream_info(xhci
, ep
->stream_info
);
2714 ep
->stream_info
= NULL
;
2715 ep
->ep_state
&= ~EP_HAS_STREAMS
;
2719 /* Called after one or more calls to xhci_add_endpoint() or
2720 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2721 * to call xhci_reset_bandwidth().
2723 * Since we are in the middle of changing either configuration or
2724 * installing a new alt setting, the USB core won't allow URBs to be
2725 * enqueued for any endpoint on the old config or interface. Nothing
2726 * else should be touching the xhci->devs[slot_id] structure, so we
2727 * don't need to take the xhci->lock for manipulating that.
2729 static int xhci_check_bandwidth(struct usb_hcd
*hcd
, struct usb_device
*udev
)
2733 struct xhci_hcd
*xhci
;
2734 struct xhci_virt_device
*virt_dev
;
2735 struct xhci_input_control_ctx
*ctrl_ctx
;
2736 struct xhci_slot_ctx
*slot_ctx
;
2737 struct xhci_command
*command
;
2739 ret
= xhci_check_args(hcd
, udev
, NULL
, 0, true, __func__
);
2742 xhci
= hcd_to_xhci(hcd
);
2743 if ((xhci
->xhc_state
& XHCI_STATE_DYING
) ||
2744 (xhci
->xhc_state
& XHCI_STATE_REMOVING
))
2747 xhci_dbg(xhci
, "%s called for udev %p\n", __func__
, udev
);
2748 virt_dev
= xhci
->devs
[udev
->slot_id
];
2750 command
= xhci_alloc_command(xhci
, false, true, GFP_KERNEL
);
2754 command
->in_ctx
= virt_dev
->in_ctx
;
2756 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2757 ctrl_ctx
= xhci_get_input_control_ctx(command
->in_ctx
);
2759 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
2762 goto command_cleanup
;
2764 ctrl_ctx
->add_flags
|= cpu_to_le32(SLOT_FLAG
);
2765 ctrl_ctx
->add_flags
&= cpu_to_le32(~EP0_FLAG
);
2766 ctrl_ctx
->drop_flags
&= cpu_to_le32(~(SLOT_FLAG
| EP0_FLAG
));
2768 /* Don't issue the command if there's no endpoints to update. */
2769 if (ctrl_ctx
->add_flags
== cpu_to_le32(SLOT_FLAG
) &&
2770 ctrl_ctx
->drop_flags
== 0) {
2772 goto command_cleanup
;
2774 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
2775 slot_ctx
= xhci_get_slot_ctx(xhci
, virt_dev
->in_ctx
);
2776 for (i
= 31; i
>= 1; i
--) {
2777 __le32 le32
= cpu_to_le32(BIT(i
));
2779 if ((virt_dev
->eps
[i
-1].ring
&& !(ctrl_ctx
->drop_flags
& le32
))
2780 || (ctrl_ctx
->add_flags
& le32
) || i
== 1) {
2781 slot_ctx
->dev_info
&= cpu_to_le32(~LAST_CTX_MASK
);
2782 slot_ctx
->dev_info
|= cpu_to_le32(LAST_CTX(i
));
2787 ret
= xhci_configure_endpoint(xhci
, udev
, command
,
2790 /* Callee should call reset_bandwidth() */
2791 goto command_cleanup
;
2793 /* Free any rings that were dropped, but not changed. */
2794 for (i
= 1; i
< 31; i
++) {
2795 if ((le32_to_cpu(ctrl_ctx
->drop_flags
) & (1 << (i
+ 1))) &&
2796 !(le32_to_cpu(ctrl_ctx
->add_flags
) & (1 << (i
+ 1)))) {
2797 xhci_free_endpoint_ring(xhci
, virt_dev
, i
);
2798 xhci_check_bw_drop_ep_streams(xhci
, virt_dev
, i
);
2801 xhci_zero_in_ctx(xhci
, virt_dev
);
2803 * Install any rings for completely new endpoints or changed endpoints,
2804 * and free any old rings from changed endpoints.
2806 for (i
= 1; i
< 31; i
++) {
2807 if (!virt_dev
->eps
[i
].new_ring
)
2809 /* Only free the old ring if it exists.
2810 * It may not if this is the first add of an endpoint.
2812 if (virt_dev
->eps
[i
].ring
) {
2813 xhci_free_endpoint_ring(xhci
, virt_dev
, i
);
2815 xhci_check_bw_drop_ep_streams(xhci
, virt_dev
, i
);
2816 virt_dev
->eps
[i
].ring
= virt_dev
->eps
[i
].new_ring
;
2817 virt_dev
->eps
[i
].new_ring
= NULL
;
2820 kfree(command
->completion
);
2826 static void xhci_reset_bandwidth(struct usb_hcd
*hcd
, struct usb_device
*udev
)
2828 struct xhci_hcd
*xhci
;
2829 struct xhci_virt_device
*virt_dev
;
2832 ret
= xhci_check_args(hcd
, udev
, NULL
, 0, true, __func__
);
2835 xhci
= hcd_to_xhci(hcd
);
2837 xhci_dbg(xhci
, "%s called for udev %p\n", __func__
, udev
);
2838 virt_dev
= xhci
->devs
[udev
->slot_id
];
2839 /* Free any rings allocated for added endpoints */
2840 for (i
= 0; i
< 31; i
++) {
2841 if (virt_dev
->eps
[i
].new_ring
) {
2842 xhci_debugfs_remove_endpoint(xhci
, virt_dev
, i
);
2843 xhci_ring_free(xhci
, virt_dev
->eps
[i
].new_ring
);
2844 virt_dev
->eps
[i
].new_ring
= NULL
;
2847 xhci_zero_in_ctx(xhci
, virt_dev
);
2850 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd
*xhci
,
2851 struct xhci_container_ctx
*in_ctx
,
2852 struct xhci_container_ctx
*out_ctx
,
2853 struct xhci_input_control_ctx
*ctrl_ctx
,
2854 u32 add_flags
, u32 drop_flags
)
2856 ctrl_ctx
->add_flags
= cpu_to_le32(add_flags
);
2857 ctrl_ctx
->drop_flags
= cpu_to_le32(drop_flags
);
2858 xhci_slot_copy(xhci
, in_ctx
, out_ctx
);
2859 ctrl_ctx
->add_flags
|= cpu_to_le32(SLOT_FLAG
);
2862 static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd
*xhci
,
2863 unsigned int slot_id
, unsigned int ep_index
,
2864 struct xhci_dequeue_state
*deq_state
)
2866 struct xhci_input_control_ctx
*ctrl_ctx
;
2867 struct xhci_container_ctx
*in_ctx
;
2868 struct xhci_ep_ctx
*ep_ctx
;
2872 in_ctx
= xhci
->devs
[slot_id
]->in_ctx
;
2873 ctrl_ctx
= xhci_get_input_control_ctx(in_ctx
);
2875 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
2880 xhci_endpoint_copy(xhci
, xhci
->devs
[slot_id
]->in_ctx
,
2881 xhci
->devs
[slot_id
]->out_ctx
, ep_index
);
2882 ep_ctx
= xhci_get_ep_ctx(xhci
, in_ctx
, ep_index
);
2883 addr
= xhci_trb_virt_to_dma(deq_state
->new_deq_seg
,
2884 deq_state
->new_deq_ptr
);
2886 xhci_warn(xhci
, "WARN Cannot submit config ep after "
2887 "reset ep command\n");
2888 xhci_warn(xhci
, "WARN deq seg = %p, deq ptr = %p\n",
2889 deq_state
->new_deq_seg
,
2890 deq_state
->new_deq_ptr
);
2893 ep_ctx
->deq
= cpu_to_le64(addr
| deq_state
->new_cycle_state
);
2895 added_ctxs
= xhci_get_endpoint_flag_from_index(ep_index
);
2896 xhci_setup_input_ctx_for_config_ep(xhci
, xhci
->devs
[slot_id
]->in_ctx
,
2897 xhci
->devs
[slot_id
]->out_ctx
, ctrl_ctx
,
2898 added_ctxs
, added_ctxs
);
2901 void xhci_cleanup_stalled_ring(struct xhci_hcd
*xhci
, unsigned int ep_index
,
2902 unsigned int stream_id
, struct xhci_td
*td
)
2904 struct xhci_dequeue_state deq_state
;
2905 struct xhci_virt_ep
*ep
;
2906 struct usb_device
*udev
= td
->urb
->dev
;
2908 xhci_dbg_trace(xhci
, trace_xhci_dbg_reset_ep
,
2909 "Cleaning up stalled endpoint ring");
2910 ep
= &xhci
->devs
[udev
->slot_id
]->eps
[ep_index
];
2911 /* We need to move the HW's dequeue pointer past this TD,
2912 * or it will attempt to resend it on the next doorbell ring.
2914 xhci_find_new_dequeue_state(xhci
, udev
->slot_id
,
2915 ep_index
, stream_id
, td
, &deq_state
);
2917 if (!deq_state
.new_deq_ptr
|| !deq_state
.new_deq_seg
)
2920 /* HW with the reset endpoint quirk will use the saved dequeue state to
2921 * issue a configure endpoint command later.
2923 if (!(xhci
->quirks
& XHCI_RESET_EP_QUIRK
)) {
2924 xhci_dbg_trace(xhci
, trace_xhci_dbg_reset_ep
,
2925 "Queueing new dequeue state");
2926 xhci_queue_new_dequeue_state(xhci
, udev
->slot_id
,
2927 ep_index
, &deq_state
);
2929 /* Better hope no one uses the input context between now and the
2930 * reset endpoint completion!
2931 * XXX: No idea how this hardware will react when stream rings
2934 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
2935 "Setting up input context for "
2936 "configure endpoint command");
2937 xhci_setup_input_ctx_for_quirk(xhci
, udev
->slot_id
,
2938 ep_index
, &deq_state
);
2942 /* Called when clearing halted device. The core should have sent the control
2943 * message to clear the device halt condition. The host side of the halt should
2944 * already be cleared with a reset endpoint command issued when the STALL tx
2945 * event was received.
2947 * Context: in_interrupt
2950 static void xhci_endpoint_reset(struct usb_hcd
*hcd
,
2951 struct usb_host_endpoint
*ep
)
2953 struct xhci_hcd
*xhci
;
2955 xhci
= hcd_to_xhci(hcd
);
2958 * We might need to implement the config ep cmd in xhci 4.8.1 note:
2959 * The Reset Endpoint Command may only be issued to endpoints in the
2960 * Halted state. If software wishes reset the Data Toggle or Sequence
2961 * Number of an endpoint that isn't in the Halted state, then software
2962 * may issue a Configure Endpoint Command with the Drop and Add bits set
2963 * for the target endpoint. that is in the Stopped state.
2966 /* For now just print debug to follow the situation */
2967 xhci_dbg(xhci
, "Endpoint 0x%x ep reset callback called\n",
2968 ep
->desc
.bEndpointAddress
);
2971 static int xhci_check_streams_endpoint(struct xhci_hcd
*xhci
,
2972 struct usb_device
*udev
, struct usb_host_endpoint
*ep
,
2973 unsigned int slot_id
)
2976 unsigned int ep_index
;
2977 unsigned int ep_state
;
2981 ret
= xhci_check_args(xhci_to_hcd(xhci
), udev
, ep
, 1, true, __func__
);
2984 if (usb_ss_max_streams(&ep
->ss_ep_comp
) == 0) {
2985 xhci_warn(xhci
, "WARN: SuperSpeed Endpoint Companion"
2986 " descriptor for ep 0x%x does not support streams\n",
2987 ep
->desc
.bEndpointAddress
);
2991 ep_index
= xhci_get_endpoint_index(&ep
->desc
);
2992 ep_state
= xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
;
2993 if (ep_state
& EP_HAS_STREAMS
||
2994 ep_state
& EP_GETTING_STREAMS
) {
2995 xhci_warn(xhci
, "WARN: SuperSpeed bulk endpoint 0x%x "
2996 "already has streams set up.\n",
2997 ep
->desc
.bEndpointAddress
);
2998 xhci_warn(xhci
, "Send email to xHCI maintainer and ask for "
2999 "dynamic stream context array reallocation.\n");
3002 if (!list_empty(&xhci
->devs
[slot_id
]->eps
[ep_index
].ring
->td_list
)) {
3003 xhci_warn(xhci
, "Cannot setup streams for SuperSpeed bulk "
3004 "endpoint 0x%x; URBs are pending.\n",
3005 ep
->desc
.bEndpointAddress
);
3011 static void xhci_calculate_streams_entries(struct xhci_hcd
*xhci
,
3012 unsigned int *num_streams
, unsigned int *num_stream_ctxs
)
3014 unsigned int max_streams
;
3016 /* The stream context array size must be a power of two */
3017 *num_stream_ctxs
= roundup_pow_of_two(*num_streams
);
3019 * Find out how many primary stream array entries the host controller
3020 * supports. Later we may use secondary stream arrays (similar to 2nd
3021 * level page entries), but that's an optional feature for xHCI host
3022 * controllers. xHCs must support at least 4 stream IDs.
3024 max_streams
= HCC_MAX_PSA(xhci
->hcc_params
);
3025 if (*num_stream_ctxs
> max_streams
) {
3026 xhci_dbg(xhci
, "xHCI HW only supports %u stream ctx entries.\n",
3028 *num_stream_ctxs
= max_streams
;
3029 *num_streams
= max_streams
;
3033 /* Returns an error code if one of the endpoint already has streams.
3034 * This does not change any data structures, it only checks and gathers
3037 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd
*xhci
,
3038 struct usb_device
*udev
,
3039 struct usb_host_endpoint
**eps
, unsigned int num_eps
,
3040 unsigned int *num_streams
, u32
*changed_ep_bitmask
)
3042 unsigned int max_streams
;
3043 unsigned int endpoint_flag
;
3047 for (i
= 0; i
< num_eps
; i
++) {
3048 ret
= xhci_check_streams_endpoint(xhci
, udev
,
3049 eps
[i
], udev
->slot_id
);
3053 max_streams
= usb_ss_max_streams(&eps
[i
]->ss_ep_comp
);
3054 if (max_streams
< (*num_streams
- 1)) {
3055 xhci_dbg(xhci
, "Ep 0x%x only supports %u stream IDs.\n",
3056 eps
[i
]->desc
.bEndpointAddress
,
3058 *num_streams
= max_streams
+1;
3061 endpoint_flag
= xhci_get_endpoint_flag(&eps
[i
]->desc
);
3062 if (*changed_ep_bitmask
& endpoint_flag
)
3064 *changed_ep_bitmask
|= endpoint_flag
;
3069 static u32
xhci_calculate_no_streams_bitmask(struct xhci_hcd
*xhci
,
3070 struct usb_device
*udev
,
3071 struct usb_host_endpoint
**eps
, unsigned int num_eps
)
3073 u32 changed_ep_bitmask
= 0;
3074 unsigned int slot_id
;
3075 unsigned int ep_index
;
3076 unsigned int ep_state
;
3079 slot_id
= udev
->slot_id
;
3080 if (!xhci
->devs
[slot_id
])
3083 for (i
= 0; i
< num_eps
; i
++) {
3084 ep_index
= xhci_get_endpoint_index(&eps
[i
]->desc
);
3085 ep_state
= xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
;
3086 /* Are streams already being freed for the endpoint? */
3087 if (ep_state
& EP_GETTING_NO_STREAMS
) {
3088 xhci_warn(xhci
, "WARN Can't disable streams for "
3090 "streams are being disabled already\n",
3091 eps
[i
]->desc
.bEndpointAddress
);
3094 /* Are there actually any streams to free? */
3095 if (!(ep_state
& EP_HAS_STREAMS
) &&
3096 !(ep_state
& EP_GETTING_STREAMS
)) {
3097 xhci_warn(xhci
, "WARN Can't disable streams for "
3099 "streams are already disabled!\n",
3100 eps
[i
]->desc
.bEndpointAddress
);
3101 xhci_warn(xhci
, "WARN xhci_free_streams() called "
3102 "with non-streams endpoint\n");
3105 changed_ep_bitmask
|= xhci_get_endpoint_flag(&eps
[i
]->desc
);
3107 return changed_ep_bitmask
;
3111 * The USB device drivers use this function (through the HCD interface in USB
3112 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3113 * coordinate mass storage command queueing across multiple endpoints (basically
3114 * a stream ID == a task ID).
3116 * Setting up streams involves allocating the same size stream context array
3117 * for each endpoint and issuing a configure endpoint command for all endpoints.
3119 * Don't allow the call to succeed if one endpoint only supports one stream
3120 * (which means it doesn't support streams at all).
3122 * Drivers may get less stream IDs than they asked for, if the host controller
3123 * hardware or endpoints claim they can't support the number of requested
3126 static int xhci_alloc_streams(struct usb_hcd
*hcd
, struct usb_device
*udev
,
3127 struct usb_host_endpoint
**eps
, unsigned int num_eps
,
3128 unsigned int num_streams
, gfp_t mem_flags
)
3131 struct xhci_hcd
*xhci
;
3132 struct xhci_virt_device
*vdev
;
3133 struct xhci_command
*config_cmd
;
3134 struct xhci_input_control_ctx
*ctrl_ctx
;
3135 unsigned int ep_index
;
3136 unsigned int num_stream_ctxs
;
3137 unsigned int max_packet
;
3138 unsigned long flags
;
3139 u32 changed_ep_bitmask
= 0;
3144 /* Add one to the number of streams requested to account for
3145 * stream 0 that is reserved for xHCI usage.
3148 xhci
= hcd_to_xhci(hcd
);
3149 xhci_dbg(xhci
, "Driver wants %u stream IDs (including stream 0).\n",
3152 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3153 if ((xhci
->quirks
& XHCI_BROKEN_STREAMS
) ||
3154 HCC_MAX_PSA(xhci
->hcc_params
) < 4) {
3155 xhci_dbg(xhci
, "xHCI controller does not support streams.\n");
3159 config_cmd
= xhci_alloc_command(xhci
, true, true, mem_flags
);
3163 ctrl_ctx
= xhci_get_input_control_ctx(config_cmd
->in_ctx
);
3165 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
3167 xhci_free_command(xhci
, config_cmd
);
3171 /* Check to make sure all endpoints are not already configured for
3172 * streams. While we're at it, find the maximum number of streams that
3173 * all the endpoints will support and check for duplicate endpoints.
3175 spin_lock_irqsave(&xhci
->lock
, flags
);
3176 ret
= xhci_calculate_streams_and_bitmask(xhci
, udev
, eps
,
3177 num_eps
, &num_streams
, &changed_ep_bitmask
);
3179 xhci_free_command(xhci
, config_cmd
);
3180 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3183 if (num_streams
<= 1) {
3184 xhci_warn(xhci
, "WARN: endpoints can't handle "
3185 "more than one stream.\n");
3186 xhci_free_command(xhci
, config_cmd
);
3187 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3190 vdev
= xhci
->devs
[udev
->slot_id
];
3191 /* Mark each endpoint as being in transition, so
3192 * xhci_urb_enqueue() will reject all URBs.
3194 for (i
= 0; i
< num_eps
; i
++) {
3195 ep_index
= xhci_get_endpoint_index(&eps
[i
]->desc
);
3196 vdev
->eps
[ep_index
].ep_state
|= EP_GETTING_STREAMS
;
3198 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3200 /* Setup internal data structures and allocate HW data structures for
3201 * streams (but don't install the HW structures in the input context
3202 * until we're sure all memory allocation succeeded).
3204 xhci_calculate_streams_entries(xhci
, &num_streams
, &num_stream_ctxs
);
3205 xhci_dbg(xhci
, "Need %u stream ctx entries for %u stream IDs.\n",
3206 num_stream_ctxs
, num_streams
);
3208 for (i
= 0; i
< num_eps
; i
++) {
3209 ep_index
= xhci_get_endpoint_index(&eps
[i
]->desc
);
3210 max_packet
= usb_endpoint_maxp(&eps
[i
]->desc
);
3211 vdev
->eps
[ep_index
].stream_info
= xhci_alloc_stream_info(xhci
,
3214 max_packet
, mem_flags
);
3215 if (!vdev
->eps
[ep_index
].stream_info
)
3217 /* Set maxPstreams in endpoint context and update deq ptr to
3218 * point to stream context array. FIXME
3222 /* Set up the input context for a configure endpoint command. */
3223 for (i
= 0; i
< num_eps
; i
++) {
3224 struct xhci_ep_ctx
*ep_ctx
;
3226 ep_index
= xhci_get_endpoint_index(&eps
[i
]->desc
);
3227 ep_ctx
= xhci_get_ep_ctx(xhci
, config_cmd
->in_ctx
, ep_index
);
3229 xhci_endpoint_copy(xhci
, config_cmd
->in_ctx
,
3230 vdev
->out_ctx
, ep_index
);
3231 xhci_setup_streams_ep_input_ctx(xhci
, ep_ctx
,
3232 vdev
->eps
[ep_index
].stream_info
);
3234 /* Tell the HW to drop its old copy of the endpoint context info
3235 * and add the updated copy from the input context.
3237 xhci_setup_input_ctx_for_config_ep(xhci
, config_cmd
->in_ctx
,
3238 vdev
->out_ctx
, ctrl_ctx
,
3239 changed_ep_bitmask
, changed_ep_bitmask
);
3241 /* Issue and wait for the configure endpoint command */
3242 ret
= xhci_configure_endpoint(xhci
, udev
, config_cmd
,
3245 /* xHC rejected the configure endpoint command for some reason, so we
3246 * leave the old ring intact and free our internal streams data
3252 spin_lock_irqsave(&xhci
->lock
, flags
);
3253 for (i
= 0; i
< num_eps
; i
++) {
3254 ep_index
= xhci_get_endpoint_index(&eps
[i
]->desc
);
3255 vdev
->eps
[ep_index
].ep_state
&= ~EP_GETTING_STREAMS
;
3256 xhci_dbg(xhci
, "Slot %u ep ctx %u now has streams.\n",
3257 udev
->slot_id
, ep_index
);
3258 vdev
->eps
[ep_index
].ep_state
|= EP_HAS_STREAMS
;
3260 xhci_free_command(xhci
, config_cmd
);
3261 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3263 /* Subtract 1 for stream 0, which drivers can't use */
3264 return num_streams
- 1;
3267 /* If it didn't work, free the streams! */
3268 for (i
= 0; i
< num_eps
; i
++) {
3269 ep_index
= xhci_get_endpoint_index(&eps
[i
]->desc
);
3270 xhci_free_stream_info(xhci
, vdev
->eps
[ep_index
].stream_info
);
3271 vdev
->eps
[ep_index
].stream_info
= NULL
;
3272 /* FIXME Unset maxPstreams in endpoint context and
3273 * update deq ptr to point to normal string ring.
3275 vdev
->eps
[ep_index
].ep_state
&= ~EP_GETTING_STREAMS
;
3276 vdev
->eps
[ep_index
].ep_state
&= ~EP_HAS_STREAMS
;
3277 xhci_endpoint_zero(xhci
, vdev
, eps
[i
]);
3279 xhci_free_command(xhci
, config_cmd
);
3283 /* Transition the endpoint from using streams to being a "normal" endpoint
3286 * Modify the endpoint context state, submit a configure endpoint command,
3287 * and free all endpoint rings for streams if that completes successfully.
3289 static int xhci_free_streams(struct usb_hcd
*hcd
, struct usb_device
*udev
,
3290 struct usb_host_endpoint
**eps
, unsigned int num_eps
,
3294 struct xhci_hcd
*xhci
;
3295 struct xhci_virt_device
*vdev
;
3296 struct xhci_command
*command
;
3297 struct xhci_input_control_ctx
*ctrl_ctx
;
3298 unsigned int ep_index
;
3299 unsigned long flags
;
3300 u32 changed_ep_bitmask
;
3302 xhci
= hcd_to_xhci(hcd
);
3303 vdev
= xhci
->devs
[udev
->slot_id
];
3305 /* Set up a configure endpoint command to remove the streams rings */
3306 spin_lock_irqsave(&xhci
->lock
, flags
);
3307 changed_ep_bitmask
= xhci_calculate_no_streams_bitmask(xhci
,
3308 udev
, eps
, num_eps
);
3309 if (changed_ep_bitmask
== 0) {
3310 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3314 /* Use the xhci_command structure from the first endpoint. We may have
3315 * allocated too many, but the driver may call xhci_free_streams() for
3316 * each endpoint it grouped into one call to xhci_alloc_streams().
3318 ep_index
= xhci_get_endpoint_index(&eps
[0]->desc
);
3319 command
= vdev
->eps
[ep_index
].stream_info
->free_streams_command
;
3320 ctrl_ctx
= xhci_get_input_control_ctx(command
->in_ctx
);
3322 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3323 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
3328 for (i
= 0; i
< num_eps
; i
++) {
3329 struct xhci_ep_ctx
*ep_ctx
;
3331 ep_index
= xhci_get_endpoint_index(&eps
[i
]->desc
);
3332 ep_ctx
= xhci_get_ep_ctx(xhci
, command
->in_ctx
, ep_index
);
3333 xhci
->devs
[udev
->slot_id
]->eps
[ep_index
].ep_state
|=
3334 EP_GETTING_NO_STREAMS
;
3336 xhci_endpoint_copy(xhci
, command
->in_ctx
,
3337 vdev
->out_ctx
, ep_index
);
3338 xhci_setup_no_streams_ep_input_ctx(ep_ctx
,
3339 &vdev
->eps
[ep_index
]);
3341 xhci_setup_input_ctx_for_config_ep(xhci
, command
->in_ctx
,
3342 vdev
->out_ctx
, ctrl_ctx
,
3343 changed_ep_bitmask
, changed_ep_bitmask
);
3344 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3346 /* Issue and wait for the configure endpoint command,
3347 * which must succeed.
3349 ret
= xhci_configure_endpoint(xhci
, udev
, command
,
3352 /* xHC rejected the configure endpoint command for some reason, so we
3353 * leave the streams rings intact.
3358 spin_lock_irqsave(&xhci
->lock
, flags
);
3359 for (i
= 0; i
< num_eps
; i
++) {
3360 ep_index
= xhci_get_endpoint_index(&eps
[i
]->desc
);
3361 xhci_free_stream_info(xhci
, vdev
->eps
[ep_index
].stream_info
);
3362 vdev
->eps
[ep_index
].stream_info
= NULL
;
3363 /* FIXME Unset maxPstreams in endpoint context and
3364 * update deq ptr to point to normal string ring.
3366 vdev
->eps
[ep_index
].ep_state
&= ~EP_GETTING_NO_STREAMS
;
3367 vdev
->eps
[ep_index
].ep_state
&= ~EP_HAS_STREAMS
;
3369 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3375 * Deletes endpoint resources for endpoints that were active before a Reset
3376 * Device command, or a Disable Slot command. The Reset Device command leaves
3377 * the control endpoint intact, whereas the Disable Slot command deletes it.
3379 * Must be called with xhci->lock held.
3381 void xhci_free_device_endpoint_resources(struct xhci_hcd
*xhci
,
3382 struct xhci_virt_device
*virt_dev
, bool drop_control_ep
)
3385 unsigned int num_dropped_eps
= 0;
3386 unsigned int drop_flags
= 0;
3388 for (i
= (drop_control_ep
? 0 : 1); i
< 31; i
++) {
3389 if (virt_dev
->eps
[i
].ring
) {
3390 drop_flags
|= 1 << i
;
3394 xhci
->num_active_eps
-= num_dropped_eps
;
3395 if (num_dropped_eps
)
3396 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
3397 "Dropped %u ep ctxs, flags = 0x%x, "
3399 num_dropped_eps
, drop_flags
,
3400 xhci
->num_active_eps
);
3404 * This submits a Reset Device Command, which will set the device state to 0,
3405 * set the device address to 0, and disable all the endpoints except the default
3406 * control endpoint. The USB core should come back and call
3407 * xhci_address_device(), and then re-set up the configuration. If this is
3408 * called because of a usb_reset_and_verify_device(), then the old alternate
3409 * settings will be re-installed through the normal bandwidth allocation
3412 * Wait for the Reset Device command to finish. Remove all structures
3413 * associated with the endpoints that were disabled. Clear the input device
3414 * structure? Reset the control endpoint 0 max packet size?
3416 * If the virt_dev to be reset does not exist or does not match the udev,
3417 * it means the device is lost, possibly due to the xHC restore error and
3418 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3419 * re-allocate the device.
3421 static int xhci_discover_or_reset_device(struct usb_hcd
*hcd
,
3422 struct usb_device
*udev
)
3425 unsigned long flags
;
3426 struct xhci_hcd
*xhci
;
3427 unsigned int slot_id
;
3428 struct xhci_virt_device
*virt_dev
;
3429 struct xhci_command
*reset_device_cmd
;
3430 int last_freed_endpoint
;
3431 struct xhci_slot_ctx
*slot_ctx
;
3432 int old_active_eps
= 0;
3434 ret
= xhci_check_args(hcd
, udev
, NULL
, 0, false, __func__
);
3437 xhci
= hcd_to_xhci(hcd
);
3438 slot_id
= udev
->slot_id
;
3439 virt_dev
= xhci
->devs
[slot_id
];
3441 xhci_dbg(xhci
, "The device to be reset with slot ID %u does "
3442 "not exist. Re-allocate the device\n", slot_id
);
3443 ret
= xhci_alloc_dev(hcd
, udev
);
3450 if (virt_dev
->tt_info
)
3451 old_active_eps
= virt_dev
->tt_info
->active_eps
;
3453 if (virt_dev
->udev
!= udev
) {
3454 /* If the virt_dev and the udev does not match, this virt_dev
3455 * may belong to another udev.
3456 * Re-allocate the device.
3458 xhci_dbg(xhci
, "The device to be reset with slot ID %u does "
3459 "not match the udev. Re-allocate the device\n",
3461 ret
= xhci_alloc_dev(hcd
, udev
);
3468 /* If device is not setup, there is no point in resetting it */
3469 slot_ctx
= xhci_get_slot_ctx(xhci
, virt_dev
->out_ctx
);
3470 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx
->dev_state
)) ==
3471 SLOT_STATE_DISABLED
)
3474 trace_xhci_discover_or_reset_device(slot_ctx
);
3476 xhci_dbg(xhci
, "Resetting device with slot ID %u\n", slot_id
);
3477 /* Allocate the command structure that holds the struct completion.
3478 * Assume we're in process context, since the normal device reset
3479 * process has to wait for the device anyway. Storage devices are
3480 * reset as part of error handling, so use GFP_NOIO instead of
3483 reset_device_cmd
= xhci_alloc_command(xhci
, false, true, GFP_NOIO
);
3484 if (!reset_device_cmd
) {
3485 xhci_dbg(xhci
, "Couldn't allocate command structure.\n");
3489 /* Attempt to submit the Reset Device command to the command ring */
3490 spin_lock_irqsave(&xhci
->lock
, flags
);
3492 ret
= xhci_queue_reset_device(xhci
, reset_device_cmd
, slot_id
);
3494 xhci_dbg(xhci
, "FIXME: allocate a command ring segment\n");
3495 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3496 goto command_cleanup
;
3498 xhci_ring_cmd_db(xhci
);
3499 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3501 /* Wait for the Reset Device command to finish */
3502 wait_for_completion(reset_device_cmd
->completion
);
3504 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3505 * unless we tried to reset a slot ID that wasn't enabled,
3506 * or the device wasn't in the addressed or configured state.
3508 ret
= reset_device_cmd
->status
;
3510 case COMP_COMMAND_ABORTED
:
3511 case COMP_COMMAND_RING_STOPPED
:
3512 xhci_warn(xhci
, "Timeout waiting for reset device command\n");
3514 goto command_cleanup
;
3515 case COMP_SLOT_NOT_ENABLED_ERROR
: /* 0.95 completion for bad slot ID */
3516 case COMP_CONTEXT_STATE_ERROR
: /* 0.96 completion code for same thing */
3517 xhci_dbg(xhci
, "Can't reset device (slot ID %u) in %s state\n",
3519 xhci_get_slot_state(xhci
, virt_dev
->out_ctx
));
3520 xhci_dbg(xhci
, "Not freeing device rings.\n");
3521 /* Don't treat this as an error. May change my mind later. */
3523 goto command_cleanup
;
3525 xhci_dbg(xhci
, "Successful reset device command.\n");
3528 if (xhci_is_vendor_info_code(xhci
, ret
))
3530 xhci_warn(xhci
, "Unknown completion code %u for "
3531 "reset device command.\n", ret
);
3533 goto command_cleanup
;
3536 /* Free up host controller endpoint resources */
3537 if ((xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
)) {
3538 spin_lock_irqsave(&xhci
->lock
, flags
);
3539 /* Don't delete the default control endpoint resources */
3540 xhci_free_device_endpoint_resources(xhci
, virt_dev
, false);
3541 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3544 /* Everything but endpoint 0 is disabled, so free the rings. */
3545 last_freed_endpoint
= 1;
3546 for (i
= 1; i
< 31; i
++) {
3547 struct xhci_virt_ep
*ep
= &virt_dev
->eps
[i
];
3549 if (ep
->ep_state
& EP_HAS_STREAMS
) {
3550 xhci_warn(xhci
, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3551 xhci_get_endpoint_address(i
));
3552 xhci_free_stream_info(xhci
, ep
->stream_info
);
3553 ep
->stream_info
= NULL
;
3554 ep
->ep_state
&= ~EP_HAS_STREAMS
;
3558 xhci_debugfs_remove_endpoint(xhci
, virt_dev
, i
);
3559 xhci_free_endpoint_ring(xhci
, virt_dev
, i
);
3560 last_freed_endpoint
= i
;
3562 if (!list_empty(&virt_dev
->eps
[i
].bw_endpoint_list
))
3563 xhci_drop_ep_from_interval_table(xhci
,
3564 &virt_dev
->eps
[i
].bw_info
,
3569 xhci_clear_endpoint_bw_info(&virt_dev
->eps
[i
].bw_info
);
3571 /* If necessary, update the number of active TTs on this root port */
3572 xhci_update_tt_active_eps(xhci
, virt_dev
, old_active_eps
);
3576 xhci_free_command(xhci
, reset_device_cmd
);
3581 * At this point, the struct usb_device is about to go away, the device has
3582 * disconnected, and all traffic has been stopped and the endpoints have been
3583 * disabled. Free any HC data structures associated with that device.
3585 static void xhci_free_dev(struct usb_hcd
*hcd
, struct usb_device
*udev
)
3587 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
3588 struct xhci_virt_device
*virt_dev
;
3589 struct xhci_slot_ctx
*slot_ctx
;
3592 #ifndef CONFIG_USB_DEFAULT_PERSIST
3594 * We called pm_runtime_get_noresume when the device was attached.
3595 * Decrement the counter here to allow controller to runtime suspend
3596 * if no devices remain.
3598 if (xhci
->quirks
& XHCI_RESET_ON_RESUME
)
3599 pm_runtime_put_noidle(hcd
->self
.controller
);
3602 ret
= xhci_check_args(hcd
, udev
, NULL
, 0, true, __func__
);
3603 /* If the host is halted due to driver unload, we still need to free the
3606 if (ret
<= 0 && ret
!= -ENODEV
)
3609 virt_dev
= xhci
->devs
[udev
->slot_id
];
3610 slot_ctx
= xhci_get_slot_ctx(xhci
, virt_dev
->out_ctx
);
3611 trace_xhci_free_dev(slot_ctx
);
3613 /* Stop any wayward timer functions (which may grab the lock) */
3614 for (i
= 0; i
< 31; i
++) {
3615 virt_dev
->eps
[i
].ep_state
&= ~EP_STOP_CMD_PENDING
;
3616 del_timer_sync(&virt_dev
->eps
[i
].stop_cmd_timer
);
3618 xhci_debugfs_remove_slot(xhci
, udev
->slot_id
);
3619 virt_dev
->udev
= NULL
;
3620 ret
= xhci_disable_slot(xhci
, udev
->slot_id
);
3622 xhci_free_virt_device(xhci
, udev
->slot_id
);
3625 int xhci_disable_slot(struct xhci_hcd
*xhci
, u32 slot_id
)
3627 struct xhci_command
*command
;
3628 unsigned long flags
;
3632 command
= xhci_alloc_command(xhci
, false, false, GFP_KERNEL
);
3636 spin_lock_irqsave(&xhci
->lock
, flags
);
3637 /* Don't disable the slot if the host controller is dead. */
3638 state
= readl(&xhci
->op_regs
->status
);
3639 if (state
== 0xffffffff || (xhci
->xhc_state
& XHCI_STATE_DYING
) ||
3640 (xhci
->xhc_state
& XHCI_STATE_HALTED
)) {
3641 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3646 ret
= xhci_queue_slot_control(xhci
, command
, TRB_DISABLE_SLOT
,
3649 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3653 xhci_ring_cmd_db(xhci
);
3654 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3659 * Checks if we have enough host controller resources for the default control
3662 * Must be called with xhci->lock held.
3664 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd
*xhci
)
3666 if (xhci
->num_active_eps
+ 1 > xhci
->limit_active_eps
) {
3667 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
3668 "Not enough ep ctxs: "
3669 "%u active, need to add 1, limit is %u.",
3670 xhci
->num_active_eps
, xhci
->limit_active_eps
);
3673 xhci
->num_active_eps
+= 1;
3674 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
3675 "Adding 1 ep ctx, %u now active.",
3676 xhci
->num_active_eps
);
3682 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3683 * timed out, or allocating memory failed. Returns 1 on success.
3685 int xhci_alloc_dev(struct usb_hcd
*hcd
, struct usb_device
*udev
)
3687 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
3688 struct xhci_virt_device
*vdev
;
3689 struct xhci_slot_ctx
*slot_ctx
;
3690 unsigned long flags
;
3692 struct xhci_command
*command
;
3694 command
= xhci_alloc_command(xhci
, false, true, GFP_KERNEL
);
3698 spin_lock_irqsave(&xhci
->lock
, flags
);
3699 ret
= xhci_queue_slot_control(xhci
, command
, TRB_ENABLE_SLOT
, 0);
3701 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3702 xhci_dbg(xhci
, "FIXME: allocate a command ring segment\n");
3703 xhci_free_command(xhci
, command
);
3706 xhci_ring_cmd_db(xhci
);
3707 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3709 wait_for_completion(command
->completion
);
3710 slot_id
= command
->slot_id
;
3712 if (!slot_id
|| command
->status
!= COMP_SUCCESS
) {
3713 xhci_err(xhci
, "Error while assigning device slot ID\n");
3714 xhci_err(xhci
, "Max number of devices this xHCI host supports is %u.\n",
3716 readl(&xhci
->cap_regs
->hcs_params1
)));
3717 xhci_free_command(xhci
, command
);
3721 xhci_free_command(xhci
, command
);
3723 if ((xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
)) {
3724 spin_lock_irqsave(&xhci
->lock
, flags
);
3725 ret
= xhci_reserve_host_control_ep_resources(xhci
);
3727 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3728 xhci_warn(xhci
, "Not enough host resources, "
3729 "active endpoint contexts = %u\n",
3730 xhci
->num_active_eps
);
3733 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3735 /* Use GFP_NOIO, since this function can be called from
3736 * xhci_discover_or_reset_device(), which may be called as part of
3737 * mass storage driver error handling.
3739 if (!xhci_alloc_virt_device(xhci
, slot_id
, udev
, GFP_NOIO
)) {
3740 xhci_warn(xhci
, "Could not allocate xHCI USB device data structures\n");
3743 vdev
= xhci
->devs
[slot_id
];
3744 slot_ctx
= xhci_get_slot_ctx(xhci
, vdev
->out_ctx
);
3745 trace_xhci_alloc_dev(slot_ctx
);
3747 udev
->slot_id
= slot_id
;
3749 xhci_debugfs_create_slot(xhci
, slot_id
);
3751 #ifndef CONFIG_USB_DEFAULT_PERSIST
3753 * If resetting upon resume, we can't put the controller into runtime
3754 * suspend if there is a device attached.
3756 if (xhci
->quirks
& XHCI_RESET_ON_RESUME
)
3757 pm_runtime_get_noresume(hcd
->self
.controller
);
3760 /* Is this a LS or FS device under a HS hub? */
3761 /* Hub or peripherial? */
3765 ret
= xhci_disable_slot(xhci
, udev
->slot_id
);
3767 xhci_free_virt_device(xhci
, udev
->slot_id
);
3773 * Issue an Address Device command and optionally send a corresponding
3774 * SetAddress request to the device.
3776 static int xhci_setup_device(struct usb_hcd
*hcd
, struct usb_device
*udev
,
3777 enum xhci_setup_dev setup
)
3779 const char *act
= setup
== SETUP_CONTEXT_ONLY
? "context" : "address";
3780 unsigned long flags
;
3781 struct xhci_virt_device
*virt_dev
;
3783 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
3784 struct xhci_slot_ctx
*slot_ctx
;
3785 struct xhci_input_control_ctx
*ctrl_ctx
;
3787 struct xhci_command
*command
= NULL
;
3789 mutex_lock(&xhci
->mutex
);
3791 if (xhci
->xhc_state
) { /* dying, removing or halted */
3796 if (!udev
->slot_id
) {
3797 xhci_dbg_trace(xhci
, trace_xhci_dbg_address
,
3798 "Bad Slot ID %d", udev
->slot_id
);
3803 virt_dev
= xhci
->devs
[udev
->slot_id
];
3805 if (WARN_ON(!virt_dev
)) {
3807 * In plug/unplug torture test with an NEC controller,
3808 * a zero-dereference was observed once due to virt_dev = 0.
3809 * Print useful debug rather than crash if it is observed again!
3811 xhci_warn(xhci
, "Virt dev invalid for slot_id 0x%x!\n",
3816 slot_ctx
= xhci_get_slot_ctx(xhci
, virt_dev
->out_ctx
);
3817 trace_xhci_setup_device_slot(slot_ctx
);
3819 if (setup
== SETUP_CONTEXT_ONLY
) {
3820 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx
->dev_state
)) ==
3821 SLOT_STATE_DEFAULT
) {
3822 xhci_dbg(xhci
, "Slot already in default state\n");
3827 command
= xhci_alloc_command(xhci
, false, true, GFP_KERNEL
);
3833 command
->in_ctx
= virt_dev
->in_ctx
;
3835 slot_ctx
= xhci_get_slot_ctx(xhci
, virt_dev
->in_ctx
);
3836 ctrl_ctx
= xhci_get_input_control_ctx(virt_dev
->in_ctx
);
3838 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
3844 * If this is the first Set Address since device plug-in or
3845 * virt_device realloaction after a resume with an xHCI power loss,
3846 * then set up the slot context.
3848 if (!slot_ctx
->dev_info
)
3849 xhci_setup_addressable_virt_dev(xhci
, udev
);
3850 /* Otherwise, update the control endpoint ring enqueue pointer. */
3852 xhci_copy_ep0_dequeue_into_input_ctx(xhci
, udev
);
3853 ctrl_ctx
->add_flags
= cpu_to_le32(SLOT_FLAG
| EP0_FLAG
);
3854 ctrl_ctx
->drop_flags
= 0;
3856 trace_xhci_address_ctx(xhci
, virt_dev
->in_ctx
,
3857 le32_to_cpu(slot_ctx
->dev_info
) >> 27);
3859 spin_lock_irqsave(&xhci
->lock
, flags
);
3860 trace_xhci_setup_device(virt_dev
);
3861 ret
= xhci_queue_address_device(xhci
, command
, virt_dev
->in_ctx
->dma
,
3862 udev
->slot_id
, setup
);
3864 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3865 xhci_dbg_trace(xhci
, trace_xhci_dbg_address
,
3866 "FIXME: allocate a command ring segment");
3869 xhci_ring_cmd_db(xhci
);
3870 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3872 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
3873 wait_for_completion(command
->completion
);
3875 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
3876 * the SetAddress() "recovery interval" required by USB and aborting the
3877 * command on a timeout.
3879 switch (command
->status
) {
3880 case COMP_COMMAND_ABORTED
:
3881 case COMP_COMMAND_RING_STOPPED
:
3882 xhci_warn(xhci
, "Timeout while waiting for setup device command\n");
3885 case COMP_CONTEXT_STATE_ERROR
:
3886 case COMP_SLOT_NOT_ENABLED_ERROR
:
3887 xhci_err(xhci
, "Setup ERROR: setup %s command for slot %d.\n",
3888 act
, udev
->slot_id
);
3891 case COMP_USB_TRANSACTION_ERROR
:
3892 dev_warn(&udev
->dev
, "Device not responding to setup %s.\n", act
);
3894 mutex_unlock(&xhci
->mutex
);
3895 ret
= xhci_disable_slot(xhci
, udev
->slot_id
);
3897 xhci_alloc_dev(hcd
, udev
);
3898 kfree(command
->completion
);
3901 case COMP_INCOMPATIBLE_DEVICE_ERROR
:
3902 dev_warn(&udev
->dev
,
3903 "ERROR: Incompatible device for setup %s command\n", act
);
3907 xhci_dbg_trace(xhci
, trace_xhci_dbg_address
,
3908 "Successful setup %s command", act
);
3912 "ERROR: unexpected setup %s command completion code 0x%x.\n",
3913 act
, command
->status
);
3914 trace_xhci_address_ctx(xhci
, virt_dev
->out_ctx
, 1);
3920 temp_64
= xhci_read_64(xhci
, &xhci
->op_regs
->dcbaa_ptr
);
3921 xhci_dbg_trace(xhci
, trace_xhci_dbg_address
,
3922 "Op regs DCBAA ptr = %#016llx", temp_64
);
3923 xhci_dbg_trace(xhci
, trace_xhci_dbg_address
,
3924 "Slot ID %d dcbaa entry @%p = %#016llx",
3926 &xhci
->dcbaa
->dev_context_ptrs
[udev
->slot_id
],
3927 (unsigned long long)
3928 le64_to_cpu(xhci
->dcbaa
->dev_context_ptrs
[udev
->slot_id
]));
3929 xhci_dbg_trace(xhci
, trace_xhci_dbg_address
,
3930 "Output Context DMA address = %#08llx",
3931 (unsigned long long)virt_dev
->out_ctx
->dma
);
3932 trace_xhci_address_ctx(xhci
, virt_dev
->in_ctx
,
3933 le32_to_cpu(slot_ctx
->dev_info
) >> 27);
3935 * USB core uses address 1 for the roothubs, so we add one to the
3936 * address given back to us by the HC.
3938 trace_xhci_address_ctx(xhci
, virt_dev
->out_ctx
,
3939 le32_to_cpu(slot_ctx
->dev_info
) >> 27);
3940 /* Zero the input context control for later use */
3941 ctrl_ctx
->add_flags
= 0;
3942 ctrl_ctx
->drop_flags
= 0;
3944 xhci_dbg_trace(xhci
, trace_xhci_dbg_address
,
3945 "Internal device address = %d",
3946 le32_to_cpu(slot_ctx
->dev_state
) & DEV_ADDR_MASK
);
3948 mutex_unlock(&xhci
->mutex
);
3950 kfree(command
->completion
);
3956 static int xhci_address_device(struct usb_hcd
*hcd
, struct usb_device
*udev
)
3958 return xhci_setup_device(hcd
, udev
, SETUP_CONTEXT_ADDRESS
);
3961 static int xhci_enable_device(struct usb_hcd
*hcd
, struct usb_device
*udev
)
3963 return xhci_setup_device(hcd
, udev
, SETUP_CONTEXT_ONLY
);
3967 * Transfer the port index into real index in the HW port status
3968 * registers. Caculate offset between the port's PORTSC register
3969 * and port status base. Divide the number of per port register
3970 * to get the real index. The raw port number bases 1.
3972 int xhci_find_raw_port_number(struct usb_hcd
*hcd
, int port1
)
3974 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
3975 __le32 __iomem
*base_addr
= &xhci
->op_regs
->port_status_base
;
3976 __le32 __iomem
*addr
;
3979 if (hcd
->speed
< HCD_USB3
)
3980 addr
= xhci
->usb2_ports
[port1
- 1];
3982 addr
= xhci
->usb3_ports
[port1
- 1];
3984 raw_port
= (addr
- base_addr
)/NUM_PORT_REGS
+ 1;
3989 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
3990 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
3992 static int __maybe_unused
xhci_change_max_exit_latency(struct xhci_hcd
*xhci
,
3993 struct usb_device
*udev
, u16 max_exit_latency
)
3995 struct xhci_virt_device
*virt_dev
;
3996 struct xhci_command
*command
;
3997 struct xhci_input_control_ctx
*ctrl_ctx
;
3998 struct xhci_slot_ctx
*slot_ctx
;
3999 unsigned long flags
;
4002 spin_lock_irqsave(&xhci
->lock
, flags
);
4004 virt_dev
= xhci
->devs
[udev
->slot_id
];
4007 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4008 * xHC was re-initialized. Exit latency will be set later after
4009 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4012 if (!virt_dev
|| max_exit_latency
== virt_dev
->current_mel
) {
4013 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4017 /* Attempt to issue an Evaluate Context command to change the MEL. */
4018 command
= xhci
->lpm_command
;
4019 ctrl_ctx
= xhci_get_input_control_ctx(command
->in_ctx
);
4021 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4022 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
4027 xhci_slot_copy(xhci
, command
->in_ctx
, virt_dev
->out_ctx
);
4028 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4030 ctrl_ctx
->add_flags
|= cpu_to_le32(SLOT_FLAG
);
4031 slot_ctx
= xhci_get_slot_ctx(xhci
, command
->in_ctx
);
4032 slot_ctx
->dev_info2
&= cpu_to_le32(~((u32
) MAX_EXIT
));
4033 slot_ctx
->dev_info2
|= cpu_to_le32(max_exit_latency
);
4034 slot_ctx
->dev_state
= 0;
4036 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
4037 "Set up evaluate context for LPM MEL change.");
4039 /* Issue and wait for the evaluate context command. */
4040 ret
= xhci_configure_endpoint(xhci
, udev
, command
,
4044 spin_lock_irqsave(&xhci
->lock
, flags
);
4045 virt_dev
->current_mel
= max_exit_latency
;
4046 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4053 /* BESL to HIRD Encoding array for USB2 LPM */
4054 static int xhci_besl_encoding
[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4055 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4057 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4058 static int xhci_calculate_hird_besl(struct xhci_hcd
*xhci
,
4059 struct usb_device
*udev
)
4061 int u2del
, besl
, besl_host
;
4062 int besl_device
= 0;
4065 u2del
= HCS_U2_LATENCY(xhci
->hcs_params3
);
4066 field
= le32_to_cpu(udev
->bos
->ext_cap
->bmAttributes
);
4068 if (field
& USB_BESL_SUPPORT
) {
4069 for (besl_host
= 0; besl_host
< 16; besl_host
++) {
4070 if (xhci_besl_encoding
[besl_host
] >= u2del
)
4073 /* Use baseline BESL value as default */
4074 if (field
& USB_BESL_BASELINE_VALID
)
4075 besl_device
= USB_GET_BESL_BASELINE(field
);
4076 else if (field
& USB_BESL_DEEP_VALID
)
4077 besl_device
= USB_GET_BESL_DEEP(field
);
4082 besl_host
= (u2del
- 51) / 75 + 1;
4085 besl
= besl_host
+ besl_device
;
4092 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4093 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device
*udev
)
4100 field
= le32_to_cpu(udev
->bos
->ext_cap
->bmAttributes
);
4102 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4103 l1
= udev
->l1_params
.timeout
/ 256;
4105 /* device has preferred BESLD */
4106 if (field
& USB_BESL_DEEP_VALID
) {
4107 besld
= USB_GET_BESL_DEEP(field
);
4111 return PORT_BESLD(besld
) | PORT_L1_TIMEOUT(l1
) | PORT_HIRDM(hirdm
);
4114 static int xhci_set_usb2_hardware_lpm(struct usb_hcd
*hcd
,
4115 struct usb_device
*udev
, int enable
)
4117 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
4118 __le32 __iomem
**port_array
;
4119 __le32 __iomem
*pm_addr
, *hlpm_addr
;
4120 u32 pm_val
, hlpm_val
, field
;
4121 unsigned int port_num
;
4122 unsigned long flags
;
4123 int hird
, exit_latency
;
4126 if (hcd
->speed
>= HCD_USB3
|| !xhci
->hw_lpm_support
||
4130 if (!udev
->parent
|| udev
->parent
->parent
||
4131 udev
->descriptor
.bDeviceClass
== USB_CLASS_HUB
)
4134 if (udev
->usb2_hw_lpm_capable
!= 1)
4137 spin_lock_irqsave(&xhci
->lock
, flags
);
4139 port_array
= xhci
->usb2_ports
;
4140 port_num
= udev
->portnum
- 1;
4141 pm_addr
= port_array
[port_num
] + PORTPMSC
;
4142 pm_val
= readl(pm_addr
);
4143 hlpm_addr
= port_array
[port_num
] + PORTHLPMC
;
4144 field
= le32_to_cpu(udev
->bos
->ext_cap
->bmAttributes
);
4146 xhci_dbg(xhci
, "%s port %d USB2 hardware LPM\n",
4147 enable
? "enable" : "disable", port_num
+ 1);
4149 if (enable
&& !(xhci
->quirks
& XHCI_HW_LPM_DISABLE
)) {
4150 /* Host supports BESL timeout instead of HIRD */
4151 if (udev
->usb2_hw_lpm_besl_capable
) {
4152 /* if device doesn't have a preferred BESL value use a
4153 * default one which works with mixed HIRD and BESL
4154 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4156 if ((field
& USB_BESL_SUPPORT
) &&
4157 (field
& USB_BESL_BASELINE_VALID
))
4158 hird
= USB_GET_BESL_BASELINE(field
);
4160 hird
= udev
->l1_params
.besl
;
4162 exit_latency
= xhci_besl_encoding
[hird
];
4163 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4165 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4166 * input context for link powermanagement evaluate
4167 * context commands. It is protected by hcd->bandwidth
4168 * mutex and is shared by all devices. We need to set
4169 * the max ext latency in USB 2 BESL LPM as well, so
4170 * use the same mutex and xhci_change_max_exit_latency()
4172 mutex_lock(hcd
->bandwidth_mutex
);
4173 ret
= xhci_change_max_exit_latency(xhci
, udev
,
4175 mutex_unlock(hcd
->bandwidth_mutex
);
4179 spin_lock_irqsave(&xhci
->lock
, flags
);
4181 hlpm_val
= xhci_calculate_usb2_hw_lpm_params(udev
);
4182 writel(hlpm_val
, hlpm_addr
);
4186 hird
= xhci_calculate_hird_besl(xhci
, udev
);
4189 pm_val
&= ~PORT_HIRD_MASK
;
4190 pm_val
|= PORT_HIRD(hird
) | PORT_RWE
| PORT_L1DS(udev
->slot_id
);
4191 writel(pm_val
, pm_addr
);
4192 pm_val
= readl(pm_addr
);
4194 writel(pm_val
, pm_addr
);
4198 pm_val
&= ~(PORT_HLE
| PORT_RWE
| PORT_HIRD_MASK
| PORT_L1DS_MASK
);
4199 writel(pm_val
, pm_addr
);
4202 if (udev
->usb2_hw_lpm_besl_capable
) {
4203 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4204 mutex_lock(hcd
->bandwidth_mutex
);
4205 xhci_change_max_exit_latency(xhci
, udev
, 0);
4206 mutex_unlock(hcd
->bandwidth_mutex
);
4211 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4215 /* check if a usb2 port supports a given extened capability protocol
4216 * only USB2 ports extended protocol capability values are cached.
4217 * Return 1 if capability is supported
4219 static int xhci_check_usb2_port_capability(struct xhci_hcd
*xhci
, int port
,
4220 unsigned capability
)
4222 u32 port_offset
, port_count
;
4225 for (i
= 0; i
< xhci
->num_ext_caps
; i
++) {
4226 if (xhci
->ext_caps
[i
] & capability
) {
4227 /* port offsets starts at 1 */
4228 port_offset
= XHCI_EXT_PORT_OFF(xhci
->ext_caps
[i
]) - 1;
4229 port_count
= XHCI_EXT_PORT_COUNT(xhci
->ext_caps
[i
]);
4230 if (port
>= port_offset
&&
4231 port
< port_offset
+ port_count
)
4238 static int xhci_update_device(struct usb_hcd
*hcd
, struct usb_device
*udev
)
4240 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
4241 int portnum
= udev
->portnum
- 1;
4243 if (hcd
->speed
>= HCD_USB3
|| !xhci
->sw_lpm_support
||
4247 /* we only support lpm for non-hub device connected to root hub yet */
4248 if (!udev
->parent
|| udev
->parent
->parent
||
4249 udev
->descriptor
.bDeviceClass
== USB_CLASS_HUB
)
4252 if (xhci
->hw_lpm_support
== 1 &&
4253 xhci_check_usb2_port_capability(
4254 xhci
, portnum
, XHCI_HLC
)) {
4255 udev
->usb2_hw_lpm_capable
= 1;
4256 udev
->l1_params
.timeout
= XHCI_L1_TIMEOUT
;
4257 udev
->l1_params
.besl
= XHCI_DEFAULT_BESL
;
4258 if (xhci_check_usb2_port_capability(xhci
, portnum
,
4260 udev
->usb2_hw_lpm_besl_capable
= 1;
4266 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4268 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4269 static unsigned long long xhci_service_interval_to_ns(
4270 struct usb_endpoint_descriptor
*desc
)
4272 return (1ULL << (desc
->bInterval
- 1)) * 125 * 1000;
4275 static u16
xhci_get_timeout_no_hub_lpm(struct usb_device
*udev
,
4276 enum usb3_link_state state
)
4278 unsigned long long sel
;
4279 unsigned long long pel
;
4280 unsigned int max_sel_pel
;
4285 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4286 sel
= DIV_ROUND_UP(udev
->u1_params
.sel
, 1000);
4287 pel
= DIV_ROUND_UP(udev
->u1_params
.pel
, 1000);
4288 max_sel_pel
= USB3_LPM_MAX_U1_SEL_PEL
;
4292 sel
= DIV_ROUND_UP(udev
->u2_params
.sel
, 1000);
4293 pel
= DIV_ROUND_UP(udev
->u2_params
.pel
, 1000);
4294 max_sel_pel
= USB3_LPM_MAX_U2_SEL_PEL
;
4298 dev_warn(&udev
->dev
, "%s: Can't get timeout for non-U1 or U2 state.\n",
4300 return USB3_LPM_DISABLED
;
4303 if (sel
<= max_sel_pel
&& pel
<= max_sel_pel
)
4304 return USB3_LPM_DEVICE_INITIATED
;
4306 if (sel
> max_sel_pel
)
4307 dev_dbg(&udev
->dev
, "Device-initiated %s disabled "
4308 "due to long SEL %llu ms\n",
4311 dev_dbg(&udev
->dev
, "Device-initiated %s disabled "
4312 "due to long PEL %llu ms\n",
4314 return USB3_LPM_DISABLED
;
4317 /* The U1 timeout should be the maximum of the following values:
4318 * - For control endpoints, U1 system exit latency (SEL) * 3
4319 * - For bulk endpoints, U1 SEL * 5
4320 * - For interrupt endpoints:
4321 * - Notification EPs, U1 SEL * 3
4322 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4323 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4325 static unsigned long long xhci_calculate_intel_u1_timeout(
4326 struct usb_device
*udev
,
4327 struct usb_endpoint_descriptor
*desc
)
4329 unsigned long long timeout_ns
;
4333 ep_type
= usb_endpoint_type(desc
);
4335 case USB_ENDPOINT_XFER_CONTROL
:
4336 timeout_ns
= udev
->u1_params
.sel
* 3;
4338 case USB_ENDPOINT_XFER_BULK
:
4339 timeout_ns
= udev
->u1_params
.sel
* 5;
4341 case USB_ENDPOINT_XFER_INT
:
4342 intr_type
= usb_endpoint_interrupt_type(desc
);
4343 if (intr_type
== USB_ENDPOINT_INTR_NOTIFICATION
) {
4344 timeout_ns
= udev
->u1_params
.sel
* 3;
4347 /* Otherwise the calculation is the same as isoc eps */
4349 case USB_ENDPOINT_XFER_ISOC
:
4350 timeout_ns
= xhci_service_interval_to_ns(desc
);
4351 timeout_ns
= DIV_ROUND_UP_ULL(timeout_ns
* 105, 100);
4352 if (timeout_ns
< udev
->u1_params
.sel
* 2)
4353 timeout_ns
= udev
->u1_params
.sel
* 2;
4362 /* Returns the hub-encoded U1 timeout value. */
4363 static u16
xhci_calculate_u1_timeout(struct xhci_hcd
*xhci
,
4364 struct usb_device
*udev
,
4365 struct usb_endpoint_descriptor
*desc
)
4367 unsigned long long timeout_ns
;
4369 if (xhci
->quirks
& XHCI_INTEL_HOST
)
4370 timeout_ns
= xhci_calculate_intel_u1_timeout(udev
, desc
);
4372 timeout_ns
= udev
->u1_params
.sel
;
4374 /* The U1 timeout is encoded in 1us intervals.
4375 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4377 if (timeout_ns
== USB3_LPM_DISABLED
)
4380 timeout_ns
= DIV_ROUND_UP_ULL(timeout_ns
, 1000);
4382 /* If the necessary timeout value is bigger than what we can set in the
4383 * USB 3.0 hub, we have to disable hub-initiated U1.
4385 if (timeout_ns
<= USB3_LPM_U1_MAX_TIMEOUT
)
4387 dev_dbg(&udev
->dev
, "Hub-initiated U1 disabled "
4388 "due to long timeout %llu ms\n", timeout_ns
);
4389 return xhci_get_timeout_no_hub_lpm(udev
, USB3_LPM_U1
);
4392 /* The U2 timeout should be the maximum of:
4393 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4394 * - largest bInterval of any active periodic endpoint (to avoid going
4395 * into lower power link states between intervals).
4396 * - the U2 Exit Latency of the device
4398 static unsigned long long xhci_calculate_intel_u2_timeout(
4399 struct usb_device
*udev
,
4400 struct usb_endpoint_descriptor
*desc
)
4402 unsigned long long timeout_ns
;
4403 unsigned long long u2_del_ns
;
4405 timeout_ns
= 10 * 1000 * 1000;
4407 if ((usb_endpoint_xfer_int(desc
) || usb_endpoint_xfer_isoc(desc
)) &&
4408 (xhci_service_interval_to_ns(desc
) > timeout_ns
))
4409 timeout_ns
= xhci_service_interval_to_ns(desc
);
4411 u2_del_ns
= le16_to_cpu(udev
->bos
->ss_cap
->bU2DevExitLat
) * 1000ULL;
4412 if (u2_del_ns
> timeout_ns
)
4413 timeout_ns
= u2_del_ns
;
4418 /* Returns the hub-encoded U2 timeout value. */
4419 static u16
xhci_calculate_u2_timeout(struct xhci_hcd
*xhci
,
4420 struct usb_device
*udev
,
4421 struct usb_endpoint_descriptor
*desc
)
4423 unsigned long long timeout_ns
;
4425 if (xhci
->quirks
& XHCI_INTEL_HOST
)
4426 timeout_ns
= xhci_calculate_intel_u2_timeout(udev
, desc
);
4428 timeout_ns
= udev
->u2_params
.sel
;
4430 /* The U2 timeout is encoded in 256us intervals */
4431 timeout_ns
= DIV_ROUND_UP_ULL(timeout_ns
, 256 * 1000);
4432 /* If the necessary timeout value is bigger than what we can set in the
4433 * USB 3.0 hub, we have to disable hub-initiated U2.
4435 if (timeout_ns
<= USB3_LPM_U2_MAX_TIMEOUT
)
4437 dev_dbg(&udev
->dev
, "Hub-initiated U2 disabled "
4438 "due to long timeout %llu ms\n", timeout_ns
);
4439 return xhci_get_timeout_no_hub_lpm(udev
, USB3_LPM_U2
);
4442 static u16
xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd
*xhci
,
4443 struct usb_device
*udev
,
4444 struct usb_endpoint_descriptor
*desc
,
4445 enum usb3_link_state state
,
4448 if (state
== USB3_LPM_U1
)
4449 return xhci_calculate_u1_timeout(xhci
, udev
, desc
);
4450 else if (state
== USB3_LPM_U2
)
4451 return xhci_calculate_u2_timeout(xhci
, udev
, desc
);
4453 return USB3_LPM_DISABLED
;
4456 static int xhci_update_timeout_for_endpoint(struct xhci_hcd
*xhci
,
4457 struct usb_device
*udev
,
4458 struct usb_endpoint_descriptor
*desc
,
4459 enum usb3_link_state state
,
4464 alt_timeout
= xhci_call_host_update_timeout_for_endpoint(xhci
, udev
,
4465 desc
, state
, timeout
);
4467 /* If we found we can't enable hub-initiated LPM, or
4468 * the U1 or U2 exit latency was too high to allow
4469 * device-initiated LPM as well, just stop searching.
4471 if (alt_timeout
== USB3_LPM_DISABLED
||
4472 alt_timeout
== USB3_LPM_DEVICE_INITIATED
) {
4473 *timeout
= alt_timeout
;
4476 if (alt_timeout
> *timeout
)
4477 *timeout
= alt_timeout
;
4481 static int xhci_update_timeout_for_interface(struct xhci_hcd
*xhci
,
4482 struct usb_device
*udev
,
4483 struct usb_host_interface
*alt
,
4484 enum usb3_link_state state
,
4489 for (j
= 0; j
< alt
->desc
.bNumEndpoints
; j
++) {
4490 if (xhci_update_timeout_for_endpoint(xhci
, udev
,
4491 &alt
->endpoint
[j
].desc
, state
, timeout
))
4498 static int xhci_check_intel_tier_policy(struct usb_device
*udev
,
4499 enum usb3_link_state state
)
4501 struct usb_device
*parent
;
4502 unsigned int num_hubs
;
4504 if (state
== USB3_LPM_U2
)
4507 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4508 for (parent
= udev
->parent
, num_hubs
= 0; parent
->parent
;
4509 parent
= parent
->parent
)
4515 dev_dbg(&udev
->dev
, "Disabling U1 link state for device"
4516 " below second-tier hub.\n");
4517 dev_dbg(&udev
->dev
, "Plug device into first-tier hub "
4518 "to decrease power consumption.\n");
4522 static int xhci_check_tier_policy(struct xhci_hcd
*xhci
,
4523 struct usb_device
*udev
,
4524 enum usb3_link_state state
)
4526 if (xhci
->quirks
& XHCI_INTEL_HOST
)
4527 return xhci_check_intel_tier_policy(udev
, state
);
4532 /* Returns the U1 or U2 timeout that should be enabled.
4533 * If the tier check or timeout setting functions return with a non-zero exit
4534 * code, that means the timeout value has been finalized and we shouldn't look
4535 * at any more endpoints.
4537 static u16
xhci_calculate_lpm_timeout(struct usb_hcd
*hcd
,
4538 struct usb_device
*udev
, enum usb3_link_state state
)
4540 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
4541 struct usb_host_config
*config
;
4544 u16 timeout
= USB3_LPM_DISABLED
;
4546 if (state
== USB3_LPM_U1
)
4548 else if (state
== USB3_LPM_U2
)
4551 dev_warn(&udev
->dev
, "Can't enable unknown link state %i\n",
4556 if (xhci_check_tier_policy(xhci
, udev
, state
) < 0)
4559 /* Gather some information about the currently installed configuration
4560 * and alternate interface settings.
4562 if (xhci_update_timeout_for_endpoint(xhci
, udev
, &udev
->ep0
.desc
,
4566 config
= udev
->actconfig
;
4570 for (i
= 0; i
< config
->desc
.bNumInterfaces
; i
++) {
4571 struct usb_driver
*driver
;
4572 struct usb_interface
*intf
= config
->interface
[i
];
4577 /* Check if any currently bound drivers want hub-initiated LPM
4580 if (intf
->dev
.driver
) {
4581 driver
= to_usb_driver(intf
->dev
.driver
);
4582 if (driver
&& driver
->disable_hub_initiated_lpm
) {
4583 dev_dbg(&udev
->dev
, "Hub-initiated %s disabled "
4584 "at request of driver %s\n",
4585 state_name
, driver
->name
);
4586 return xhci_get_timeout_no_hub_lpm(udev
, state
);
4590 /* Not sure how this could happen... */
4591 if (!intf
->cur_altsetting
)
4594 if (xhci_update_timeout_for_interface(xhci
, udev
,
4595 intf
->cur_altsetting
,
4602 static int calculate_max_exit_latency(struct usb_device
*udev
,
4603 enum usb3_link_state state_changed
,
4604 u16 hub_encoded_timeout
)
4606 unsigned long long u1_mel_us
= 0;
4607 unsigned long long u2_mel_us
= 0;
4608 unsigned long long mel_us
= 0;
4614 disabling_u1
= (state_changed
== USB3_LPM_U1
&&
4615 hub_encoded_timeout
== USB3_LPM_DISABLED
);
4616 disabling_u2
= (state_changed
== USB3_LPM_U2
&&
4617 hub_encoded_timeout
== USB3_LPM_DISABLED
);
4619 enabling_u1
= (state_changed
== USB3_LPM_U1
&&
4620 hub_encoded_timeout
!= USB3_LPM_DISABLED
);
4621 enabling_u2
= (state_changed
== USB3_LPM_U2
&&
4622 hub_encoded_timeout
!= USB3_LPM_DISABLED
);
4624 /* If U1 was already enabled and we're not disabling it,
4625 * or we're going to enable U1, account for the U1 max exit latency.
4627 if ((udev
->u1_params
.timeout
!= USB3_LPM_DISABLED
&& !disabling_u1
) ||
4629 u1_mel_us
= DIV_ROUND_UP(udev
->u1_params
.mel
, 1000);
4630 if ((udev
->u2_params
.timeout
!= USB3_LPM_DISABLED
&& !disabling_u2
) ||
4632 u2_mel_us
= DIV_ROUND_UP(udev
->u2_params
.mel
, 1000);
4634 if (u1_mel_us
> u2_mel_us
)
4638 /* xHCI host controller max exit latency field is only 16 bits wide. */
4639 if (mel_us
> MAX_EXIT
) {
4640 dev_warn(&udev
->dev
, "Link PM max exit latency of %lluus "
4641 "is too big.\n", mel_us
);
4647 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4648 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd
*hcd
,
4649 struct usb_device
*udev
, enum usb3_link_state state
)
4651 struct xhci_hcd
*xhci
;
4652 u16 hub_encoded_timeout
;
4656 xhci
= hcd_to_xhci(hcd
);
4657 /* The LPM timeout values are pretty host-controller specific, so don't
4658 * enable hub-initiated timeouts unless the vendor has provided
4659 * information about their timeout algorithm.
4661 if (!xhci
|| !(xhci
->quirks
& XHCI_LPM_SUPPORT
) ||
4662 !xhci
->devs
[udev
->slot_id
])
4663 return USB3_LPM_DISABLED
;
4665 hub_encoded_timeout
= xhci_calculate_lpm_timeout(hcd
, udev
, state
);
4666 mel
= calculate_max_exit_latency(udev
, state
, hub_encoded_timeout
);
4668 /* Max Exit Latency is too big, disable LPM. */
4669 hub_encoded_timeout
= USB3_LPM_DISABLED
;
4673 ret
= xhci_change_max_exit_latency(xhci
, udev
, mel
);
4676 return hub_encoded_timeout
;
4679 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd
*hcd
,
4680 struct usb_device
*udev
, enum usb3_link_state state
)
4682 struct xhci_hcd
*xhci
;
4685 xhci
= hcd_to_xhci(hcd
);
4686 if (!xhci
|| !(xhci
->quirks
& XHCI_LPM_SUPPORT
) ||
4687 !xhci
->devs
[udev
->slot_id
])
4690 mel
= calculate_max_exit_latency(udev
, state
, USB3_LPM_DISABLED
);
4691 return xhci_change_max_exit_latency(xhci
, udev
, mel
);
4693 #else /* CONFIG_PM */
4695 static int xhci_set_usb2_hardware_lpm(struct usb_hcd
*hcd
,
4696 struct usb_device
*udev
, int enable
)
4701 static int xhci_update_device(struct usb_hcd
*hcd
, struct usb_device
*udev
)
4706 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd
*hcd
,
4707 struct usb_device
*udev
, enum usb3_link_state state
)
4709 return USB3_LPM_DISABLED
;
4712 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd
*hcd
,
4713 struct usb_device
*udev
, enum usb3_link_state state
)
4717 #endif /* CONFIG_PM */
4719 /*-------------------------------------------------------------------------*/
4721 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
4722 * internal data structures for the device.
4724 static int xhci_update_hub_device(struct usb_hcd
*hcd
, struct usb_device
*hdev
,
4725 struct usb_tt
*tt
, gfp_t mem_flags
)
4727 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
4728 struct xhci_virt_device
*vdev
;
4729 struct xhci_command
*config_cmd
;
4730 struct xhci_input_control_ctx
*ctrl_ctx
;
4731 struct xhci_slot_ctx
*slot_ctx
;
4732 unsigned long flags
;
4733 unsigned think_time
;
4736 /* Ignore root hubs */
4740 vdev
= xhci
->devs
[hdev
->slot_id
];
4742 xhci_warn(xhci
, "Cannot update hub desc for unknown device.\n");
4746 config_cmd
= xhci_alloc_command(xhci
, true, true, mem_flags
);
4750 ctrl_ctx
= xhci_get_input_control_ctx(config_cmd
->in_ctx
);
4752 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
4754 xhci_free_command(xhci
, config_cmd
);
4758 spin_lock_irqsave(&xhci
->lock
, flags
);
4759 if (hdev
->speed
== USB_SPEED_HIGH
&&
4760 xhci_alloc_tt_info(xhci
, vdev
, hdev
, tt
, GFP_ATOMIC
)) {
4761 xhci_dbg(xhci
, "Could not allocate xHCI TT structure.\n");
4762 xhci_free_command(xhci
, config_cmd
);
4763 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4767 xhci_slot_copy(xhci
, config_cmd
->in_ctx
, vdev
->out_ctx
);
4768 ctrl_ctx
->add_flags
|= cpu_to_le32(SLOT_FLAG
);
4769 slot_ctx
= xhci_get_slot_ctx(xhci
, config_cmd
->in_ctx
);
4770 slot_ctx
->dev_info
|= cpu_to_le32(DEV_HUB
);
4772 * refer to section 6.2.2: MTT should be 0 for full speed hub,
4773 * but it may be already set to 1 when setup an xHCI virtual
4774 * device, so clear it anyway.
4777 slot_ctx
->dev_info
|= cpu_to_le32(DEV_MTT
);
4778 else if (hdev
->speed
== USB_SPEED_FULL
)
4779 slot_ctx
->dev_info
&= cpu_to_le32(~DEV_MTT
);
4781 if (xhci
->hci_version
> 0x95) {
4782 xhci_dbg(xhci
, "xHCI version %x needs hub "
4783 "TT think time and number of ports\n",
4784 (unsigned int) xhci
->hci_version
);
4785 slot_ctx
->dev_info2
|= cpu_to_le32(XHCI_MAX_PORTS(hdev
->maxchild
));
4786 /* Set TT think time - convert from ns to FS bit times.
4787 * 0 = 8 FS bit times, 1 = 16 FS bit times,
4788 * 2 = 24 FS bit times, 3 = 32 FS bit times.
4790 * xHCI 1.0: this field shall be 0 if the device is not a
4793 think_time
= tt
->think_time
;
4794 if (think_time
!= 0)
4795 think_time
= (think_time
/ 666) - 1;
4796 if (xhci
->hci_version
< 0x100 || hdev
->speed
== USB_SPEED_HIGH
)
4797 slot_ctx
->tt_info
|=
4798 cpu_to_le32(TT_THINK_TIME(think_time
));
4800 xhci_dbg(xhci
, "xHCI version %x doesn't need hub "
4801 "TT think time or number of ports\n",
4802 (unsigned int) xhci
->hci_version
);
4804 slot_ctx
->dev_state
= 0;
4805 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4807 xhci_dbg(xhci
, "Set up %s for hub device.\n",
4808 (xhci
->hci_version
> 0x95) ?
4809 "configure endpoint" : "evaluate context");
4811 /* Issue and wait for the configure endpoint or
4812 * evaluate context command.
4814 if (xhci
->hci_version
> 0x95)
4815 ret
= xhci_configure_endpoint(xhci
, hdev
, config_cmd
,
4818 ret
= xhci_configure_endpoint(xhci
, hdev
, config_cmd
,
4821 xhci_free_command(xhci
, config_cmd
);
4825 static int xhci_get_frame(struct usb_hcd
*hcd
)
4827 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
4828 /* EHCI mods by the periodic size. Why? */
4829 return readl(&xhci
->run_regs
->microframe_index
) >> 3;
4832 int xhci_gen_setup(struct usb_hcd
*hcd
, xhci_get_quirks_t get_quirks
)
4834 struct xhci_hcd
*xhci
;
4836 * TODO: Check with DWC3 clients for sysdev according to
4839 struct device
*dev
= hcd
->self
.sysdev
;
4840 unsigned int minor_rev
;
4843 /* Accept arbitrarily long scatter-gather lists */
4844 hcd
->self
.sg_tablesize
= ~0;
4846 /* support to build packet from discontinuous buffers */
4847 hcd
->self
.no_sg_constraint
= 1;
4849 /* XHCI controllers don't stop the ep queue on short packets :| */
4850 hcd
->self
.no_stop_on_short
= 1;
4852 xhci
= hcd_to_xhci(hcd
);
4854 if (usb_hcd_is_primary_hcd(hcd
)) {
4855 xhci
->main_hcd
= hcd
;
4856 /* Mark the first roothub as being USB 2.0.
4857 * The xHCI driver will register the USB 3.0 roothub.
4859 hcd
->speed
= HCD_USB2
;
4860 hcd
->self
.root_hub
->speed
= USB_SPEED_HIGH
;
4862 * USB 2.0 roothub under xHCI has an integrated TT,
4863 * (rate matching hub) as opposed to having an OHCI/UHCI
4864 * companion controller.
4869 * Some 3.1 hosts return sbrn 0x30, use xhci supported protocol
4870 * minor revision instead of sbrn
4872 minor_rev
= xhci
->usb3_rhub
.min_rev
;
4874 hcd
->speed
= HCD_USB31
;
4875 hcd
->self
.root_hub
->speed
= USB_SPEED_SUPER_PLUS
;
4877 xhci_info(xhci
, "Host supports USB 3.%x %s SuperSpeed\n",
4879 minor_rev
? "Enhanced" : "");
4881 /* xHCI private pointer was set in xhci_pci_probe for the second
4882 * registered roothub.
4887 mutex_init(&xhci
->mutex
);
4888 xhci
->cap_regs
= hcd
->regs
;
4889 xhci
->op_regs
= hcd
->regs
+
4890 HC_LENGTH(readl(&xhci
->cap_regs
->hc_capbase
));
4891 xhci
->run_regs
= hcd
->regs
+
4892 (readl(&xhci
->cap_regs
->run_regs_off
) & RTSOFF_MASK
);
4893 /* Cache read-only capability registers */
4894 xhci
->hcs_params1
= readl(&xhci
->cap_regs
->hcs_params1
);
4895 xhci
->hcs_params2
= readl(&xhci
->cap_regs
->hcs_params2
);
4896 xhci
->hcs_params3
= readl(&xhci
->cap_regs
->hcs_params3
);
4897 xhci
->hcc_params
= readl(&xhci
->cap_regs
->hc_capbase
);
4898 xhci
->hci_version
= HC_VERSION(xhci
->hcc_params
);
4899 xhci
->hcc_params
= readl(&xhci
->cap_regs
->hcc_params
);
4900 if (xhci
->hci_version
> 0x100)
4901 xhci
->hcc_params2
= readl(&xhci
->cap_regs
->hcc_params2
);
4902 xhci_print_registers(xhci
);
4904 xhci
->quirks
|= quirks
;
4906 get_quirks(dev
, xhci
);
4908 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
4909 * success event after a short transfer. This quirk will ignore such
4912 if (xhci
->hci_version
> 0x96)
4913 xhci
->quirks
|= XHCI_SPURIOUS_SUCCESS
;
4915 /* Make sure the HC is halted. */
4916 retval
= xhci_halt(xhci
);
4920 xhci_dbg(xhci
, "Resetting HCD\n");
4921 /* Reset the internal HC memory state and registers. */
4922 retval
= xhci_reset(xhci
);
4925 xhci_dbg(xhci
, "Reset complete\n");
4928 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
4929 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
4930 * address memory pointers actually. So, this driver clears the AC64
4931 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
4932 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
4934 if (xhci
->quirks
& XHCI_NO_64BIT_SUPPORT
)
4935 xhci
->hcc_params
&= ~BIT(0);
4937 /* Set dma_mask and coherent_dma_mask to 64-bits,
4938 * if xHC supports 64-bit addressing */
4939 if (HCC_64BIT_ADDR(xhci
->hcc_params
) &&
4940 !dma_set_mask(dev
, DMA_BIT_MASK(64))) {
4941 xhci_dbg(xhci
, "Enabling 64-bit DMA addresses.\n");
4942 dma_set_coherent_mask(dev
, DMA_BIT_MASK(64));
4945 * This is to avoid error in cases where a 32-bit USB
4946 * controller is used on a 64-bit capable system.
4948 retval
= dma_set_mask(dev
, DMA_BIT_MASK(32));
4951 xhci_dbg(xhci
, "Enabling 32-bit DMA addresses.\n");
4952 dma_set_coherent_mask(dev
, DMA_BIT_MASK(32));
4955 xhci_dbg(xhci
, "Calling HCD init\n");
4956 /* Initialize HCD and host controller data structures. */
4957 retval
= xhci_init(hcd
);
4960 xhci_dbg(xhci
, "Called HCD init\n");
4962 xhci_info(xhci
, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
4963 xhci
->hcc_params
, xhci
->hci_version
, xhci
->quirks
);
4967 EXPORT_SYMBOL_GPL(xhci_gen_setup
);
4969 static const struct hc_driver xhci_hc_driver
= {
4970 .description
= "xhci-hcd",
4971 .product_desc
= "xHCI Host Controller",
4972 .hcd_priv_size
= sizeof(struct xhci_hcd
),
4975 * generic hardware linkage
4978 .flags
= HCD_MEMORY
| HCD_USB3
| HCD_SHARED
,
4981 * basic lifecycle operations
4983 .reset
= NULL
, /* set in xhci_init_driver() */
4986 .shutdown
= xhci_shutdown
,
4989 * managing i/o requests and associated device resources
4991 .urb_enqueue
= xhci_urb_enqueue
,
4992 .urb_dequeue
= xhci_urb_dequeue
,
4993 .alloc_dev
= xhci_alloc_dev
,
4994 .free_dev
= xhci_free_dev
,
4995 .alloc_streams
= xhci_alloc_streams
,
4996 .free_streams
= xhci_free_streams
,
4997 .add_endpoint
= xhci_add_endpoint
,
4998 .drop_endpoint
= xhci_drop_endpoint
,
4999 .endpoint_reset
= xhci_endpoint_reset
,
5000 .check_bandwidth
= xhci_check_bandwidth
,
5001 .reset_bandwidth
= xhci_reset_bandwidth
,
5002 .address_device
= xhci_address_device
,
5003 .enable_device
= xhci_enable_device
,
5004 .update_hub_device
= xhci_update_hub_device
,
5005 .reset_device
= xhci_discover_or_reset_device
,
5008 * scheduling support
5010 .get_frame_number
= xhci_get_frame
,
5015 .hub_control
= xhci_hub_control
,
5016 .hub_status_data
= xhci_hub_status_data
,
5017 .bus_suspend
= xhci_bus_suspend
,
5018 .bus_resume
= xhci_bus_resume
,
5021 * call back when device connected and addressed
5023 .update_device
= xhci_update_device
,
5024 .set_usb2_hw_lpm
= xhci_set_usb2_hardware_lpm
,
5025 .enable_usb3_lpm_timeout
= xhci_enable_usb3_lpm_timeout
,
5026 .disable_usb3_lpm_timeout
= xhci_disable_usb3_lpm_timeout
,
5027 .find_raw_port_number
= xhci_find_raw_port_number
,
5030 void xhci_init_driver(struct hc_driver
*drv
,
5031 const struct xhci_driver_overrides
*over
)
5035 /* Copy the generic table to drv then apply the overrides */
5036 *drv
= xhci_hc_driver
;
5039 drv
->hcd_priv_size
+= over
->extra_priv_size
;
5041 drv
->reset
= over
->reset
;
5043 drv
->start
= over
->start
;
5046 EXPORT_SYMBOL_GPL(xhci_init_driver
);
5048 MODULE_DESCRIPTION(DRIVER_DESC
);
5049 MODULE_AUTHOR(DRIVER_AUTHOR
);
5050 MODULE_LICENSE("GPL");
5052 static int __init
xhci_hcd_init(void)
5055 * Check the compiler generated sizes of structures that must be laid
5056 * out in specific ways for hardware access.
5058 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array
) != 256*32/8);
5059 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx
) != 8*32/8);
5060 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx
) != 8*32/8);
5061 /* xhci_device_control has eight fields, and also
5062 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5064 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx
) != 4*32/8);
5065 BUILD_BUG_ON(sizeof(union xhci_trb
) != 4*32/8);
5066 BUILD_BUG_ON(sizeof(struct xhci_erst_entry
) != 4*32/8);
5067 BUILD_BUG_ON(sizeof(struct xhci_cap_regs
) != 8*32/8);
5068 BUILD_BUG_ON(sizeof(struct xhci_intr_reg
) != 8*32/8);
5069 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5070 BUILD_BUG_ON(sizeof(struct xhci_run_regs
) != (8+8*128)*32/8);
5075 xhci_debugfs_create_root();
5081 * If an init function is provided, an exit function must also be provided
5082 * to allow module unload.
5084 static void __exit
xhci_hcd_fini(void)
5086 xhci_debugfs_remove_root();
5089 module_init(xhci_hcd_init
);
5090 module_exit(xhci_hcd_fini
);