1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
11 #include <linux/pci.h>
12 #include <linux/irq.h>
13 #include <linux/log2.h>
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/slab.h>
17 #include <linux/dmi.h>
18 #include <linux/dma-mapping.h>
21 #include "xhci-trace.h"
23 #include "xhci-debugfs.h"
24 #include "xhci-dbgcap.h"
26 #define DRIVER_AUTHOR "Sarah Sharp"
27 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
29 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
31 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
32 static int link_quirk
;
33 module_param(link_quirk
, int, S_IRUGO
| S_IWUSR
);
34 MODULE_PARM_DESC(link_quirk
, "Don't clear the chain bit on a link TRB");
36 static unsigned long long quirks
;
37 module_param(quirks
, ullong
, S_IRUGO
);
38 MODULE_PARM_DESC(quirks
, "Bit flags for quirks to be enabled as default");
40 /* TODO: copied from ehci-hcd.c - can this be refactored? */
42 * xhci_handshake - spin reading hc until handshake completes or fails
43 * @ptr: address of hc register to be read
44 * @mask: bits to look at in result of read
45 * @done: value of those bits when handshake succeeds
46 * @usec: timeout in microseconds
48 * Returns negative errno, or zero on success
50 * Success happens when the "mask" bits have the specified value (hardware
51 * handshake done). There are two failure modes: "usec" have passed (major
52 * hardware flakeout), or the register reads as all-ones (hardware removed).
54 int xhci_handshake(void __iomem
*ptr
, u32 mask
, u32 done
, int usec
)
60 if (result
== ~(u32
)0) /* card removed */
72 * Disable interrupts and begin the xHCI halting process.
74 void xhci_quiesce(struct xhci_hcd
*xhci
)
81 halted
= readl(&xhci
->op_regs
->status
) & STS_HALT
;
85 cmd
= readl(&xhci
->op_regs
->command
);
87 writel(cmd
, &xhci
->op_regs
->command
);
91 * Force HC into halt state.
93 * Disable any IRQs and clear the run/stop bit.
94 * HC will complete any current and actively pipelined transactions, and
95 * should halt within 16 ms of the run/stop bit being cleared.
96 * Read HC Halted bit in the status register to see when the HC is finished.
98 int xhci_halt(struct xhci_hcd
*xhci
)
101 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "// Halt the HC");
104 ret
= xhci_handshake(&xhci
->op_regs
->status
,
105 STS_HALT
, STS_HALT
, XHCI_MAX_HALT_USEC
);
107 xhci_warn(xhci
, "Host halt failed, %d\n", ret
);
110 xhci
->xhc_state
|= XHCI_STATE_HALTED
;
111 xhci
->cmd_ring_state
= CMD_RING_STATE_STOPPED
;
116 * Set the run bit and wait for the host to be running.
118 int xhci_start(struct xhci_hcd
*xhci
)
123 temp
= readl(&xhci
->op_regs
->command
);
125 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "// Turn on HC, cmd = 0x%x.",
127 writel(temp
, &xhci
->op_regs
->command
);
130 * Wait for the HCHalted Status bit to be 0 to indicate the host is
133 ret
= xhci_handshake(&xhci
->op_regs
->status
,
134 STS_HALT
, 0, XHCI_MAX_HALT_USEC
);
135 if (ret
== -ETIMEDOUT
)
136 xhci_err(xhci
, "Host took too long to start, "
137 "waited %u microseconds.\n",
140 /* clear state flags. Including dying, halted or removing */
149 * This resets pipelines, timers, counters, state machines, etc.
150 * Transactions will be terminated immediately, and operational registers
151 * will be set to their defaults.
153 int xhci_reset(struct xhci_hcd
*xhci
)
159 state
= readl(&xhci
->op_regs
->status
);
161 if (state
== ~(u32
)0) {
162 xhci_warn(xhci
, "Host not accessible, reset failed.\n");
166 if ((state
& STS_HALT
) == 0) {
167 xhci_warn(xhci
, "Host controller not halted, aborting reset.\n");
171 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "// Reset the HC");
172 command
= readl(&xhci
->op_regs
->command
);
173 command
|= CMD_RESET
;
174 writel(command
, &xhci
->op_regs
->command
);
176 /* Existing Intel xHCI controllers require a delay of 1 mS,
177 * after setting the CMD_RESET bit, and before accessing any
178 * HC registers. This allows the HC to complete the
179 * reset operation and be ready for HC register access.
180 * Without this delay, the subsequent HC register access,
181 * may result in a system hang very rarely.
183 if (xhci
->quirks
& XHCI_INTEL_HOST
)
186 ret
= xhci_handshake(&xhci
->op_regs
->command
,
187 CMD_RESET
, 0, 10 * 1000 * 1000);
191 if (xhci
->quirks
& XHCI_ASMEDIA_MODIFY_FLOWCONTROL
)
192 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
));
194 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
195 "Wait for controller to be ready for doorbell rings");
197 * xHCI cannot write to any doorbells or operational registers other
198 * than status until the "Controller Not Ready" flag is cleared.
200 ret
= xhci_handshake(&xhci
->op_regs
->status
,
201 STS_CNR
, 0, 10 * 1000 * 1000);
203 for (i
= 0; i
< 2; i
++) {
204 xhci
->bus_state
[i
].port_c_suspend
= 0;
205 xhci
->bus_state
[i
].suspended_ports
= 0;
206 xhci
->bus_state
[i
].resuming_ports
= 0;
213 #ifdef CONFIG_USB_PCI
217 static int xhci_setup_msi(struct xhci_hcd
*xhci
)
221 * TODO:Check with MSI Soc for sysdev
223 struct pci_dev
*pdev
= to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
);
225 ret
= pci_alloc_irq_vectors(pdev
, 1, 1, PCI_IRQ_MSI
);
227 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
228 "failed to allocate MSI entry");
232 ret
= request_irq(pdev
->irq
, xhci_msi_irq
,
233 0, "xhci_hcd", xhci_to_hcd(xhci
));
235 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
236 "disable MSI interrupt");
237 pci_free_irq_vectors(pdev
);
246 static int xhci_setup_msix(struct xhci_hcd
*xhci
)
249 struct usb_hcd
*hcd
= xhci_to_hcd(xhci
);
250 struct pci_dev
*pdev
= to_pci_dev(hcd
->self
.controller
);
253 * calculate number of msi-x vectors supported.
254 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
255 * with max number of interrupters based on the xhci HCSPARAMS1.
256 * - num_online_cpus: maximum msi-x vectors per CPUs core.
257 * Add additional 1 vector to ensure always available interrupt.
259 xhci
->msix_count
= min(num_online_cpus() + 1,
260 HCS_MAX_INTRS(xhci
->hcs_params1
));
262 ret
= pci_alloc_irq_vectors(pdev
, xhci
->msix_count
, xhci
->msix_count
,
265 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
266 "Failed to enable MSI-X");
270 for (i
= 0; i
< xhci
->msix_count
; i
++) {
271 ret
= request_irq(pci_irq_vector(pdev
, i
), xhci_msi_irq
, 0,
272 "xhci_hcd", xhci_to_hcd(xhci
));
277 hcd
->msix_enabled
= 1;
281 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "disable MSI-X interrupt");
283 free_irq(pci_irq_vector(pdev
, i
), xhci_to_hcd(xhci
));
284 pci_free_irq_vectors(pdev
);
288 /* Free any IRQs and disable MSI-X */
289 static void xhci_cleanup_msix(struct xhci_hcd
*xhci
)
291 struct usb_hcd
*hcd
= xhci_to_hcd(xhci
);
292 struct pci_dev
*pdev
= to_pci_dev(hcd
->self
.controller
);
294 if (xhci
->quirks
& XHCI_PLAT
)
297 /* return if using legacy interrupt */
301 if (hcd
->msix_enabled
) {
304 for (i
= 0; i
< xhci
->msix_count
; i
++)
305 free_irq(pci_irq_vector(pdev
, i
), xhci_to_hcd(xhci
));
307 free_irq(pci_irq_vector(pdev
, 0), xhci_to_hcd(xhci
));
310 pci_free_irq_vectors(pdev
);
311 hcd
->msix_enabled
= 0;
314 static void __maybe_unused
xhci_msix_sync_irqs(struct xhci_hcd
*xhci
)
316 struct usb_hcd
*hcd
= xhci_to_hcd(xhci
);
318 if (hcd
->msix_enabled
) {
319 struct pci_dev
*pdev
= to_pci_dev(hcd
->self
.controller
);
322 for (i
= 0; i
< xhci
->msix_count
; i
++)
323 synchronize_irq(pci_irq_vector(pdev
, i
));
327 static int xhci_try_enable_msi(struct usb_hcd
*hcd
)
329 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
330 struct pci_dev
*pdev
;
333 /* The xhci platform device has set up IRQs through usb_add_hcd. */
334 if (xhci
->quirks
& XHCI_PLAT
)
337 pdev
= to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
);
339 * Some Fresco Logic host controllers advertise MSI, but fail to
340 * generate interrupts. Don't even try to enable MSI.
342 if (xhci
->quirks
& XHCI_BROKEN_MSI
)
345 /* unregister the legacy interrupt */
347 free_irq(hcd
->irq
, hcd
);
350 ret
= xhci_setup_msix(xhci
);
352 /* fall back to msi*/
353 ret
= xhci_setup_msi(xhci
);
356 hcd
->msi_enabled
= 1;
361 xhci_err(xhci
, "No msi-x/msi found and no IRQ in BIOS\n");
366 if (!strlen(hcd
->irq_descr
))
367 snprintf(hcd
->irq_descr
, sizeof(hcd
->irq_descr
), "%s:usb%d",
368 hcd
->driver
->description
, hcd
->self
.busnum
);
370 /* fall back to legacy interrupt*/
371 ret
= request_irq(pdev
->irq
, &usb_hcd_irq
, IRQF_SHARED
,
372 hcd
->irq_descr
, hcd
);
374 xhci_err(xhci
, "request interrupt %d failed\n",
378 hcd
->irq
= pdev
->irq
;
384 static inline int xhci_try_enable_msi(struct usb_hcd
*hcd
)
389 static inline void xhci_cleanup_msix(struct xhci_hcd
*xhci
)
393 static inline void xhci_msix_sync_irqs(struct xhci_hcd
*xhci
)
399 static void compliance_mode_recovery(struct timer_list
*t
)
401 struct xhci_hcd
*xhci
;
406 xhci
= from_timer(xhci
, t
, comp_mode_recovery_timer
);
408 for (i
= 0; i
< xhci
->num_usb3_ports
; i
++) {
409 temp
= readl(xhci
->usb3_ports
[i
]);
410 if ((temp
& PORT_PLS_MASK
) == USB_SS_PORT_LS_COMP_MOD
) {
412 * Compliance Mode Detected. Letting USB Core
413 * handle the Warm Reset
415 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
416 "Compliance mode detected->port %d",
418 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
419 "Attempting compliance mode recovery");
420 hcd
= xhci
->shared_hcd
;
422 if (hcd
->state
== HC_STATE_SUSPENDED
)
423 usb_hcd_resume_root_hub(hcd
);
425 usb_hcd_poll_rh_status(hcd
);
429 if (xhci
->port_status_u0
!= ((1 << xhci
->num_usb3_ports
)-1))
430 mod_timer(&xhci
->comp_mode_recovery_timer
,
431 jiffies
+ msecs_to_jiffies(COMP_MODE_RCVRY_MSECS
));
435 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
436 * that causes ports behind that hardware to enter compliance mode sometimes.
437 * The quirk creates a timer that polls every 2 seconds the link state of
438 * each host controller's port and recovers it by issuing a Warm reset
439 * if Compliance mode is detected, otherwise the port will become "dead" (no
440 * device connections or disconnections will be detected anymore). Becasue no
441 * status event is generated when entering compliance mode (per xhci spec),
442 * this quirk is needed on systems that have the failing hardware installed.
444 static void compliance_mode_recovery_timer_init(struct xhci_hcd
*xhci
)
446 xhci
->port_status_u0
= 0;
447 timer_setup(&xhci
->comp_mode_recovery_timer
, compliance_mode_recovery
,
449 xhci
->comp_mode_recovery_timer
.expires
= jiffies
+
450 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS
);
452 add_timer(&xhci
->comp_mode_recovery_timer
);
453 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
454 "Compliance mode recovery timer initialized");
458 * This function identifies the systems that have installed the SN65LVPE502CP
459 * USB3.0 re-driver and that need the Compliance Mode Quirk.
461 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
463 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
465 const char *dmi_product_name
, *dmi_sys_vendor
;
467 dmi_product_name
= dmi_get_system_info(DMI_PRODUCT_NAME
);
468 dmi_sys_vendor
= dmi_get_system_info(DMI_SYS_VENDOR
);
469 if (!dmi_product_name
|| !dmi_sys_vendor
)
472 if (!(strstr(dmi_sys_vendor
, "Hewlett-Packard")))
475 if (strstr(dmi_product_name
, "Z420") ||
476 strstr(dmi_product_name
, "Z620") ||
477 strstr(dmi_product_name
, "Z820") ||
478 strstr(dmi_product_name
, "Z1 Workstation"))
484 static int xhci_all_ports_seen_u0(struct xhci_hcd
*xhci
)
486 return (xhci
->port_status_u0
== ((1 << xhci
->num_usb3_ports
)-1));
491 * Initialize memory for HCD and xHC (one-time init).
493 * Program the PAGESIZE register, initialize the device context array, create
494 * device contexts (?), set up a command ring segment (or two?), create event
495 * ring (one for now).
497 static int xhci_init(struct usb_hcd
*hcd
)
499 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
502 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "xhci_init");
503 spin_lock_init(&xhci
->lock
);
504 if (xhci
->hci_version
== 0x95 && link_quirk
) {
505 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
506 "QUIRK: Not clearing Link TRB chain bits.");
507 xhci
->quirks
|= XHCI_LINK_TRB_QUIRK
;
509 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
510 "xHCI doesn't need link TRB QUIRK");
512 retval
= xhci_mem_init(xhci
, GFP_KERNEL
);
513 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "Finished xhci_init");
515 /* Initializing Compliance Mode Recovery Data If Needed */
516 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
517 xhci
->quirks
|= XHCI_COMP_MODE_QUIRK
;
518 compliance_mode_recovery_timer_init(xhci
);
524 /*-------------------------------------------------------------------------*/
527 static int xhci_run_finished(struct xhci_hcd
*xhci
)
529 if (xhci_start(xhci
)) {
533 xhci
->shared_hcd
->state
= HC_STATE_RUNNING
;
534 xhci
->cmd_ring_state
= CMD_RING_STATE_RUNNING
;
536 if (xhci
->quirks
& XHCI_NEC_HOST
)
537 xhci_ring_cmd_db(xhci
);
539 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
540 "Finished xhci_run for USB3 roothub");
545 * Start the HC after it was halted.
547 * This function is called by the USB core when the HC driver is added.
548 * Its opposite is xhci_stop().
550 * xhci_init() must be called once before this function can be called.
551 * Reset the HC, enable device slot contexts, program DCBAAP, and
552 * set command ring pointer and event ring pointer.
554 * Setup MSI-X vectors and enable interrupts.
556 int xhci_run(struct usb_hcd
*hcd
)
561 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
563 /* Start the xHCI host controller running only after the USB 2.0 roothub
567 hcd
->uses_new_polling
= 1;
568 if (!usb_hcd_is_primary_hcd(hcd
))
569 return xhci_run_finished(xhci
);
571 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "xhci_run");
573 ret
= xhci_try_enable_msi(hcd
);
577 xhci_dbg_cmd_ptrs(xhci
);
579 xhci_dbg(xhci
, "ERST memory map follows:\n");
580 xhci_dbg_erst(xhci
, &xhci
->erst
);
581 temp_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
582 temp_64
&= ~ERST_PTR_MASK
;
583 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
584 "ERST deq = 64'h%0lx", (long unsigned int) temp_64
);
586 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
587 "// Set the interrupt modulation register");
588 temp
= readl(&xhci
->ir_set
->irq_control
);
589 temp
&= ~ER_IRQ_INTERVAL_MASK
;
591 * the increment interval is 8 times as much as that defined
592 * in xHCI spec on MTK's controller
594 temp
|= (u32
) ((xhci
->quirks
& XHCI_MTK_HOST
) ? 20 : 160);
595 writel(temp
, &xhci
->ir_set
->irq_control
);
597 /* Set the HCD state before we enable the irqs */
598 temp
= readl(&xhci
->op_regs
->command
);
600 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
601 "// Enable interrupts, cmd = 0x%x.", temp
);
602 writel(temp
, &xhci
->op_regs
->command
);
604 temp
= readl(&xhci
->ir_set
->irq_pending
);
605 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
606 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
607 xhci
->ir_set
, (unsigned int) ER_IRQ_ENABLE(temp
));
608 writel(ER_IRQ_ENABLE(temp
), &xhci
->ir_set
->irq_pending
);
609 xhci_print_ir_set(xhci
, 0);
611 if (xhci
->quirks
& XHCI_NEC_HOST
) {
612 struct xhci_command
*command
;
614 command
= xhci_alloc_command(xhci
, false, false, GFP_KERNEL
);
618 ret
= xhci_queue_vendor_command(xhci
, command
, 0, 0, 0,
619 TRB_TYPE(TRB_NEC_GET_FW
));
621 xhci_free_command(xhci
, command
);
623 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
624 "Finished xhci_run for USB2 roothub");
628 xhci_debugfs_init(xhci
);
632 EXPORT_SYMBOL_GPL(xhci_run
);
637 * This function is called by the USB core when the HC driver is removed.
638 * Its opposite is xhci_run().
640 * Disable device contexts, disable IRQs, and quiesce the HC.
641 * Reset the HC, finish any completed transactions, and cleanup memory.
643 static void xhci_stop(struct usb_hcd
*hcd
)
646 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
648 mutex_lock(&xhci
->mutex
);
650 /* Only halt host and free memory after both hcds are removed */
651 if (!usb_hcd_is_primary_hcd(hcd
)) {
652 /* usb core will free this hcd shortly, unset pointer */
653 xhci
->shared_hcd
= NULL
;
654 mutex_unlock(&xhci
->mutex
);
660 spin_lock_irq(&xhci
->lock
);
661 xhci
->xhc_state
|= XHCI_STATE_HALTED
;
662 xhci
->cmd_ring_state
= CMD_RING_STATE_STOPPED
;
665 spin_unlock_irq(&xhci
->lock
);
667 xhci_cleanup_msix(xhci
);
669 /* Deleting Compliance Mode Recovery Timer */
670 if ((xhci
->quirks
& XHCI_COMP_MODE_QUIRK
) &&
671 (!(xhci_all_ports_seen_u0(xhci
)))) {
672 del_timer_sync(&xhci
->comp_mode_recovery_timer
);
673 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
674 "%s: compliance mode recovery timer deleted",
678 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
681 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
682 "// Disabling event ring interrupts");
683 temp
= readl(&xhci
->op_regs
->status
);
684 writel((temp
& ~0x1fff) | STS_EINT
, &xhci
->op_regs
->status
);
685 temp
= readl(&xhci
->ir_set
->irq_pending
);
686 writel(ER_IRQ_DISABLE(temp
), &xhci
->ir_set
->irq_pending
);
687 xhci_print_ir_set(xhci
, 0);
689 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "cleaning up memory");
690 xhci_mem_cleanup(xhci
);
691 xhci_debugfs_exit(xhci
);
692 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
693 "xhci_stop completed - status = %x",
694 readl(&xhci
->op_regs
->status
));
695 mutex_unlock(&xhci
->mutex
);
699 * Shutdown HC (not bus-specific)
701 * This is called when the machine is rebooting or halting. We assume that the
702 * machine will be powered off, and the HC's internal state will be reset.
703 * Don't bother to free memory.
705 * This will only ever be called with the main usb_hcd (the USB3 roothub).
707 static void xhci_shutdown(struct usb_hcd
*hcd
)
709 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
711 if (xhci
->quirks
& XHCI_SPURIOUS_REBOOT
)
712 usb_disable_xhci_ports(to_pci_dev(hcd
->self
.sysdev
));
714 spin_lock_irq(&xhci
->lock
);
716 /* Workaround for spurious wakeups at shutdown with HSW */
717 if (xhci
->quirks
& XHCI_SPURIOUS_WAKEUP
)
719 spin_unlock_irq(&xhci
->lock
);
721 xhci_cleanup_msix(xhci
);
723 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
724 "xhci_shutdown completed - status = %x",
725 readl(&xhci
->op_regs
->status
));
727 /* Yet another workaround for spurious wakeups at shutdown with HSW */
728 if (xhci
->quirks
& XHCI_SPURIOUS_WAKEUP
)
729 pci_set_power_state(to_pci_dev(hcd
->self
.sysdev
), PCI_D3hot
);
733 static void xhci_save_registers(struct xhci_hcd
*xhci
)
735 xhci
->s3
.command
= readl(&xhci
->op_regs
->command
);
736 xhci
->s3
.dev_nt
= readl(&xhci
->op_regs
->dev_notification
);
737 xhci
->s3
.dcbaa_ptr
= xhci_read_64(xhci
, &xhci
->op_regs
->dcbaa_ptr
);
738 xhci
->s3
.config_reg
= readl(&xhci
->op_regs
->config_reg
);
739 xhci
->s3
.erst_size
= readl(&xhci
->ir_set
->erst_size
);
740 xhci
->s3
.erst_base
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_base
);
741 xhci
->s3
.erst_dequeue
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
742 xhci
->s3
.irq_pending
= readl(&xhci
->ir_set
->irq_pending
);
743 xhci
->s3
.irq_control
= readl(&xhci
->ir_set
->irq_control
);
746 static void xhci_restore_registers(struct xhci_hcd
*xhci
)
748 writel(xhci
->s3
.command
, &xhci
->op_regs
->command
);
749 writel(xhci
->s3
.dev_nt
, &xhci
->op_regs
->dev_notification
);
750 xhci_write_64(xhci
, xhci
->s3
.dcbaa_ptr
, &xhci
->op_regs
->dcbaa_ptr
);
751 writel(xhci
->s3
.config_reg
, &xhci
->op_regs
->config_reg
);
752 writel(xhci
->s3
.erst_size
, &xhci
->ir_set
->erst_size
);
753 xhci_write_64(xhci
, xhci
->s3
.erst_base
, &xhci
->ir_set
->erst_base
);
754 xhci_write_64(xhci
, xhci
->s3
.erst_dequeue
, &xhci
->ir_set
->erst_dequeue
);
755 writel(xhci
->s3
.irq_pending
, &xhci
->ir_set
->irq_pending
);
756 writel(xhci
->s3
.irq_control
, &xhci
->ir_set
->irq_control
);
759 static void xhci_set_cmd_ring_deq(struct xhci_hcd
*xhci
)
763 /* step 2: initialize command ring buffer */
764 val_64
= xhci_read_64(xhci
, &xhci
->op_regs
->cmd_ring
);
765 val_64
= (val_64
& (u64
) CMD_RING_RSVD_BITS
) |
766 (xhci_trb_virt_to_dma(xhci
->cmd_ring
->deq_seg
,
767 xhci
->cmd_ring
->dequeue
) &
768 (u64
) ~CMD_RING_RSVD_BITS
) |
769 xhci
->cmd_ring
->cycle_state
;
770 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
771 "// Setting command ring address to 0x%llx",
772 (long unsigned long) val_64
);
773 xhci_write_64(xhci
, val_64
, &xhci
->op_regs
->cmd_ring
);
777 * The whole command ring must be cleared to zero when we suspend the host.
779 * The host doesn't save the command ring pointer in the suspend well, so we
780 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
781 * aligned, because of the reserved bits in the command ring dequeue pointer
782 * register. Therefore, we can't just set the dequeue pointer back in the
783 * middle of the ring (TRBs are 16-byte aligned).
785 static void xhci_clear_command_ring(struct xhci_hcd
*xhci
)
787 struct xhci_ring
*ring
;
788 struct xhci_segment
*seg
;
790 ring
= xhci
->cmd_ring
;
794 sizeof(union xhci_trb
) * (TRBS_PER_SEGMENT
- 1));
795 seg
->trbs
[TRBS_PER_SEGMENT
- 1].link
.control
&=
796 cpu_to_le32(~TRB_CYCLE
);
798 } while (seg
!= ring
->deq_seg
);
800 /* Reset the software enqueue and dequeue pointers */
801 ring
->deq_seg
= ring
->first_seg
;
802 ring
->dequeue
= ring
->first_seg
->trbs
;
803 ring
->enq_seg
= ring
->deq_seg
;
804 ring
->enqueue
= ring
->dequeue
;
806 ring
->num_trbs_free
= ring
->num_segs
* (TRBS_PER_SEGMENT
- 1) - 1;
808 * Ring is now zeroed, so the HW should look for change of ownership
809 * when the cycle bit is set to 1.
811 ring
->cycle_state
= 1;
814 * Reset the hardware dequeue pointer.
815 * Yes, this will need to be re-written after resume, but we're paranoid
816 * and want to make sure the hardware doesn't access bogus memory
817 * because, say, the BIOS or an SMI started the host without changing
818 * the command ring pointers.
820 xhci_set_cmd_ring_deq(xhci
);
823 static void xhci_disable_port_wake_on_bits(struct xhci_hcd
*xhci
)
826 __le32 __iomem
**port_array
;
830 spin_lock_irqsave(&xhci
->lock
, flags
);
832 /* disable usb3 ports Wake bits */
833 port_index
= xhci
->num_usb3_ports
;
834 port_array
= xhci
->usb3_ports
;
835 while (port_index
--) {
836 t1
= readl(port_array
[port_index
]);
837 t1
= xhci_port_state_to_neutral(t1
);
838 t2
= t1
& ~PORT_WAKE_BITS
;
840 writel(t2
, port_array
[port_index
]);
843 /* disable usb2 ports Wake bits */
844 port_index
= xhci
->num_usb2_ports
;
845 port_array
= xhci
->usb2_ports
;
846 while (port_index
--) {
847 t1
= readl(port_array
[port_index
]);
848 t1
= xhci_port_state_to_neutral(t1
);
849 t2
= t1
& ~PORT_WAKE_BITS
;
851 writel(t2
, port_array
[port_index
]);
854 spin_unlock_irqrestore(&xhci
->lock
, flags
);
858 * Stop HC (not bus-specific)
860 * This is called when the machine transition into S3/S4 mode.
863 int xhci_suspend(struct xhci_hcd
*xhci
, bool do_wakeup
)
866 unsigned int delay
= XHCI_MAX_HALT_USEC
;
867 struct usb_hcd
*hcd
= xhci_to_hcd(xhci
);
874 if (hcd
->state
!= HC_STATE_SUSPENDED
||
875 xhci
->shared_hcd
->state
!= HC_STATE_SUSPENDED
)
878 xhci_dbc_suspend(xhci
);
880 /* Clear root port wake on bits if wakeup not allowed. */
882 xhci_disable_port_wake_on_bits(xhci
);
884 /* Don't poll the roothubs on bus suspend. */
885 xhci_dbg(xhci
, "%s: stopping port polling.\n", __func__
);
886 clear_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
887 del_timer_sync(&hcd
->rh_timer
);
888 clear_bit(HCD_FLAG_POLL_RH
, &xhci
->shared_hcd
->flags
);
889 del_timer_sync(&xhci
->shared_hcd
->rh_timer
);
891 if (xhci
->quirks
& XHCI_SUSPEND_DELAY
)
892 usleep_range(1000, 1500);
894 spin_lock_irq(&xhci
->lock
);
895 clear_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
896 clear_bit(HCD_FLAG_HW_ACCESSIBLE
, &xhci
->shared_hcd
->flags
);
897 /* step 1: stop endpoint */
898 /* skipped assuming that port suspend has done */
900 /* step 2: clear Run/Stop bit */
901 command
= readl(&xhci
->op_regs
->command
);
903 writel(command
, &xhci
->op_regs
->command
);
905 /* Some chips from Fresco Logic need an extraordinary delay */
906 delay
*= (xhci
->quirks
& XHCI_SLOW_SUSPEND
) ? 10 : 1;
908 if (xhci_handshake(&xhci
->op_regs
->status
,
909 STS_HALT
, STS_HALT
, delay
)) {
910 xhci_warn(xhci
, "WARN: xHC CMD_RUN timeout\n");
911 spin_unlock_irq(&xhci
->lock
);
914 xhci_clear_command_ring(xhci
);
916 /* step 3: save registers */
917 xhci_save_registers(xhci
);
919 /* step 4: set CSS flag */
920 command
= readl(&xhci
->op_regs
->command
);
922 writel(command
, &xhci
->op_regs
->command
);
923 xhci
->broken_suspend
= 0;
924 if (xhci_handshake(&xhci
->op_regs
->status
,
925 STS_SAVE
, 0, 10 * 1000)) {
927 * AMD SNPS xHC 3.0 occasionally does not clear the
928 * SSS bit of USBSTS and when driver tries to poll
929 * to see if the xHC clears BIT(8) which never happens
930 * and driver assumes that controller is not responding
931 * and times out. To workaround this, its good to check
932 * if SRE and HCE bits are not set (as per xhci
933 * Section 5.4.2) and bypass the timeout.
935 res
= readl(&xhci
->op_regs
->status
);
936 if ((xhci
->quirks
& XHCI_SNPS_BROKEN_SUSPEND
) &&
937 (((res
& STS_SRE
) == 0) &&
938 ((res
& STS_HCE
) == 0))) {
939 xhci
->broken_suspend
= 1;
941 xhci_warn(xhci
, "WARN: xHC save state timeout\n");
942 spin_unlock_irq(&xhci
->lock
);
946 spin_unlock_irq(&xhci
->lock
);
949 * Deleting Compliance Mode Recovery Timer because the xHCI Host
950 * is about to be suspended.
952 if ((xhci
->quirks
& XHCI_COMP_MODE_QUIRK
) &&
953 (!(xhci_all_ports_seen_u0(xhci
)))) {
954 del_timer_sync(&xhci
->comp_mode_recovery_timer
);
955 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
956 "%s: compliance mode recovery timer deleted",
960 /* step 5: remove core well power */
961 /* synchronize irq when using MSI-X */
962 xhci_msix_sync_irqs(xhci
);
966 EXPORT_SYMBOL_GPL(xhci_suspend
);
969 * start xHC (not bus-specific)
971 * This is called when the machine transition from S3/S4 mode.
974 int xhci_resume(struct xhci_hcd
*xhci
, bool hibernated
)
976 u32 command
, temp
= 0, status
;
977 struct usb_hcd
*hcd
= xhci_to_hcd(xhci
);
978 struct usb_hcd
*secondary_hcd
;
980 bool comp_timer_running
= false;
985 /* Wait a bit if either of the roothubs need to settle from the
986 * transition into bus suspend.
988 if (time_before(jiffies
, xhci
->bus_state
[0].next_statechange
) ||
990 xhci
->bus_state
[1].next_statechange
))
993 set_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
994 set_bit(HCD_FLAG_HW_ACCESSIBLE
, &xhci
->shared_hcd
->flags
);
996 spin_lock_irq(&xhci
->lock
);
997 if ((xhci
->quirks
& XHCI_RESET_ON_RESUME
) || xhci
->broken_suspend
)
1001 /* step 1: restore register */
1002 xhci_restore_registers(xhci
);
1003 /* step 2: initialize command ring buffer */
1004 xhci_set_cmd_ring_deq(xhci
);
1005 /* step 3: restore state and start state*/
1006 /* step 3: set CRS flag */
1007 command
= readl(&xhci
->op_regs
->command
);
1009 writel(command
, &xhci
->op_regs
->command
);
1010 if (xhci_handshake(&xhci
->op_regs
->status
,
1011 STS_RESTORE
, 0, 10 * 1000)) {
1012 xhci_warn(xhci
, "WARN: xHC restore state timeout\n");
1013 spin_unlock_irq(&xhci
->lock
);
1016 temp
= readl(&xhci
->op_regs
->status
);
1019 /* If restore operation fails, re-initialize the HC during resume */
1020 if ((temp
& STS_SRE
) || hibernated
) {
1022 if ((xhci
->quirks
& XHCI_COMP_MODE_QUIRK
) &&
1023 !(xhci_all_ports_seen_u0(xhci
))) {
1024 del_timer_sync(&xhci
->comp_mode_recovery_timer
);
1025 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
1026 "Compliance Mode Recovery Timer deleted!");
1029 /* Let the USB core know _both_ roothubs lost power. */
1030 usb_root_hub_lost_power(xhci
->main_hcd
->self
.root_hub
);
1031 usb_root_hub_lost_power(xhci
->shared_hcd
->self
.root_hub
);
1033 xhci_dbg(xhci
, "Stop HCD\n");
1036 spin_unlock_irq(&xhci
->lock
);
1037 xhci_cleanup_msix(xhci
);
1039 xhci_dbg(xhci
, "// Disabling event ring interrupts\n");
1040 temp
= readl(&xhci
->op_regs
->status
);
1041 writel((temp
& ~0x1fff) | STS_EINT
, &xhci
->op_regs
->status
);
1042 temp
= readl(&xhci
->ir_set
->irq_pending
);
1043 writel(ER_IRQ_DISABLE(temp
), &xhci
->ir_set
->irq_pending
);
1044 xhci_print_ir_set(xhci
, 0);
1046 xhci_dbg(xhci
, "cleaning up memory\n");
1047 xhci_mem_cleanup(xhci
);
1048 xhci_debugfs_exit(xhci
);
1049 xhci_dbg(xhci
, "xhci_stop completed - status = %x\n",
1050 readl(&xhci
->op_regs
->status
));
1052 /* USB core calls the PCI reinit and start functions twice:
1053 * first with the primary HCD, and then with the secondary HCD.
1054 * If we don't do the same, the host will never be started.
1056 if (!usb_hcd_is_primary_hcd(hcd
))
1057 secondary_hcd
= hcd
;
1059 secondary_hcd
= xhci
->shared_hcd
;
1061 xhci_dbg(xhci
, "Initialize the xhci_hcd\n");
1062 retval
= xhci_init(hcd
->primary_hcd
);
1065 comp_timer_running
= true;
1067 xhci_dbg(xhci
, "Start the primary HCD\n");
1068 retval
= xhci_run(hcd
->primary_hcd
);
1070 xhci_dbg(xhci
, "Start the secondary HCD\n");
1071 retval
= xhci_run(secondary_hcd
);
1073 hcd
->state
= HC_STATE_SUSPENDED
;
1074 xhci
->shared_hcd
->state
= HC_STATE_SUSPENDED
;
1078 /* step 4: set Run/Stop bit */
1079 command
= readl(&xhci
->op_regs
->command
);
1081 writel(command
, &xhci
->op_regs
->command
);
1082 xhci_handshake(&xhci
->op_regs
->status
, STS_HALT
,
1085 /* step 5: walk topology and initialize portsc,
1086 * portpmsc and portli
1088 /* this is done in bus_resume */
1090 /* step 6: restart each of the previously
1091 * Running endpoints by ringing their doorbells
1094 spin_unlock_irq(&xhci
->lock
);
1096 xhci_dbc_resume(xhci
);
1100 /* Resume root hubs only when have pending events. */
1101 status
= readl(&xhci
->op_regs
->status
);
1102 if (status
& STS_EINT
) {
1103 usb_hcd_resume_root_hub(xhci
->shared_hcd
);
1104 usb_hcd_resume_root_hub(hcd
);
1109 * If system is subject to the Quirk, Compliance Mode Timer needs to
1110 * be re-initialized Always after a system resume. Ports are subject
1111 * to suffer the Compliance Mode issue again. It doesn't matter if
1112 * ports have entered previously to U0 before system's suspension.
1114 if ((xhci
->quirks
& XHCI_COMP_MODE_QUIRK
) && !comp_timer_running
)
1115 compliance_mode_recovery_timer_init(xhci
);
1117 if (xhci
->quirks
& XHCI_ASMEDIA_MODIFY_FLOWCONTROL
)
1118 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd
->self
.controller
));
1120 /* Re-enable port polling. */
1121 xhci_dbg(xhci
, "%s: starting port polling.\n", __func__
);
1122 set_bit(HCD_FLAG_POLL_RH
, &xhci
->shared_hcd
->flags
);
1123 usb_hcd_poll_rh_status(xhci
->shared_hcd
);
1124 set_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
1125 usb_hcd_poll_rh_status(hcd
);
1129 EXPORT_SYMBOL_GPL(xhci_resume
);
1130 #endif /* CONFIG_PM */
1132 /*-------------------------------------------------------------------------*/
1135 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1136 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1137 * value to right shift 1 for the bitmask.
1139 * Index = (epnum * 2) + direction - 1,
1140 * where direction = 0 for OUT, 1 for IN.
1141 * For control endpoints, the IN index is used (OUT index is unused), so
1142 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1144 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor
*desc
)
1147 if (usb_endpoint_xfer_control(desc
))
1148 index
= (unsigned int) (usb_endpoint_num(desc
)*2);
1150 index
= (unsigned int) (usb_endpoint_num(desc
)*2) +
1151 (usb_endpoint_dir_in(desc
) ? 1 : 0) - 1;
1155 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1156 * address from the XHCI endpoint index.
1158 unsigned int xhci_get_endpoint_address(unsigned int ep_index
)
1160 unsigned int number
= DIV_ROUND_UP(ep_index
, 2);
1161 unsigned int direction
= ep_index
% 2 ? USB_DIR_OUT
: USB_DIR_IN
;
1162 return direction
| number
;
1165 /* Find the flag for this endpoint (for use in the control context). Use the
1166 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1169 static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor
*desc
)
1171 return 1 << (xhci_get_endpoint_index(desc
) + 1);
1174 /* Find the flag for this endpoint (for use in the control context). Use the
1175 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1178 static unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index
)
1180 return 1 << (ep_index
+ 1);
1183 /* Compute the last valid endpoint context index. Basically, this is the
1184 * endpoint index plus one. For slot contexts with more than valid endpoint,
1185 * we find the most significant bit set in the added contexts flags.
1186 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1187 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1189 unsigned int xhci_last_valid_endpoint(u32 added_ctxs
)
1191 return fls(added_ctxs
) - 1;
1194 /* Returns 1 if the arguments are OK;
1195 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1197 static int xhci_check_args(struct usb_hcd
*hcd
, struct usb_device
*udev
,
1198 struct usb_host_endpoint
*ep
, int check_ep
, bool check_virt_dev
,
1200 struct xhci_hcd
*xhci
;
1201 struct xhci_virt_device
*virt_dev
;
1203 if (!hcd
|| (check_ep
&& !ep
) || !udev
) {
1204 pr_debug("xHCI %s called with invalid args\n", func
);
1207 if (!udev
->parent
) {
1208 pr_debug("xHCI %s called for root hub\n", func
);
1212 xhci
= hcd_to_xhci(hcd
);
1213 if (check_virt_dev
) {
1214 if (!udev
->slot_id
|| !xhci
->devs
[udev
->slot_id
]) {
1215 xhci_dbg(xhci
, "xHCI %s called with unaddressed device\n",
1220 virt_dev
= xhci
->devs
[udev
->slot_id
];
1221 if (virt_dev
->udev
!= udev
) {
1222 xhci_dbg(xhci
, "xHCI %s called with udev and "
1223 "virt_dev does not match\n", func
);
1228 if (xhci
->xhc_state
& XHCI_STATE_HALTED
)
1234 static int xhci_configure_endpoint(struct xhci_hcd
*xhci
,
1235 struct usb_device
*udev
, struct xhci_command
*command
,
1236 bool ctx_change
, bool must_succeed
);
1239 * Full speed devices may have a max packet size greater than 8 bytes, but the
1240 * USB core doesn't know that until it reads the first 8 bytes of the
1241 * descriptor. If the usb_device's max packet size changes after that point,
1242 * we need to issue an evaluate context command and wait on it.
1244 static int xhci_check_maxpacket(struct xhci_hcd
*xhci
, unsigned int slot_id
,
1245 unsigned int ep_index
, struct urb
*urb
)
1247 struct xhci_container_ctx
*out_ctx
;
1248 struct xhci_input_control_ctx
*ctrl_ctx
;
1249 struct xhci_ep_ctx
*ep_ctx
;
1250 struct xhci_command
*command
;
1251 int max_packet_size
;
1252 int hw_max_packet_size
;
1255 out_ctx
= xhci
->devs
[slot_id
]->out_ctx
;
1256 ep_ctx
= xhci_get_ep_ctx(xhci
, out_ctx
, ep_index
);
1257 hw_max_packet_size
= MAX_PACKET_DECODED(le32_to_cpu(ep_ctx
->ep_info2
));
1258 max_packet_size
= usb_endpoint_maxp(&urb
->dev
->ep0
.desc
);
1259 if (hw_max_packet_size
!= max_packet_size
) {
1260 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
1261 "Max Packet Size for ep 0 changed.");
1262 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
1263 "Max packet size in usb_device = %d",
1265 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
1266 "Max packet size in xHCI HW = %d",
1267 hw_max_packet_size
);
1268 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
1269 "Issuing evaluate context command.");
1271 /* Set up the input context flags for the command */
1272 /* FIXME: This won't work if a non-default control endpoint
1273 * changes max packet sizes.
1276 command
= xhci_alloc_command(xhci
, false, true, GFP_KERNEL
);
1280 command
->in_ctx
= xhci
->devs
[slot_id
]->in_ctx
;
1281 ctrl_ctx
= xhci_get_input_control_ctx(command
->in_ctx
);
1283 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
1286 goto command_cleanup
;
1288 /* Set up the modified control endpoint 0 */
1289 xhci_endpoint_copy(xhci
, xhci
->devs
[slot_id
]->in_ctx
,
1290 xhci
->devs
[slot_id
]->out_ctx
, ep_index
);
1292 ep_ctx
= xhci_get_ep_ctx(xhci
, command
->in_ctx
, ep_index
);
1293 ep_ctx
->ep_info2
&= cpu_to_le32(~MAX_PACKET_MASK
);
1294 ep_ctx
->ep_info2
|= cpu_to_le32(MAX_PACKET(max_packet_size
));
1296 ctrl_ctx
->add_flags
= cpu_to_le32(EP0_FLAG
);
1297 ctrl_ctx
->drop_flags
= 0;
1299 ret
= xhci_configure_endpoint(xhci
, urb
->dev
, command
,
1302 /* Clean up the input context for later use by bandwidth
1305 ctrl_ctx
->add_flags
= cpu_to_le32(SLOT_FLAG
);
1307 kfree(command
->completion
);
1314 * non-error returns are a promise to giveback() the urb later
1315 * we drop ownership so next owner (or urb unlink) can get it
1317 static int xhci_urb_enqueue(struct usb_hcd
*hcd
, struct urb
*urb
, gfp_t mem_flags
)
1319 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
1320 unsigned long flags
;
1322 unsigned int slot_id
, ep_index
, ep_state
;
1323 struct urb_priv
*urb_priv
;
1326 if (!urb
|| xhci_check_args(hcd
, urb
->dev
, urb
->ep
,
1327 true, true, __func__
) <= 0)
1330 slot_id
= urb
->dev
->slot_id
;
1331 ep_index
= xhci_get_endpoint_index(&urb
->ep
->desc
);
1333 if (!HCD_HW_ACCESSIBLE(hcd
)) {
1334 if (!in_interrupt())
1335 xhci_dbg(xhci
, "urb submitted during PCI suspend\n");
1339 if (usb_endpoint_xfer_isoc(&urb
->ep
->desc
))
1340 num_tds
= urb
->number_of_packets
;
1341 else if (usb_endpoint_is_bulk_out(&urb
->ep
->desc
) &&
1342 urb
->transfer_buffer_length
> 0 &&
1343 urb
->transfer_flags
& URB_ZERO_PACKET
&&
1344 !(urb
->transfer_buffer_length
% usb_endpoint_maxp(&urb
->ep
->desc
)))
1349 urb_priv
= kzalloc(sizeof(struct urb_priv
) +
1350 num_tds
* sizeof(struct xhci_td
), mem_flags
);
1354 urb_priv
->num_tds
= num_tds
;
1355 urb_priv
->num_tds_done
= 0;
1356 urb
->hcpriv
= urb_priv
;
1358 trace_xhci_urb_enqueue(urb
);
1360 if (usb_endpoint_xfer_control(&urb
->ep
->desc
)) {
1361 /* Check to see if the max packet size for the default control
1362 * endpoint changed during FS device enumeration
1364 if (urb
->dev
->speed
== USB_SPEED_FULL
) {
1365 ret
= xhci_check_maxpacket(xhci
, slot_id
,
1368 xhci_urb_free_priv(urb_priv
);
1375 spin_lock_irqsave(&xhci
->lock
, flags
);
1377 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
1378 xhci_dbg(xhci
, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1379 urb
->ep
->desc
.bEndpointAddress
, urb
);
1384 switch (usb_endpoint_type(&urb
->ep
->desc
)) {
1386 case USB_ENDPOINT_XFER_CONTROL
:
1387 ret
= xhci_queue_ctrl_tx(xhci
, GFP_ATOMIC
, urb
,
1390 case USB_ENDPOINT_XFER_BULK
:
1391 ep_state
= xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
;
1392 if (ep_state
& (EP_GETTING_STREAMS
| EP_GETTING_NO_STREAMS
)) {
1393 xhci_warn(xhci
, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1398 ret
= xhci_queue_bulk_tx(xhci
, GFP_ATOMIC
, urb
,
1403 case USB_ENDPOINT_XFER_INT
:
1404 ret
= xhci_queue_intr_tx(xhci
, GFP_ATOMIC
, urb
,
1408 case USB_ENDPOINT_XFER_ISOC
:
1409 ret
= xhci_queue_isoc_tx_prepare(xhci
, GFP_ATOMIC
, urb
,
1415 xhci_urb_free_priv(urb_priv
);
1418 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1423 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1424 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1425 * should pick up where it left off in the TD, unless a Set Transfer Ring
1426 * Dequeue Pointer is issued.
1428 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1429 * the ring. Since the ring is a contiguous structure, they can't be physically
1430 * removed. Instead, there are two options:
1432 * 1) If the HC is in the middle of processing the URB to be canceled, we
1433 * simply move the ring's dequeue pointer past those TRBs using the Set
1434 * Transfer Ring Dequeue Pointer command. This will be the common case,
1435 * when drivers timeout on the last submitted URB and attempt to cancel.
1437 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1438 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1439 * HC will need to invalidate the any TRBs it has cached after the stop
1440 * endpoint command, as noted in the xHCI 0.95 errata.
1442 * 3) The TD may have completed by the time the Stop Endpoint Command
1443 * completes, so software needs to handle that case too.
1445 * This function should protect against the TD enqueueing code ringing the
1446 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1447 * It also needs to account for multiple cancellations on happening at the same
1448 * time for the same endpoint.
1450 * Note that this function can be called in any context, or so says
1451 * usb_hcd_unlink_urb()
1453 static int xhci_urb_dequeue(struct usb_hcd
*hcd
, struct urb
*urb
, int status
)
1455 unsigned long flags
;
1458 struct xhci_hcd
*xhci
;
1459 struct urb_priv
*urb_priv
;
1461 unsigned int ep_index
;
1462 struct xhci_ring
*ep_ring
;
1463 struct xhci_virt_ep
*ep
;
1464 struct xhci_command
*command
;
1465 struct xhci_virt_device
*vdev
;
1467 xhci
= hcd_to_xhci(hcd
);
1468 spin_lock_irqsave(&xhci
->lock
, flags
);
1470 trace_xhci_urb_dequeue(urb
);
1472 /* Make sure the URB hasn't completed or been unlinked already */
1473 ret
= usb_hcd_check_unlink_urb(hcd
, urb
, status
);
1477 /* give back URB now if we can't queue it for cancel */
1478 vdev
= xhci
->devs
[urb
->dev
->slot_id
];
1479 urb_priv
= urb
->hcpriv
;
1480 if (!vdev
|| !urb_priv
)
1483 ep_index
= xhci_get_endpoint_index(&urb
->ep
->desc
);
1484 ep
= &vdev
->eps
[ep_index
];
1485 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
1486 if (!ep
|| !ep_ring
)
1489 /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1490 temp
= readl(&xhci
->op_regs
->status
);
1491 if (temp
== ~(u32
)0 || xhci
->xhc_state
& XHCI_STATE_DYING
) {
1496 if (xhci
->xhc_state
& XHCI_STATE_HALTED
) {
1497 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
1498 "HC halted, freeing TD manually.");
1499 for (i
= urb_priv
->num_tds_done
;
1500 i
< urb_priv
->num_tds
;
1502 td
= &urb_priv
->td
[i
];
1503 if (!list_empty(&td
->td_list
))
1504 list_del_init(&td
->td_list
);
1505 if (!list_empty(&td
->cancelled_td_list
))
1506 list_del_init(&td
->cancelled_td_list
);
1511 i
= urb_priv
->num_tds_done
;
1512 if (i
< urb_priv
->num_tds
)
1513 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
1514 "Cancel URB %p, dev %s, ep 0x%x, "
1515 "starting at offset 0x%llx",
1516 urb
, urb
->dev
->devpath
,
1517 urb
->ep
->desc
.bEndpointAddress
,
1518 (unsigned long long) xhci_trb_virt_to_dma(
1519 urb_priv
->td
[i
].start_seg
,
1520 urb_priv
->td
[i
].first_trb
));
1522 for (; i
< urb_priv
->num_tds
; i
++) {
1523 td
= &urb_priv
->td
[i
];
1524 list_add_tail(&td
->cancelled_td_list
, &ep
->cancelled_td_list
);
1527 /* Queue a stop endpoint command, but only if this is
1528 * the first cancellation to be handled.
1530 if (!(ep
->ep_state
& EP_STOP_CMD_PENDING
)) {
1531 command
= xhci_alloc_command(xhci
, false, false, GFP_ATOMIC
);
1536 ep
->ep_state
|= EP_STOP_CMD_PENDING
;
1537 ep
->stop_cmd_timer
.expires
= jiffies
+
1538 XHCI_STOP_EP_CMD_TIMEOUT
* HZ
;
1539 add_timer(&ep
->stop_cmd_timer
);
1540 xhci_queue_stop_endpoint(xhci
, command
, urb
->dev
->slot_id
,
1542 xhci_ring_cmd_db(xhci
);
1545 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1550 xhci_urb_free_priv(urb_priv
);
1551 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
1552 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1553 usb_hcd_giveback_urb(hcd
, urb
, -ESHUTDOWN
);
1557 /* Drop an endpoint from a new bandwidth configuration for this device.
1558 * Only one call to this function is allowed per endpoint before
1559 * check_bandwidth() or reset_bandwidth() must be called.
1560 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1561 * add the endpoint to the schedule with possibly new parameters denoted by a
1562 * different endpoint descriptor in usb_host_endpoint.
1563 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1566 * The USB core will not allow URBs to be queued to an endpoint that is being
1567 * disabled, so there's no need for mutual exclusion to protect
1568 * the xhci->devs[slot_id] structure.
1570 static int xhci_drop_endpoint(struct usb_hcd
*hcd
, struct usb_device
*udev
,
1571 struct usb_host_endpoint
*ep
)
1573 struct xhci_hcd
*xhci
;
1574 struct xhci_container_ctx
*in_ctx
, *out_ctx
;
1575 struct xhci_input_control_ctx
*ctrl_ctx
;
1576 unsigned int ep_index
;
1577 struct xhci_ep_ctx
*ep_ctx
;
1579 u32 new_add_flags
, new_drop_flags
;
1582 ret
= xhci_check_args(hcd
, udev
, ep
, 1, true, __func__
);
1585 xhci
= hcd_to_xhci(hcd
);
1586 if (xhci
->xhc_state
& XHCI_STATE_DYING
)
1589 xhci_dbg(xhci
, "%s called for udev %p\n", __func__
, udev
);
1590 drop_flag
= xhci_get_endpoint_flag(&ep
->desc
);
1591 if (drop_flag
== SLOT_FLAG
|| drop_flag
== EP0_FLAG
) {
1592 xhci_dbg(xhci
, "xHCI %s - can't drop slot or ep 0 %#x\n",
1593 __func__
, drop_flag
);
1597 in_ctx
= xhci
->devs
[udev
->slot_id
]->in_ctx
;
1598 out_ctx
= xhci
->devs
[udev
->slot_id
]->out_ctx
;
1599 ctrl_ctx
= xhci_get_input_control_ctx(in_ctx
);
1601 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
1606 ep_index
= xhci_get_endpoint_index(&ep
->desc
);
1607 ep_ctx
= xhci_get_ep_ctx(xhci
, out_ctx
, ep_index
);
1608 /* If the HC already knows the endpoint is disabled,
1609 * or the HCD has noted it is disabled, ignore this request
1611 if ((GET_EP_CTX_STATE(ep_ctx
) == EP_STATE_DISABLED
) ||
1612 le32_to_cpu(ctrl_ctx
->drop_flags
) &
1613 xhci_get_endpoint_flag(&ep
->desc
)) {
1614 /* Do not warn when called after a usb_device_reset */
1615 if (xhci
->devs
[udev
->slot_id
]->eps
[ep_index
].ring
!= NULL
)
1616 xhci_warn(xhci
, "xHCI %s called with disabled ep %p\n",
1621 ctrl_ctx
->drop_flags
|= cpu_to_le32(drop_flag
);
1622 new_drop_flags
= le32_to_cpu(ctrl_ctx
->drop_flags
);
1624 ctrl_ctx
->add_flags
&= cpu_to_le32(~drop_flag
);
1625 new_add_flags
= le32_to_cpu(ctrl_ctx
->add_flags
);
1627 xhci_debugfs_remove_endpoint(xhci
, xhci
->devs
[udev
->slot_id
], ep_index
);
1629 xhci_endpoint_zero(xhci
, xhci
->devs
[udev
->slot_id
], ep
);
1631 if (xhci
->quirks
& XHCI_MTK_HOST
)
1632 xhci_mtk_drop_ep_quirk(hcd
, udev
, ep
);
1634 xhci_dbg(xhci
, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1635 (unsigned int) ep
->desc
.bEndpointAddress
,
1637 (unsigned int) new_drop_flags
,
1638 (unsigned int) new_add_flags
);
1642 /* Add an endpoint to a new possible bandwidth configuration for this device.
1643 * Only one call to this function is allowed per endpoint before
1644 * check_bandwidth() or reset_bandwidth() must be called.
1645 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1646 * add the endpoint to the schedule with possibly new parameters denoted by a
1647 * different endpoint descriptor in usb_host_endpoint.
1648 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1651 * The USB core will not allow URBs to be queued to an endpoint until the
1652 * configuration or alt setting is installed in the device, so there's no need
1653 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1655 static int xhci_add_endpoint(struct usb_hcd
*hcd
, struct usb_device
*udev
,
1656 struct usb_host_endpoint
*ep
)
1658 struct xhci_hcd
*xhci
;
1659 struct xhci_container_ctx
*in_ctx
;
1660 unsigned int ep_index
;
1661 struct xhci_input_control_ctx
*ctrl_ctx
;
1663 u32 new_add_flags
, new_drop_flags
;
1664 struct xhci_virt_device
*virt_dev
;
1667 ret
= xhci_check_args(hcd
, udev
, ep
, 1, true, __func__
);
1669 /* So we won't queue a reset ep command for a root hub */
1673 xhci
= hcd_to_xhci(hcd
);
1674 if (xhci
->xhc_state
& XHCI_STATE_DYING
)
1677 added_ctxs
= xhci_get_endpoint_flag(&ep
->desc
);
1678 if (added_ctxs
== SLOT_FLAG
|| added_ctxs
== EP0_FLAG
) {
1679 /* FIXME when we have to issue an evaluate endpoint command to
1680 * deal with ep0 max packet size changing once we get the
1683 xhci_dbg(xhci
, "xHCI %s - can't add slot or ep 0 %#x\n",
1684 __func__
, added_ctxs
);
1688 virt_dev
= xhci
->devs
[udev
->slot_id
];
1689 in_ctx
= virt_dev
->in_ctx
;
1690 ctrl_ctx
= xhci_get_input_control_ctx(in_ctx
);
1692 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
1697 ep_index
= xhci_get_endpoint_index(&ep
->desc
);
1698 /* If this endpoint is already in use, and the upper layers are trying
1699 * to add it again without dropping it, reject the addition.
1701 if (virt_dev
->eps
[ep_index
].ring
&&
1702 !(le32_to_cpu(ctrl_ctx
->drop_flags
) & added_ctxs
)) {
1703 xhci_warn(xhci
, "Trying to add endpoint 0x%x "
1704 "without dropping it.\n",
1705 (unsigned int) ep
->desc
.bEndpointAddress
);
1709 /* If the HCD has already noted the endpoint is enabled,
1710 * ignore this request.
1712 if (le32_to_cpu(ctrl_ctx
->add_flags
) & added_ctxs
) {
1713 xhci_warn(xhci
, "xHCI %s called with enabled ep %p\n",
1719 * Configuration and alternate setting changes must be done in
1720 * process context, not interrupt context (or so documenation
1721 * for usb_set_interface() and usb_set_configuration() claim).
1723 if (xhci_endpoint_init(xhci
, virt_dev
, udev
, ep
, GFP_NOIO
) < 0) {
1724 dev_dbg(&udev
->dev
, "%s - could not initialize ep %#x\n",
1725 __func__
, ep
->desc
.bEndpointAddress
);
1729 if (xhci
->quirks
& XHCI_MTK_HOST
) {
1730 ret
= xhci_mtk_add_ep_quirk(hcd
, udev
, ep
);
1732 xhci_ring_free(xhci
, virt_dev
->eps
[ep_index
].new_ring
);
1733 virt_dev
->eps
[ep_index
].new_ring
= NULL
;
1738 ctrl_ctx
->add_flags
|= cpu_to_le32(added_ctxs
);
1739 new_add_flags
= le32_to_cpu(ctrl_ctx
->add_flags
);
1741 /* If xhci_endpoint_disable() was called for this endpoint, but the
1742 * xHC hasn't been notified yet through the check_bandwidth() call,
1743 * this re-adds a new state for the endpoint from the new endpoint
1744 * descriptors. We must drop and re-add this endpoint, so we leave the
1747 new_drop_flags
= le32_to_cpu(ctrl_ctx
->drop_flags
);
1749 /* Store the usb_device pointer for later use */
1752 xhci_debugfs_create_endpoint(xhci
, virt_dev
, ep_index
);
1754 xhci_dbg(xhci
, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1755 (unsigned int) ep
->desc
.bEndpointAddress
,
1757 (unsigned int) new_drop_flags
,
1758 (unsigned int) new_add_flags
);
1762 static void xhci_zero_in_ctx(struct xhci_hcd
*xhci
, struct xhci_virt_device
*virt_dev
)
1764 struct xhci_input_control_ctx
*ctrl_ctx
;
1765 struct xhci_ep_ctx
*ep_ctx
;
1766 struct xhci_slot_ctx
*slot_ctx
;
1769 ctrl_ctx
= xhci_get_input_control_ctx(virt_dev
->in_ctx
);
1771 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
1776 /* When a device's add flag and drop flag are zero, any subsequent
1777 * configure endpoint command will leave that endpoint's state
1778 * untouched. Make sure we don't leave any old state in the input
1779 * endpoint contexts.
1781 ctrl_ctx
->drop_flags
= 0;
1782 ctrl_ctx
->add_flags
= 0;
1783 slot_ctx
= xhci_get_slot_ctx(xhci
, virt_dev
->in_ctx
);
1784 slot_ctx
->dev_info
&= cpu_to_le32(~LAST_CTX_MASK
);
1785 /* Endpoint 0 is always valid */
1786 slot_ctx
->dev_info
|= cpu_to_le32(LAST_CTX(1));
1787 for (i
= 1; i
< 31; i
++) {
1788 ep_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->in_ctx
, i
);
1789 ep_ctx
->ep_info
= 0;
1790 ep_ctx
->ep_info2
= 0;
1792 ep_ctx
->tx_info
= 0;
1796 static int xhci_configure_endpoint_result(struct xhci_hcd
*xhci
,
1797 struct usb_device
*udev
, u32
*cmd_status
)
1801 switch (*cmd_status
) {
1802 case COMP_COMMAND_ABORTED
:
1803 case COMP_COMMAND_RING_STOPPED
:
1804 xhci_warn(xhci
, "Timeout while waiting for configure endpoint command\n");
1807 case COMP_RESOURCE_ERROR
:
1808 dev_warn(&udev
->dev
,
1809 "Not enough host controller resources for new device state.\n");
1811 /* FIXME: can we allocate more resources for the HC? */
1813 case COMP_BANDWIDTH_ERROR
:
1814 case COMP_SECONDARY_BANDWIDTH_ERROR
:
1815 dev_warn(&udev
->dev
,
1816 "Not enough bandwidth for new device state.\n");
1818 /* FIXME: can we go back to the old state? */
1820 case COMP_TRB_ERROR
:
1821 /* the HCD set up something wrong */
1822 dev_warn(&udev
->dev
, "ERROR: Endpoint drop flag = 0, "
1824 "and endpoint is not disabled.\n");
1827 case COMP_INCOMPATIBLE_DEVICE_ERROR
:
1828 dev_warn(&udev
->dev
,
1829 "ERROR: Incompatible device for endpoint configure command.\n");
1833 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
1834 "Successful Endpoint Configure command");
1838 xhci_err(xhci
, "ERROR: unexpected command completion code 0x%x.\n",
1846 static int xhci_evaluate_context_result(struct xhci_hcd
*xhci
,
1847 struct usb_device
*udev
, u32
*cmd_status
)
1851 switch (*cmd_status
) {
1852 case COMP_COMMAND_ABORTED
:
1853 case COMP_COMMAND_RING_STOPPED
:
1854 xhci_warn(xhci
, "Timeout while waiting for evaluate context command\n");
1857 case COMP_PARAMETER_ERROR
:
1858 dev_warn(&udev
->dev
,
1859 "WARN: xHCI driver setup invalid evaluate context command.\n");
1862 case COMP_SLOT_NOT_ENABLED_ERROR
:
1863 dev_warn(&udev
->dev
,
1864 "WARN: slot not enabled for evaluate context command.\n");
1867 case COMP_CONTEXT_STATE_ERROR
:
1868 dev_warn(&udev
->dev
,
1869 "WARN: invalid context state for evaluate context command.\n");
1872 case COMP_INCOMPATIBLE_DEVICE_ERROR
:
1873 dev_warn(&udev
->dev
,
1874 "ERROR: Incompatible device for evaluate context command.\n");
1877 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR
:
1878 /* Max Exit Latency too large error */
1879 dev_warn(&udev
->dev
, "WARN: Max Exit Latency too large\n");
1883 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
1884 "Successful evaluate context command");
1888 xhci_err(xhci
, "ERROR: unexpected command completion code 0x%x.\n",
1896 static u32
xhci_count_num_new_endpoints(struct xhci_hcd
*xhci
,
1897 struct xhci_input_control_ctx
*ctrl_ctx
)
1899 u32 valid_add_flags
;
1900 u32 valid_drop_flags
;
1902 /* Ignore the slot flag (bit 0), and the default control endpoint flag
1903 * (bit 1). The default control endpoint is added during the Address
1904 * Device command and is never removed until the slot is disabled.
1906 valid_add_flags
= le32_to_cpu(ctrl_ctx
->add_flags
) >> 2;
1907 valid_drop_flags
= le32_to_cpu(ctrl_ctx
->drop_flags
) >> 2;
1909 /* Use hweight32 to count the number of ones in the add flags, or
1910 * number of endpoints added. Don't count endpoints that are changed
1911 * (both added and dropped).
1913 return hweight32(valid_add_flags
) -
1914 hweight32(valid_add_flags
& valid_drop_flags
);
1917 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd
*xhci
,
1918 struct xhci_input_control_ctx
*ctrl_ctx
)
1920 u32 valid_add_flags
;
1921 u32 valid_drop_flags
;
1923 valid_add_flags
= le32_to_cpu(ctrl_ctx
->add_flags
) >> 2;
1924 valid_drop_flags
= le32_to_cpu(ctrl_ctx
->drop_flags
) >> 2;
1926 return hweight32(valid_drop_flags
) -
1927 hweight32(valid_add_flags
& valid_drop_flags
);
1931 * We need to reserve the new number of endpoints before the configure endpoint
1932 * command completes. We can't subtract the dropped endpoints from the number
1933 * of active endpoints until the command completes because we can oversubscribe
1934 * the host in this case:
1936 * - the first configure endpoint command drops more endpoints than it adds
1937 * - a second configure endpoint command that adds more endpoints is queued
1938 * - the first configure endpoint command fails, so the config is unchanged
1939 * - the second command may succeed, even though there isn't enough resources
1941 * Must be called with xhci->lock held.
1943 static int xhci_reserve_host_resources(struct xhci_hcd
*xhci
,
1944 struct xhci_input_control_ctx
*ctrl_ctx
)
1948 added_eps
= xhci_count_num_new_endpoints(xhci
, ctrl_ctx
);
1949 if (xhci
->num_active_eps
+ added_eps
> xhci
->limit_active_eps
) {
1950 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
1951 "Not enough ep ctxs: "
1952 "%u active, need to add %u, limit is %u.",
1953 xhci
->num_active_eps
, added_eps
,
1954 xhci
->limit_active_eps
);
1957 xhci
->num_active_eps
+= added_eps
;
1958 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
1959 "Adding %u ep ctxs, %u now active.", added_eps
,
1960 xhci
->num_active_eps
);
1965 * The configure endpoint was failed by the xHC for some other reason, so we
1966 * need to revert the resources that failed configuration would have used.
1968 * Must be called with xhci->lock held.
1970 static void xhci_free_host_resources(struct xhci_hcd
*xhci
,
1971 struct xhci_input_control_ctx
*ctrl_ctx
)
1975 num_failed_eps
= xhci_count_num_new_endpoints(xhci
, ctrl_ctx
);
1976 xhci
->num_active_eps
-= num_failed_eps
;
1977 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
1978 "Removing %u failed ep ctxs, %u now active.",
1980 xhci
->num_active_eps
);
1984 * Now that the command has completed, clean up the active endpoint count by
1985 * subtracting out the endpoints that were dropped (but not changed).
1987 * Must be called with xhci->lock held.
1989 static void xhci_finish_resource_reservation(struct xhci_hcd
*xhci
,
1990 struct xhci_input_control_ctx
*ctrl_ctx
)
1992 u32 num_dropped_eps
;
1994 num_dropped_eps
= xhci_count_num_dropped_endpoints(xhci
, ctrl_ctx
);
1995 xhci
->num_active_eps
-= num_dropped_eps
;
1996 if (num_dropped_eps
)
1997 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
1998 "Removing %u dropped ep ctxs, %u now active.",
2000 xhci
->num_active_eps
);
2003 static unsigned int xhci_get_block_size(struct usb_device
*udev
)
2005 switch (udev
->speed
) {
2007 case USB_SPEED_FULL
:
2009 case USB_SPEED_HIGH
:
2011 case USB_SPEED_SUPER
:
2012 case USB_SPEED_SUPER_PLUS
:
2014 case USB_SPEED_UNKNOWN
:
2015 case USB_SPEED_WIRELESS
:
2017 /* Should never happen */
2023 xhci_get_largest_overhead(struct xhci_interval_bw
*interval_bw
)
2025 if (interval_bw
->overhead
[LS_OVERHEAD_TYPE
])
2027 if (interval_bw
->overhead
[FS_OVERHEAD_TYPE
])
2032 /* If we are changing a LS/FS device under a HS hub,
2033 * make sure (if we are activating a new TT) that the HS bus has enough
2034 * bandwidth for this new TT.
2036 static int xhci_check_tt_bw_table(struct xhci_hcd
*xhci
,
2037 struct xhci_virt_device
*virt_dev
,
2040 struct xhci_interval_bw_table
*bw_table
;
2041 struct xhci_tt_bw_info
*tt_info
;
2043 /* Find the bandwidth table for the root port this TT is attached to. */
2044 bw_table
= &xhci
->rh_bw
[virt_dev
->real_port
- 1].bw_table
;
2045 tt_info
= virt_dev
->tt_info
;
2046 /* If this TT already had active endpoints, the bandwidth for this TT
2047 * has already been added. Removing all periodic endpoints (and thus
2048 * making the TT enactive) will only decrease the bandwidth used.
2052 if (old_active_eps
== 0 && tt_info
->active_eps
!= 0) {
2053 if (bw_table
->bw_used
+ TT_HS_OVERHEAD
> HS_BW_LIMIT
)
2057 /* Not sure why we would have no new active endpoints...
2059 * Maybe because of an Evaluate Context change for a hub update or a
2060 * control endpoint 0 max packet size change?
2061 * FIXME: skip the bandwidth calculation in that case.
2066 static int xhci_check_ss_bw(struct xhci_hcd
*xhci
,
2067 struct xhci_virt_device
*virt_dev
)
2069 unsigned int bw_reserved
;
2071 bw_reserved
= DIV_ROUND_UP(SS_BW_RESERVED
*SS_BW_LIMIT_IN
, 100);
2072 if (virt_dev
->bw_table
->ss_bw_in
> (SS_BW_LIMIT_IN
- bw_reserved
))
2075 bw_reserved
= DIV_ROUND_UP(SS_BW_RESERVED
*SS_BW_LIMIT_OUT
, 100);
2076 if (virt_dev
->bw_table
->ss_bw_out
> (SS_BW_LIMIT_OUT
- bw_reserved
))
2083 * This algorithm is a very conservative estimate of the worst-case scheduling
2084 * scenario for any one interval. The hardware dynamically schedules the
2085 * packets, so we can't tell which microframe could be the limiting factor in
2086 * the bandwidth scheduling. This only takes into account periodic endpoints.
2088 * Obviously, we can't solve an NP complete problem to find the minimum worst
2089 * case scenario. Instead, we come up with an estimate that is no less than
2090 * the worst case bandwidth used for any one microframe, but may be an
2093 * We walk the requirements for each endpoint by interval, starting with the
2094 * smallest interval, and place packets in the schedule where there is only one
2095 * possible way to schedule packets for that interval. In order to simplify
2096 * this algorithm, we record the largest max packet size for each interval, and
2097 * assume all packets will be that size.
2099 * For interval 0, we obviously must schedule all packets for each interval.
2100 * The bandwidth for interval 0 is just the amount of data to be transmitted
2101 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2102 * the number of packets).
2104 * For interval 1, we have two possible microframes to schedule those packets
2105 * in. For this algorithm, if we can schedule the same number of packets for
2106 * each possible scheduling opportunity (each microframe), we will do so. The
2107 * remaining number of packets will be saved to be transmitted in the gaps in
2108 * the next interval's scheduling sequence.
2110 * As we move those remaining packets to be scheduled with interval 2 packets,
2111 * we have to double the number of remaining packets to transmit. This is
2112 * because the intervals are actually powers of 2, and we would be transmitting
2113 * the previous interval's packets twice in this interval. We also have to be
2114 * sure that when we look at the largest max packet size for this interval, we
2115 * also look at the largest max packet size for the remaining packets and take
2116 * the greater of the two.
2118 * The algorithm continues to evenly distribute packets in each scheduling
2119 * opportunity, and push the remaining packets out, until we get to the last
2120 * interval. Then those packets and their associated overhead are just added
2121 * to the bandwidth used.
2123 static int xhci_check_bw_table(struct xhci_hcd
*xhci
,
2124 struct xhci_virt_device
*virt_dev
,
2127 unsigned int bw_reserved
;
2128 unsigned int max_bandwidth
;
2129 unsigned int bw_used
;
2130 unsigned int block_size
;
2131 struct xhci_interval_bw_table
*bw_table
;
2132 unsigned int packet_size
= 0;
2133 unsigned int overhead
= 0;
2134 unsigned int packets_transmitted
= 0;
2135 unsigned int packets_remaining
= 0;
2138 if (virt_dev
->udev
->speed
>= USB_SPEED_SUPER
)
2139 return xhci_check_ss_bw(xhci
, virt_dev
);
2141 if (virt_dev
->udev
->speed
== USB_SPEED_HIGH
) {
2142 max_bandwidth
= HS_BW_LIMIT
;
2143 /* Convert percent of bus BW reserved to blocks reserved */
2144 bw_reserved
= DIV_ROUND_UP(HS_BW_RESERVED
* max_bandwidth
, 100);
2146 max_bandwidth
= FS_BW_LIMIT
;
2147 bw_reserved
= DIV_ROUND_UP(FS_BW_RESERVED
* max_bandwidth
, 100);
2150 bw_table
= virt_dev
->bw_table
;
2151 /* We need to translate the max packet size and max ESIT payloads into
2152 * the units the hardware uses.
2154 block_size
= xhci_get_block_size(virt_dev
->udev
);
2156 /* If we are manipulating a LS/FS device under a HS hub, double check
2157 * that the HS bus has enough bandwidth if we are activing a new TT.
2159 if (virt_dev
->tt_info
) {
2160 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
2161 "Recalculating BW for rootport %u",
2162 virt_dev
->real_port
);
2163 if (xhci_check_tt_bw_table(xhci
, virt_dev
, old_active_eps
)) {
2164 xhci_warn(xhci
, "Not enough bandwidth on HS bus for "
2165 "newly activated TT.\n");
2168 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
2169 "Recalculating BW for TT slot %u port %u",
2170 virt_dev
->tt_info
->slot_id
,
2171 virt_dev
->tt_info
->ttport
);
2173 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
2174 "Recalculating BW for rootport %u",
2175 virt_dev
->real_port
);
2178 /* Add in how much bandwidth will be used for interval zero, or the
2179 * rounded max ESIT payload + number of packets * largest overhead.
2181 bw_used
= DIV_ROUND_UP(bw_table
->interval0_esit_payload
, block_size
) +
2182 bw_table
->interval_bw
[0].num_packets
*
2183 xhci_get_largest_overhead(&bw_table
->interval_bw
[0]);
2185 for (i
= 1; i
< XHCI_MAX_INTERVAL
; i
++) {
2186 unsigned int bw_added
;
2187 unsigned int largest_mps
;
2188 unsigned int interval_overhead
;
2191 * How many packets could we transmit in this interval?
2192 * If packets didn't fit in the previous interval, we will need
2193 * to transmit that many packets twice within this interval.
2195 packets_remaining
= 2 * packets_remaining
+
2196 bw_table
->interval_bw
[i
].num_packets
;
2198 /* Find the largest max packet size of this or the previous
2201 if (list_empty(&bw_table
->interval_bw
[i
].endpoints
))
2204 struct xhci_virt_ep
*virt_ep
;
2205 struct list_head
*ep_entry
;
2207 ep_entry
= bw_table
->interval_bw
[i
].endpoints
.next
;
2208 virt_ep
= list_entry(ep_entry
,
2209 struct xhci_virt_ep
, bw_endpoint_list
);
2210 /* Convert to blocks, rounding up */
2211 largest_mps
= DIV_ROUND_UP(
2212 virt_ep
->bw_info
.max_packet_size
,
2215 if (largest_mps
> packet_size
)
2216 packet_size
= largest_mps
;
2218 /* Use the larger overhead of this or the previous interval. */
2219 interval_overhead
= xhci_get_largest_overhead(
2220 &bw_table
->interval_bw
[i
]);
2221 if (interval_overhead
> overhead
)
2222 overhead
= interval_overhead
;
2224 /* How many packets can we evenly distribute across
2225 * (1 << (i + 1)) possible scheduling opportunities?
2227 packets_transmitted
= packets_remaining
>> (i
+ 1);
2229 /* Add in the bandwidth used for those scheduled packets */
2230 bw_added
= packets_transmitted
* (overhead
+ packet_size
);
2232 /* How many packets do we have remaining to transmit? */
2233 packets_remaining
= packets_remaining
% (1 << (i
+ 1));
2235 /* What largest max packet size should those packets have? */
2236 /* If we've transmitted all packets, don't carry over the
2237 * largest packet size.
2239 if (packets_remaining
== 0) {
2242 } else if (packets_transmitted
> 0) {
2243 /* Otherwise if we do have remaining packets, and we've
2244 * scheduled some packets in this interval, take the
2245 * largest max packet size from endpoints with this
2248 packet_size
= largest_mps
;
2249 overhead
= interval_overhead
;
2251 /* Otherwise carry over packet_size and overhead from the last
2252 * time we had a remainder.
2254 bw_used
+= bw_added
;
2255 if (bw_used
> max_bandwidth
) {
2256 xhci_warn(xhci
, "Not enough bandwidth. "
2257 "Proposed: %u, Max: %u\n",
2258 bw_used
, max_bandwidth
);
2263 * Ok, we know we have some packets left over after even-handedly
2264 * scheduling interval 15. We don't know which microframes they will
2265 * fit into, so we over-schedule and say they will be scheduled every
2268 if (packets_remaining
> 0)
2269 bw_used
+= overhead
+ packet_size
;
2271 if (!virt_dev
->tt_info
&& virt_dev
->udev
->speed
== USB_SPEED_HIGH
) {
2272 unsigned int port_index
= virt_dev
->real_port
- 1;
2274 /* OK, we're manipulating a HS device attached to a
2275 * root port bandwidth domain. Include the number of active TTs
2276 * in the bandwidth used.
2278 bw_used
+= TT_HS_OVERHEAD
*
2279 xhci
->rh_bw
[port_index
].num_active_tts
;
2282 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
2283 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2284 "Available: %u " "percent",
2285 bw_used
, max_bandwidth
, bw_reserved
,
2286 (max_bandwidth
- bw_used
- bw_reserved
) * 100 /
2289 bw_used
+= bw_reserved
;
2290 if (bw_used
> max_bandwidth
) {
2291 xhci_warn(xhci
, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2292 bw_used
, max_bandwidth
);
2296 bw_table
->bw_used
= bw_used
;
2300 static bool xhci_is_async_ep(unsigned int ep_type
)
2302 return (ep_type
!= ISOC_OUT_EP
&& ep_type
!= INT_OUT_EP
&&
2303 ep_type
!= ISOC_IN_EP
&&
2304 ep_type
!= INT_IN_EP
);
2307 static bool xhci_is_sync_in_ep(unsigned int ep_type
)
2309 return (ep_type
== ISOC_IN_EP
|| ep_type
== INT_IN_EP
);
2312 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info
*ep_bw
)
2314 unsigned int mps
= DIV_ROUND_UP(ep_bw
->max_packet_size
, SS_BLOCK
);
2316 if (ep_bw
->ep_interval
== 0)
2317 return SS_OVERHEAD_BURST
+
2318 (ep_bw
->mult
* ep_bw
->num_packets
*
2319 (SS_OVERHEAD
+ mps
));
2320 return DIV_ROUND_UP(ep_bw
->mult
* ep_bw
->num_packets
*
2321 (SS_OVERHEAD
+ mps
+ SS_OVERHEAD_BURST
),
2322 1 << ep_bw
->ep_interval
);
2326 static void xhci_drop_ep_from_interval_table(struct xhci_hcd
*xhci
,
2327 struct xhci_bw_info
*ep_bw
,
2328 struct xhci_interval_bw_table
*bw_table
,
2329 struct usb_device
*udev
,
2330 struct xhci_virt_ep
*virt_ep
,
2331 struct xhci_tt_bw_info
*tt_info
)
2333 struct xhci_interval_bw
*interval_bw
;
2334 int normalized_interval
;
2336 if (xhci_is_async_ep(ep_bw
->type
))
2339 if (udev
->speed
>= USB_SPEED_SUPER
) {
2340 if (xhci_is_sync_in_ep(ep_bw
->type
))
2341 xhci
->devs
[udev
->slot_id
]->bw_table
->ss_bw_in
-=
2342 xhci_get_ss_bw_consumed(ep_bw
);
2344 xhci
->devs
[udev
->slot_id
]->bw_table
->ss_bw_out
-=
2345 xhci_get_ss_bw_consumed(ep_bw
);
2349 /* SuperSpeed endpoints never get added to intervals in the table, so
2350 * this check is only valid for HS/FS/LS devices.
2352 if (list_empty(&virt_ep
->bw_endpoint_list
))
2354 /* For LS/FS devices, we need to translate the interval expressed in
2355 * microframes to frames.
2357 if (udev
->speed
== USB_SPEED_HIGH
)
2358 normalized_interval
= ep_bw
->ep_interval
;
2360 normalized_interval
= ep_bw
->ep_interval
- 3;
2362 if (normalized_interval
== 0)
2363 bw_table
->interval0_esit_payload
-= ep_bw
->max_esit_payload
;
2364 interval_bw
= &bw_table
->interval_bw
[normalized_interval
];
2365 interval_bw
->num_packets
-= ep_bw
->num_packets
;
2366 switch (udev
->speed
) {
2368 interval_bw
->overhead
[LS_OVERHEAD_TYPE
] -= 1;
2370 case USB_SPEED_FULL
:
2371 interval_bw
->overhead
[FS_OVERHEAD_TYPE
] -= 1;
2373 case USB_SPEED_HIGH
:
2374 interval_bw
->overhead
[HS_OVERHEAD_TYPE
] -= 1;
2376 case USB_SPEED_SUPER
:
2377 case USB_SPEED_SUPER_PLUS
:
2378 case USB_SPEED_UNKNOWN
:
2379 case USB_SPEED_WIRELESS
:
2380 /* Should never happen because only LS/FS/HS endpoints will get
2381 * added to the endpoint list.
2386 tt_info
->active_eps
-= 1;
2387 list_del_init(&virt_ep
->bw_endpoint_list
);
2390 static void xhci_add_ep_to_interval_table(struct xhci_hcd
*xhci
,
2391 struct xhci_bw_info
*ep_bw
,
2392 struct xhci_interval_bw_table
*bw_table
,
2393 struct usb_device
*udev
,
2394 struct xhci_virt_ep
*virt_ep
,
2395 struct xhci_tt_bw_info
*tt_info
)
2397 struct xhci_interval_bw
*interval_bw
;
2398 struct xhci_virt_ep
*smaller_ep
;
2399 int normalized_interval
;
2401 if (xhci_is_async_ep(ep_bw
->type
))
2404 if (udev
->speed
== USB_SPEED_SUPER
) {
2405 if (xhci_is_sync_in_ep(ep_bw
->type
))
2406 xhci
->devs
[udev
->slot_id
]->bw_table
->ss_bw_in
+=
2407 xhci_get_ss_bw_consumed(ep_bw
);
2409 xhci
->devs
[udev
->slot_id
]->bw_table
->ss_bw_out
+=
2410 xhci_get_ss_bw_consumed(ep_bw
);
2414 /* For LS/FS devices, we need to translate the interval expressed in
2415 * microframes to frames.
2417 if (udev
->speed
== USB_SPEED_HIGH
)
2418 normalized_interval
= ep_bw
->ep_interval
;
2420 normalized_interval
= ep_bw
->ep_interval
- 3;
2422 if (normalized_interval
== 0)
2423 bw_table
->interval0_esit_payload
+= ep_bw
->max_esit_payload
;
2424 interval_bw
= &bw_table
->interval_bw
[normalized_interval
];
2425 interval_bw
->num_packets
+= ep_bw
->num_packets
;
2426 switch (udev
->speed
) {
2428 interval_bw
->overhead
[LS_OVERHEAD_TYPE
] += 1;
2430 case USB_SPEED_FULL
:
2431 interval_bw
->overhead
[FS_OVERHEAD_TYPE
] += 1;
2433 case USB_SPEED_HIGH
:
2434 interval_bw
->overhead
[HS_OVERHEAD_TYPE
] += 1;
2436 case USB_SPEED_SUPER
:
2437 case USB_SPEED_SUPER_PLUS
:
2438 case USB_SPEED_UNKNOWN
:
2439 case USB_SPEED_WIRELESS
:
2440 /* Should never happen because only LS/FS/HS endpoints will get
2441 * added to the endpoint list.
2447 tt_info
->active_eps
+= 1;
2448 /* Insert the endpoint into the list, largest max packet size first. */
2449 list_for_each_entry(smaller_ep
, &interval_bw
->endpoints
,
2451 if (ep_bw
->max_packet_size
>=
2452 smaller_ep
->bw_info
.max_packet_size
) {
2453 /* Add the new ep before the smaller endpoint */
2454 list_add_tail(&virt_ep
->bw_endpoint_list
,
2455 &smaller_ep
->bw_endpoint_list
);
2459 /* Add the new endpoint at the end of the list. */
2460 list_add_tail(&virt_ep
->bw_endpoint_list
,
2461 &interval_bw
->endpoints
);
2464 void xhci_update_tt_active_eps(struct xhci_hcd
*xhci
,
2465 struct xhci_virt_device
*virt_dev
,
2468 struct xhci_root_port_bw_info
*rh_bw_info
;
2469 if (!virt_dev
->tt_info
)
2472 rh_bw_info
= &xhci
->rh_bw
[virt_dev
->real_port
- 1];
2473 if (old_active_eps
== 0 &&
2474 virt_dev
->tt_info
->active_eps
!= 0) {
2475 rh_bw_info
->num_active_tts
+= 1;
2476 rh_bw_info
->bw_table
.bw_used
+= TT_HS_OVERHEAD
;
2477 } else if (old_active_eps
!= 0 &&
2478 virt_dev
->tt_info
->active_eps
== 0) {
2479 rh_bw_info
->num_active_tts
-= 1;
2480 rh_bw_info
->bw_table
.bw_used
-= TT_HS_OVERHEAD
;
2484 static int xhci_reserve_bandwidth(struct xhci_hcd
*xhci
,
2485 struct xhci_virt_device
*virt_dev
,
2486 struct xhci_container_ctx
*in_ctx
)
2488 struct xhci_bw_info ep_bw_info
[31];
2490 struct xhci_input_control_ctx
*ctrl_ctx
;
2491 int old_active_eps
= 0;
2493 if (virt_dev
->tt_info
)
2494 old_active_eps
= virt_dev
->tt_info
->active_eps
;
2496 ctrl_ctx
= xhci_get_input_control_ctx(in_ctx
);
2498 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
2503 for (i
= 0; i
< 31; i
++) {
2504 if (!EP_IS_ADDED(ctrl_ctx
, i
) && !EP_IS_DROPPED(ctrl_ctx
, i
))
2507 /* Make a copy of the BW info in case we need to revert this */
2508 memcpy(&ep_bw_info
[i
], &virt_dev
->eps
[i
].bw_info
,
2509 sizeof(ep_bw_info
[i
]));
2510 /* Drop the endpoint from the interval table if the endpoint is
2511 * being dropped or changed.
2513 if (EP_IS_DROPPED(ctrl_ctx
, i
))
2514 xhci_drop_ep_from_interval_table(xhci
,
2515 &virt_dev
->eps
[i
].bw_info
,
2521 /* Overwrite the information stored in the endpoints' bw_info */
2522 xhci_update_bw_info(xhci
, virt_dev
->in_ctx
, ctrl_ctx
, virt_dev
);
2523 for (i
= 0; i
< 31; i
++) {
2524 /* Add any changed or added endpoints to the interval table */
2525 if (EP_IS_ADDED(ctrl_ctx
, i
))
2526 xhci_add_ep_to_interval_table(xhci
,
2527 &virt_dev
->eps
[i
].bw_info
,
2534 if (!xhci_check_bw_table(xhci
, virt_dev
, old_active_eps
)) {
2535 /* Ok, this fits in the bandwidth we have.
2536 * Update the number of active TTs.
2538 xhci_update_tt_active_eps(xhci
, virt_dev
, old_active_eps
);
2542 /* We don't have enough bandwidth for this, revert the stored info. */
2543 for (i
= 0; i
< 31; i
++) {
2544 if (!EP_IS_ADDED(ctrl_ctx
, i
) && !EP_IS_DROPPED(ctrl_ctx
, i
))
2547 /* Drop the new copies of any added or changed endpoints from
2548 * the interval table.
2550 if (EP_IS_ADDED(ctrl_ctx
, i
)) {
2551 xhci_drop_ep_from_interval_table(xhci
,
2552 &virt_dev
->eps
[i
].bw_info
,
2558 /* Revert the endpoint back to its old information */
2559 memcpy(&virt_dev
->eps
[i
].bw_info
, &ep_bw_info
[i
],
2560 sizeof(ep_bw_info
[i
]));
2561 /* Add any changed or dropped endpoints back into the table */
2562 if (EP_IS_DROPPED(ctrl_ctx
, i
))
2563 xhci_add_ep_to_interval_table(xhci
,
2564 &virt_dev
->eps
[i
].bw_info
,
2574 /* Issue a configure endpoint command or evaluate context command
2575 * and wait for it to finish.
2577 static int xhci_configure_endpoint(struct xhci_hcd
*xhci
,
2578 struct usb_device
*udev
,
2579 struct xhci_command
*command
,
2580 bool ctx_change
, bool must_succeed
)
2583 unsigned long flags
;
2584 struct xhci_input_control_ctx
*ctrl_ctx
;
2585 struct xhci_virt_device
*virt_dev
;
2586 struct xhci_slot_ctx
*slot_ctx
;
2591 spin_lock_irqsave(&xhci
->lock
, flags
);
2593 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
2594 spin_unlock_irqrestore(&xhci
->lock
, flags
);
2598 virt_dev
= xhci
->devs
[udev
->slot_id
];
2600 ctrl_ctx
= xhci_get_input_control_ctx(command
->in_ctx
);
2602 spin_unlock_irqrestore(&xhci
->lock
, flags
);
2603 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
2608 if ((xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
) &&
2609 xhci_reserve_host_resources(xhci
, ctrl_ctx
)) {
2610 spin_unlock_irqrestore(&xhci
->lock
, flags
);
2611 xhci_warn(xhci
, "Not enough host resources, "
2612 "active endpoint contexts = %u\n",
2613 xhci
->num_active_eps
);
2616 if ((xhci
->quirks
& XHCI_SW_BW_CHECKING
) &&
2617 xhci_reserve_bandwidth(xhci
, virt_dev
, command
->in_ctx
)) {
2618 if ((xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
))
2619 xhci_free_host_resources(xhci
, ctrl_ctx
);
2620 spin_unlock_irqrestore(&xhci
->lock
, flags
);
2621 xhci_warn(xhci
, "Not enough bandwidth\n");
2625 slot_ctx
= xhci_get_slot_ctx(xhci
, command
->in_ctx
);
2626 trace_xhci_configure_endpoint(slot_ctx
);
2629 ret
= xhci_queue_configure_endpoint(xhci
, command
,
2630 command
->in_ctx
->dma
,
2631 udev
->slot_id
, must_succeed
);
2633 ret
= xhci_queue_evaluate_context(xhci
, command
,
2634 command
->in_ctx
->dma
,
2635 udev
->slot_id
, must_succeed
);
2637 if ((xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
))
2638 xhci_free_host_resources(xhci
, ctrl_ctx
);
2639 spin_unlock_irqrestore(&xhci
->lock
, flags
);
2640 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
2641 "FIXME allocate a new ring segment");
2644 xhci_ring_cmd_db(xhci
);
2645 spin_unlock_irqrestore(&xhci
->lock
, flags
);
2647 /* Wait for the configure endpoint command to complete */
2648 wait_for_completion(command
->completion
);
2651 ret
= xhci_configure_endpoint_result(xhci
, udev
,
2654 ret
= xhci_evaluate_context_result(xhci
, udev
,
2657 if ((xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
)) {
2658 spin_lock_irqsave(&xhci
->lock
, flags
);
2659 /* If the command failed, remove the reserved resources.
2660 * Otherwise, clean up the estimate to include dropped eps.
2663 xhci_free_host_resources(xhci
, ctrl_ctx
);
2665 xhci_finish_resource_reservation(xhci
, ctrl_ctx
);
2666 spin_unlock_irqrestore(&xhci
->lock
, flags
);
2671 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd
*xhci
,
2672 struct xhci_virt_device
*vdev
, int i
)
2674 struct xhci_virt_ep
*ep
= &vdev
->eps
[i
];
2676 if (ep
->ep_state
& EP_HAS_STREAMS
) {
2677 xhci_warn(xhci
, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2678 xhci_get_endpoint_address(i
));
2679 xhci_free_stream_info(xhci
, ep
->stream_info
);
2680 ep
->stream_info
= NULL
;
2681 ep
->ep_state
&= ~EP_HAS_STREAMS
;
2685 /* Called after one or more calls to xhci_add_endpoint() or
2686 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2687 * to call xhci_reset_bandwidth().
2689 * Since we are in the middle of changing either configuration or
2690 * installing a new alt setting, the USB core won't allow URBs to be
2691 * enqueued for any endpoint on the old config or interface. Nothing
2692 * else should be touching the xhci->devs[slot_id] structure, so we
2693 * don't need to take the xhci->lock for manipulating that.
2695 static int xhci_check_bandwidth(struct usb_hcd
*hcd
, struct usb_device
*udev
)
2699 struct xhci_hcd
*xhci
;
2700 struct xhci_virt_device
*virt_dev
;
2701 struct xhci_input_control_ctx
*ctrl_ctx
;
2702 struct xhci_slot_ctx
*slot_ctx
;
2703 struct xhci_command
*command
;
2705 ret
= xhci_check_args(hcd
, udev
, NULL
, 0, true, __func__
);
2708 xhci
= hcd_to_xhci(hcd
);
2709 if ((xhci
->xhc_state
& XHCI_STATE_DYING
) ||
2710 (xhci
->xhc_state
& XHCI_STATE_REMOVING
))
2713 xhci_dbg(xhci
, "%s called for udev %p\n", __func__
, udev
);
2714 virt_dev
= xhci
->devs
[udev
->slot_id
];
2716 command
= xhci_alloc_command(xhci
, false, true, GFP_KERNEL
);
2720 command
->in_ctx
= virt_dev
->in_ctx
;
2722 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2723 ctrl_ctx
= xhci_get_input_control_ctx(command
->in_ctx
);
2725 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
2728 goto command_cleanup
;
2730 ctrl_ctx
->add_flags
|= cpu_to_le32(SLOT_FLAG
);
2731 ctrl_ctx
->add_flags
&= cpu_to_le32(~EP0_FLAG
);
2732 ctrl_ctx
->drop_flags
&= cpu_to_le32(~(SLOT_FLAG
| EP0_FLAG
));
2734 /* Don't issue the command if there's no endpoints to update. */
2735 if (ctrl_ctx
->add_flags
== cpu_to_le32(SLOT_FLAG
) &&
2736 ctrl_ctx
->drop_flags
== 0) {
2738 goto command_cleanup
;
2740 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
2741 slot_ctx
= xhci_get_slot_ctx(xhci
, virt_dev
->in_ctx
);
2742 for (i
= 31; i
>= 1; i
--) {
2743 __le32 le32
= cpu_to_le32(BIT(i
));
2745 if ((virt_dev
->eps
[i
-1].ring
&& !(ctrl_ctx
->drop_flags
& le32
))
2746 || (ctrl_ctx
->add_flags
& le32
) || i
== 1) {
2747 slot_ctx
->dev_info
&= cpu_to_le32(~LAST_CTX_MASK
);
2748 slot_ctx
->dev_info
|= cpu_to_le32(LAST_CTX(i
));
2753 ret
= xhci_configure_endpoint(xhci
, udev
, command
,
2756 /* Callee should call reset_bandwidth() */
2757 goto command_cleanup
;
2759 /* Free any rings that were dropped, but not changed. */
2760 for (i
= 1; i
< 31; i
++) {
2761 if ((le32_to_cpu(ctrl_ctx
->drop_flags
) & (1 << (i
+ 1))) &&
2762 !(le32_to_cpu(ctrl_ctx
->add_flags
) & (1 << (i
+ 1)))) {
2763 xhci_free_endpoint_ring(xhci
, virt_dev
, i
);
2764 xhci_check_bw_drop_ep_streams(xhci
, virt_dev
, i
);
2767 xhci_zero_in_ctx(xhci
, virt_dev
);
2769 * Install any rings for completely new endpoints or changed endpoints,
2770 * and free any old rings from changed endpoints.
2772 for (i
= 1; i
< 31; i
++) {
2773 if (!virt_dev
->eps
[i
].new_ring
)
2775 /* Only free the old ring if it exists.
2776 * It may not if this is the first add of an endpoint.
2778 if (virt_dev
->eps
[i
].ring
) {
2779 xhci_free_endpoint_ring(xhci
, virt_dev
, i
);
2781 xhci_check_bw_drop_ep_streams(xhci
, virt_dev
, i
);
2782 virt_dev
->eps
[i
].ring
= virt_dev
->eps
[i
].new_ring
;
2783 virt_dev
->eps
[i
].new_ring
= NULL
;
2786 kfree(command
->completion
);
2792 static void xhci_reset_bandwidth(struct usb_hcd
*hcd
, struct usb_device
*udev
)
2794 struct xhci_hcd
*xhci
;
2795 struct xhci_virt_device
*virt_dev
;
2798 ret
= xhci_check_args(hcd
, udev
, NULL
, 0, true, __func__
);
2801 xhci
= hcd_to_xhci(hcd
);
2803 xhci_dbg(xhci
, "%s called for udev %p\n", __func__
, udev
);
2804 virt_dev
= xhci
->devs
[udev
->slot_id
];
2805 /* Free any rings allocated for added endpoints */
2806 for (i
= 0; i
< 31; i
++) {
2807 if (virt_dev
->eps
[i
].new_ring
) {
2808 xhci_debugfs_remove_endpoint(xhci
, virt_dev
, i
);
2809 xhci_ring_free(xhci
, virt_dev
->eps
[i
].new_ring
);
2810 virt_dev
->eps
[i
].new_ring
= NULL
;
2813 xhci_zero_in_ctx(xhci
, virt_dev
);
2816 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd
*xhci
,
2817 struct xhci_container_ctx
*in_ctx
,
2818 struct xhci_container_ctx
*out_ctx
,
2819 struct xhci_input_control_ctx
*ctrl_ctx
,
2820 u32 add_flags
, u32 drop_flags
)
2822 ctrl_ctx
->add_flags
= cpu_to_le32(add_flags
);
2823 ctrl_ctx
->drop_flags
= cpu_to_le32(drop_flags
);
2824 xhci_slot_copy(xhci
, in_ctx
, out_ctx
);
2825 ctrl_ctx
->add_flags
|= cpu_to_le32(SLOT_FLAG
);
2828 static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd
*xhci
,
2829 unsigned int slot_id
, unsigned int ep_index
,
2830 struct xhci_dequeue_state
*deq_state
)
2832 struct xhci_input_control_ctx
*ctrl_ctx
;
2833 struct xhci_container_ctx
*in_ctx
;
2834 struct xhci_ep_ctx
*ep_ctx
;
2838 in_ctx
= xhci
->devs
[slot_id
]->in_ctx
;
2839 ctrl_ctx
= xhci_get_input_control_ctx(in_ctx
);
2841 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
2846 xhci_endpoint_copy(xhci
, xhci
->devs
[slot_id
]->in_ctx
,
2847 xhci
->devs
[slot_id
]->out_ctx
, ep_index
);
2848 ep_ctx
= xhci_get_ep_ctx(xhci
, in_ctx
, ep_index
);
2849 addr
= xhci_trb_virt_to_dma(deq_state
->new_deq_seg
,
2850 deq_state
->new_deq_ptr
);
2852 xhci_warn(xhci
, "WARN Cannot submit config ep after "
2853 "reset ep command\n");
2854 xhci_warn(xhci
, "WARN deq seg = %p, deq ptr = %p\n",
2855 deq_state
->new_deq_seg
,
2856 deq_state
->new_deq_ptr
);
2859 ep_ctx
->deq
= cpu_to_le64(addr
| deq_state
->new_cycle_state
);
2861 added_ctxs
= xhci_get_endpoint_flag_from_index(ep_index
);
2862 xhci_setup_input_ctx_for_config_ep(xhci
, xhci
->devs
[slot_id
]->in_ctx
,
2863 xhci
->devs
[slot_id
]->out_ctx
, ctrl_ctx
,
2864 added_ctxs
, added_ctxs
);
2867 void xhci_cleanup_stalled_ring(struct xhci_hcd
*xhci
, unsigned int ep_index
,
2868 unsigned int stream_id
, struct xhci_td
*td
)
2870 struct xhci_dequeue_state deq_state
;
2871 struct xhci_virt_ep
*ep
;
2872 struct usb_device
*udev
= td
->urb
->dev
;
2874 xhci_dbg_trace(xhci
, trace_xhci_dbg_reset_ep
,
2875 "Cleaning up stalled endpoint ring");
2876 ep
= &xhci
->devs
[udev
->slot_id
]->eps
[ep_index
];
2877 /* We need to move the HW's dequeue pointer past this TD,
2878 * or it will attempt to resend it on the next doorbell ring.
2880 xhci_find_new_dequeue_state(xhci
, udev
->slot_id
,
2881 ep_index
, stream_id
, td
, &deq_state
);
2883 if (!deq_state
.new_deq_ptr
|| !deq_state
.new_deq_seg
)
2886 /* HW with the reset endpoint quirk will use the saved dequeue state to
2887 * issue a configure endpoint command later.
2889 if (!(xhci
->quirks
& XHCI_RESET_EP_QUIRK
)) {
2890 xhci_dbg_trace(xhci
, trace_xhci_dbg_reset_ep
,
2891 "Queueing new dequeue state");
2892 xhci_queue_new_dequeue_state(xhci
, udev
->slot_id
,
2893 ep_index
, &deq_state
);
2895 /* Better hope no one uses the input context between now and the
2896 * reset endpoint completion!
2897 * XXX: No idea how this hardware will react when stream rings
2900 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
2901 "Setting up input context for "
2902 "configure endpoint command");
2903 xhci_setup_input_ctx_for_quirk(xhci
, udev
->slot_id
,
2904 ep_index
, &deq_state
);
2908 /* Called when clearing halted device. The core should have sent the control
2909 * message to clear the device halt condition. The host side of the halt should
2910 * already be cleared with a reset endpoint command issued when the STALL tx
2911 * event was received.
2913 * Context: in_interrupt
2916 static void xhci_endpoint_reset(struct usb_hcd
*hcd
,
2917 struct usb_host_endpoint
*ep
)
2919 struct xhci_hcd
*xhci
;
2921 xhci
= hcd_to_xhci(hcd
);
2924 * We might need to implement the config ep cmd in xhci 4.8.1 note:
2925 * The Reset Endpoint Command may only be issued to endpoints in the
2926 * Halted state. If software wishes reset the Data Toggle or Sequence
2927 * Number of an endpoint that isn't in the Halted state, then software
2928 * may issue a Configure Endpoint Command with the Drop and Add bits set
2929 * for the target endpoint. that is in the Stopped state.
2932 /* For now just print debug to follow the situation */
2933 xhci_dbg(xhci
, "Endpoint 0x%x ep reset callback called\n",
2934 ep
->desc
.bEndpointAddress
);
2937 static int xhci_check_streams_endpoint(struct xhci_hcd
*xhci
,
2938 struct usb_device
*udev
, struct usb_host_endpoint
*ep
,
2939 unsigned int slot_id
)
2942 unsigned int ep_index
;
2943 unsigned int ep_state
;
2947 ret
= xhci_check_args(xhci_to_hcd(xhci
), udev
, ep
, 1, true, __func__
);
2950 if (usb_ss_max_streams(&ep
->ss_ep_comp
) == 0) {
2951 xhci_warn(xhci
, "WARN: SuperSpeed Endpoint Companion"
2952 " descriptor for ep 0x%x does not support streams\n",
2953 ep
->desc
.bEndpointAddress
);
2957 ep_index
= xhci_get_endpoint_index(&ep
->desc
);
2958 ep_state
= xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
;
2959 if (ep_state
& EP_HAS_STREAMS
||
2960 ep_state
& EP_GETTING_STREAMS
) {
2961 xhci_warn(xhci
, "WARN: SuperSpeed bulk endpoint 0x%x "
2962 "already has streams set up.\n",
2963 ep
->desc
.bEndpointAddress
);
2964 xhci_warn(xhci
, "Send email to xHCI maintainer and ask for "
2965 "dynamic stream context array reallocation.\n");
2968 if (!list_empty(&xhci
->devs
[slot_id
]->eps
[ep_index
].ring
->td_list
)) {
2969 xhci_warn(xhci
, "Cannot setup streams for SuperSpeed bulk "
2970 "endpoint 0x%x; URBs are pending.\n",
2971 ep
->desc
.bEndpointAddress
);
2977 static void xhci_calculate_streams_entries(struct xhci_hcd
*xhci
,
2978 unsigned int *num_streams
, unsigned int *num_stream_ctxs
)
2980 unsigned int max_streams
;
2982 /* The stream context array size must be a power of two */
2983 *num_stream_ctxs
= roundup_pow_of_two(*num_streams
);
2985 * Find out how many primary stream array entries the host controller
2986 * supports. Later we may use secondary stream arrays (similar to 2nd
2987 * level page entries), but that's an optional feature for xHCI host
2988 * controllers. xHCs must support at least 4 stream IDs.
2990 max_streams
= HCC_MAX_PSA(xhci
->hcc_params
);
2991 if (*num_stream_ctxs
> max_streams
) {
2992 xhci_dbg(xhci
, "xHCI HW only supports %u stream ctx entries.\n",
2994 *num_stream_ctxs
= max_streams
;
2995 *num_streams
= max_streams
;
2999 /* Returns an error code if one of the endpoint already has streams.
3000 * This does not change any data structures, it only checks and gathers
3003 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd
*xhci
,
3004 struct usb_device
*udev
,
3005 struct usb_host_endpoint
**eps
, unsigned int num_eps
,
3006 unsigned int *num_streams
, u32
*changed_ep_bitmask
)
3008 unsigned int max_streams
;
3009 unsigned int endpoint_flag
;
3013 for (i
= 0; i
< num_eps
; i
++) {
3014 ret
= xhci_check_streams_endpoint(xhci
, udev
,
3015 eps
[i
], udev
->slot_id
);
3019 max_streams
= usb_ss_max_streams(&eps
[i
]->ss_ep_comp
);
3020 if (max_streams
< (*num_streams
- 1)) {
3021 xhci_dbg(xhci
, "Ep 0x%x only supports %u stream IDs.\n",
3022 eps
[i
]->desc
.bEndpointAddress
,
3024 *num_streams
= max_streams
+1;
3027 endpoint_flag
= xhci_get_endpoint_flag(&eps
[i
]->desc
);
3028 if (*changed_ep_bitmask
& endpoint_flag
)
3030 *changed_ep_bitmask
|= endpoint_flag
;
3035 static u32
xhci_calculate_no_streams_bitmask(struct xhci_hcd
*xhci
,
3036 struct usb_device
*udev
,
3037 struct usb_host_endpoint
**eps
, unsigned int num_eps
)
3039 u32 changed_ep_bitmask
= 0;
3040 unsigned int slot_id
;
3041 unsigned int ep_index
;
3042 unsigned int ep_state
;
3045 slot_id
= udev
->slot_id
;
3046 if (!xhci
->devs
[slot_id
])
3049 for (i
= 0; i
< num_eps
; i
++) {
3050 ep_index
= xhci_get_endpoint_index(&eps
[i
]->desc
);
3051 ep_state
= xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
;
3052 /* Are streams already being freed for the endpoint? */
3053 if (ep_state
& EP_GETTING_NO_STREAMS
) {
3054 xhci_warn(xhci
, "WARN Can't disable streams for "
3056 "streams are being disabled already\n",
3057 eps
[i
]->desc
.bEndpointAddress
);
3060 /* Are there actually any streams to free? */
3061 if (!(ep_state
& EP_HAS_STREAMS
) &&
3062 !(ep_state
& EP_GETTING_STREAMS
)) {
3063 xhci_warn(xhci
, "WARN Can't disable streams for "
3065 "streams are already disabled!\n",
3066 eps
[i
]->desc
.bEndpointAddress
);
3067 xhci_warn(xhci
, "WARN xhci_free_streams() called "
3068 "with non-streams endpoint\n");
3071 changed_ep_bitmask
|= xhci_get_endpoint_flag(&eps
[i
]->desc
);
3073 return changed_ep_bitmask
;
3077 * The USB device drivers use this function (through the HCD interface in USB
3078 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3079 * coordinate mass storage command queueing across multiple endpoints (basically
3080 * a stream ID == a task ID).
3082 * Setting up streams involves allocating the same size stream context array
3083 * for each endpoint and issuing a configure endpoint command for all endpoints.
3085 * Don't allow the call to succeed if one endpoint only supports one stream
3086 * (which means it doesn't support streams at all).
3088 * Drivers may get less stream IDs than they asked for, if the host controller
3089 * hardware or endpoints claim they can't support the number of requested
3092 static int xhci_alloc_streams(struct usb_hcd
*hcd
, struct usb_device
*udev
,
3093 struct usb_host_endpoint
**eps
, unsigned int num_eps
,
3094 unsigned int num_streams
, gfp_t mem_flags
)
3097 struct xhci_hcd
*xhci
;
3098 struct xhci_virt_device
*vdev
;
3099 struct xhci_command
*config_cmd
;
3100 struct xhci_input_control_ctx
*ctrl_ctx
;
3101 unsigned int ep_index
;
3102 unsigned int num_stream_ctxs
;
3103 unsigned int max_packet
;
3104 unsigned long flags
;
3105 u32 changed_ep_bitmask
= 0;
3110 /* Add one to the number of streams requested to account for
3111 * stream 0 that is reserved for xHCI usage.
3114 xhci
= hcd_to_xhci(hcd
);
3115 xhci_dbg(xhci
, "Driver wants %u stream IDs (including stream 0).\n",
3118 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3119 if ((xhci
->quirks
& XHCI_BROKEN_STREAMS
) ||
3120 HCC_MAX_PSA(xhci
->hcc_params
) < 4) {
3121 xhci_dbg(xhci
, "xHCI controller does not support streams.\n");
3125 config_cmd
= xhci_alloc_command(xhci
, true, true, mem_flags
);
3129 ctrl_ctx
= xhci_get_input_control_ctx(config_cmd
->in_ctx
);
3131 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
3133 xhci_free_command(xhci
, config_cmd
);
3137 /* Check to make sure all endpoints are not already configured for
3138 * streams. While we're at it, find the maximum number of streams that
3139 * all the endpoints will support and check for duplicate endpoints.
3141 spin_lock_irqsave(&xhci
->lock
, flags
);
3142 ret
= xhci_calculate_streams_and_bitmask(xhci
, udev
, eps
,
3143 num_eps
, &num_streams
, &changed_ep_bitmask
);
3145 xhci_free_command(xhci
, config_cmd
);
3146 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3149 if (num_streams
<= 1) {
3150 xhci_warn(xhci
, "WARN: endpoints can't handle "
3151 "more than one stream.\n");
3152 xhci_free_command(xhci
, config_cmd
);
3153 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3156 vdev
= xhci
->devs
[udev
->slot_id
];
3157 /* Mark each endpoint as being in transition, so
3158 * xhci_urb_enqueue() will reject all URBs.
3160 for (i
= 0; i
< num_eps
; i
++) {
3161 ep_index
= xhci_get_endpoint_index(&eps
[i
]->desc
);
3162 vdev
->eps
[ep_index
].ep_state
|= EP_GETTING_STREAMS
;
3164 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3166 /* Setup internal data structures and allocate HW data structures for
3167 * streams (but don't install the HW structures in the input context
3168 * until we're sure all memory allocation succeeded).
3170 xhci_calculate_streams_entries(xhci
, &num_streams
, &num_stream_ctxs
);
3171 xhci_dbg(xhci
, "Need %u stream ctx entries for %u stream IDs.\n",
3172 num_stream_ctxs
, num_streams
);
3174 for (i
= 0; i
< num_eps
; i
++) {
3175 ep_index
= xhci_get_endpoint_index(&eps
[i
]->desc
);
3176 max_packet
= usb_endpoint_maxp(&eps
[i
]->desc
);
3177 vdev
->eps
[ep_index
].stream_info
= xhci_alloc_stream_info(xhci
,
3180 max_packet
, mem_flags
);
3181 if (!vdev
->eps
[ep_index
].stream_info
)
3183 /* Set maxPstreams in endpoint context and update deq ptr to
3184 * point to stream context array. FIXME
3188 /* Set up the input context for a configure endpoint command. */
3189 for (i
= 0; i
< num_eps
; i
++) {
3190 struct xhci_ep_ctx
*ep_ctx
;
3192 ep_index
= xhci_get_endpoint_index(&eps
[i
]->desc
);
3193 ep_ctx
= xhci_get_ep_ctx(xhci
, config_cmd
->in_ctx
, ep_index
);
3195 xhci_endpoint_copy(xhci
, config_cmd
->in_ctx
,
3196 vdev
->out_ctx
, ep_index
);
3197 xhci_setup_streams_ep_input_ctx(xhci
, ep_ctx
,
3198 vdev
->eps
[ep_index
].stream_info
);
3200 /* Tell the HW to drop its old copy of the endpoint context info
3201 * and add the updated copy from the input context.
3203 xhci_setup_input_ctx_for_config_ep(xhci
, config_cmd
->in_ctx
,
3204 vdev
->out_ctx
, ctrl_ctx
,
3205 changed_ep_bitmask
, changed_ep_bitmask
);
3207 /* Issue and wait for the configure endpoint command */
3208 ret
= xhci_configure_endpoint(xhci
, udev
, config_cmd
,
3211 /* xHC rejected the configure endpoint command for some reason, so we
3212 * leave the old ring intact and free our internal streams data
3218 spin_lock_irqsave(&xhci
->lock
, flags
);
3219 for (i
= 0; i
< num_eps
; i
++) {
3220 ep_index
= xhci_get_endpoint_index(&eps
[i
]->desc
);
3221 vdev
->eps
[ep_index
].ep_state
&= ~EP_GETTING_STREAMS
;
3222 xhci_dbg(xhci
, "Slot %u ep ctx %u now has streams.\n",
3223 udev
->slot_id
, ep_index
);
3224 vdev
->eps
[ep_index
].ep_state
|= EP_HAS_STREAMS
;
3226 xhci_free_command(xhci
, config_cmd
);
3227 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3229 /* Subtract 1 for stream 0, which drivers can't use */
3230 return num_streams
- 1;
3233 /* If it didn't work, free the streams! */
3234 for (i
= 0; i
< num_eps
; i
++) {
3235 ep_index
= xhci_get_endpoint_index(&eps
[i
]->desc
);
3236 xhci_free_stream_info(xhci
, vdev
->eps
[ep_index
].stream_info
);
3237 vdev
->eps
[ep_index
].stream_info
= NULL
;
3238 /* FIXME Unset maxPstreams in endpoint context and
3239 * update deq ptr to point to normal string ring.
3241 vdev
->eps
[ep_index
].ep_state
&= ~EP_GETTING_STREAMS
;
3242 vdev
->eps
[ep_index
].ep_state
&= ~EP_HAS_STREAMS
;
3243 xhci_endpoint_zero(xhci
, vdev
, eps
[i
]);
3245 xhci_free_command(xhci
, config_cmd
);
3249 /* Transition the endpoint from using streams to being a "normal" endpoint
3252 * Modify the endpoint context state, submit a configure endpoint command,
3253 * and free all endpoint rings for streams if that completes successfully.
3255 static int xhci_free_streams(struct usb_hcd
*hcd
, struct usb_device
*udev
,
3256 struct usb_host_endpoint
**eps
, unsigned int num_eps
,
3260 struct xhci_hcd
*xhci
;
3261 struct xhci_virt_device
*vdev
;
3262 struct xhci_command
*command
;
3263 struct xhci_input_control_ctx
*ctrl_ctx
;
3264 unsigned int ep_index
;
3265 unsigned long flags
;
3266 u32 changed_ep_bitmask
;
3268 xhci
= hcd_to_xhci(hcd
);
3269 vdev
= xhci
->devs
[udev
->slot_id
];
3271 /* Set up a configure endpoint command to remove the streams rings */
3272 spin_lock_irqsave(&xhci
->lock
, flags
);
3273 changed_ep_bitmask
= xhci_calculate_no_streams_bitmask(xhci
,
3274 udev
, eps
, num_eps
);
3275 if (changed_ep_bitmask
== 0) {
3276 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3280 /* Use the xhci_command structure from the first endpoint. We may have
3281 * allocated too many, but the driver may call xhci_free_streams() for
3282 * each endpoint it grouped into one call to xhci_alloc_streams().
3284 ep_index
= xhci_get_endpoint_index(&eps
[0]->desc
);
3285 command
= vdev
->eps
[ep_index
].stream_info
->free_streams_command
;
3286 ctrl_ctx
= xhci_get_input_control_ctx(command
->in_ctx
);
3288 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3289 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
3294 for (i
= 0; i
< num_eps
; i
++) {
3295 struct xhci_ep_ctx
*ep_ctx
;
3297 ep_index
= xhci_get_endpoint_index(&eps
[i
]->desc
);
3298 ep_ctx
= xhci_get_ep_ctx(xhci
, command
->in_ctx
, ep_index
);
3299 xhci
->devs
[udev
->slot_id
]->eps
[ep_index
].ep_state
|=
3300 EP_GETTING_NO_STREAMS
;
3302 xhci_endpoint_copy(xhci
, command
->in_ctx
,
3303 vdev
->out_ctx
, ep_index
);
3304 xhci_setup_no_streams_ep_input_ctx(ep_ctx
,
3305 &vdev
->eps
[ep_index
]);
3307 xhci_setup_input_ctx_for_config_ep(xhci
, command
->in_ctx
,
3308 vdev
->out_ctx
, ctrl_ctx
,
3309 changed_ep_bitmask
, changed_ep_bitmask
);
3310 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3312 /* Issue and wait for the configure endpoint command,
3313 * which must succeed.
3315 ret
= xhci_configure_endpoint(xhci
, udev
, command
,
3318 /* xHC rejected the configure endpoint command for some reason, so we
3319 * leave the streams rings intact.
3324 spin_lock_irqsave(&xhci
->lock
, flags
);
3325 for (i
= 0; i
< num_eps
; i
++) {
3326 ep_index
= xhci_get_endpoint_index(&eps
[i
]->desc
);
3327 xhci_free_stream_info(xhci
, vdev
->eps
[ep_index
].stream_info
);
3328 vdev
->eps
[ep_index
].stream_info
= NULL
;
3329 /* FIXME Unset maxPstreams in endpoint context and
3330 * update deq ptr to point to normal string ring.
3332 vdev
->eps
[ep_index
].ep_state
&= ~EP_GETTING_NO_STREAMS
;
3333 vdev
->eps
[ep_index
].ep_state
&= ~EP_HAS_STREAMS
;
3335 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3341 * Deletes endpoint resources for endpoints that were active before a Reset
3342 * Device command, or a Disable Slot command. The Reset Device command leaves
3343 * the control endpoint intact, whereas the Disable Slot command deletes it.
3345 * Must be called with xhci->lock held.
3347 void xhci_free_device_endpoint_resources(struct xhci_hcd
*xhci
,
3348 struct xhci_virt_device
*virt_dev
, bool drop_control_ep
)
3351 unsigned int num_dropped_eps
= 0;
3352 unsigned int drop_flags
= 0;
3354 for (i
= (drop_control_ep
? 0 : 1); i
< 31; i
++) {
3355 if (virt_dev
->eps
[i
].ring
) {
3356 drop_flags
|= 1 << i
;
3360 xhci
->num_active_eps
-= num_dropped_eps
;
3361 if (num_dropped_eps
)
3362 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
3363 "Dropped %u ep ctxs, flags = 0x%x, "
3365 num_dropped_eps
, drop_flags
,
3366 xhci
->num_active_eps
);
3370 * This submits a Reset Device Command, which will set the device state to 0,
3371 * set the device address to 0, and disable all the endpoints except the default
3372 * control endpoint. The USB core should come back and call
3373 * xhci_address_device(), and then re-set up the configuration. If this is
3374 * called because of a usb_reset_and_verify_device(), then the old alternate
3375 * settings will be re-installed through the normal bandwidth allocation
3378 * Wait for the Reset Device command to finish. Remove all structures
3379 * associated with the endpoints that were disabled. Clear the input device
3380 * structure? Reset the control endpoint 0 max packet size?
3382 * If the virt_dev to be reset does not exist or does not match the udev,
3383 * it means the device is lost, possibly due to the xHC restore error and
3384 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3385 * re-allocate the device.
3387 static int xhci_discover_or_reset_device(struct usb_hcd
*hcd
,
3388 struct usb_device
*udev
)
3391 unsigned long flags
;
3392 struct xhci_hcd
*xhci
;
3393 unsigned int slot_id
;
3394 struct xhci_virt_device
*virt_dev
;
3395 struct xhci_command
*reset_device_cmd
;
3396 int last_freed_endpoint
;
3397 struct xhci_slot_ctx
*slot_ctx
;
3398 int old_active_eps
= 0;
3400 ret
= xhci_check_args(hcd
, udev
, NULL
, 0, false, __func__
);
3403 xhci
= hcd_to_xhci(hcd
);
3404 slot_id
= udev
->slot_id
;
3405 virt_dev
= xhci
->devs
[slot_id
];
3407 xhci_dbg(xhci
, "The device to be reset with slot ID %u does "
3408 "not exist. Re-allocate the device\n", slot_id
);
3409 ret
= xhci_alloc_dev(hcd
, udev
);
3416 if (virt_dev
->tt_info
)
3417 old_active_eps
= virt_dev
->tt_info
->active_eps
;
3419 if (virt_dev
->udev
!= udev
) {
3420 /* If the virt_dev and the udev does not match, this virt_dev
3421 * may belong to another udev.
3422 * Re-allocate the device.
3424 xhci_dbg(xhci
, "The device to be reset with slot ID %u does "
3425 "not match the udev. Re-allocate the device\n",
3427 ret
= xhci_alloc_dev(hcd
, udev
);
3434 /* If device is not setup, there is no point in resetting it */
3435 slot_ctx
= xhci_get_slot_ctx(xhci
, virt_dev
->out_ctx
);
3436 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx
->dev_state
)) ==
3437 SLOT_STATE_DISABLED
)
3440 trace_xhci_discover_or_reset_device(slot_ctx
);
3442 xhci_dbg(xhci
, "Resetting device with slot ID %u\n", slot_id
);
3443 /* Allocate the command structure that holds the struct completion.
3444 * Assume we're in process context, since the normal device reset
3445 * process has to wait for the device anyway. Storage devices are
3446 * reset as part of error handling, so use GFP_NOIO instead of
3449 reset_device_cmd
= xhci_alloc_command(xhci
, false, true, GFP_NOIO
);
3450 if (!reset_device_cmd
) {
3451 xhci_dbg(xhci
, "Couldn't allocate command structure.\n");
3455 /* Attempt to submit the Reset Device command to the command ring */
3456 spin_lock_irqsave(&xhci
->lock
, flags
);
3458 ret
= xhci_queue_reset_device(xhci
, reset_device_cmd
, slot_id
);
3460 xhci_dbg(xhci
, "FIXME: allocate a command ring segment\n");
3461 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3462 goto command_cleanup
;
3464 xhci_ring_cmd_db(xhci
);
3465 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3467 /* Wait for the Reset Device command to finish */
3468 wait_for_completion(reset_device_cmd
->completion
);
3470 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3471 * unless we tried to reset a slot ID that wasn't enabled,
3472 * or the device wasn't in the addressed or configured state.
3474 ret
= reset_device_cmd
->status
;
3476 case COMP_COMMAND_ABORTED
:
3477 case COMP_COMMAND_RING_STOPPED
:
3478 xhci_warn(xhci
, "Timeout waiting for reset device command\n");
3480 goto command_cleanup
;
3481 case COMP_SLOT_NOT_ENABLED_ERROR
: /* 0.95 completion for bad slot ID */
3482 case COMP_CONTEXT_STATE_ERROR
: /* 0.96 completion code for same thing */
3483 xhci_dbg(xhci
, "Can't reset device (slot ID %u) in %s state\n",
3485 xhci_get_slot_state(xhci
, virt_dev
->out_ctx
));
3486 xhci_dbg(xhci
, "Not freeing device rings.\n");
3487 /* Don't treat this as an error. May change my mind later. */
3489 goto command_cleanup
;
3491 xhci_dbg(xhci
, "Successful reset device command.\n");
3494 if (xhci_is_vendor_info_code(xhci
, ret
))
3496 xhci_warn(xhci
, "Unknown completion code %u for "
3497 "reset device command.\n", ret
);
3499 goto command_cleanup
;
3502 /* Free up host controller endpoint resources */
3503 if ((xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
)) {
3504 spin_lock_irqsave(&xhci
->lock
, flags
);
3505 /* Don't delete the default control endpoint resources */
3506 xhci_free_device_endpoint_resources(xhci
, virt_dev
, false);
3507 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3510 /* Everything but endpoint 0 is disabled, so free the rings. */
3511 last_freed_endpoint
= 1;
3512 for (i
= 1; i
< 31; i
++) {
3513 struct xhci_virt_ep
*ep
= &virt_dev
->eps
[i
];
3515 if (ep
->ep_state
& EP_HAS_STREAMS
) {
3516 xhci_warn(xhci
, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3517 xhci_get_endpoint_address(i
));
3518 xhci_free_stream_info(xhci
, ep
->stream_info
);
3519 ep
->stream_info
= NULL
;
3520 ep
->ep_state
&= ~EP_HAS_STREAMS
;
3524 xhci_debugfs_remove_endpoint(xhci
, virt_dev
, i
);
3525 xhci_free_endpoint_ring(xhci
, virt_dev
, i
);
3526 last_freed_endpoint
= i
;
3528 if (!list_empty(&virt_dev
->eps
[i
].bw_endpoint_list
))
3529 xhci_drop_ep_from_interval_table(xhci
,
3530 &virt_dev
->eps
[i
].bw_info
,
3535 xhci_clear_endpoint_bw_info(&virt_dev
->eps
[i
].bw_info
);
3537 /* If necessary, update the number of active TTs on this root port */
3538 xhci_update_tt_active_eps(xhci
, virt_dev
, old_active_eps
);
3542 xhci_free_command(xhci
, reset_device_cmd
);
3547 * At this point, the struct usb_device is about to go away, the device has
3548 * disconnected, and all traffic has been stopped and the endpoints have been
3549 * disabled. Free any HC data structures associated with that device.
3551 static void xhci_free_dev(struct usb_hcd
*hcd
, struct usb_device
*udev
)
3553 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
3554 struct xhci_virt_device
*virt_dev
;
3555 struct xhci_slot_ctx
*slot_ctx
;
3558 #ifndef CONFIG_USB_DEFAULT_PERSIST
3560 * We called pm_runtime_get_noresume when the device was attached.
3561 * Decrement the counter here to allow controller to runtime suspend
3562 * if no devices remain.
3564 if (xhci
->quirks
& XHCI_RESET_ON_RESUME
)
3565 pm_runtime_put_noidle(hcd
->self
.controller
);
3568 ret
= xhci_check_args(hcd
, udev
, NULL
, 0, true, __func__
);
3569 /* If the host is halted due to driver unload, we still need to free the
3572 if (ret
<= 0 && ret
!= -ENODEV
)
3575 virt_dev
= xhci
->devs
[udev
->slot_id
];
3576 slot_ctx
= xhci_get_slot_ctx(xhci
, virt_dev
->out_ctx
);
3577 trace_xhci_free_dev(slot_ctx
);
3579 /* Stop any wayward timer functions (which may grab the lock) */
3580 for (i
= 0; i
< 31; i
++) {
3581 virt_dev
->eps
[i
].ep_state
&= ~EP_STOP_CMD_PENDING
;
3582 del_timer_sync(&virt_dev
->eps
[i
].stop_cmd_timer
);
3584 xhci_debugfs_remove_slot(xhci
, udev
->slot_id
);
3585 virt_dev
->udev
= NULL
;
3586 ret
= xhci_disable_slot(xhci
, udev
->slot_id
);
3588 xhci_free_virt_device(xhci
, udev
->slot_id
);
3591 int xhci_disable_slot(struct xhci_hcd
*xhci
, u32 slot_id
)
3593 struct xhci_command
*command
;
3594 unsigned long flags
;
3598 command
= xhci_alloc_command(xhci
, false, false, GFP_KERNEL
);
3602 spin_lock_irqsave(&xhci
->lock
, flags
);
3603 /* Don't disable the slot if the host controller is dead. */
3604 state
= readl(&xhci
->op_regs
->status
);
3605 if (state
== 0xffffffff || (xhci
->xhc_state
& XHCI_STATE_DYING
) ||
3606 (xhci
->xhc_state
& XHCI_STATE_HALTED
)) {
3607 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3612 ret
= xhci_queue_slot_control(xhci
, command
, TRB_DISABLE_SLOT
,
3615 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3619 xhci_ring_cmd_db(xhci
);
3620 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3625 * Checks if we have enough host controller resources for the default control
3628 * Must be called with xhci->lock held.
3630 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd
*xhci
)
3632 if (xhci
->num_active_eps
+ 1 > xhci
->limit_active_eps
) {
3633 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
3634 "Not enough ep ctxs: "
3635 "%u active, need to add 1, limit is %u.",
3636 xhci
->num_active_eps
, xhci
->limit_active_eps
);
3639 xhci
->num_active_eps
+= 1;
3640 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
3641 "Adding 1 ep ctx, %u now active.",
3642 xhci
->num_active_eps
);
3648 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3649 * timed out, or allocating memory failed. Returns 1 on success.
3651 int xhci_alloc_dev(struct usb_hcd
*hcd
, struct usb_device
*udev
)
3653 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
3654 struct xhci_virt_device
*vdev
;
3655 struct xhci_slot_ctx
*slot_ctx
;
3656 unsigned long flags
;
3658 struct xhci_command
*command
;
3660 command
= xhci_alloc_command(xhci
, false, true, GFP_KERNEL
);
3664 spin_lock_irqsave(&xhci
->lock
, flags
);
3665 ret
= xhci_queue_slot_control(xhci
, command
, TRB_ENABLE_SLOT
, 0);
3667 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3668 xhci_dbg(xhci
, "FIXME: allocate a command ring segment\n");
3669 xhci_free_command(xhci
, command
);
3672 xhci_ring_cmd_db(xhci
);
3673 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3675 wait_for_completion(command
->completion
);
3676 slot_id
= command
->slot_id
;
3678 if (!slot_id
|| command
->status
!= COMP_SUCCESS
) {
3679 xhci_err(xhci
, "Error while assigning device slot ID\n");
3680 xhci_err(xhci
, "Max number of devices this xHCI host supports is %u.\n",
3682 readl(&xhci
->cap_regs
->hcs_params1
)));
3683 xhci_free_command(xhci
, command
);
3687 xhci_free_command(xhci
, command
);
3689 if ((xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
)) {
3690 spin_lock_irqsave(&xhci
->lock
, flags
);
3691 ret
= xhci_reserve_host_control_ep_resources(xhci
);
3693 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3694 xhci_warn(xhci
, "Not enough host resources, "
3695 "active endpoint contexts = %u\n",
3696 xhci
->num_active_eps
);
3699 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3701 /* Use GFP_NOIO, since this function can be called from
3702 * xhci_discover_or_reset_device(), which may be called as part of
3703 * mass storage driver error handling.
3705 if (!xhci_alloc_virt_device(xhci
, slot_id
, udev
, GFP_NOIO
)) {
3706 xhci_warn(xhci
, "Could not allocate xHCI USB device data structures\n");
3709 vdev
= xhci
->devs
[slot_id
];
3710 slot_ctx
= xhci_get_slot_ctx(xhci
, vdev
->out_ctx
);
3711 trace_xhci_alloc_dev(slot_ctx
);
3713 udev
->slot_id
= slot_id
;
3715 xhci_debugfs_create_slot(xhci
, slot_id
);
3717 #ifndef CONFIG_USB_DEFAULT_PERSIST
3719 * If resetting upon resume, we can't put the controller into runtime
3720 * suspend if there is a device attached.
3722 if (xhci
->quirks
& XHCI_RESET_ON_RESUME
)
3723 pm_runtime_get_noresume(hcd
->self
.controller
);
3726 /* Is this a LS or FS device under a HS hub? */
3727 /* Hub or peripherial? */
3731 ret
= xhci_disable_slot(xhci
, udev
->slot_id
);
3733 xhci_free_virt_device(xhci
, udev
->slot_id
);
3739 * Issue an Address Device command and optionally send a corresponding
3740 * SetAddress request to the device.
3742 static int xhci_setup_device(struct usb_hcd
*hcd
, struct usb_device
*udev
,
3743 enum xhci_setup_dev setup
)
3745 const char *act
= setup
== SETUP_CONTEXT_ONLY
? "context" : "address";
3746 unsigned long flags
;
3747 struct xhci_virt_device
*virt_dev
;
3749 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
3750 struct xhci_slot_ctx
*slot_ctx
;
3751 struct xhci_input_control_ctx
*ctrl_ctx
;
3753 struct xhci_command
*command
= NULL
;
3755 mutex_lock(&xhci
->mutex
);
3757 if (xhci
->xhc_state
) { /* dying, removing or halted */
3762 if (!udev
->slot_id
) {
3763 xhci_dbg_trace(xhci
, trace_xhci_dbg_address
,
3764 "Bad Slot ID %d", udev
->slot_id
);
3769 virt_dev
= xhci
->devs
[udev
->slot_id
];
3771 if (WARN_ON(!virt_dev
)) {
3773 * In plug/unplug torture test with an NEC controller,
3774 * a zero-dereference was observed once due to virt_dev = 0.
3775 * Print useful debug rather than crash if it is observed again!
3777 xhci_warn(xhci
, "Virt dev invalid for slot_id 0x%x!\n",
3782 slot_ctx
= xhci_get_slot_ctx(xhci
, virt_dev
->out_ctx
);
3783 trace_xhci_setup_device_slot(slot_ctx
);
3785 if (setup
== SETUP_CONTEXT_ONLY
) {
3786 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx
->dev_state
)) ==
3787 SLOT_STATE_DEFAULT
) {
3788 xhci_dbg(xhci
, "Slot already in default state\n");
3793 command
= xhci_alloc_command(xhci
, false, true, GFP_KERNEL
);
3799 command
->in_ctx
= virt_dev
->in_ctx
;
3801 slot_ctx
= xhci_get_slot_ctx(xhci
, virt_dev
->in_ctx
);
3802 ctrl_ctx
= xhci_get_input_control_ctx(virt_dev
->in_ctx
);
3804 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
3810 * If this is the first Set Address since device plug-in or
3811 * virt_device realloaction after a resume with an xHCI power loss,
3812 * then set up the slot context.
3814 if (!slot_ctx
->dev_info
)
3815 xhci_setup_addressable_virt_dev(xhci
, udev
);
3816 /* Otherwise, update the control endpoint ring enqueue pointer. */
3818 xhci_copy_ep0_dequeue_into_input_ctx(xhci
, udev
);
3819 ctrl_ctx
->add_flags
= cpu_to_le32(SLOT_FLAG
| EP0_FLAG
);
3820 ctrl_ctx
->drop_flags
= 0;
3822 trace_xhci_address_ctx(xhci
, virt_dev
->in_ctx
,
3823 le32_to_cpu(slot_ctx
->dev_info
) >> 27);
3825 spin_lock_irqsave(&xhci
->lock
, flags
);
3826 trace_xhci_setup_device(virt_dev
);
3827 ret
= xhci_queue_address_device(xhci
, command
, virt_dev
->in_ctx
->dma
,
3828 udev
->slot_id
, setup
);
3830 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3831 xhci_dbg_trace(xhci
, trace_xhci_dbg_address
,
3832 "FIXME: allocate a command ring segment");
3835 xhci_ring_cmd_db(xhci
);
3836 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3838 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
3839 wait_for_completion(command
->completion
);
3841 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
3842 * the SetAddress() "recovery interval" required by USB and aborting the
3843 * command on a timeout.
3845 switch (command
->status
) {
3846 case COMP_COMMAND_ABORTED
:
3847 case COMP_COMMAND_RING_STOPPED
:
3848 xhci_warn(xhci
, "Timeout while waiting for setup device command\n");
3851 case COMP_CONTEXT_STATE_ERROR
:
3852 case COMP_SLOT_NOT_ENABLED_ERROR
:
3853 xhci_err(xhci
, "Setup ERROR: setup %s command for slot %d.\n",
3854 act
, udev
->slot_id
);
3857 case COMP_USB_TRANSACTION_ERROR
:
3858 dev_warn(&udev
->dev
, "Device not responding to setup %s.\n", act
);
3860 mutex_unlock(&xhci
->mutex
);
3861 ret
= xhci_disable_slot(xhci
, udev
->slot_id
);
3863 xhci_alloc_dev(hcd
, udev
);
3864 kfree(command
->completion
);
3867 case COMP_INCOMPATIBLE_DEVICE_ERROR
:
3868 dev_warn(&udev
->dev
,
3869 "ERROR: Incompatible device for setup %s command\n", act
);
3873 xhci_dbg_trace(xhci
, trace_xhci_dbg_address
,
3874 "Successful setup %s command", act
);
3878 "ERROR: unexpected setup %s command completion code 0x%x.\n",
3879 act
, command
->status
);
3880 trace_xhci_address_ctx(xhci
, virt_dev
->out_ctx
, 1);
3886 temp_64
= xhci_read_64(xhci
, &xhci
->op_regs
->dcbaa_ptr
);
3887 xhci_dbg_trace(xhci
, trace_xhci_dbg_address
,
3888 "Op regs DCBAA ptr = %#016llx", temp_64
);
3889 xhci_dbg_trace(xhci
, trace_xhci_dbg_address
,
3890 "Slot ID %d dcbaa entry @%p = %#016llx",
3892 &xhci
->dcbaa
->dev_context_ptrs
[udev
->slot_id
],
3893 (unsigned long long)
3894 le64_to_cpu(xhci
->dcbaa
->dev_context_ptrs
[udev
->slot_id
]));
3895 xhci_dbg_trace(xhci
, trace_xhci_dbg_address
,
3896 "Output Context DMA address = %#08llx",
3897 (unsigned long long)virt_dev
->out_ctx
->dma
);
3898 trace_xhci_address_ctx(xhci
, virt_dev
->in_ctx
,
3899 le32_to_cpu(slot_ctx
->dev_info
) >> 27);
3901 * USB core uses address 1 for the roothubs, so we add one to the
3902 * address given back to us by the HC.
3904 trace_xhci_address_ctx(xhci
, virt_dev
->out_ctx
,
3905 le32_to_cpu(slot_ctx
->dev_info
) >> 27);
3906 /* Zero the input context control for later use */
3907 ctrl_ctx
->add_flags
= 0;
3908 ctrl_ctx
->drop_flags
= 0;
3910 xhci_dbg_trace(xhci
, trace_xhci_dbg_address
,
3911 "Internal device address = %d",
3912 le32_to_cpu(slot_ctx
->dev_state
) & DEV_ADDR_MASK
);
3914 mutex_unlock(&xhci
->mutex
);
3916 kfree(command
->completion
);
3922 static int xhci_address_device(struct usb_hcd
*hcd
, struct usb_device
*udev
)
3924 return xhci_setup_device(hcd
, udev
, SETUP_CONTEXT_ADDRESS
);
3927 static int xhci_enable_device(struct usb_hcd
*hcd
, struct usb_device
*udev
)
3929 return xhci_setup_device(hcd
, udev
, SETUP_CONTEXT_ONLY
);
3933 * Transfer the port index into real index in the HW port status
3934 * registers. Caculate offset between the port's PORTSC register
3935 * and port status base. Divide the number of per port register
3936 * to get the real index. The raw port number bases 1.
3938 int xhci_find_raw_port_number(struct usb_hcd
*hcd
, int port1
)
3940 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
3941 __le32 __iomem
*base_addr
= &xhci
->op_regs
->port_status_base
;
3942 __le32 __iomem
*addr
;
3945 if (hcd
->speed
< HCD_USB3
)
3946 addr
= xhci
->usb2_ports
[port1
- 1];
3948 addr
= xhci
->usb3_ports
[port1
- 1];
3950 raw_port
= (addr
- base_addr
)/NUM_PORT_REGS
+ 1;
3955 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
3956 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
3958 static int __maybe_unused
xhci_change_max_exit_latency(struct xhci_hcd
*xhci
,
3959 struct usb_device
*udev
, u16 max_exit_latency
)
3961 struct xhci_virt_device
*virt_dev
;
3962 struct xhci_command
*command
;
3963 struct xhci_input_control_ctx
*ctrl_ctx
;
3964 struct xhci_slot_ctx
*slot_ctx
;
3965 unsigned long flags
;
3968 spin_lock_irqsave(&xhci
->lock
, flags
);
3970 virt_dev
= xhci
->devs
[udev
->slot_id
];
3973 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
3974 * xHC was re-initialized. Exit latency will be set later after
3975 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
3978 if (!virt_dev
|| max_exit_latency
== virt_dev
->current_mel
) {
3979 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3983 /* Attempt to issue an Evaluate Context command to change the MEL. */
3984 command
= xhci
->lpm_command
;
3985 ctrl_ctx
= xhci_get_input_control_ctx(command
->in_ctx
);
3987 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3988 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
3993 xhci_slot_copy(xhci
, command
->in_ctx
, virt_dev
->out_ctx
);
3994 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3996 ctrl_ctx
->add_flags
|= cpu_to_le32(SLOT_FLAG
);
3997 slot_ctx
= xhci_get_slot_ctx(xhci
, command
->in_ctx
);
3998 slot_ctx
->dev_info2
&= cpu_to_le32(~((u32
) MAX_EXIT
));
3999 slot_ctx
->dev_info2
|= cpu_to_le32(max_exit_latency
);
4000 slot_ctx
->dev_state
= 0;
4002 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
4003 "Set up evaluate context for LPM MEL change.");
4005 /* Issue and wait for the evaluate context command. */
4006 ret
= xhci_configure_endpoint(xhci
, udev
, command
,
4010 spin_lock_irqsave(&xhci
->lock
, flags
);
4011 virt_dev
->current_mel
= max_exit_latency
;
4012 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4019 /* BESL to HIRD Encoding array for USB2 LPM */
4020 static int xhci_besl_encoding
[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4021 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4023 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4024 static int xhci_calculate_hird_besl(struct xhci_hcd
*xhci
,
4025 struct usb_device
*udev
)
4027 int u2del
, besl
, besl_host
;
4028 int besl_device
= 0;
4031 u2del
= HCS_U2_LATENCY(xhci
->hcs_params3
);
4032 field
= le32_to_cpu(udev
->bos
->ext_cap
->bmAttributes
);
4034 if (field
& USB_BESL_SUPPORT
) {
4035 for (besl_host
= 0; besl_host
< 16; besl_host
++) {
4036 if (xhci_besl_encoding
[besl_host
] >= u2del
)
4039 /* Use baseline BESL value as default */
4040 if (field
& USB_BESL_BASELINE_VALID
)
4041 besl_device
= USB_GET_BESL_BASELINE(field
);
4042 else if (field
& USB_BESL_DEEP_VALID
)
4043 besl_device
= USB_GET_BESL_DEEP(field
);
4048 besl_host
= (u2del
- 51) / 75 + 1;
4051 besl
= besl_host
+ besl_device
;
4058 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4059 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device
*udev
)
4066 field
= le32_to_cpu(udev
->bos
->ext_cap
->bmAttributes
);
4068 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4069 l1
= udev
->l1_params
.timeout
/ 256;
4071 /* device has preferred BESLD */
4072 if (field
& USB_BESL_DEEP_VALID
) {
4073 besld
= USB_GET_BESL_DEEP(field
);
4077 return PORT_BESLD(besld
) | PORT_L1_TIMEOUT(l1
) | PORT_HIRDM(hirdm
);
4080 static int xhci_set_usb2_hardware_lpm(struct usb_hcd
*hcd
,
4081 struct usb_device
*udev
, int enable
)
4083 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
4084 __le32 __iomem
**port_array
;
4085 __le32 __iomem
*pm_addr
, *hlpm_addr
;
4086 u32 pm_val
, hlpm_val
, field
;
4087 unsigned int port_num
;
4088 unsigned long flags
;
4089 int hird
, exit_latency
;
4092 if (hcd
->speed
>= HCD_USB3
|| !xhci
->hw_lpm_support
||
4096 if (!udev
->parent
|| udev
->parent
->parent
||
4097 udev
->descriptor
.bDeviceClass
== USB_CLASS_HUB
)
4100 if (udev
->usb2_hw_lpm_capable
!= 1)
4103 spin_lock_irqsave(&xhci
->lock
, flags
);
4105 port_array
= xhci
->usb2_ports
;
4106 port_num
= udev
->portnum
- 1;
4107 pm_addr
= port_array
[port_num
] + PORTPMSC
;
4108 pm_val
= readl(pm_addr
);
4109 hlpm_addr
= port_array
[port_num
] + PORTHLPMC
;
4110 field
= le32_to_cpu(udev
->bos
->ext_cap
->bmAttributes
);
4112 xhci_dbg(xhci
, "%s port %d USB2 hardware LPM\n",
4113 enable
? "enable" : "disable", port_num
+ 1);
4115 if (enable
&& !(xhci
->quirks
& XHCI_HW_LPM_DISABLE
)) {
4116 /* Host supports BESL timeout instead of HIRD */
4117 if (udev
->usb2_hw_lpm_besl_capable
) {
4118 /* if device doesn't have a preferred BESL value use a
4119 * default one which works with mixed HIRD and BESL
4120 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4122 if ((field
& USB_BESL_SUPPORT
) &&
4123 (field
& USB_BESL_BASELINE_VALID
))
4124 hird
= USB_GET_BESL_BASELINE(field
);
4126 hird
= udev
->l1_params
.besl
;
4128 exit_latency
= xhci_besl_encoding
[hird
];
4129 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4131 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4132 * input context for link powermanagement evaluate
4133 * context commands. It is protected by hcd->bandwidth
4134 * mutex and is shared by all devices. We need to set
4135 * the max ext latency in USB 2 BESL LPM as well, so
4136 * use the same mutex and xhci_change_max_exit_latency()
4138 mutex_lock(hcd
->bandwidth_mutex
);
4139 ret
= xhci_change_max_exit_latency(xhci
, udev
,
4141 mutex_unlock(hcd
->bandwidth_mutex
);
4145 spin_lock_irqsave(&xhci
->lock
, flags
);
4147 hlpm_val
= xhci_calculate_usb2_hw_lpm_params(udev
);
4148 writel(hlpm_val
, hlpm_addr
);
4152 hird
= xhci_calculate_hird_besl(xhci
, udev
);
4155 pm_val
&= ~PORT_HIRD_MASK
;
4156 pm_val
|= PORT_HIRD(hird
) | PORT_RWE
| PORT_L1DS(udev
->slot_id
);
4157 writel(pm_val
, pm_addr
);
4158 pm_val
= readl(pm_addr
);
4160 writel(pm_val
, pm_addr
);
4164 pm_val
&= ~(PORT_HLE
| PORT_RWE
| PORT_HIRD_MASK
| PORT_L1DS_MASK
);
4165 writel(pm_val
, pm_addr
);
4168 if (udev
->usb2_hw_lpm_besl_capable
) {
4169 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4170 mutex_lock(hcd
->bandwidth_mutex
);
4171 xhci_change_max_exit_latency(xhci
, udev
, 0);
4172 mutex_unlock(hcd
->bandwidth_mutex
);
4177 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4181 /* check if a usb2 port supports a given extened capability protocol
4182 * only USB2 ports extended protocol capability values are cached.
4183 * Return 1 if capability is supported
4185 static int xhci_check_usb2_port_capability(struct xhci_hcd
*xhci
, int port
,
4186 unsigned capability
)
4188 u32 port_offset
, port_count
;
4191 for (i
= 0; i
< xhci
->num_ext_caps
; i
++) {
4192 if (xhci
->ext_caps
[i
] & capability
) {
4193 /* port offsets starts at 1 */
4194 port_offset
= XHCI_EXT_PORT_OFF(xhci
->ext_caps
[i
]) - 1;
4195 port_count
= XHCI_EXT_PORT_COUNT(xhci
->ext_caps
[i
]);
4196 if (port
>= port_offset
&&
4197 port
< port_offset
+ port_count
)
4204 static int xhci_update_device(struct usb_hcd
*hcd
, struct usb_device
*udev
)
4206 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
4207 int portnum
= udev
->portnum
- 1;
4209 if (hcd
->speed
>= HCD_USB3
|| !xhci
->sw_lpm_support
||
4213 /* we only support lpm for non-hub device connected to root hub yet */
4214 if (!udev
->parent
|| udev
->parent
->parent
||
4215 udev
->descriptor
.bDeviceClass
== USB_CLASS_HUB
)
4218 if (xhci
->hw_lpm_support
== 1 &&
4219 xhci_check_usb2_port_capability(
4220 xhci
, portnum
, XHCI_HLC
)) {
4221 udev
->usb2_hw_lpm_capable
= 1;
4222 udev
->l1_params
.timeout
= XHCI_L1_TIMEOUT
;
4223 udev
->l1_params
.besl
= XHCI_DEFAULT_BESL
;
4224 if (xhci_check_usb2_port_capability(xhci
, portnum
,
4226 udev
->usb2_hw_lpm_besl_capable
= 1;
4232 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4234 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4235 static unsigned long long xhci_service_interval_to_ns(
4236 struct usb_endpoint_descriptor
*desc
)
4238 return (1ULL << (desc
->bInterval
- 1)) * 125 * 1000;
4241 static u16
xhci_get_timeout_no_hub_lpm(struct usb_device
*udev
,
4242 enum usb3_link_state state
)
4244 unsigned long long sel
;
4245 unsigned long long pel
;
4246 unsigned int max_sel_pel
;
4251 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4252 sel
= DIV_ROUND_UP(udev
->u1_params
.sel
, 1000);
4253 pel
= DIV_ROUND_UP(udev
->u1_params
.pel
, 1000);
4254 max_sel_pel
= USB3_LPM_MAX_U1_SEL_PEL
;
4258 sel
= DIV_ROUND_UP(udev
->u2_params
.sel
, 1000);
4259 pel
= DIV_ROUND_UP(udev
->u2_params
.pel
, 1000);
4260 max_sel_pel
= USB3_LPM_MAX_U2_SEL_PEL
;
4264 dev_warn(&udev
->dev
, "%s: Can't get timeout for non-U1 or U2 state.\n",
4266 return USB3_LPM_DISABLED
;
4269 if (sel
<= max_sel_pel
&& pel
<= max_sel_pel
)
4270 return USB3_LPM_DEVICE_INITIATED
;
4272 if (sel
> max_sel_pel
)
4273 dev_dbg(&udev
->dev
, "Device-initiated %s disabled "
4274 "due to long SEL %llu ms\n",
4277 dev_dbg(&udev
->dev
, "Device-initiated %s disabled "
4278 "due to long PEL %llu ms\n",
4280 return USB3_LPM_DISABLED
;
4283 /* The U1 timeout should be the maximum of the following values:
4284 * - For control endpoints, U1 system exit latency (SEL) * 3
4285 * - For bulk endpoints, U1 SEL * 5
4286 * - For interrupt endpoints:
4287 * - Notification EPs, U1 SEL * 3
4288 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4289 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4291 static unsigned long long xhci_calculate_intel_u1_timeout(
4292 struct usb_device
*udev
,
4293 struct usb_endpoint_descriptor
*desc
)
4295 unsigned long long timeout_ns
;
4299 ep_type
= usb_endpoint_type(desc
);
4301 case USB_ENDPOINT_XFER_CONTROL
:
4302 timeout_ns
= udev
->u1_params
.sel
* 3;
4304 case USB_ENDPOINT_XFER_BULK
:
4305 timeout_ns
= udev
->u1_params
.sel
* 5;
4307 case USB_ENDPOINT_XFER_INT
:
4308 intr_type
= usb_endpoint_interrupt_type(desc
);
4309 if (intr_type
== USB_ENDPOINT_INTR_NOTIFICATION
) {
4310 timeout_ns
= udev
->u1_params
.sel
* 3;
4313 /* Otherwise the calculation is the same as isoc eps */
4315 case USB_ENDPOINT_XFER_ISOC
:
4316 timeout_ns
= xhci_service_interval_to_ns(desc
);
4317 timeout_ns
= DIV_ROUND_UP_ULL(timeout_ns
* 105, 100);
4318 if (timeout_ns
< udev
->u1_params
.sel
* 2)
4319 timeout_ns
= udev
->u1_params
.sel
* 2;
4328 /* Returns the hub-encoded U1 timeout value. */
4329 static u16
xhci_calculate_u1_timeout(struct xhci_hcd
*xhci
,
4330 struct usb_device
*udev
,
4331 struct usb_endpoint_descriptor
*desc
)
4333 unsigned long long timeout_ns
;
4335 if (xhci
->quirks
& XHCI_INTEL_HOST
)
4336 timeout_ns
= xhci_calculate_intel_u1_timeout(udev
, desc
);
4338 timeout_ns
= udev
->u1_params
.sel
;
4340 /* The U1 timeout is encoded in 1us intervals.
4341 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4343 if (timeout_ns
== USB3_LPM_DISABLED
)
4346 timeout_ns
= DIV_ROUND_UP_ULL(timeout_ns
, 1000);
4348 /* If the necessary timeout value is bigger than what we can set in the
4349 * USB 3.0 hub, we have to disable hub-initiated U1.
4351 if (timeout_ns
<= USB3_LPM_U1_MAX_TIMEOUT
)
4353 dev_dbg(&udev
->dev
, "Hub-initiated U1 disabled "
4354 "due to long timeout %llu ms\n", timeout_ns
);
4355 return xhci_get_timeout_no_hub_lpm(udev
, USB3_LPM_U1
);
4358 /* The U2 timeout should be the maximum of:
4359 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4360 * - largest bInterval of any active periodic endpoint (to avoid going
4361 * into lower power link states between intervals).
4362 * - the U2 Exit Latency of the device
4364 static unsigned long long xhci_calculate_intel_u2_timeout(
4365 struct usb_device
*udev
,
4366 struct usb_endpoint_descriptor
*desc
)
4368 unsigned long long timeout_ns
;
4369 unsigned long long u2_del_ns
;
4371 timeout_ns
= 10 * 1000 * 1000;
4373 if ((usb_endpoint_xfer_int(desc
) || usb_endpoint_xfer_isoc(desc
)) &&
4374 (xhci_service_interval_to_ns(desc
) > timeout_ns
))
4375 timeout_ns
= xhci_service_interval_to_ns(desc
);
4377 u2_del_ns
= le16_to_cpu(udev
->bos
->ss_cap
->bU2DevExitLat
) * 1000ULL;
4378 if (u2_del_ns
> timeout_ns
)
4379 timeout_ns
= u2_del_ns
;
4384 /* Returns the hub-encoded U2 timeout value. */
4385 static u16
xhci_calculate_u2_timeout(struct xhci_hcd
*xhci
,
4386 struct usb_device
*udev
,
4387 struct usb_endpoint_descriptor
*desc
)
4389 unsigned long long timeout_ns
;
4391 if (xhci
->quirks
& XHCI_INTEL_HOST
)
4392 timeout_ns
= xhci_calculate_intel_u2_timeout(udev
, desc
);
4394 timeout_ns
= udev
->u2_params
.sel
;
4396 /* The U2 timeout is encoded in 256us intervals */
4397 timeout_ns
= DIV_ROUND_UP_ULL(timeout_ns
, 256 * 1000);
4398 /* If the necessary timeout value is bigger than what we can set in the
4399 * USB 3.0 hub, we have to disable hub-initiated U2.
4401 if (timeout_ns
<= USB3_LPM_U2_MAX_TIMEOUT
)
4403 dev_dbg(&udev
->dev
, "Hub-initiated U2 disabled "
4404 "due to long timeout %llu ms\n", timeout_ns
);
4405 return xhci_get_timeout_no_hub_lpm(udev
, USB3_LPM_U2
);
4408 static u16
xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd
*xhci
,
4409 struct usb_device
*udev
,
4410 struct usb_endpoint_descriptor
*desc
,
4411 enum usb3_link_state state
,
4414 if (state
== USB3_LPM_U1
)
4415 return xhci_calculate_u1_timeout(xhci
, udev
, desc
);
4416 else if (state
== USB3_LPM_U2
)
4417 return xhci_calculate_u2_timeout(xhci
, udev
, desc
);
4419 return USB3_LPM_DISABLED
;
4422 static int xhci_update_timeout_for_endpoint(struct xhci_hcd
*xhci
,
4423 struct usb_device
*udev
,
4424 struct usb_endpoint_descriptor
*desc
,
4425 enum usb3_link_state state
,
4430 alt_timeout
= xhci_call_host_update_timeout_for_endpoint(xhci
, udev
,
4431 desc
, state
, timeout
);
4433 /* If we found we can't enable hub-initiated LPM, or
4434 * the U1 or U2 exit latency was too high to allow
4435 * device-initiated LPM as well, just stop searching.
4437 if (alt_timeout
== USB3_LPM_DISABLED
||
4438 alt_timeout
== USB3_LPM_DEVICE_INITIATED
) {
4439 *timeout
= alt_timeout
;
4442 if (alt_timeout
> *timeout
)
4443 *timeout
= alt_timeout
;
4447 static int xhci_update_timeout_for_interface(struct xhci_hcd
*xhci
,
4448 struct usb_device
*udev
,
4449 struct usb_host_interface
*alt
,
4450 enum usb3_link_state state
,
4455 for (j
= 0; j
< alt
->desc
.bNumEndpoints
; j
++) {
4456 if (xhci_update_timeout_for_endpoint(xhci
, udev
,
4457 &alt
->endpoint
[j
].desc
, state
, timeout
))
4464 static int xhci_check_intel_tier_policy(struct usb_device
*udev
,
4465 enum usb3_link_state state
)
4467 struct usb_device
*parent
;
4468 unsigned int num_hubs
;
4470 if (state
== USB3_LPM_U2
)
4473 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4474 for (parent
= udev
->parent
, num_hubs
= 0; parent
->parent
;
4475 parent
= parent
->parent
)
4481 dev_dbg(&udev
->dev
, "Disabling U1 link state for device"
4482 " below second-tier hub.\n");
4483 dev_dbg(&udev
->dev
, "Plug device into first-tier hub "
4484 "to decrease power consumption.\n");
4488 static int xhci_check_tier_policy(struct xhci_hcd
*xhci
,
4489 struct usb_device
*udev
,
4490 enum usb3_link_state state
)
4492 if (xhci
->quirks
& XHCI_INTEL_HOST
)
4493 return xhci_check_intel_tier_policy(udev
, state
);
4498 /* Returns the U1 or U2 timeout that should be enabled.
4499 * If the tier check or timeout setting functions return with a non-zero exit
4500 * code, that means the timeout value has been finalized and we shouldn't look
4501 * at any more endpoints.
4503 static u16
xhci_calculate_lpm_timeout(struct usb_hcd
*hcd
,
4504 struct usb_device
*udev
, enum usb3_link_state state
)
4506 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
4507 struct usb_host_config
*config
;
4510 u16 timeout
= USB3_LPM_DISABLED
;
4512 if (state
== USB3_LPM_U1
)
4514 else if (state
== USB3_LPM_U2
)
4517 dev_warn(&udev
->dev
, "Can't enable unknown link state %i\n",
4522 if (xhci_check_tier_policy(xhci
, udev
, state
) < 0)
4525 /* Gather some information about the currently installed configuration
4526 * and alternate interface settings.
4528 if (xhci_update_timeout_for_endpoint(xhci
, udev
, &udev
->ep0
.desc
,
4532 config
= udev
->actconfig
;
4536 for (i
= 0; i
< config
->desc
.bNumInterfaces
; i
++) {
4537 struct usb_driver
*driver
;
4538 struct usb_interface
*intf
= config
->interface
[i
];
4543 /* Check if any currently bound drivers want hub-initiated LPM
4546 if (intf
->dev
.driver
) {
4547 driver
= to_usb_driver(intf
->dev
.driver
);
4548 if (driver
&& driver
->disable_hub_initiated_lpm
) {
4549 dev_dbg(&udev
->dev
, "Hub-initiated %s disabled "
4550 "at request of driver %s\n",
4551 state_name
, driver
->name
);
4552 return xhci_get_timeout_no_hub_lpm(udev
, state
);
4556 /* Not sure how this could happen... */
4557 if (!intf
->cur_altsetting
)
4560 if (xhci_update_timeout_for_interface(xhci
, udev
,
4561 intf
->cur_altsetting
,
4568 static int calculate_max_exit_latency(struct usb_device
*udev
,
4569 enum usb3_link_state state_changed
,
4570 u16 hub_encoded_timeout
)
4572 unsigned long long u1_mel_us
= 0;
4573 unsigned long long u2_mel_us
= 0;
4574 unsigned long long mel_us
= 0;
4580 disabling_u1
= (state_changed
== USB3_LPM_U1
&&
4581 hub_encoded_timeout
== USB3_LPM_DISABLED
);
4582 disabling_u2
= (state_changed
== USB3_LPM_U2
&&
4583 hub_encoded_timeout
== USB3_LPM_DISABLED
);
4585 enabling_u1
= (state_changed
== USB3_LPM_U1
&&
4586 hub_encoded_timeout
!= USB3_LPM_DISABLED
);
4587 enabling_u2
= (state_changed
== USB3_LPM_U2
&&
4588 hub_encoded_timeout
!= USB3_LPM_DISABLED
);
4590 /* If U1 was already enabled and we're not disabling it,
4591 * or we're going to enable U1, account for the U1 max exit latency.
4593 if ((udev
->u1_params
.timeout
!= USB3_LPM_DISABLED
&& !disabling_u1
) ||
4595 u1_mel_us
= DIV_ROUND_UP(udev
->u1_params
.mel
, 1000);
4596 if ((udev
->u2_params
.timeout
!= USB3_LPM_DISABLED
&& !disabling_u2
) ||
4598 u2_mel_us
= DIV_ROUND_UP(udev
->u2_params
.mel
, 1000);
4600 if (u1_mel_us
> u2_mel_us
)
4604 /* xHCI host controller max exit latency field is only 16 bits wide. */
4605 if (mel_us
> MAX_EXIT
) {
4606 dev_warn(&udev
->dev
, "Link PM max exit latency of %lluus "
4607 "is too big.\n", mel_us
);
4613 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4614 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd
*hcd
,
4615 struct usb_device
*udev
, enum usb3_link_state state
)
4617 struct xhci_hcd
*xhci
;
4618 u16 hub_encoded_timeout
;
4622 xhci
= hcd_to_xhci(hcd
);
4623 /* The LPM timeout values are pretty host-controller specific, so don't
4624 * enable hub-initiated timeouts unless the vendor has provided
4625 * information about their timeout algorithm.
4627 if (!xhci
|| !(xhci
->quirks
& XHCI_LPM_SUPPORT
) ||
4628 !xhci
->devs
[udev
->slot_id
])
4629 return USB3_LPM_DISABLED
;
4631 hub_encoded_timeout
= xhci_calculate_lpm_timeout(hcd
, udev
, state
);
4632 mel
= calculate_max_exit_latency(udev
, state
, hub_encoded_timeout
);
4634 /* Max Exit Latency is too big, disable LPM. */
4635 hub_encoded_timeout
= USB3_LPM_DISABLED
;
4639 ret
= xhci_change_max_exit_latency(xhci
, udev
, mel
);
4642 return hub_encoded_timeout
;
4645 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd
*hcd
,
4646 struct usb_device
*udev
, enum usb3_link_state state
)
4648 struct xhci_hcd
*xhci
;
4651 xhci
= hcd_to_xhci(hcd
);
4652 if (!xhci
|| !(xhci
->quirks
& XHCI_LPM_SUPPORT
) ||
4653 !xhci
->devs
[udev
->slot_id
])
4656 mel
= calculate_max_exit_latency(udev
, state
, USB3_LPM_DISABLED
);
4657 return xhci_change_max_exit_latency(xhci
, udev
, mel
);
4659 #else /* CONFIG_PM */
4661 static int xhci_set_usb2_hardware_lpm(struct usb_hcd
*hcd
,
4662 struct usb_device
*udev
, int enable
)
4667 static int xhci_update_device(struct usb_hcd
*hcd
, struct usb_device
*udev
)
4672 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd
*hcd
,
4673 struct usb_device
*udev
, enum usb3_link_state state
)
4675 return USB3_LPM_DISABLED
;
4678 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd
*hcd
,
4679 struct usb_device
*udev
, enum usb3_link_state state
)
4683 #endif /* CONFIG_PM */
4685 /*-------------------------------------------------------------------------*/
4687 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
4688 * internal data structures for the device.
4690 static int xhci_update_hub_device(struct usb_hcd
*hcd
, struct usb_device
*hdev
,
4691 struct usb_tt
*tt
, gfp_t mem_flags
)
4693 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
4694 struct xhci_virt_device
*vdev
;
4695 struct xhci_command
*config_cmd
;
4696 struct xhci_input_control_ctx
*ctrl_ctx
;
4697 struct xhci_slot_ctx
*slot_ctx
;
4698 unsigned long flags
;
4699 unsigned think_time
;
4702 /* Ignore root hubs */
4706 vdev
= xhci
->devs
[hdev
->slot_id
];
4708 xhci_warn(xhci
, "Cannot update hub desc for unknown device.\n");
4712 config_cmd
= xhci_alloc_command(xhci
, true, true, mem_flags
);
4716 ctrl_ctx
= xhci_get_input_control_ctx(config_cmd
->in_ctx
);
4718 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
4720 xhci_free_command(xhci
, config_cmd
);
4724 spin_lock_irqsave(&xhci
->lock
, flags
);
4725 if (hdev
->speed
== USB_SPEED_HIGH
&&
4726 xhci_alloc_tt_info(xhci
, vdev
, hdev
, tt
, GFP_ATOMIC
)) {
4727 xhci_dbg(xhci
, "Could not allocate xHCI TT structure.\n");
4728 xhci_free_command(xhci
, config_cmd
);
4729 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4733 xhci_slot_copy(xhci
, config_cmd
->in_ctx
, vdev
->out_ctx
);
4734 ctrl_ctx
->add_flags
|= cpu_to_le32(SLOT_FLAG
);
4735 slot_ctx
= xhci_get_slot_ctx(xhci
, config_cmd
->in_ctx
);
4736 slot_ctx
->dev_info
|= cpu_to_le32(DEV_HUB
);
4738 * refer to section 6.2.2: MTT should be 0 for full speed hub,
4739 * but it may be already set to 1 when setup an xHCI virtual
4740 * device, so clear it anyway.
4743 slot_ctx
->dev_info
|= cpu_to_le32(DEV_MTT
);
4744 else if (hdev
->speed
== USB_SPEED_FULL
)
4745 slot_ctx
->dev_info
&= cpu_to_le32(~DEV_MTT
);
4747 if (xhci
->hci_version
> 0x95) {
4748 xhci_dbg(xhci
, "xHCI version %x needs hub "
4749 "TT think time and number of ports\n",
4750 (unsigned int) xhci
->hci_version
);
4751 slot_ctx
->dev_info2
|= cpu_to_le32(XHCI_MAX_PORTS(hdev
->maxchild
));
4752 /* Set TT think time - convert from ns to FS bit times.
4753 * 0 = 8 FS bit times, 1 = 16 FS bit times,
4754 * 2 = 24 FS bit times, 3 = 32 FS bit times.
4756 * xHCI 1.0: this field shall be 0 if the device is not a
4759 think_time
= tt
->think_time
;
4760 if (think_time
!= 0)
4761 think_time
= (think_time
/ 666) - 1;
4762 if (xhci
->hci_version
< 0x100 || hdev
->speed
== USB_SPEED_HIGH
)
4763 slot_ctx
->tt_info
|=
4764 cpu_to_le32(TT_THINK_TIME(think_time
));
4766 xhci_dbg(xhci
, "xHCI version %x doesn't need hub "
4767 "TT think time or number of ports\n",
4768 (unsigned int) xhci
->hci_version
);
4770 slot_ctx
->dev_state
= 0;
4771 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4773 xhci_dbg(xhci
, "Set up %s for hub device.\n",
4774 (xhci
->hci_version
> 0x95) ?
4775 "configure endpoint" : "evaluate context");
4777 /* Issue and wait for the configure endpoint or
4778 * evaluate context command.
4780 if (xhci
->hci_version
> 0x95)
4781 ret
= xhci_configure_endpoint(xhci
, hdev
, config_cmd
,
4784 ret
= xhci_configure_endpoint(xhci
, hdev
, config_cmd
,
4787 xhci_free_command(xhci
, config_cmd
);
4791 static int xhci_get_frame(struct usb_hcd
*hcd
)
4793 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
4794 /* EHCI mods by the periodic size. Why? */
4795 return readl(&xhci
->run_regs
->microframe_index
) >> 3;
4798 int xhci_gen_setup(struct usb_hcd
*hcd
, xhci_get_quirks_t get_quirks
)
4800 struct xhci_hcd
*xhci
;
4802 * TODO: Check with DWC3 clients for sysdev according to
4805 struct device
*dev
= hcd
->self
.sysdev
;
4806 unsigned int minor_rev
;
4809 /* Accept arbitrarily long scatter-gather lists */
4810 hcd
->self
.sg_tablesize
= ~0;
4812 /* support to build packet from discontinuous buffers */
4813 hcd
->self
.no_sg_constraint
= 1;
4815 /* XHCI controllers don't stop the ep queue on short packets :| */
4816 hcd
->self
.no_stop_on_short
= 1;
4818 xhci
= hcd_to_xhci(hcd
);
4820 if (usb_hcd_is_primary_hcd(hcd
)) {
4821 xhci
->main_hcd
= hcd
;
4822 /* Mark the first roothub as being USB 2.0.
4823 * The xHCI driver will register the USB 3.0 roothub.
4825 hcd
->speed
= HCD_USB2
;
4826 hcd
->self
.root_hub
->speed
= USB_SPEED_HIGH
;
4828 * USB 2.0 roothub under xHCI has an integrated TT,
4829 * (rate matching hub) as opposed to having an OHCI/UHCI
4830 * companion controller.
4835 * Some 3.1 hosts return sbrn 0x30, use xhci supported protocol
4836 * minor revision instead of sbrn
4838 minor_rev
= xhci
->usb3_rhub
.min_rev
;
4840 hcd
->speed
= HCD_USB31
;
4841 hcd
->self
.root_hub
->speed
= USB_SPEED_SUPER_PLUS
;
4843 xhci_info(xhci
, "Host supports USB 3.%x %s SuperSpeed\n",
4845 minor_rev
? "Enhanced" : "");
4847 /* xHCI private pointer was set in xhci_pci_probe for the second
4848 * registered roothub.
4853 mutex_init(&xhci
->mutex
);
4854 xhci
->cap_regs
= hcd
->regs
;
4855 xhci
->op_regs
= hcd
->regs
+
4856 HC_LENGTH(readl(&xhci
->cap_regs
->hc_capbase
));
4857 xhci
->run_regs
= hcd
->regs
+
4858 (readl(&xhci
->cap_regs
->run_regs_off
) & RTSOFF_MASK
);
4859 /* Cache read-only capability registers */
4860 xhci
->hcs_params1
= readl(&xhci
->cap_regs
->hcs_params1
);
4861 xhci
->hcs_params2
= readl(&xhci
->cap_regs
->hcs_params2
);
4862 xhci
->hcs_params3
= readl(&xhci
->cap_regs
->hcs_params3
);
4863 xhci
->hcc_params
= readl(&xhci
->cap_regs
->hc_capbase
);
4864 xhci
->hci_version
= HC_VERSION(xhci
->hcc_params
);
4865 xhci
->hcc_params
= readl(&xhci
->cap_regs
->hcc_params
);
4866 if (xhci
->hci_version
> 0x100)
4867 xhci
->hcc_params2
= readl(&xhci
->cap_regs
->hcc_params2
);
4868 xhci_print_registers(xhci
);
4870 xhci
->quirks
|= quirks
;
4872 get_quirks(dev
, xhci
);
4874 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
4875 * success event after a short transfer. This quirk will ignore such
4878 if (xhci
->hci_version
> 0x96)
4879 xhci
->quirks
|= XHCI_SPURIOUS_SUCCESS
;
4881 /* Make sure the HC is halted. */
4882 retval
= xhci_halt(xhci
);
4886 xhci_dbg(xhci
, "Resetting HCD\n");
4887 /* Reset the internal HC memory state and registers. */
4888 retval
= xhci_reset(xhci
);
4891 xhci_dbg(xhci
, "Reset complete\n");
4894 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
4895 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
4896 * address memory pointers actually. So, this driver clears the AC64
4897 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
4898 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
4900 if (xhci
->quirks
& XHCI_NO_64BIT_SUPPORT
)
4901 xhci
->hcc_params
&= ~BIT(0);
4903 /* Set dma_mask and coherent_dma_mask to 64-bits,
4904 * if xHC supports 64-bit addressing */
4905 if (HCC_64BIT_ADDR(xhci
->hcc_params
) &&
4906 !dma_set_mask(dev
, DMA_BIT_MASK(64))) {
4907 xhci_dbg(xhci
, "Enabling 64-bit DMA addresses.\n");
4908 dma_set_coherent_mask(dev
, DMA_BIT_MASK(64));
4911 * This is to avoid error in cases where a 32-bit USB
4912 * controller is used on a 64-bit capable system.
4914 retval
= dma_set_mask(dev
, DMA_BIT_MASK(32));
4917 xhci_dbg(xhci
, "Enabling 32-bit DMA addresses.\n");
4918 dma_set_coherent_mask(dev
, DMA_BIT_MASK(32));
4921 xhci_dbg(xhci
, "Calling HCD init\n");
4922 /* Initialize HCD and host controller data structures. */
4923 retval
= xhci_init(hcd
);
4926 xhci_dbg(xhci
, "Called HCD init\n");
4928 xhci_info(xhci
, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
4929 xhci
->hcc_params
, xhci
->hci_version
, xhci
->quirks
);
4933 EXPORT_SYMBOL_GPL(xhci_gen_setup
);
4935 static const struct hc_driver xhci_hc_driver
= {
4936 .description
= "xhci-hcd",
4937 .product_desc
= "xHCI Host Controller",
4938 .hcd_priv_size
= sizeof(struct xhci_hcd
),
4941 * generic hardware linkage
4944 .flags
= HCD_MEMORY
| HCD_USB3
| HCD_SHARED
,
4947 * basic lifecycle operations
4949 .reset
= NULL
, /* set in xhci_init_driver() */
4952 .shutdown
= xhci_shutdown
,
4955 * managing i/o requests and associated device resources
4957 .urb_enqueue
= xhci_urb_enqueue
,
4958 .urb_dequeue
= xhci_urb_dequeue
,
4959 .alloc_dev
= xhci_alloc_dev
,
4960 .free_dev
= xhci_free_dev
,
4961 .alloc_streams
= xhci_alloc_streams
,
4962 .free_streams
= xhci_free_streams
,
4963 .add_endpoint
= xhci_add_endpoint
,
4964 .drop_endpoint
= xhci_drop_endpoint
,
4965 .endpoint_reset
= xhci_endpoint_reset
,
4966 .check_bandwidth
= xhci_check_bandwidth
,
4967 .reset_bandwidth
= xhci_reset_bandwidth
,
4968 .address_device
= xhci_address_device
,
4969 .enable_device
= xhci_enable_device
,
4970 .update_hub_device
= xhci_update_hub_device
,
4971 .reset_device
= xhci_discover_or_reset_device
,
4974 * scheduling support
4976 .get_frame_number
= xhci_get_frame
,
4981 .hub_control
= xhci_hub_control
,
4982 .hub_status_data
= xhci_hub_status_data
,
4983 .bus_suspend
= xhci_bus_suspend
,
4984 .bus_resume
= xhci_bus_resume
,
4987 * call back when device connected and addressed
4989 .update_device
= xhci_update_device
,
4990 .set_usb2_hw_lpm
= xhci_set_usb2_hardware_lpm
,
4991 .enable_usb3_lpm_timeout
= xhci_enable_usb3_lpm_timeout
,
4992 .disable_usb3_lpm_timeout
= xhci_disable_usb3_lpm_timeout
,
4993 .find_raw_port_number
= xhci_find_raw_port_number
,
4996 void xhci_init_driver(struct hc_driver
*drv
,
4997 const struct xhci_driver_overrides
*over
)
5001 /* Copy the generic table to drv then apply the overrides */
5002 *drv
= xhci_hc_driver
;
5005 drv
->hcd_priv_size
+= over
->extra_priv_size
;
5007 drv
->reset
= over
->reset
;
5009 drv
->start
= over
->start
;
5012 EXPORT_SYMBOL_GPL(xhci_init_driver
);
5014 MODULE_DESCRIPTION(DRIVER_DESC
);
5015 MODULE_AUTHOR(DRIVER_AUTHOR
);
5016 MODULE_LICENSE("GPL");
5018 static int __init
xhci_hcd_init(void)
5021 * Check the compiler generated sizes of structures that must be laid
5022 * out in specific ways for hardware access.
5024 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array
) != 256*32/8);
5025 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx
) != 8*32/8);
5026 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx
) != 8*32/8);
5027 /* xhci_device_control has eight fields, and also
5028 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5030 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx
) != 4*32/8);
5031 BUILD_BUG_ON(sizeof(union xhci_trb
) != 4*32/8);
5032 BUILD_BUG_ON(sizeof(struct xhci_erst_entry
) != 4*32/8);
5033 BUILD_BUG_ON(sizeof(struct xhci_cap_regs
) != 8*32/8);
5034 BUILD_BUG_ON(sizeof(struct xhci_intr_reg
) != 8*32/8);
5035 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5036 BUILD_BUG_ON(sizeof(struct xhci_run_regs
) != (8+8*128)*32/8);
5041 xhci_debugfs_create_root();
5047 * If an init function is provided, an exit function must also be provided
5048 * to allow module unload.
5050 static void __exit
xhci_hcd_fini(void)
5052 xhci_debugfs_remove_root();
5055 module_init(xhci_hcd_init
);
5056 module_exit(xhci_hcd_fini
);