1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
11 #include <linux/pci.h>
12 #include <linux/iopoll.h>
13 #include <linux/irq.h>
14 #include <linux/log2.h>
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/slab.h>
18 #include <linux/dmi.h>
19 #include <linux/dma-mapping.h>
22 #include "xhci-trace.h"
23 #include "xhci-debugfs.h"
24 #include "xhci-dbgcap.h"
26 #define DRIVER_AUTHOR "Sarah Sharp"
27 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
29 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
31 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
32 static int link_quirk
;
33 module_param(link_quirk
, int, S_IRUGO
| S_IWUSR
);
34 MODULE_PARM_DESC(link_quirk
, "Don't clear the chain bit on a link TRB");
36 static unsigned long long quirks
;
37 module_param(quirks
, ullong
, S_IRUGO
);
38 MODULE_PARM_DESC(quirks
, "Bit flags for quirks to be enabled as default");
40 static bool td_on_ring(struct xhci_td
*td
, struct xhci_ring
*ring
)
42 struct xhci_segment
*seg
= ring
->first_seg
;
44 if (!td
|| !td
->start_seg
)
47 if (seg
== td
->start_seg
)
50 } while (seg
&& seg
!= ring
->first_seg
);
56 * xhci_handshake - spin reading hc until handshake completes or fails
57 * @ptr: address of hc register to be read
58 * @mask: bits to look at in result of read
59 * @done: value of those bits when handshake succeeds
60 * @usec: timeout in microseconds
62 * Returns negative errno, or zero on success
64 * Success happens when the "mask" bits have the specified value (hardware
65 * handshake done). There are two failure modes: "usec" have passed (major
66 * hardware flakeout), or the register reads as all-ones (hardware removed).
68 int xhci_handshake(void __iomem
*ptr
, u32 mask
, u32 done
, u64 timeout_us
)
73 ret
= readl_poll_timeout_atomic(ptr
, result
,
74 (result
& mask
) == done
||
77 if (result
== U32_MAX
) /* card removed */
84 * Disable interrupts and begin the xHCI halting process.
86 void xhci_quiesce(struct xhci_hcd
*xhci
)
93 halted
= readl(&xhci
->op_regs
->status
) & STS_HALT
;
97 cmd
= readl(&xhci
->op_regs
->command
);
99 writel(cmd
, &xhci
->op_regs
->command
);
103 * Force HC into halt state.
105 * Disable any IRQs and clear the run/stop bit.
106 * HC will complete any current and actively pipelined transactions, and
107 * should halt within 16 ms of the run/stop bit being cleared.
108 * Read HC Halted bit in the status register to see when the HC is finished.
110 int xhci_halt(struct xhci_hcd
*xhci
)
113 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "// Halt the HC");
116 ret
= xhci_handshake(&xhci
->op_regs
->status
,
117 STS_HALT
, STS_HALT
, XHCI_MAX_HALT_USEC
);
119 xhci_warn(xhci
, "Host halt failed, %d\n", ret
);
122 xhci
->xhc_state
|= XHCI_STATE_HALTED
;
123 xhci
->cmd_ring_state
= CMD_RING_STATE_STOPPED
;
128 * Set the run bit and wait for the host to be running.
130 int xhci_start(struct xhci_hcd
*xhci
)
135 temp
= readl(&xhci
->op_regs
->command
);
137 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "// Turn on HC, cmd = 0x%x.",
139 writel(temp
, &xhci
->op_regs
->command
);
142 * Wait for the HCHalted Status bit to be 0 to indicate the host is
145 ret
= xhci_handshake(&xhci
->op_regs
->status
,
146 STS_HALT
, 0, XHCI_MAX_HALT_USEC
);
147 if (ret
== -ETIMEDOUT
)
148 xhci_err(xhci
, "Host took too long to start, "
149 "waited %u microseconds.\n",
152 /* clear state flags. Including dying, halted or removing */
161 * This resets pipelines, timers, counters, state machines, etc.
162 * Transactions will be terminated immediately, and operational registers
163 * will be set to their defaults.
165 int xhci_reset(struct xhci_hcd
*xhci
, u64 timeout_us
)
171 state
= readl(&xhci
->op_regs
->status
);
173 if (state
== ~(u32
)0) {
174 xhci_warn(xhci
, "Host not accessible, reset failed.\n");
178 if ((state
& STS_HALT
) == 0) {
179 xhci_warn(xhci
, "Host controller not halted, aborting reset.\n");
183 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "// Reset the HC");
184 command
= readl(&xhci
->op_regs
->command
);
185 command
|= CMD_RESET
;
186 writel(command
, &xhci
->op_regs
->command
);
188 /* Existing Intel xHCI controllers require a delay of 1 mS,
189 * after setting the CMD_RESET bit, and before accessing any
190 * HC registers. This allows the HC to complete the
191 * reset operation and be ready for HC register access.
192 * Without this delay, the subsequent HC register access,
193 * may result in a system hang very rarely.
195 if (xhci
->quirks
& XHCI_INTEL_HOST
)
198 ret
= xhci_handshake(&xhci
->op_regs
->command
, CMD_RESET
, 0, timeout_us
);
202 if (xhci
->quirks
& XHCI_ASMEDIA_MODIFY_FLOWCONTROL
)
203 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
));
205 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
206 "Wait for controller to be ready for doorbell rings");
208 * xHCI cannot write to any doorbells or operational registers other
209 * than status until the "Controller Not Ready" flag is cleared.
211 ret
= xhci_handshake(&xhci
->op_regs
->status
, STS_CNR
, 0, timeout_us
);
213 xhci
->usb2_rhub
.bus_state
.port_c_suspend
= 0;
214 xhci
->usb2_rhub
.bus_state
.suspended_ports
= 0;
215 xhci
->usb2_rhub
.bus_state
.resuming_ports
= 0;
216 xhci
->usb3_rhub
.bus_state
.port_c_suspend
= 0;
217 xhci
->usb3_rhub
.bus_state
.suspended_ports
= 0;
218 xhci
->usb3_rhub
.bus_state
.resuming_ports
= 0;
223 static void xhci_zero_64b_regs(struct xhci_hcd
*xhci
)
225 struct device
*dev
= xhci_to_hcd(xhci
)->self
.sysdev
;
231 * Some Renesas controllers get into a weird state if they are
232 * reset while programmed with 64bit addresses (they will preserve
233 * the top half of the address in internal, non visible
234 * registers). You end up with half the address coming from the
235 * kernel, and the other half coming from the firmware. Also,
236 * changing the programming leads to extra accesses even if the
237 * controller is supposed to be halted. The controller ends up with
238 * a fatal fault, and is then ripe for being properly reset.
240 * Special care is taken to only apply this if the device is behind
241 * an iommu. Doing anything when there is no iommu is definitely
244 if (!(xhci
->quirks
& XHCI_ZERO_64B_REGS
) || !device_iommu_mapped(dev
))
247 xhci_info(xhci
, "Zeroing 64bit base registers, expecting fault\n");
249 /* Clear HSEIE so that faults do not get signaled */
250 val
= readl(&xhci
->op_regs
->command
);
252 writel(val
, &xhci
->op_regs
->command
);
254 /* Clear HSE (aka FATAL) */
255 val
= readl(&xhci
->op_regs
->status
);
257 writel(val
, &xhci
->op_regs
->status
);
259 /* Now zero the registers, and brace for impact */
260 val
= xhci_read_64(xhci
, &xhci
->op_regs
->dcbaa_ptr
);
261 if (upper_32_bits(val
))
262 xhci_write_64(xhci
, 0, &xhci
->op_regs
->dcbaa_ptr
);
263 val
= xhci_read_64(xhci
, &xhci
->op_regs
->cmd_ring
);
264 if (upper_32_bits(val
))
265 xhci_write_64(xhci
, 0, &xhci
->op_regs
->cmd_ring
);
267 intrs
= min_t(u32
, HCS_MAX_INTRS(xhci
->hcs_params1
),
268 ARRAY_SIZE(xhci
->run_regs
->ir_set
));
270 for (i
= 0; i
< intrs
; i
++) {
271 struct xhci_intr_reg __iomem
*ir
;
273 ir
= &xhci
->run_regs
->ir_set
[i
];
274 val
= xhci_read_64(xhci
, &ir
->erst_base
);
275 if (upper_32_bits(val
))
276 xhci_write_64(xhci
, 0, &ir
->erst_base
);
277 val
= xhci_read_64(xhci
, &ir
->erst_dequeue
);
278 if (upper_32_bits(val
))
279 xhci_write_64(xhci
, 0, &ir
->erst_dequeue
);
282 /* Wait for the fault to appear. It will be cleared on reset */
283 err
= xhci_handshake(&xhci
->op_regs
->status
,
284 STS_FATAL
, STS_FATAL
,
287 xhci_info(xhci
, "Fault detected\n");
290 #ifdef CONFIG_USB_PCI
294 static int xhci_setup_msi(struct xhci_hcd
*xhci
)
298 * TODO:Check with MSI Soc for sysdev
300 struct pci_dev
*pdev
= to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
);
302 ret
= pci_alloc_irq_vectors(pdev
, 1, 1, PCI_IRQ_MSI
);
304 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
305 "failed to allocate MSI entry");
309 ret
= request_irq(pdev
->irq
, xhci_msi_irq
,
310 0, "xhci_hcd", xhci_to_hcd(xhci
));
312 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
313 "disable MSI interrupt");
314 pci_free_irq_vectors(pdev
);
323 static int xhci_setup_msix(struct xhci_hcd
*xhci
)
326 struct usb_hcd
*hcd
= xhci_to_hcd(xhci
);
327 struct pci_dev
*pdev
= to_pci_dev(hcd
->self
.controller
);
330 * calculate number of msi-x vectors supported.
331 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
332 * with max number of interrupters based on the xhci HCSPARAMS1.
333 * - num_online_cpus: maximum msi-x vectors per CPUs core.
334 * Add additional 1 vector to ensure always available interrupt.
336 xhci
->msix_count
= min(num_online_cpus() + 1,
337 HCS_MAX_INTRS(xhci
->hcs_params1
));
339 ret
= pci_alloc_irq_vectors(pdev
, xhci
->msix_count
, xhci
->msix_count
,
342 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
343 "Failed to enable MSI-X");
347 for (i
= 0; i
< xhci
->msix_count
; i
++) {
348 ret
= request_irq(pci_irq_vector(pdev
, i
), xhci_msi_irq
, 0,
349 "xhci_hcd", xhci_to_hcd(xhci
));
354 hcd
->msix_enabled
= 1;
358 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "disable MSI-X interrupt");
360 free_irq(pci_irq_vector(pdev
, i
), xhci_to_hcd(xhci
));
361 pci_free_irq_vectors(pdev
);
365 /* Free any IRQs and disable MSI-X */
366 static void xhci_cleanup_msix(struct xhci_hcd
*xhci
)
368 struct usb_hcd
*hcd
= xhci_to_hcd(xhci
);
369 struct pci_dev
*pdev
= to_pci_dev(hcd
->self
.controller
);
371 if (xhci
->quirks
& XHCI_PLAT
)
374 /* return if using legacy interrupt */
378 if (hcd
->msix_enabled
) {
381 for (i
= 0; i
< xhci
->msix_count
; i
++)
382 free_irq(pci_irq_vector(pdev
, i
), xhci_to_hcd(xhci
));
384 free_irq(pci_irq_vector(pdev
, 0), xhci_to_hcd(xhci
));
387 pci_free_irq_vectors(pdev
);
388 hcd
->msix_enabled
= 0;
391 static void __maybe_unused
xhci_msix_sync_irqs(struct xhci_hcd
*xhci
)
393 struct usb_hcd
*hcd
= xhci_to_hcd(xhci
);
395 if (hcd
->msix_enabled
) {
396 struct pci_dev
*pdev
= to_pci_dev(hcd
->self
.controller
);
399 for (i
= 0; i
< xhci
->msix_count
; i
++)
400 synchronize_irq(pci_irq_vector(pdev
, i
));
404 static int xhci_try_enable_msi(struct usb_hcd
*hcd
)
406 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
407 struct pci_dev
*pdev
;
410 /* The xhci platform device has set up IRQs through usb_add_hcd. */
411 if (xhci
->quirks
& XHCI_PLAT
)
414 pdev
= to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
);
416 * Some Fresco Logic host controllers advertise MSI, but fail to
417 * generate interrupts. Don't even try to enable MSI.
419 if (xhci
->quirks
& XHCI_BROKEN_MSI
)
422 /* unregister the legacy interrupt */
424 free_irq(hcd
->irq
, hcd
);
427 ret
= xhci_setup_msix(xhci
);
429 /* fall back to msi*/
430 ret
= xhci_setup_msi(xhci
);
433 hcd
->msi_enabled
= 1;
438 xhci_err(xhci
, "No msi-x/msi found and no IRQ in BIOS\n");
443 if (!strlen(hcd
->irq_descr
))
444 snprintf(hcd
->irq_descr
, sizeof(hcd
->irq_descr
), "%s:usb%d",
445 hcd
->driver
->description
, hcd
->self
.busnum
);
447 /* fall back to legacy interrupt*/
448 ret
= request_irq(pdev
->irq
, &usb_hcd_irq
, IRQF_SHARED
,
449 hcd
->irq_descr
, hcd
);
451 xhci_err(xhci
, "request interrupt %d failed\n",
455 hcd
->irq
= pdev
->irq
;
461 static inline int xhci_try_enable_msi(struct usb_hcd
*hcd
)
466 static inline void xhci_cleanup_msix(struct xhci_hcd
*xhci
)
470 static inline void xhci_msix_sync_irqs(struct xhci_hcd
*xhci
)
476 static void compliance_mode_recovery(struct timer_list
*t
)
478 struct xhci_hcd
*xhci
;
480 struct xhci_hub
*rhub
;
484 xhci
= from_timer(xhci
, t
, comp_mode_recovery_timer
);
485 rhub
= &xhci
->usb3_rhub
;
487 for (i
= 0; i
< rhub
->num_ports
; i
++) {
488 temp
= readl(rhub
->ports
[i
]->addr
);
489 if ((temp
& PORT_PLS_MASK
) == USB_SS_PORT_LS_COMP_MOD
) {
491 * Compliance Mode Detected. Letting USB Core
492 * handle the Warm Reset
494 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
495 "Compliance mode detected->port %d",
497 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
498 "Attempting compliance mode recovery");
499 hcd
= xhci
->shared_hcd
;
501 if (hcd
->state
== HC_STATE_SUSPENDED
)
502 usb_hcd_resume_root_hub(hcd
);
504 usb_hcd_poll_rh_status(hcd
);
508 if (xhci
->port_status_u0
!= ((1 << rhub
->num_ports
) - 1))
509 mod_timer(&xhci
->comp_mode_recovery_timer
,
510 jiffies
+ msecs_to_jiffies(COMP_MODE_RCVRY_MSECS
));
514 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
515 * that causes ports behind that hardware to enter compliance mode sometimes.
516 * The quirk creates a timer that polls every 2 seconds the link state of
517 * each host controller's port and recovers it by issuing a Warm reset
518 * if Compliance mode is detected, otherwise the port will become "dead" (no
519 * device connections or disconnections will be detected anymore). Becasue no
520 * status event is generated when entering compliance mode (per xhci spec),
521 * this quirk is needed on systems that have the failing hardware installed.
523 static void compliance_mode_recovery_timer_init(struct xhci_hcd
*xhci
)
525 xhci
->port_status_u0
= 0;
526 timer_setup(&xhci
->comp_mode_recovery_timer
, compliance_mode_recovery
,
528 xhci
->comp_mode_recovery_timer
.expires
= jiffies
+
529 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS
);
531 add_timer(&xhci
->comp_mode_recovery_timer
);
532 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
533 "Compliance mode recovery timer initialized");
537 * This function identifies the systems that have installed the SN65LVPE502CP
538 * USB3.0 re-driver and that need the Compliance Mode Quirk.
540 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
542 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
544 const char *dmi_product_name
, *dmi_sys_vendor
;
546 dmi_product_name
= dmi_get_system_info(DMI_PRODUCT_NAME
);
547 dmi_sys_vendor
= dmi_get_system_info(DMI_SYS_VENDOR
);
548 if (!dmi_product_name
|| !dmi_sys_vendor
)
551 if (!(strstr(dmi_sys_vendor
, "Hewlett-Packard")))
554 if (strstr(dmi_product_name
, "Z420") ||
555 strstr(dmi_product_name
, "Z620") ||
556 strstr(dmi_product_name
, "Z820") ||
557 strstr(dmi_product_name
, "Z1 Workstation"))
563 static int xhci_all_ports_seen_u0(struct xhci_hcd
*xhci
)
565 return (xhci
->port_status_u0
== ((1 << xhci
->usb3_rhub
.num_ports
) - 1));
570 * Initialize memory for HCD and xHC (one-time init).
572 * Program the PAGESIZE register, initialize the device context array, create
573 * device contexts (?), set up a command ring segment (or two?), create event
574 * ring (one for now).
576 static int xhci_init(struct usb_hcd
*hcd
)
578 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
581 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "xhci_init");
582 spin_lock_init(&xhci
->lock
);
583 if (xhci
->hci_version
== 0x95 && link_quirk
) {
584 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
585 "QUIRK: Not clearing Link TRB chain bits.");
586 xhci
->quirks
|= XHCI_LINK_TRB_QUIRK
;
588 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
589 "xHCI doesn't need link TRB QUIRK");
591 retval
= xhci_mem_init(xhci
, GFP_KERNEL
);
592 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "Finished xhci_init");
594 /* Initializing Compliance Mode Recovery Data If Needed */
595 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
596 xhci
->quirks
|= XHCI_COMP_MODE_QUIRK
;
597 compliance_mode_recovery_timer_init(xhci
);
603 /*-------------------------------------------------------------------------*/
606 static int xhci_run_finished(struct xhci_hcd
*xhci
)
608 if (xhci_start(xhci
)) {
612 xhci
->shared_hcd
->state
= HC_STATE_RUNNING
;
613 xhci
->cmd_ring_state
= CMD_RING_STATE_RUNNING
;
615 if (xhci
->quirks
& XHCI_NEC_HOST
)
616 xhci_ring_cmd_db(xhci
);
618 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
619 "Finished xhci_run for USB3 roothub");
624 * Start the HC after it was halted.
626 * This function is called by the USB core when the HC driver is added.
627 * Its opposite is xhci_stop().
629 * xhci_init() must be called once before this function can be called.
630 * Reset the HC, enable device slot contexts, program DCBAAP, and
631 * set command ring pointer and event ring pointer.
633 * Setup MSI-X vectors and enable interrupts.
635 int xhci_run(struct usb_hcd
*hcd
)
640 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
642 /* Start the xHCI host controller running only after the USB 2.0 roothub
646 hcd
->uses_new_polling
= 1;
647 if (!usb_hcd_is_primary_hcd(hcd
))
648 return xhci_run_finished(xhci
);
650 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "xhci_run");
652 ret
= xhci_try_enable_msi(hcd
);
656 temp_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
657 temp_64
&= ~ERST_PTR_MASK
;
658 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
659 "ERST deq = 64'h%0lx", (long unsigned int) temp_64
);
661 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
662 "// Set the interrupt modulation register");
663 temp
= readl(&xhci
->ir_set
->irq_control
);
664 temp
&= ~ER_IRQ_INTERVAL_MASK
;
665 temp
|= (xhci
->imod_interval
/ 250) & ER_IRQ_INTERVAL_MASK
;
666 writel(temp
, &xhci
->ir_set
->irq_control
);
668 /* Set the HCD state before we enable the irqs */
669 temp
= readl(&xhci
->op_regs
->command
);
671 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
672 "// Enable interrupts, cmd = 0x%x.", temp
);
673 writel(temp
, &xhci
->op_regs
->command
);
675 temp
= readl(&xhci
->ir_set
->irq_pending
);
676 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
677 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
678 xhci
->ir_set
, (unsigned int) ER_IRQ_ENABLE(temp
));
679 writel(ER_IRQ_ENABLE(temp
), &xhci
->ir_set
->irq_pending
);
681 if (xhci
->quirks
& XHCI_NEC_HOST
) {
682 struct xhci_command
*command
;
684 command
= xhci_alloc_command(xhci
, false, GFP_KERNEL
);
688 ret
= xhci_queue_vendor_command(xhci
, command
, 0, 0, 0,
689 TRB_TYPE(TRB_NEC_GET_FW
));
691 xhci_free_command(xhci
, command
);
693 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
694 "Finished xhci_run for USB2 roothub");
698 xhci_debugfs_init(xhci
);
702 EXPORT_SYMBOL_GPL(xhci_run
);
707 * This function is called by the USB core when the HC driver is removed.
708 * Its opposite is xhci_run().
710 * Disable device contexts, disable IRQs, and quiesce the HC.
711 * Reset the HC, finish any completed transactions, and cleanup memory.
713 static void xhci_stop(struct usb_hcd
*hcd
)
716 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
718 mutex_lock(&xhci
->mutex
);
720 /* Only halt host and free memory after both hcds are removed */
721 if (!usb_hcd_is_primary_hcd(hcd
)) {
722 mutex_unlock(&xhci
->mutex
);
728 spin_lock_irq(&xhci
->lock
);
729 xhci
->xhc_state
|= XHCI_STATE_HALTED
;
730 xhci
->cmd_ring_state
= CMD_RING_STATE_STOPPED
;
732 xhci_reset(xhci
, XHCI_RESET_SHORT_USEC
);
733 spin_unlock_irq(&xhci
->lock
);
735 xhci_cleanup_msix(xhci
);
737 /* Deleting Compliance Mode Recovery Timer */
738 if ((xhci
->quirks
& XHCI_COMP_MODE_QUIRK
) &&
739 (!(xhci_all_ports_seen_u0(xhci
)))) {
740 del_timer_sync(&xhci
->comp_mode_recovery_timer
);
741 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
742 "%s: compliance mode recovery timer deleted",
746 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
749 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
750 "// Disabling event ring interrupts");
751 temp
= readl(&xhci
->op_regs
->status
);
752 writel((temp
& ~0x1fff) | STS_EINT
, &xhci
->op_regs
->status
);
753 temp
= readl(&xhci
->ir_set
->irq_pending
);
754 writel(ER_IRQ_DISABLE(temp
), &xhci
->ir_set
->irq_pending
);
756 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "cleaning up memory");
757 xhci_mem_cleanup(xhci
);
758 xhci_debugfs_exit(xhci
);
759 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
760 "xhci_stop completed - status = %x",
761 readl(&xhci
->op_regs
->status
));
762 mutex_unlock(&xhci
->mutex
);
766 * Shutdown HC (not bus-specific)
768 * This is called when the machine is rebooting or halting. We assume that the
769 * machine will be powered off, and the HC's internal state will be reset.
770 * Don't bother to free memory.
772 * This will only ever be called with the main usb_hcd (the USB3 roothub).
774 void xhci_shutdown(struct usb_hcd
*hcd
)
776 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
778 if (xhci
->quirks
& XHCI_SPURIOUS_REBOOT
)
779 usb_disable_xhci_ports(to_pci_dev(hcd
->self
.sysdev
));
781 spin_lock_irq(&xhci
->lock
);
783 /* Workaround for spurious wakeups at shutdown with HSW */
784 if (xhci
->quirks
& XHCI_SPURIOUS_WAKEUP
)
785 xhci_reset(xhci
, XHCI_RESET_SHORT_USEC
);
786 spin_unlock_irq(&xhci
->lock
);
788 xhci_cleanup_msix(xhci
);
790 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
791 "xhci_shutdown completed - status = %x",
792 readl(&xhci
->op_regs
->status
));
794 EXPORT_SYMBOL_GPL(xhci_shutdown
);
797 static void xhci_save_registers(struct xhci_hcd
*xhci
)
799 xhci
->s3
.command
= readl(&xhci
->op_regs
->command
);
800 xhci
->s3
.dev_nt
= readl(&xhci
->op_regs
->dev_notification
);
801 xhci
->s3
.dcbaa_ptr
= xhci_read_64(xhci
, &xhci
->op_regs
->dcbaa_ptr
);
802 xhci
->s3
.config_reg
= readl(&xhci
->op_regs
->config_reg
);
803 xhci
->s3
.erst_size
= readl(&xhci
->ir_set
->erst_size
);
804 xhci
->s3
.erst_base
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_base
);
805 xhci
->s3
.erst_dequeue
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
806 xhci
->s3
.irq_pending
= readl(&xhci
->ir_set
->irq_pending
);
807 xhci
->s3
.irq_control
= readl(&xhci
->ir_set
->irq_control
);
810 static void xhci_restore_registers(struct xhci_hcd
*xhci
)
812 writel(xhci
->s3
.command
, &xhci
->op_regs
->command
);
813 writel(xhci
->s3
.dev_nt
, &xhci
->op_regs
->dev_notification
);
814 xhci_write_64(xhci
, xhci
->s3
.dcbaa_ptr
, &xhci
->op_regs
->dcbaa_ptr
);
815 writel(xhci
->s3
.config_reg
, &xhci
->op_regs
->config_reg
);
816 writel(xhci
->s3
.erst_size
, &xhci
->ir_set
->erst_size
);
817 xhci_write_64(xhci
, xhci
->s3
.erst_base
, &xhci
->ir_set
->erst_base
);
818 xhci_write_64(xhci
, xhci
->s3
.erst_dequeue
, &xhci
->ir_set
->erst_dequeue
);
819 writel(xhci
->s3
.irq_pending
, &xhci
->ir_set
->irq_pending
);
820 writel(xhci
->s3
.irq_control
, &xhci
->ir_set
->irq_control
);
823 static void xhci_set_cmd_ring_deq(struct xhci_hcd
*xhci
)
827 /* step 2: initialize command ring buffer */
828 val_64
= xhci_read_64(xhci
, &xhci
->op_regs
->cmd_ring
);
829 val_64
= (val_64
& (u64
) CMD_RING_RSVD_BITS
) |
830 (xhci_trb_virt_to_dma(xhci
->cmd_ring
->deq_seg
,
831 xhci
->cmd_ring
->dequeue
) &
832 (u64
) ~CMD_RING_RSVD_BITS
) |
833 xhci
->cmd_ring
->cycle_state
;
834 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
835 "// Setting command ring address to 0x%llx",
836 (long unsigned long) val_64
);
837 xhci_write_64(xhci
, val_64
, &xhci
->op_regs
->cmd_ring
);
841 * The whole command ring must be cleared to zero when we suspend the host.
843 * The host doesn't save the command ring pointer in the suspend well, so we
844 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
845 * aligned, because of the reserved bits in the command ring dequeue pointer
846 * register. Therefore, we can't just set the dequeue pointer back in the
847 * middle of the ring (TRBs are 16-byte aligned).
849 static void xhci_clear_command_ring(struct xhci_hcd
*xhci
)
851 struct xhci_ring
*ring
;
852 struct xhci_segment
*seg
;
854 ring
= xhci
->cmd_ring
;
858 sizeof(union xhci_trb
) * (TRBS_PER_SEGMENT
- 1));
859 seg
->trbs
[TRBS_PER_SEGMENT
- 1].link
.control
&=
860 cpu_to_le32(~TRB_CYCLE
);
862 } while (seg
!= ring
->deq_seg
);
864 /* Reset the software enqueue and dequeue pointers */
865 ring
->deq_seg
= ring
->first_seg
;
866 ring
->dequeue
= ring
->first_seg
->trbs
;
867 ring
->enq_seg
= ring
->deq_seg
;
868 ring
->enqueue
= ring
->dequeue
;
870 ring
->num_trbs_free
= ring
->num_segs
* (TRBS_PER_SEGMENT
- 1) - 1;
872 * Ring is now zeroed, so the HW should look for change of ownership
873 * when the cycle bit is set to 1.
875 ring
->cycle_state
= 1;
878 * Reset the hardware dequeue pointer.
879 * Yes, this will need to be re-written after resume, but we're paranoid
880 * and want to make sure the hardware doesn't access bogus memory
881 * because, say, the BIOS or an SMI started the host without changing
882 * the command ring pointers.
884 xhci_set_cmd_ring_deq(xhci
);
888 * Disable port wake bits if do_wakeup is not set.
890 * Also clear a possible internal port wake state left hanging for ports that
891 * detected termination but never successfully enumerated (trained to 0U).
892 * Internal wake causes immediate xHCI wake after suspend. PORT_CSC write done
893 * at enumeration clears this wake, force one here as well for unconnected ports
896 static void xhci_disable_hub_port_wake(struct xhci_hcd
*xhci
,
897 struct xhci_hub
*rhub
,
904 spin_lock_irqsave(&xhci
->lock
, flags
);
906 for (i
= 0; i
< rhub
->num_ports
; i
++) {
907 portsc
= readl(rhub
->ports
[i
]->addr
);
908 t1
= xhci_port_state_to_neutral(portsc
);
911 /* clear wake bits if do_wake is not set */
913 t2
&= ~PORT_WAKE_BITS
;
915 /* Don't touch csc bit if connected or connect change is set */
916 if (!(portsc
& (PORT_CSC
| PORT_CONNECT
)))
920 writel(t2
, rhub
->ports
[i
]->addr
);
921 xhci_dbg(xhci
, "config port %d-%d wake bits, portsc: 0x%x, write: 0x%x\n",
922 rhub
->hcd
->self
.busnum
, i
+ 1, portsc
, t2
);
925 spin_unlock_irqrestore(&xhci
->lock
, flags
);
928 static bool xhci_pending_portevent(struct xhci_hcd
*xhci
)
930 struct xhci_port
**ports
;
935 status
= readl(&xhci
->op_regs
->status
);
936 if (status
& STS_EINT
)
939 * Checking STS_EINT is not enough as there is a lag between a change
940 * bit being set and the Port Status Change Event that it generated
941 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
944 port_index
= xhci
->usb2_rhub
.num_ports
;
945 ports
= xhci
->usb2_rhub
.ports
;
946 while (port_index
--) {
947 portsc
= readl(ports
[port_index
]->addr
);
948 if (portsc
& PORT_CHANGE_MASK
||
949 (portsc
& PORT_PLS_MASK
) == XDEV_RESUME
)
952 port_index
= xhci
->usb3_rhub
.num_ports
;
953 ports
= xhci
->usb3_rhub
.ports
;
954 while (port_index
--) {
955 portsc
= readl(ports
[port_index
]->addr
);
956 if (portsc
& PORT_CHANGE_MASK
||
957 (portsc
& PORT_PLS_MASK
) == XDEV_RESUME
)
964 * Stop HC (not bus-specific)
966 * This is called when the machine transition into S3/S4 mode.
969 int xhci_suspend(struct xhci_hcd
*xhci
, bool do_wakeup
)
972 unsigned int delay
= XHCI_MAX_HALT_USEC
* 2;
973 struct usb_hcd
*hcd
= xhci_to_hcd(xhci
);
980 if (hcd
->state
!= HC_STATE_SUSPENDED
||
981 xhci
->shared_hcd
->state
!= HC_STATE_SUSPENDED
)
984 /* Clear root port wake on bits if wakeup not allowed. */
985 xhci_disable_hub_port_wake(xhci
, &xhci
->usb3_rhub
, do_wakeup
);
986 xhci_disable_hub_port_wake(xhci
, &xhci
->usb2_rhub
, do_wakeup
);
988 if (!HCD_HW_ACCESSIBLE(hcd
))
991 xhci_dbc_suspend(xhci
);
993 /* Don't poll the roothubs on bus suspend. */
994 xhci_dbg(xhci
, "%s: stopping usb%d port polling.\n",
995 __func__
, hcd
->self
.busnum
);
996 clear_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
997 del_timer_sync(&hcd
->rh_timer
);
998 clear_bit(HCD_FLAG_POLL_RH
, &xhci
->shared_hcd
->flags
);
999 del_timer_sync(&xhci
->shared_hcd
->rh_timer
);
1001 if (xhci
->quirks
& XHCI_SUSPEND_DELAY
)
1002 usleep_range(1000, 1500);
1004 spin_lock_irq(&xhci
->lock
);
1005 clear_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
1006 clear_bit(HCD_FLAG_HW_ACCESSIBLE
, &xhci
->shared_hcd
->flags
);
1007 /* step 1: stop endpoint */
1008 /* skipped assuming that port suspend has done */
1010 /* step 2: clear Run/Stop bit */
1011 command
= readl(&xhci
->op_regs
->command
);
1012 command
&= ~CMD_RUN
;
1013 writel(command
, &xhci
->op_regs
->command
);
1015 /* Some chips from Fresco Logic need an extraordinary delay */
1016 delay
*= (xhci
->quirks
& XHCI_SLOW_SUSPEND
) ? 10 : 1;
1018 if (xhci_handshake(&xhci
->op_regs
->status
,
1019 STS_HALT
, STS_HALT
, delay
)) {
1020 xhci_warn(xhci
, "WARN: xHC CMD_RUN timeout\n");
1021 spin_unlock_irq(&xhci
->lock
);
1024 xhci_clear_command_ring(xhci
);
1026 /* step 3: save registers */
1027 xhci_save_registers(xhci
);
1029 /* step 4: set CSS flag */
1030 command
= readl(&xhci
->op_regs
->command
);
1032 writel(command
, &xhci
->op_regs
->command
);
1033 xhci
->broken_suspend
= 0;
1034 if (xhci_handshake(&xhci
->op_regs
->status
,
1035 STS_SAVE
, 0, 20 * 1000)) {
1037 * AMD SNPS xHC 3.0 occasionally does not clear the
1038 * SSS bit of USBSTS and when driver tries to poll
1039 * to see if the xHC clears BIT(8) which never happens
1040 * and driver assumes that controller is not responding
1041 * and times out. To workaround this, its good to check
1042 * if SRE and HCE bits are not set (as per xhci
1043 * Section 5.4.2) and bypass the timeout.
1045 res
= readl(&xhci
->op_regs
->status
);
1046 if ((xhci
->quirks
& XHCI_SNPS_BROKEN_SUSPEND
) &&
1047 (((res
& STS_SRE
) == 0) &&
1048 ((res
& STS_HCE
) == 0))) {
1049 xhci
->broken_suspend
= 1;
1051 xhci_warn(xhci
, "WARN: xHC save state timeout\n");
1052 spin_unlock_irq(&xhci
->lock
);
1056 spin_unlock_irq(&xhci
->lock
);
1059 * Deleting Compliance Mode Recovery Timer because the xHCI Host
1060 * is about to be suspended.
1062 if ((xhci
->quirks
& XHCI_COMP_MODE_QUIRK
) &&
1063 (!(xhci_all_ports_seen_u0(xhci
)))) {
1064 del_timer_sync(&xhci
->comp_mode_recovery_timer
);
1065 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
1066 "%s: compliance mode recovery timer deleted",
1070 /* step 5: remove core well power */
1071 /* synchronize irq when using MSI-X */
1072 xhci_msix_sync_irqs(xhci
);
1076 EXPORT_SYMBOL_GPL(xhci_suspend
);
1079 * start xHC (not bus-specific)
1081 * This is called when the machine transition from S3/S4 mode.
1084 int xhci_resume(struct xhci_hcd
*xhci
, bool hibernated
)
1086 u32 command
, temp
= 0;
1087 struct usb_hcd
*hcd
= xhci_to_hcd(xhci
);
1088 struct usb_hcd
*secondary_hcd
;
1090 bool comp_timer_running
= false;
1091 bool pending_portevent
= false;
1092 bool reinit_xhc
= false;
1097 /* Wait a bit if either of the roothubs need to settle from the
1098 * transition into bus suspend.
1101 if (time_before(jiffies
, xhci
->usb2_rhub
.bus_state
.next_statechange
) ||
1102 time_before(jiffies
, xhci
->usb3_rhub
.bus_state
.next_statechange
))
1105 set_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
);
1106 set_bit(HCD_FLAG_HW_ACCESSIBLE
, &xhci
->shared_hcd
->flags
);
1108 spin_lock_irq(&xhci
->lock
);
1110 if (hibernated
|| xhci
->quirks
& XHCI_RESET_ON_RESUME
|| xhci
->broken_suspend
)
1115 * Some controllers might lose power during suspend, so wait
1116 * for controller not ready bit to clear, just as in xHC init.
1118 retval
= xhci_handshake(&xhci
->op_regs
->status
,
1119 STS_CNR
, 0, 10 * 1000 * 1000);
1121 xhci_warn(xhci
, "Controller not ready at resume %d\n",
1123 spin_unlock_irq(&xhci
->lock
);
1126 /* step 1: restore register */
1127 xhci_restore_registers(xhci
);
1128 /* step 2: initialize command ring buffer */
1129 xhci_set_cmd_ring_deq(xhci
);
1130 /* step 3: restore state and start state*/
1131 /* step 3: set CRS flag */
1132 command
= readl(&xhci
->op_regs
->command
);
1134 writel(command
, &xhci
->op_regs
->command
);
1136 * Some controllers take up to 55+ ms to complete the controller
1137 * restore so setting the timeout to 100ms. Xhci specification
1138 * doesn't mention any timeout value.
1140 if (xhci_handshake(&xhci
->op_regs
->status
,
1141 STS_RESTORE
, 0, 100 * 1000)) {
1142 xhci_warn(xhci
, "WARN: xHC restore state timeout\n");
1143 spin_unlock_irq(&xhci
->lock
);
1148 temp
= readl(&xhci
->op_regs
->status
);
1150 /* re-initialize the HC on Restore Error, or Host Controller Error */
1151 if (temp
& (STS_SRE
| STS_HCE
)) {
1153 xhci_warn(xhci
, "xHC error in resume, USBSTS 0x%x, Reinit\n", temp
);
1157 if ((xhci
->quirks
& XHCI_COMP_MODE_QUIRK
) &&
1158 !(xhci_all_ports_seen_u0(xhci
))) {
1159 del_timer_sync(&xhci
->comp_mode_recovery_timer
);
1160 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
1161 "Compliance Mode Recovery Timer deleted!");
1164 /* Let the USB core know _both_ roothubs lost power. */
1165 usb_root_hub_lost_power(xhci
->main_hcd
->self
.root_hub
);
1166 usb_root_hub_lost_power(xhci
->shared_hcd
->self
.root_hub
);
1168 xhci_dbg(xhci
, "Stop HCD\n");
1170 xhci_zero_64b_regs(xhci
);
1171 retval
= xhci_reset(xhci
, XHCI_RESET_LONG_USEC
);
1172 spin_unlock_irq(&xhci
->lock
);
1175 xhci_cleanup_msix(xhci
);
1177 xhci_dbg(xhci
, "// Disabling event ring interrupts\n");
1178 temp
= readl(&xhci
->op_regs
->status
);
1179 writel((temp
& ~0x1fff) | STS_EINT
, &xhci
->op_regs
->status
);
1180 temp
= readl(&xhci
->ir_set
->irq_pending
);
1181 writel(ER_IRQ_DISABLE(temp
), &xhci
->ir_set
->irq_pending
);
1183 xhci_dbg(xhci
, "cleaning up memory\n");
1184 xhci_mem_cleanup(xhci
);
1185 xhci_debugfs_exit(xhci
);
1186 xhci_dbg(xhci
, "xhci_stop completed - status = %x\n",
1187 readl(&xhci
->op_regs
->status
));
1189 /* USB core calls the PCI reinit and start functions twice:
1190 * first with the primary HCD, and then with the secondary HCD.
1191 * If we don't do the same, the host will never be started.
1193 if (!usb_hcd_is_primary_hcd(hcd
))
1194 secondary_hcd
= hcd
;
1196 secondary_hcd
= xhci
->shared_hcd
;
1198 xhci_dbg(xhci
, "Initialize the xhci_hcd\n");
1199 retval
= xhci_init(hcd
->primary_hcd
);
1202 comp_timer_running
= true;
1204 xhci_dbg(xhci
, "Start the primary HCD\n");
1205 retval
= xhci_run(hcd
->primary_hcd
);
1207 xhci_dbg(xhci
, "Start the secondary HCD\n");
1208 retval
= xhci_run(secondary_hcd
);
1210 hcd
->state
= HC_STATE_SUSPENDED
;
1211 xhci
->shared_hcd
->state
= HC_STATE_SUSPENDED
;
1215 /* step 4: set Run/Stop bit */
1216 command
= readl(&xhci
->op_regs
->command
);
1218 writel(command
, &xhci
->op_regs
->command
);
1219 xhci_handshake(&xhci
->op_regs
->status
, STS_HALT
,
1222 /* step 5: walk topology and initialize portsc,
1223 * portpmsc and portli
1225 /* this is done in bus_resume */
1227 /* step 6: restart each of the previously
1228 * Running endpoints by ringing their doorbells
1231 spin_unlock_irq(&xhci
->lock
);
1233 xhci_dbc_resume(xhci
);
1238 * Resume roothubs only if there are pending events.
1239 * USB 3 devices resend U3 LFPS wake after a 100ms delay if
1240 * the first wake signalling failed, give it that chance.
1242 pending_portevent
= xhci_pending_portevent(xhci
);
1243 if (!pending_portevent
) {
1245 pending_portevent
= xhci_pending_portevent(xhci
);
1248 if (pending_portevent
) {
1249 usb_hcd_resume_root_hub(xhci
->shared_hcd
);
1250 usb_hcd_resume_root_hub(hcd
);
1254 * If system is subject to the Quirk, Compliance Mode Timer needs to
1255 * be re-initialized Always after a system resume. Ports are subject
1256 * to suffer the Compliance Mode issue again. It doesn't matter if
1257 * ports have entered previously to U0 before system's suspension.
1259 if ((xhci
->quirks
& XHCI_COMP_MODE_QUIRK
) && !comp_timer_running
)
1260 compliance_mode_recovery_timer_init(xhci
);
1262 if (xhci
->quirks
& XHCI_ASMEDIA_MODIFY_FLOWCONTROL
)
1263 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd
->self
.controller
));
1265 /* Re-enable port polling. */
1266 xhci_dbg(xhci
, "%s: starting usb%d port polling.\n",
1267 __func__
, hcd
->self
.busnum
);
1268 set_bit(HCD_FLAG_POLL_RH
, &xhci
->shared_hcd
->flags
);
1269 usb_hcd_poll_rh_status(xhci
->shared_hcd
);
1270 set_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
1271 usb_hcd_poll_rh_status(hcd
);
1275 EXPORT_SYMBOL_GPL(xhci_resume
);
1276 #endif /* CONFIG_PM */
1278 /*-------------------------------------------------------------------------*/
1280 static int xhci_map_temp_buffer(struct usb_hcd
*hcd
, struct urb
*urb
)
1284 unsigned int buf_len
;
1285 enum dma_data_direction dir
;
1287 dir
= usb_urb_dir_in(urb
) ? DMA_FROM_DEVICE
: DMA_TO_DEVICE
;
1288 buf_len
= urb
->transfer_buffer_length
;
1290 temp
= kzalloc_node(buf_len
, GFP_ATOMIC
,
1291 dev_to_node(hcd
->self
.sysdev
));
1293 if (usb_urb_dir_out(urb
))
1294 sg_pcopy_to_buffer(urb
->sg
, urb
->num_sgs
,
1297 urb
->transfer_buffer
= temp
;
1298 urb
->transfer_dma
= dma_map_single(hcd
->self
.sysdev
,
1299 urb
->transfer_buffer
,
1300 urb
->transfer_buffer_length
,
1303 if (dma_mapping_error(hcd
->self
.sysdev
,
1304 urb
->transfer_dma
)) {
1308 urb
->transfer_flags
|= URB_DMA_MAP_SINGLE
;
1314 static bool xhci_urb_temp_buffer_required(struct usb_hcd
*hcd
,
1319 unsigned int len
= 0;
1320 unsigned int trb_size
;
1321 unsigned int max_pkt
;
1322 struct scatterlist
*sg
;
1323 struct scatterlist
*tail_sg
;
1326 max_pkt
= usb_endpoint_maxp(&urb
->ep
->desc
);
1331 if (urb
->dev
->speed
>= USB_SPEED_SUPER
)
1332 trb_size
= TRB_CACHE_SIZE_SS
;
1334 trb_size
= TRB_CACHE_SIZE_HS
;
1336 if (urb
->transfer_buffer_length
!= 0 &&
1337 !(urb
->transfer_flags
& URB_NO_TRANSFER_DMA_MAP
)) {
1338 for_each_sg(urb
->sg
, sg
, urb
->num_sgs
, i
) {
1339 len
= len
+ sg
->length
;
1340 if (i
> trb_size
- 2) {
1341 len
= len
- tail_sg
->length
;
1342 if (len
< max_pkt
) {
1347 tail_sg
= sg_next(tail_sg
);
1354 static void xhci_unmap_temp_buf(struct usb_hcd
*hcd
, struct urb
*urb
)
1357 unsigned int buf_len
;
1358 enum dma_data_direction dir
;
1360 dir
= usb_urb_dir_in(urb
) ? DMA_FROM_DEVICE
: DMA_TO_DEVICE
;
1362 buf_len
= urb
->transfer_buffer_length
;
1364 if (IS_ENABLED(CONFIG_HAS_DMA
) &&
1365 (urb
->transfer_flags
& URB_DMA_MAP_SINGLE
))
1366 dma_unmap_single(hcd
->self
.sysdev
,
1368 urb
->transfer_buffer_length
,
1371 if (usb_urb_dir_in(urb
)) {
1372 len
= sg_pcopy_from_buffer(urb
->sg
, urb
->num_sgs
,
1373 urb
->transfer_buffer
,
1376 if (len
!= buf_len
) {
1377 xhci_dbg(hcd_to_xhci(hcd
),
1378 "Copy from tmp buf to urb sg list failed\n");
1379 urb
->actual_length
= len
;
1382 urb
->transfer_flags
&= ~URB_DMA_MAP_SINGLE
;
1383 kfree(urb
->transfer_buffer
);
1384 urb
->transfer_buffer
= NULL
;
1388 * Bypass the DMA mapping if URB is suitable for Immediate Transfer (IDT),
1389 * we'll copy the actual data into the TRB address register. This is limited to
1390 * transfers up to 8 bytes on output endpoints of any kind with wMaxPacketSize
1391 * >= 8 bytes. If suitable for IDT only one Transfer TRB per TD is allowed.
1393 static int xhci_map_urb_for_dma(struct usb_hcd
*hcd
, struct urb
*urb
,
1396 struct xhci_hcd
*xhci
;
1398 xhci
= hcd_to_xhci(hcd
);
1400 if (xhci_urb_suitable_for_idt(urb
))
1403 if (xhci
->quirks
& XHCI_SG_TRB_CACHE_SIZE_QUIRK
) {
1404 if (xhci_urb_temp_buffer_required(hcd
, urb
))
1405 return xhci_map_temp_buffer(hcd
, urb
);
1407 return usb_hcd_map_urb_for_dma(hcd
, urb
, mem_flags
);
1410 static void xhci_unmap_urb_for_dma(struct usb_hcd
*hcd
, struct urb
*urb
)
1412 struct xhci_hcd
*xhci
;
1413 bool unmap_temp_buf
= false;
1415 xhci
= hcd_to_xhci(hcd
);
1417 if (urb
->num_sgs
&& (urb
->transfer_flags
& URB_DMA_MAP_SINGLE
))
1418 unmap_temp_buf
= true;
1420 if ((xhci
->quirks
& XHCI_SG_TRB_CACHE_SIZE_QUIRK
) && unmap_temp_buf
)
1421 xhci_unmap_temp_buf(hcd
, urb
);
1423 usb_hcd_unmap_urb_for_dma(hcd
, urb
);
1427 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1428 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1429 * value to right shift 1 for the bitmask.
1431 * Index = (epnum * 2) + direction - 1,
1432 * where direction = 0 for OUT, 1 for IN.
1433 * For control endpoints, the IN index is used (OUT index is unused), so
1434 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1436 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor
*desc
)
1439 if (usb_endpoint_xfer_control(desc
))
1440 index
= (unsigned int) (usb_endpoint_num(desc
)*2);
1442 index
= (unsigned int) (usb_endpoint_num(desc
)*2) +
1443 (usb_endpoint_dir_in(desc
) ? 1 : 0) - 1;
1446 EXPORT_SYMBOL_GPL(xhci_get_endpoint_index
);
1448 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1449 * address from the XHCI endpoint index.
1451 unsigned int xhci_get_endpoint_address(unsigned int ep_index
)
1453 unsigned int number
= DIV_ROUND_UP(ep_index
, 2);
1454 unsigned int direction
= ep_index
% 2 ? USB_DIR_OUT
: USB_DIR_IN
;
1455 return direction
| number
;
1458 /* Find the flag for this endpoint (for use in the control context). Use the
1459 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1462 static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor
*desc
)
1464 return 1 << (xhci_get_endpoint_index(desc
) + 1);
1467 /* Compute the last valid endpoint context index. Basically, this is the
1468 * endpoint index plus one. For slot contexts with more than valid endpoint,
1469 * we find the most significant bit set in the added contexts flags.
1470 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1471 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1473 unsigned int xhci_last_valid_endpoint(u32 added_ctxs
)
1475 return fls(added_ctxs
) - 1;
1478 /* Returns 1 if the arguments are OK;
1479 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1481 static int xhci_check_args(struct usb_hcd
*hcd
, struct usb_device
*udev
,
1482 struct usb_host_endpoint
*ep
, int check_ep
, bool check_virt_dev
,
1484 struct xhci_hcd
*xhci
;
1485 struct xhci_virt_device
*virt_dev
;
1487 if (!hcd
|| (check_ep
&& !ep
) || !udev
) {
1488 pr_debug("xHCI %s called with invalid args\n", func
);
1491 if (!udev
->parent
) {
1492 pr_debug("xHCI %s called for root hub\n", func
);
1496 xhci
= hcd_to_xhci(hcd
);
1497 if (check_virt_dev
) {
1498 if (!udev
->slot_id
|| !xhci
->devs
[udev
->slot_id
]) {
1499 xhci_dbg(xhci
, "xHCI %s called with unaddressed device\n",
1504 virt_dev
= xhci
->devs
[udev
->slot_id
];
1505 if (virt_dev
->udev
!= udev
) {
1506 xhci_dbg(xhci
, "xHCI %s called with udev and "
1507 "virt_dev does not match\n", func
);
1512 if (xhci
->xhc_state
& XHCI_STATE_HALTED
)
1518 static int xhci_configure_endpoint(struct xhci_hcd
*xhci
,
1519 struct usb_device
*udev
, struct xhci_command
*command
,
1520 bool ctx_change
, bool must_succeed
);
1523 * Full speed devices may have a max packet size greater than 8 bytes, but the
1524 * USB core doesn't know that until it reads the first 8 bytes of the
1525 * descriptor. If the usb_device's max packet size changes after that point,
1526 * we need to issue an evaluate context command and wait on it.
1528 static int xhci_check_maxpacket(struct xhci_hcd
*xhci
, unsigned int slot_id
,
1529 unsigned int ep_index
, struct urb
*urb
, gfp_t mem_flags
)
1531 struct xhci_container_ctx
*out_ctx
;
1532 struct xhci_input_control_ctx
*ctrl_ctx
;
1533 struct xhci_ep_ctx
*ep_ctx
;
1534 struct xhci_command
*command
;
1535 int max_packet_size
;
1536 int hw_max_packet_size
;
1539 out_ctx
= xhci
->devs
[slot_id
]->out_ctx
;
1540 ep_ctx
= xhci_get_ep_ctx(xhci
, out_ctx
, ep_index
);
1541 hw_max_packet_size
= MAX_PACKET_DECODED(le32_to_cpu(ep_ctx
->ep_info2
));
1542 max_packet_size
= usb_endpoint_maxp(&urb
->dev
->ep0
.desc
);
1543 if (hw_max_packet_size
!= max_packet_size
) {
1544 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
1545 "Max Packet Size for ep 0 changed.");
1546 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
1547 "Max packet size in usb_device = %d",
1549 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
1550 "Max packet size in xHCI HW = %d",
1551 hw_max_packet_size
);
1552 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
1553 "Issuing evaluate context command.");
1555 /* Set up the input context flags for the command */
1556 /* FIXME: This won't work if a non-default control endpoint
1557 * changes max packet sizes.
1560 command
= xhci_alloc_command(xhci
, true, mem_flags
);
1564 command
->in_ctx
= xhci
->devs
[slot_id
]->in_ctx
;
1565 ctrl_ctx
= xhci_get_input_control_ctx(command
->in_ctx
);
1567 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
1570 goto command_cleanup
;
1572 /* Set up the modified control endpoint 0 */
1573 xhci_endpoint_copy(xhci
, xhci
->devs
[slot_id
]->in_ctx
,
1574 xhci
->devs
[slot_id
]->out_ctx
, ep_index
);
1576 ep_ctx
= xhci_get_ep_ctx(xhci
, command
->in_ctx
, ep_index
);
1577 ep_ctx
->ep_info
&= cpu_to_le32(~EP_STATE_MASK
);/* must clear */
1578 ep_ctx
->ep_info2
&= cpu_to_le32(~MAX_PACKET_MASK
);
1579 ep_ctx
->ep_info2
|= cpu_to_le32(MAX_PACKET(max_packet_size
));
1581 ctrl_ctx
->add_flags
= cpu_to_le32(EP0_FLAG
);
1582 ctrl_ctx
->drop_flags
= 0;
1584 ret
= xhci_configure_endpoint(xhci
, urb
->dev
, command
,
1587 /* Clean up the input context for later use by bandwidth
1590 ctrl_ctx
->add_flags
= cpu_to_le32(SLOT_FLAG
);
1592 kfree(command
->completion
);
1599 * non-error returns are a promise to giveback() the urb later
1600 * we drop ownership so next owner (or urb unlink) can get it
1602 static int xhci_urb_enqueue(struct usb_hcd
*hcd
, struct urb
*urb
, gfp_t mem_flags
)
1604 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
1605 unsigned long flags
;
1607 unsigned int slot_id
, ep_index
;
1608 unsigned int *ep_state
;
1609 struct urb_priv
*urb_priv
;
1614 ret
= xhci_check_args(hcd
, urb
->dev
, urb
->ep
,
1615 true, true, __func__
);
1617 return ret
? ret
: -EINVAL
;
1619 slot_id
= urb
->dev
->slot_id
;
1620 ep_index
= xhci_get_endpoint_index(&urb
->ep
->desc
);
1621 ep_state
= &xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
;
1623 if (!HCD_HW_ACCESSIBLE(hcd
))
1626 if (xhci
->devs
[slot_id
]->flags
& VDEV_PORT_ERROR
) {
1627 xhci_dbg(xhci
, "Can't queue urb, port error, link inactive\n");
1631 if (usb_endpoint_xfer_isoc(&urb
->ep
->desc
))
1632 num_tds
= urb
->number_of_packets
;
1633 else if (usb_endpoint_is_bulk_out(&urb
->ep
->desc
) &&
1634 urb
->transfer_buffer_length
> 0 &&
1635 urb
->transfer_flags
& URB_ZERO_PACKET
&&
1636 !(urb
->transfer_buffer_length
% usb_endpoint_maxp(&urb
->ep
->desc
)))
1641 urb_priv
= kzalloc(struct_size(urb_priv
, td
, num_tds
), mem_flags
);
1645 urb_priv
->num_tds
= num_tds
;
1646 urb_priv
->num_tds_done
= 0;
1647 urb
->hcpriv
= urb_priv
;
1649 trace_xhci_urb_enqueue(urb
);
1651 if (usb_endpoint_xfer_control(&urb
->ep
->desc
)) {
1652 /* Check to see if the max packet size for the default control
1653 * endpoint changed during FS device enumeration
1655 if (urb
->dev
->speed
== USB_SPEED_FULL
) {
1656 ret
= xhci_check_maxpacket(xhci
, slot_id
,
1657 ep_index
, urb
, mem_flags
);
1659 xhci_urb_free_priv(urb_priv
);
1666 spin_lock_irqsave(&xhci
->lock
, flags
);
1668 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
1669 xhci_dbg(xhci
, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1670 urb
->ep
->desc
.bEndpointAddress
, urb
);
1674 if (*ep_state
& (EP_GETTING_STREAMS
| EP_GETTING_NO_STREAMS
)) {
1675 xhci_warn(xhci
, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1680 if (*ep_state
& EP_SOFT_CLEAR_TOGGLE
) {
1681 xhci_warn(xhci
, "Can't enqueue URB while manually clearing toggle\n");
1686 switch (usb_endpoint_type(&urb
->ep
->desc
)) {
1688 case USB_ENDPOINT_XFER_CONTROL
:
1689 ret
= xhci_queue_ctrl_tx(xhci
, GFP_ATOMIC
, urb
,
1692 case USB_ENDPOINT_XFER_BULK
:
1693 ret
= xhci_queue_bulk_tx(xhci
, GFP_ATOMIC
, urb
,
1696 case USB_ENDPOINT_XFER_INT
:
1697 ret
= xhci_queue_intr_tx(xhci
, GFP_ATOMIC
, urb
,
1700 case USB_ENDPOINT_XFER_ISOC
:
1701 ret
= xhci_queue_isoc_tx_prepare(xhci
, GFP_ATOMIC
, urb
,
1707 xhci_urb_free_priv(urb_priv
);
1710 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1715 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1716 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1717 * should pick up where it left off in the TD, unless a Set Transfer Ring
1718 * Dequeue Pointer is issued.
1720 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1721 * the ring. Since the ring is a contiguous structure, they can't be physically
1722 * removed. Instead, there are two options:
1724 * 1) If the HC is in the middle of processing the URB to be canceled, we
1725 * simply move the ring's dequeue pointer past those TRBs using the Set
1726 * Transfer Ring Dequeue Pointer command. This will be the common case,
1727 * when drivers timeout on the last submitted URB and attempt to cancel.
1729 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1730 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1731 * HC will need to invalidate the any TRBs it has cached after the stop
1732 * endpoint command, as noted in the xHCI 0.95 errata.
1734 * 3) The TD may have completed by the time the Stop Endpoint Command
1735 * completes, so software needs to handle that case too.
1737 * This function should protect against the TD enqueueing code ringing the
1738 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1739 * It also needs to account for multiple cancellations on happening at the same
1740 * time for the same endpoint.
1742 * Note that this function can be called in any context, or so says
1743 * usb_hcd_unlink_urb()
1745 static int xhci_urb_dequeue(struct usb_hcd
*hcd
, struct urb
*urb
, int status
)
1747 unsigned long flags
;
1750 struct xhci_hcd
*xhci
;
1751 struct urb_priv
*urb_priv
;
1753 unsigned int ep_index
;
1754 struct xhci_ring
*ep_ring
;
1755 struct xhci_virt_ep
*ep
;
1756 struct xhci_command
*command
;
1757 struct xhci_virt_device
*vdev
;
1759 xhci
= hcd_to_xhci(hcd
);
1760 spin_lock_irqsave(&xhci
->lock
, flags
);
1762 trace_xhci_urb_dequeue(urb
);
1764 /* Make sure the URB hasn't completed or been unlinked already */
1765 ret
= usb_hcd_check_unlink_urb(hcd
, urb
, status
);
1769 /* give back URB now if we can't queue it for cancel */
1770 vdev
= xhci
->devs
[urb
->dev
->slot_id
];
1771 urb_priv
= urb
->hcpriv
;
1772 if (!vdev
|| !urb_priv
)
1775 ep_index
= xhci_get_endpoint_index(&urb
->ep
->desc
);
1776 ep
= &vdev
->eps
[ep_index
];
1777 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
1778 if (!ep
|| !ep_ring
)
1781 /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1782 temp
= readl(&xhci
->op_regs
->status
);
1783 if (temp
== ~(u32
)0 || xhci
->xhc_state
& XHCI_STATE_DYING
) {
1789 * check ring is not re-allocated since URB was enqueued. If it is, then
1790 * make sure none of the ring related pointers in this URB private data
1791 * are touched, such as td_list, otherwise we overwrite freed data
1793 if (!td_on_ring(&urb_priv
->td
[0], ep_ring
)) {
1794 xhci_err(xhci
, "Canceled URB td not found on endpoint ring");
1795 for (i
= urb_priv
->num_tds_done
; i
< urb_priv
->num_tds
; i
++) {
1796 td
= &urb_priv
->td
[i
];
1797 if (!list_empty(&td
->cancelled_td_list
))
1798 list_del_init(&td
->cancelled_td_list
);
1803 if (xhci
->xhc_state
& XHCI_STATE_HALTED
) {
1804 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
1805 "HC halted, freeing TD manually.");
1806 for (i
= urb_priv
->num_tds_done
;
1807 i
< urb_priv
->num_tds
;
1809 td
= &urb_priv
->td
[i
];
1810 if (!list_empty(&td
->td_list
))
1811 list_del_init(&td
->td_list
);
1812 if (!list_empty(&td
->cancelled_td_list
))
1813 list_del_init(&td
->cancelled_td_list
);
1818 i
= urb_priv
->num_tds_done
;
1819 if (i
< urb_priv
->num_tds
)
1820 xhci_dbg_trace(xhci
, trace_xhci_dbg_cancel_urb
,
1821 "Cancel URB %p, dev %s, ep 0x%x, "
1822 "starting at offset 0x%llx",
1823 urb
, urb
->dev
->devpath
,
1824 urb
->ep
->desc
.bEndpointAddress
,
1825 (unsigned long long) xhci_trb_virt_to_dma(
1826 urb_priv
->td
[i
].start_seg
,
1827 urb_priv
->td
[i
].first_trb
));
1829 for (; i
< urb_priv
->num_tds
; i
++) {
1830 td
= &urb_priv
->td
[i
];
1831 /* TD can already be on cancelled list if ep halted on it */
1832 if (list_empty(&td
->cancelled_td_list
)) {
1833 td
->cancel_status
= TD_DIRTY
;
1834 list_add_tail(&td
->cancelled_td_list
,
1835 &ep
->cancelled_td_list
);
1839 /* Queue a stop endpoint command, but only if this is
1840 * the first cancellation to be handled.
1842 if (!(ep
->ep_state
& EP_STOP_CMD_PENDING
)) {
1843 command
= xhci_alloc_command(xhci
, false, GFP_ATOMIC
);
1848 ep
->ep_state
|= EP_STOP_CMD_PENDING
;
1849 ep
->stop_cmd_timer
.expires
= jiffies
+
1850 XHCI_STOP_EP_CMD_TIMEOUT
* HZ
;
1851 add_timer(&ep
->stop_cmd_timer
);
1852 xhci_queue_stop_endpoint(xhci
, command
, urb
->dev
->slot_id
,
1854 xhci_ring_cmd_db(xhci
);
1857 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1862 xhci_urb_free_priv(urb_priv
);
1863 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
1864 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1865 usb_hcd_giveback_urb(hcd
, urb
, -ESHUTDOWN
);
1869 /* Drop an endpoint from a new bandwidth configuration for this device.
1870 * Only one call to this function is allowed per endpoint before
1871 * check_bandwidth() or reset_bandwidth() must be called.
1872 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1873 * add the endpoint to the schedule with possibly new parameters denoted by a
1874 * different endpoint descriptor in usb_host_endpoint.
1875 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1878 * The USB core will not allow URBs to be queued to an endpoint that is being
1879 * disabled, so there's no need for mutual exclusion to protect
1880 * the xhci->devs[slot_id] structure.
1882 int xhci_drop_endpoint(struct usb_hcd
*hcd
, struct usb_device
*udev
,
1883 struct usb_host_endpoint
*ep
)
1885 struct xhci_hcd
*xhci
;
1886 struct xhci_container_ctx
*in_ctx
, *out_ctx
;
1887 struct xhci_input_control_ctx
*ctrl_ctx
;
1888 unsigned int ep_index
;
1889 struct xhci_ep_ctx
*ep_ctx
;
1891 u32 new_add_flags
, new_drop_flags
;
1894 ret
= xhci_check_args(hcd
, udev
, ep
, 1, true, __func__
);
1897 xhci
= hcd_to_xhci(hcd
);
1898 if (xhci
->xhc_state
& XHCI_STATE_DYING
)
1901 xhci_dbg(xhci
, "%s called for udev %p\n", __func__
, udev
);
1902 drop_flag
= xhci_get_endpoint_flag(&ep
->desc
);
1903 if (drop_flag
== SLOT_FLAG
|| drop_flag
== EP0_FLAG
) {
1904 xhci_dbg(xhci
, "xHCI %s - can't drop slot or ep 0 %#x\n",
1905 __func__
, drop_flag
);
1909 in_ctx
= xhci
->devs
[udev
->slot_id
]->in_ctx
;
1910 out_ctx
= xhci
->devs
[udev
->slot_id
]->out_ctx
;
1911 ctrl_ctx
= xhci_get_input_control_ctx(in_ctx
);
1913 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
1918 ep_index
= xhci_get_endpoint_index(&ep
->desc
);
1919 ep_ctx
= xhci_get_ep_ctx(xhci
, out_ctx
, ep_index
);
1920 /* If the HC already knows the endpoint is disabled,
1921 * or the HCD has noted it is disabled, ignore this request
1923 if ((GET_EP_CTX_STATE(ep_ctx
) == EP_STATE_DISABLED
) ||
1924 le32_to_cpu(ctrl_ctx
->drop_flags
) &
1925 xhci_get_endpoint_flag(&ep
->desc
)) {
1926 /* Do not warn when called after a usb_device_reset */
1927 if (xhci
->devs
[udev
->slot_id
]->eps
[ep_index
].ring
!= NULL
)
1928 xhci_warn(xhci
, "xHCI %s called with disabled ep %p\n",
1933 ctrl_ctx
->drop_flags
|= cpu_to_le32(drop_flag
);
1934 new_drop_flags
= le32_to_cpu(ctrl_ctx
->drop_flags
);
1936 ctrl_ctx
->add_flags
&= cpu_to_le32(~drop_flag
);
1937 new_add_flags
= le32_to_cpu(ctrl_ctx
->add_flags
);
1939 xhci_debugfs_remove_endpoint(xhci
, xhci
->devs
[udev
->slot_id
], ep_index
);
1941 xhci_endpoint_zero(xhci
, xhci
->devs
[udev
->slot_id
], ep
);
1943 xhci_dbg(xhci
, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1944 (unsigned int) ep
->desc
.bEndpointAddress
,
1946 (unsigned int) new_drop_flags
,
1947 (unsigned int) new_add_flags
);
1950 EXPORT_SYMBOL_GPL(xhci_drop_endpoint
);
1952 /* Add an endpoint to a new possible bandwidth configuration for this device.
1953 * Only one call to this function is allowed per endpoint before
1954 * check_bandwidth() or reset_bandwidth() must be called.
1955 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1956 * add the endpoint to the schedule with possibly new parameters denoted by a
1957 * different endpoint descriptor in usb_host_endpoint.
1958 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1961 * The USB core will not allow URBs to be queued to an endpoint until the
1962 * configuration or alt setting is installed in the device, so there's no need
1963 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1965 int xhci_add_endpoint(struct usb_hcd
*hcd
, struct usb_device
*udev
,
1966 struct usb_host_endpoint
*ep
)
1968 struct xhci_hcd
*xhci
;
1969 struct xhci_container_ctx
*in_ctx
;
1970 unsigned int ep_index
;
1971 struct xhci_input_control_ctx
*ctrl_ctx
;
1972 struct xhci_ep_ctx
*ep_ctx
;
1974 u32 new_add_flags
, new_drop_flags
;
1975 struct xhci_virt_device
*virt_dev
;
1978 ret
= xhci_check_args(hcd
, udev
, ep
, 1, true, __func__
);
1980 /* So we won't queue a reset ep command for a root hub */
1984 xhci
= hcd_to_xhci(hcd
);
1985 if (xhci
->xhc_state
& XHCI_STATE_DYING
)
1988 added_ctxs
= xhci_get_endpoint_flag(&ep
->desc
);
1989 if (added_ctxs
== SLOT_FLAG
|| added_ctxs
== EP0_FLAG
) {
1990 /* FIXME when we have to issue an evaluate endpoint command to
1991 * deal with ep0 max packet size changing once we get the
1994 xhci_dbg(xhci
, "xHCI %s - can't add slot or ep 0 %#x\n",
1995 __func__
, added_ctxs
);
1999 virt_dev
= xhci
->devs
[udev
->slot_id
];
2000 in_ctx
= virt_dev
->in_ctx
;
2001 ctrl_ctx
= xhci_get_input_control_ctx(in_ctx
);
2003 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
2008 ep_index
= xhci_get_endpoint_index(&ep
->desc
);
2009 /* If this endpoint is already in use, and the upper layers are trying
2010 * to add it again without dropping it, reject the addition.
2012 if (virt_dev
->eps
[ep_index
].ring
&&
2013 !(le32_to_cpu(ctrl_ctx
->drop_flags
) & added_ctxs
)) {
2014 xhci_warn(xhci
, "Trying to add endpoint 0x%x "
2015 "without dropping it.\n",
2016 (unsigned int) ep
->desc
.bEndpointAddress
);
2020 /* If the HCD has already noted the endpoint is enabled,
2021 * ignore this request.
2023 if (le32_to_cpu(ctrl_ctx
->add_flags
) & added_ctxs
) {
2024 xhci_warn(xhci
, "xHCI %s called with enabled ep %p\n",
2030 * Configuration and alternate setting changes must be done in
2031 * process context, not interrupt context (or so documenation
2032 * for usb_set_interface() and usb_set_configuration() claim).
2034 if (xhci_endpoint_init(xhci
, virt_dev
, udev
, ep
, GFP_NOIO
) < 0) {
2035 dev_dbg(&udev
->dev
, "%s - could not initialize ep %#x\n",
2036 __func__
, ep
->desc
.bEndpointAddress
);
2040 ctrl_ctx
->add_flags
|= cpu_to_le32(added_ctxs
);
2041 new_add_flags
= le32_to_cpu(ctrl_ctx
->add_flags
);
2043 /* If xhci_endpoint_disable() was called for this endpoint, but the
2044 * xHC hasn't been notified yet through the check_bandwidth() call,
2045 * this re-adds a new state for the endpoint from the new endpoint
2046 * descriptors. We must drop and re-add this endpoint, so we leave the
2049 new_drop_flags
= le32_to_cpu(ctrl_ctx
->drop_flags
);
2051 /* Store the usb_device pointer for later use */
2054 ep_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->in_ctx
, ep_index
);
2055 trace_xhci_add_endpoint(ep_ctx
);
2057 xhci_dbg(xhci
, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
2058 (unsigned int) ep
->desc
.bEndpointAddress
,
2060 (unsigned int) new_drop_flags
,
2061 (unsigned int) new_add_flags
);
2064 EXPORT_SYMBOL_GPL(xhci_add_endpoint
);
2066 static void xhci_zero_in_ctx(struct xhci_hcd
*xhci
, struct xhci_virt_device
*virt_dev
)
2068 struct xhci_input_control_ctx
*ctrl_ctx
;
2069 struct xhci_ep_ctx
*ep_ctx
;
2070 struct xhci_slot_ctx
*slot_ctx
;
2073 ctrl_ctx
= xhci_get_input_control_ctx(virt_dev
->in_ctx
);
2075 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
2080 /* When a device's add flag and drop flag are zero, any subsequent
2081 * configure endpoint command will leave that endpoint's state
2082 * untouched. Make sure we don't leave any old state in the input
2083 * endpoint contexts.
2085 ctrl_ctx
->drop_flags
= 0;
2086 ctrl_ctx
->add_flags
= 0;
2087 slot_ctx
= xhci_get_slot_ctx(xhci
, virt_dev
->in_ctx
);
2088 slot_ctx
->dev_info
&= cpu_to_le32(~LAST_CTX_MASK
);
2089 /* Endpoint 0 is always valid */
2090 slot_ctx
->dev_info
|= cpu_to_le32(LAST_CTX(1));
2091 for (i
= 1; i
< 31; i
++) {
2092 ep_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->in_ctx
, i
);
2093 ep_ctx
->ep_info
= 0;
2094 ep_ctx
->ep_info2
= 0;
2096 ep_ctx
->tx_info
= 0;
2100 static int xhci_configure_endpoint_result(struct xhci_hcd
*xhci
,
2101 struct usb_device
*udev
, u32
*cmd_status
)
2105 switch (*cmd_status
) {
2106 case COMP_COMMAND_ABORTED
:
2107 case COMP_COMMAND_RING_STOPPED
:
2108 xhci_warn(xhci
, "Timeout while waiting for configure endpoint command\n");
2111 case COMP_RESOURCE_ERROR
:
2112 dev_warn(&udev
->dev
,
2113 "Not enough host controller resources for new device state.\n");
2115 /* FIXME: can we allocate more resources for the HC? */
2117 case COMP_BANDWIDTH_ERROR
:
2118 case COMP_SECONDARY_BANDWIDTH_ERROR
:
2119 dev_warn(&udev
->dev
,
2120 "Not enough bandwidth for new device state.\n");
2122 /* FIXME: can we go back to the old state? */
2124 case COMP_TRB_ERROR
:
2125 /* the HCD set up something wrong */
2126 dev_warn(&udev
->dev
, "ERROR: Endpoint drop flag = 0, "
2128 "and endpoint is not disabled.\n");
2131 case COMP_INCOMPATIBLE_DEVICE_ERROR
:
2132 dev_warn(&udev
->dev
,
2133 "ERROR: Incompatible device for endpoint configure command.\n");
2137 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
2138 "Successful Endpoint Configure command");
2142 xhci_err(xhci
, "ERROR: unexpected command completion code 0x%x.\n",
2150 static int xhci_evaluate_context_result(struct xhci_hcd
*xhci
,
2151 struct usb_device
*udev
, u32
*cmd_status
)
2155 switch (*cmd_status
) {
2156 case COMP_COMMAND_ABORTED
:
2157 case COMP_COMMAND_RING_STOPPED
:
2158 xhci_warn(xhci
, "Timeout while waiting for evaluate context command\n");
2161 case COMP_PARAMETER_ERROR
:
2162 dev_warn(&udev
->dev
,
2163 "WARN: xHCI driver setup invalid evaluate context command.\n");
2166 case COMP_SLOT_NOT_ENABLED_ERROR
:
2167 dev_warn(&udev
->dev
,
2168 "WARN: slot not enabled for evaluate context command.\n");
2171 case COMP_CONTEXT_STATE_ERROR
:
2172 dev_warn(&udev
->dev
,
2173 "WARN: invalid context state for evaluate context command.\n");
2176 case COMP_INCOMPATIBLE_DEVICE_ERROR
:
2177 dev_warn(&udev
->dev
,
2178 "ERROR: Incompatible device for evaluate context command.\n");
2181 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR
:
2182 /* Max Exit Latency too large error */
2183 dev_warn(&udev
->dev
, "WARN: Max Exit Latency too large\n");
2187 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
2188 "Successful evaluate context command");
2192 xhci_err(xhci
, "ERROR: unexpected command completion code 0x%x.\n",
2200 static u32
xhci_count_num_new_endpoints(struct xhci_hcd
*xhci
,
2201 struct xhci_input_control_ctx
*ctrl_ctx
)
2203 u32 valid_add_flags
;
2204 u32 valid_drop_flags
;
2206 /* Ignore the slot flag (bit 0), and the default control endpoint flag
2207 * (bit 1). The default control endpoint is added during the Address
2208 * Device command and is never removed until the slot is disabled.
2210 valid_add_flags
= le32_to_cpu(ctrl_ctx
->add_flags
) >> 2;
2211 valid_drop_flags
= le32_to_cpu(ctrl_ctx
->drop_flags
) >> 2;
2213 /* Use hweight32 to count the number of ones in the add flags, or
2214 * number of endpoints added. Don't count endpoints that are changed
2215 * (both added and dropped).
2217 return hweight32(valid_add_flags
) -
2218 hweight32(valid_add_flags
& valid_drop_flags
);
2221 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd
*xhci
,
2222 struct xhci_input_control_ctx
*ctrl_ctx
)
2224 u32 valid_add_flags
;
2225 u32 valid_drop_flags
;
2227 valid_add_flags
= le32_to_cpu(ctrl_ctx
->add_flags
) >> 2;
2228 valid_drop_flags
= le32_to_cpu(ctrl_ctx
->drop_flags
) >> 2;
2230 return hweight32(valid_drop_flags
) -
2231 hweight32(valid_add_flags
& valid_drop_flags
);
2235 * We need to reserve the new number of endpoints before the configure endpoint
2236 * command completes. We can't subtract the dropped endpoints from the number
2237 * of active endpoints until the command completes because we can oversubscribe
2238 * the host in this case:
2240 * - the first configure endpoint command drops more endpoints than it adds
2241 * - a second configure endpoint command that adds more endpoints is queued
2242 * - the first configure endpoint command fails, so the config is unchanged
2243 * - the second command may succeed, even though there isn't enough resources
2245 * Must be called with xhci->lock held.
2247 static int xhci_reserve_host_resources(struct xhci_hcd
*xhci
,
2248 struct xhci_input_control_ctx
*ctrl_ctx
)
2252 added_eps
= xhci_count_num_new_endpoints(xhci
, ctrl_ctx
);
2253 if (xhci
->num_active_eps
+ added_eps
> xhci
->limit_active_eps
) {
2254 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
2255 "Not enough ep ctxs: "
2256 "%u active, need to add %u, limit is %u.",
2257 xhci
->num_active_eps
, added_eps
,
2258 xhci
->limit_active_eps
);
2261 xhci
->num_active_eps
+= added_eps
;
2262 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
2263 "Adding %u ep ctxs, %u now active.", added_eps
,
2264 xhci
->num_active_eps
);
2269 * The configure endpoint was failed by the xHC for some other reason, so we
2270 * need to revert the resources that failed configuration would have used.
2272 * Must be called with xhci->lock held.
2274 static void xhci_free_host_resources(struct xhci_hcd
*xhci
,
2275 struct xhci_input_control_ctx
*ctrl_ctx
)
2279 num_failed_eps
= xhci_count_num_new_endpoints(xhci
, ctrl_ctx
);
2280 xhci
->num_active_eps
-= num_failed_eps
;
2281 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
2282 "Removing %u failed ep ctxs, %u now active.",
2284 xhci
->num_active_eps
);
2288 * Now that the command has completed, clean up the active endpoint count by
2289 * subtracting out the endpoints that were dropped (but not changed).
2291 * Must be called with xhci->lock held.
2293 static void xhci_finish_resource_reservation(struct xhci_hcd
*xhci
,
2294 struct xhci_input_control_ctx
*ctrl_ctx
)
2296 u32 num_dropped_eps
;
2298 num_dropped_eps
= xhci_count_num_dropped_endpoints(xhci
, ctrl_ctx
);
2299 xhci
->num_active_eps
-= num_dropped_eps
;
2300 if (num_dropped_eps
)
2301 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
2302 "Removing %u dropped ep ctxs, %u now active.",
2304 xhci
->num_active_eps
);
2307 static unsigned int xhci_get_block_size(struct usb_device
*udev
)
2309 switch (udev
->speed
) {
2311 case USB_SPEED_FULL
:
2313 case USB_SPEED_HIGH
:
2315 case USB_SPEED_SUPER
:
2316 case USB_SPEED_SUPER_PLUS
:
2318 case USB_SPEED_UNKNOWN
:
2319 case USB_SPEED_WIRELESS
:
2321 /* Should never happen */
2327 xhci_get_largest_overhead(struct xhci_interval_bw
*interval_bw
)
2329 if (interval_bw
->overhead
[LS_OVERHEAD_TYPE
])
2331 if (interval_bw
->overhead
[FS_OVERHEAD_TYPE
])
2336 /* If we are changing a LS/FS device under a HS hub,
2337 * make sure (if we are activating a new TT) that the HS bus has enough
2338 * bandwidth for this new TT.
2340 static int xhci_check_tt_bw_table(struct xhci_hcd
*xhci
,
2341 struct xhci_virt_device
*virt_dev
,
2344 struct xhci_interval_bw_table
*bw_table
;
2345 struct xhci_tt_bw_info
*tt_info
;
2347 /* Find the bandwidth table for the root port this TT is attached to. */
2348 bw_table
= &xhci
->rh_bw
[virt_dev
->real_port
- 1].bw_table
;
2349 tt_info
= virt_dev
->tt_info
;
2350 /* If this TT already had active endpoints, the bandwidth for this TT
2351 * has already been added. Removing all periodic endpoints (and thus
2352 * making the TT enactive) will only decrease the bandwidth used.
2356 if (old_active_eps
== 0 && tt_info
->active_eps
!= 0) {
2357 if (bw_table
->bw_used
+ TT_HS_OVERHEAD
> HS_BW_LIMIT
)
2361 /* Not sure why we would have no new active endpoints...
2363 * Maybe because of an Evaluate Context change for a hub update or a
2364 * control endpoint 0 max packet size change?
2365 * FIXME: skip the bandwidth calculation in that case.
2370 static int xhci_check_ss_bw(struct xhci_hcd
*xhci
,
2371 struct xhci_virt_device
*virt_dev
)
2373 unsigned int bw_reserved
;
2375 bw_reserved
= DIV_ROUND_UP(SS_BW_RESERVED
*SS_BW_LIMIT_IN
, 100);
2376 if (virt_dev
->bw_table
->ss_bw_in
> (SS_BW_LIMIT_IN
- bw_reserved
))
2379 bw_reserved
= DIV_ROUND_UP(SS_BW_RESERVED
*SS_BW_LIMIT_OUT
, 100);
2380 if (virt_dev
->bw_table
->ss_bw_out
> (SS_BW_LIMIT_OUT
- bw_reserved
))
2387 * This algorithm is a very conservative estimate of the worst-case scheduling
2388 * scenario for any one interval. The hardware dynamically schedules the
2389 * packets, so we can't tell which microframe could be the limiting factor in
2390 * the bandwidth scheduling. This only takes into account periodic endpoints.
2392 * Obviously, we can't solve an NP complete problem to find the minimum worst
2393 * case scenario. Instead, we come up with an estimate that is no less than
2394 * the worst case bandwidth used for any one microframe, but may be an
2397 * We walk the requirements for each endpoint by interval, starting with the
2398 * smallest interval, and place packets in the schedule where there is only one
2399 * possible way to schedule packets for that interval. In order to simplify
2400 * this algorithm, we record the largest max packet size for each interval, and
2401 * assume all packets will be that size.
2403 * For interval 0, we obviously must schedule all packets for each interval.
2404 * The bandwidth for interval 0 is just the amount of data to be transmitted
2405 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2406 * the number of packets).
2408 * For interval 1, we have two possible microframes to schedule those packets
2409 * in. For this algorithm, if we can schedule the same number of packets for
2410 * each possible scheduling opportunity (each microframe), we will do so. The
2411 * remaining number of packets will be saved to be transmitted in the gaps in
2412 * the next interval's scheduling sequence.
2414 * As we move those remaining packets to be scheduled with interval 2 packets,
2415 * we have to double the number of remaining packets to transmit. This is
2416 * because the intervals are actually powers of 2, and we would be transmitting
2417 * the previous interval's packets twice in this interval. We also have to be
2418 * sure that when we look at the largest max packet size for this interval, we
2419 * also look at the largest max packet size for the remaining packets and take
2420 * the greater of the two.
2422 * The algorithm continues to evenly distribute packets in each scheduling
2423 * opportunity, and push the remaining packets out, until we get to the last
2424 * interval. Then those packets and their associated overhead are just added
2425 * to the bandwidth used.
2427 static int xhci_check_bw_table(struct xhci_hcd
*xhci
,
2428 struct xhci_virt_device
*virt_dev
,
2431 unsigned int bw_reserved
;
2432 unsigned int max_bandwidth
;
2433 unsigned int bw_used
;
2434 unsigned int block_size
;
2435 struct xhci_interval_bw_table
*bw_table
;
2436 unsigned int packet_size
= 0;
2437 unsigned int overhead
= 0;
2438 unsigned int packets_transmitted
= 0;
2439 unsigned int packets_remaining
= 0;
2442 if (virt_dev
->udev
->speed
>= USB_SPEED_SUPER
)
2443 return xhci_check_ss_bw(xhci
, virt_dev
);
2445 if (virt_dev
->udev
->speed
== USB_SPEED_HIGH
) {
2446 max_bandwidth
= HS_BW_LIMIT
;
2447 /* Convert percent of bus BW reserved to blocks reserved */
2448 bw_reserved
= DIV_ROUND_UP(HS_BW_RESERVED
* max_bandwidth
, 100);
2450 max_bandwidth
= FS_BW_LIMIT
;
2451 bw_reserved
= DIV_ROUND_UP(FS_BW_RESERVED
* max_bandwidth
, 100);
2454 bw_table
= virt_dev
->bw_table
;
2455 /* We need to translate the max packet size and max ESIT payloads into
2456 * the units the hardware uses.
2458 block_size
= xhci_get_block_size(virt_dev
->udev
);
2460 /* If we are manipulating a LS/FS device under a HS hub, double check
2461 * that the HS bus has enough bandwidth if we are activing a new TT.
2463 if (virt_dev
->tt_info
) {
2464 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
2465 "Recalculating BW for rootport %u",
2466 virt_dev
->real_port
);
2467 if (xhci_check_tt_bw_table(xhci
, virt_dev
, old_active_eps
)) {
2468 xhci_warn(xhci
, "Not enough bandwidth on HS bus for "
2469 "newly activated TT.\n");
2472 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
2473 "Recalculating BW for TT slot %u port %u",
2474 virt_dev
->tt_info
->slot_id
,
2475 virt_dev
->tt_info
->ttport
);
2477 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
2478 "Recalculating BW for rootport %u",
2479 virt_dev
->real_port
);
2482 /* Add in how much bandwidth will be used for interval zero, or the
2483 * rounded max ESIT payload + number of packets * largest overhead.
2485 bw_used
= DIV_ROUND_UP(bw_table
->interval0_esit_payload
, block_size
) +
2486 bw_table
->interval_bw
[0].num_packets
*
2487 xhci_get_largest_overhead(&bw_table
->interval_bw
[0]);
2489 for (i
= 1; i
< XHCI_MAX_INTERVAL
; i
++) {
2490 unsigned int bw_added
;
2491 unsigned int largest_mps
;
2492 unsigned int interval_overhead
;
2495 * How many packets could we transmit in this interval?
2496 * If packets didn't fit in the previous interval, we will need
2497 * to transmit that many packets twice within this interval.
2499 packets_remaining
= 2 * packets_remaining
+
2500 bw_table
->interval_bw
[i
].num_packets
;
2502 /* Find the largest max packet size of this or the previous
2505 if (list_empty(&bw_table
->interval_bw
[i
].endpoints
))
2508 struct xhci_virt_ep
*virt_ep
;
2509 struct list_head
*ep_entry
;
2511 ep_entry
= bw_table
->interval_bw
[i
].endpoints
.next
;
2512 virt_ep
= list_entry(ep_entry
,
2513 struct xhci_virt_ep
, bw_endpoint_list
);
2514 /* Convert to blocks, rounding up */
2515 largest_mps
= DIV_ROUND_UP(
2516 virt_ep
->bw_info
.max_packet_size
,
2519 if (largest_mps
> packet_size
)
2520 packet_size
= largest_mps
;
2522 /* Use the larger overhead of this or the previous interval. */
2523 interval_overhead
= xhci_get_largest_overhead(
2524 &bw_table
->interval_bw
[i
]);
2525 if (interval_overhead
> overhead
)
2526 overhead
= interval_overhead
;
2528 /* How many packets can we evenly distribute across
2529 * (1 << (i + 1)) possible scheduling opportunities?
2531 packets_transmitted
= packets_remaining
>> (i
+ 1);
2533 /* Add in the bandwidth used for those scheduled packets */
2534 bw_added
= packets_transmitted
* (overhead
+ packet_size
);
2536 /* How many packets do we have remaining to transmit? */
2537 packets_remaining
= packets_remaining
% (1 << (i
+ 1));
2539 /* What largest max packet size should those packets have? */
2540 /* If we've transmitted all packets, don't carry over the
2541 * largest packet size.
2543 if (packets_remaining
== 0) {
2546 } else if (packets_transmitted
> 0) {
2547 /* Otherwise if we do have remaining packets, and we've
2548 * scheduled some packets in this interval, take the
2549 * largest max packet size from endpoints with this
2552 packet_size
= largest_mps
;
2553 overhead
= interval_overhead
;
2555 /* Otherwise carry over packet_size and overhead from the last
2556 * time we had a remainder.
2558 bw_used
+= bw_added
;
2559 if (bw_used
> max_bandwidth
) {
2560 xhci_warn(xhci
, "Not enough bandwidth. "
2561 "Proposed: %u, Max: %u\n",
2562 bw_used
, max_bandwidth
);
2567 * Ok, we know we have some packets left over after even-handedly
2568 * scheduling interval 15. We don't know which microframes they will
2569 * fit into, so we over-schedule and say they will be scheduled every
2572 if (packets_remaining
> 0)
2573 bw_used
+= overhead
+ packet_size
;
2575 if (!virt_dev
->tt_info
&& virt_dev
->udev
->speed
== USB_SPEED_HIGH
) {
2576 unsigned int port_index
= virt_dev
->real_port
- 1;
2578 /* OK, we're manipulating a HS device attached to a
2579 * root port bandwidth domain. Include the number of active TTs
2580 * in the bandwidth used.
2582 bw_used
+= TT_HS_OVERHEAD
*
2583 xhci
->rh_bw
[port_index
].num_active_tts
;
2586 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
2587 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2588 "Available: %u " "percent",
2589 bw_used
, max_bandwidth
, bw_reserved
,
2590 (max_bandwidth
- bw_used
- bw_reserved
) * 100 /
2593 bw_used
+= bw_reserved
;
2594 if (bw_used
> max_bandwidth
) {
2595 xhci_warn(xhci
, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2596 bw_used
, max_bandwidth
);
2600 bw_table
->bw_used
= bw_used
;
2604 static bool xhci_is_async_ep(unsigned int ep_type
)
2606 return (ep_type
!= ISOC_OUT_EP
&& ep_type
!= INT_OUT_EP
&&
2607 ep_type
!= ISOC_IN_EP
&&
2608 ep_type
!= INT_IN_EP
);
2611 static bool xhci_is_sync_in_ep(unsigned int ep_type
)
2613 return (ep_type
== ISOC_IN_EP
|| ep_type
== INT_IN_EP
);
2616 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info
*ep_bw
)
2618 unsigned int mps
= DIV_ROUND_UP(ep_bw
->max_packet_size
, SS_BLOCK
);
2620 if (ep_bw
->ep_interval
== 0)
2621 return SS_OVERHEAD_BURST
+
2622 (ep_bw
->mult
* ep_bw
->num_packets
*
2623 (SS_OVERHEAD
+ mps
));
2624 return DIV_ROUND_UP(ep_bw
->mult
* ep_bw
->num_packets
*
2625 (SS_OVERHEAD
+ mps
+ SS_OVERHEAD_BURST
),
2626 1 << ep_bw
->ep_interval
);
2630 static void xhci_drop_ep_from_interval_table(struct xhci_hcd
*xhci
,
2631 struct xhci_bw_info
*ep_bw
,
2632 struct xhci_interval_bw_table
*bw_table
,
2633 struct usb_device
*udev
,
2634 struct xhci_virt_ep
*virt_ep
,
2635 struct xhci_tt_bw_info
*tt_info
)
2637 struct xhci_interval_bw
*interval_bw
;
2638 int normalized_interval
;
2640 if (xhci_is_async_ep(ep_bw
->type
))
2643 if (udev
->speed
>= USB_SPEED_SUPER
) {
2644 if (xhci_is_sync_in_ep(ep_bw
->type
))
2645 xhci
->devs
[udev
->slot_id
]->bw_table
->ss_bw_in
-=
2646 xhci_get_ss_bw_consumed(ep_bw
);
2648 xhci
->devs
[udev
->slot_id
]->bw_table
->ss_bw_out
-=
2649 xhci_get_ss_bw_consumed(ep_bw
);
2653 /* SuperSpeed endpoints never get added to intervals in the table, so
2654 * this check is only valid for HS/FS/LS devices.
2656 if (list_empty(&virt_ep
->bw_endpoint_list
))
2658 /* For LS/FS devices, we need to translate the interval expressed in
2659 * microframes to frames.
2661 if (udev
->speed
== USB_SPEED_HIGH
)
2662 normalized_interval
= ep_bw
->ep_interval
;
2664 normalized_interval
= ep_bw
->ep_interval
- 3;
2666 if (normalized_interval
== 0)
2667 bw_table
->interval0_esit_payload
-= ep_bw
->max_esit_payload
;
2668 interval_bw
= &bw_table
->interval_bw
[normalized_interval
];
2669 interval_bw
->num_packets
-= ep_bw
->num_packets
;
2670 switch (udev
->speed
) {
2672 interval_bw
->overhead
[LS_OVERHEAD_TYPE
] -= 1;
2674 case USB_SPEED_FULL
:
2675 interval_bw
->overhead
[FS_OVERHEAD_TYPE
] -= 1;
2677 case USB_SPEED_HIGH
:
2678 interval_bw
->overhead
[HS_OVERHEAD_TYPE
] -= 1;
2680 case USB_SPEED_SUPER
:
2681 case USB_SPEED_SUPER_PLUS
:
2682 case USB_SPEED_UNKNOWN
:
2683 case USB_SPEED_WIRELESS
:
2684 /* Should never happen because only LS/FS/HS endpoints will get
2685 * added to the endpoint list.
2690 tt_info
->active_eps
-= 1;
2691 list_del_init(&virt_ep
->bw_endpoint_list
);
2694 static void xhci_add_ep_to_interval_table(struct xhci_hcd
*xhci
,
2695 struct xhci_bw_info
*ep_bw
,
2696 struct xhci_interval_bw_table
*bw_table
,
2697 struct usb_device
*udev
,
2698 struct xhci_virt_ep
*virt_ep
,
2699 struct xhci_tt_bw_info
*tt_info
)
2701 struct xhci_interval_bw
*interval_bw
;
2702 struct xhci_virt_ep
*smaller_ep
;
2703 int normalized_interval
;
2705 if (xhci_is_async_ep(ep_bw
->type
))
2708 if (udev
->speed
== USB_SPEED_SUPER
) {
2709 if (xhci_is_sync_in_ep(ep_bw
->type
))
2710 xhci
->devs
[udev
->slot_id
]->bw_table
->ss_bw_in
+=
2711 xhci_get_ss_bw_consumed(ep_bw
);
2713 xhci
->devs
[udev
->slot_id
]->bw_table
->ss_bw_out
+=
2714 xhci_get_ss_bw_consumed(ep_bw
);
2718 /* For LS/FS devices, we need to translate the interval expressed in
2719 * microframes to frames.
2721 if (udev
->speed
== USB_SPEED_HIGH
)
2722 normalized_interval
= ep_bw
->ep_interval
;
2724 normalized_interval
= ep_bw
->ep_interval
- 3;
2726 if (normalized_interval
== 0)
2727 bw_table
->interval0_esit_payload
+= ep_bw
->max_esit_payload
;
2728 interval_bw
= &bw_table
->interval_bw
[normalized_interval
];
2729 interval_bw
->num_packets
+= ep_bw
->num_packets
;
2730 switch (udev
->speed
) {
2732 interval_bw
->overhead
[LS_OVERHEAD_TYPE
] += 1;
2734 case USB_SPEED_FULL
:
2735 interval_bw
->overhead
[FS_OVERHEAD_TYPE
] += 1;
2737 case USB_SPEED_HIGH
:
2738 interval_bw
->overhead
[HS_OVERHEAD_TYPE
] += 1;
2740 case USB_SPEED_SUPER
:
2741 case USB_SPEED_SUPER_PLUS
:
2742 case USB_SPEED_UNKNOWN
:
2743 case USB_SPEED_WIRELESS
:
2744 /* Should never happen because only LS/FS/HS endpoints will get
2745 * added to the endpoint list.
2751 tt_info
->active_eps
+= 1;
2752 /* Insert the endpoint into the list, largest max packet size first. */
2753 list_for_each_entry(smaller_ep
, &interval_bw
->endpoints
,
2755 if (ep_bw
->max_packet_size
>=
2756 smaller_ep
->bw_info
.max_packet_size
) {
2757 /* Add the new ep before the smaller endpoint */
2758 list_add_tail(&virt_ep
->bw_endpoint_list
,
2759 &smaller_ep
->bw_endpoint_list
);
2763 /* Add the new endpoint at the end of the list. */
2764 list_add_tail(&virt_ep
->bw_endpoint_list
,
2765 &interval_bw
->endpoints
);
2768 void xhci_update_tt_active_eps(struct xhci_hcd
*xhci
,
2769 struct xhci_virt_device
*virt_dev
,
2772 struct xhci_root_port_bw_info
*rh_bw_info
;
2773 if (!virt_dev
->tt_info
)
2776 rh_bw_info
= &xhci
->rh_bw
[virt_dev
->real_port
- 1];
2777 if (old_active_eps
== 0 &&
2778 virt_dev
->tt_info
->active_eps
!= 0) {
2779 rh_bw_info
->num_active_tts
+= 1;
2780 rh_bw_info
->bw_table
.bw_used
+= TT_HS_OVERHEAD
;
2781 } else if (old_active_eps
!= 0 &&
2782 virt_dev
->tt_info
->active_eps
== 0) {
2783 rh_bw_info
->num_active_tts
-= 1;
2784 rh_bw_info
->bw_table
.bw_used
-= TT_HS_OVERHEAD
;
2788 static int xhci_reserve_bandwidth(struct xhci_hcd
*xhci
,
2789 struct xhci_virt_device
*virt_dev
,
2790 struct xhci_container_ctx
*in_ctx
)
2792 struct xhci_bw_info ep_bw_info
[31];
2794 struct xhci_input_control_ctx
*ctrl_ctx
;
2795 int old_active_eps
= 0;
2797 if (virt_dev
->tt_info
)
2798 old_active_eps
= virt_dev
->tt_info
->active_eps
;
2800 ctrl_ctx
= xhci_get_input_control_ctx(in_ctx
);
2802 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
2807 for (i
= 0; i
< 31; i
++) {
2808 if (!EP_IS_ADDED(ctrl_ctx
, i
) && !EP_IS_DROPPED(ctrl_ctx
, i
))
2811 /* Make a copy of the BW info in case we need to revert this */
2812 memcpy(&ep_bw_info
[i
], &virt_dev
->eps
[i
].bw_info
,
2813 sizeof(ep_bw_info
[i
]));
2814 /* Drop the endpoint from the interval table if the endpoint is
2815 * being dropped or changed.
2817 if (EP_IS_DROPPED(ctrl_ctx
, i
))
2818 xhci_drop_ep_from_interval_table(xhci
,
2819 &virt_dev
->eps
[i
].bw_info
,
2825 /* Overwrite the information stored in the endpoints' bw_info */
2826 xhci_update_bw_info(xhci
, virt_dev
->in_ctx
, ctrl_ctx
, virt_dev
);
2827 for (i
= 0; i
< 31; i
++) {
2828 /* Add any changed or added endpoints to the interval table */
2829 if (EP_IS_ADDED(ctrl_ctx
, i
))
2830 xhci_add_ep_to_interval_table(xhci
,
2831 &virt_dev
->eps
[i
].bw_info
,
2838 if (!xhci_check_bw_table(xhci
, virt_dev
, old_active_eps
)) {
2839 /* Ok, this fits in the bandwidth we have.
2840 * Update the number of active TTs.
2842 xhci_update_tt_active_eps(xhci
, virt_dev
, old_active_eps
);
2846 /* We don't have enough bandwidth for this, revert the stored info. */
2847 for (i
= 0; i
< 31; i
++) {
2848 if (!EP_IS_ADDED(ctrl_ctx
, i
) && !EP_IS_DROPPED(ctrl_ctx
, i
))
2851 /* Drop the new copies of any added or changed endpoints from
2852 * the interval table.
2854 if (EP_IS_ADDED(ctrl_ctx
, i
)) {
2855 xhci_drop_ep_from_interval_table(xhci
,
2856 &virt_dev
->eps
[i
].bw_info
,
2862 /* Revert the endpoint back to its old information */
2863 memcpy(&virt_dev
->eps
[i
].bw_info
, &ep_bw_info
[i
],
2864 sizeof(ep_bw_info
[i
]));
2865 /* Add any changed or dropped endpoints back into the table */
2866 if (EP_IS_DROPPED(ctrl_ctx
, i
))
2867 xhci_add_ep_to_interval_table(xhci
,
2868 &virt_dev
->eps
[i
].bw_info
,
2878 /* Issue a configure endpoint command or evaluate context command
2879 * and wait for it to finish.
2881 static int xhci_configure_endpoint(struct xhci_hcd
*xhci
,
2882 struct usb_device
*udev
,
2883 struct xhci_command
*command
,
2884 bool ctx_change
, bool must_succeed
)
2887 unsigned long flags
;
2888 struct xhci_input_control_ctx
*ctrl_ctx
;
2889 struct xhci_virt_device
*virt_dev
;
2890 struct xhci_slot_ctx
*slot_ctx
;
2895 spin_lock_irqsave(&xhci
->lock
, flags
);
2897 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
2898 spin_unlock_irqrestore(&xhci
->lock
, flags
);
2902 virt_dev
= xhci
->devs
[udev
->slot_id
];
2904 ctrl_ctx
= xhci_get_input_control_ctx(command
->in_ctx
);
2906 spin_unlock_irqrestore(&xhci
->lock
, flags
);
2907 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
2912 if ((xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
) &&
2913 xhci_reserve_host_resources(xhci
, ctrl_ctx
)) {
2914 spin_unlock_irqrestore(&xhci
->lock
, flags
);
2915 xhci_warn(xhci
, "Not enough host resources, "
2916 "active endpoint contexts = %u\n",
2917 xhci
->num_active_eps
);
2920 if ((xhci
->quirks
& XHCI_SW_BW_CHECKING
) &&
2921 xhci_reserve_bandwidth(xhci
, virt_dev
, command
->in_ctx
)) {
2922 if ((xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
))
2923 xhci_free_host_resources(xhci
, ctrl_ctx
);
2924 spin_unlock_irqrestore(&xhci
->lock
, flags
);
2925 xhci_warn(xhci
, "Not enough bandwidth\n");
2929 slot_ctx
= xhci_get_slot_ctx(xhci
, command
->in_ctx
);
2931 trace_xhci_configure_endpoint_ctrl_ctx(ctrl_ctx
);
2932 trace_xhci_configure_endpoint(slot_ctx
);
2935 ret
= xhci_queue_configure_endpoint(xhci
, command
,
2936 command
->in_ctx
->dma
,
2937 udev
->slot_id
, must_succeed
);
2939 ret
= xhci_queue_evaluate_context(xhci
, command
,
2940 command
->in_ctx
->dma
,
2941 udev
->slot_id
, must_succeed
);
2943 if ((xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
))
2944 xhci_free_host_resources(xhci
, ctrl_ctx
);
2945 spin_unlock_irqrestore(&xhci
->lock
, flags
);
2946 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
2947 "FIXME allocate a new ring segment");
2950 xhci_ring_cmd_db(xhci
);
2951 spin_unlock_irqrestore(&xhci
->lock
, flags
);
2953 /* Wait for the configure endpoint command to complete */
2954 wait_for_completion(command
->completion
);
2957 ret
= xhci_configure_endpoint_result(xhci
, udev
,
2960 ret
= xhci_evaluate_context_result(xhci
, udev
,
2963 if ((xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
)) {
2964 spin_lock_irqsave(&xhci
->lock
, flags
);
2965 /* If the command failed, remove the reserved resources.
2966 * Otherwise, clean up the estimate to include dropped eps.
2969 xhci_free_host_resources(xhci
, ctrl_ctx
);
2971 xhci_finish_resource_reservation(xhci
, ctrl_ctx
);
2972 spin_unlock_irqrestore(&xhci
->lock
, flags
);
2977 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd
*xhci
,
2978 struct xhci_virt_device
*vdev
, int i
)
2980 struct xhci_virt_ep
*ep
= &vdev
->eps
[i
];
2982 if (ep
->ep_state
& EP_HAS_STREAMS
) {
2983 xhci_warn(xhci
, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2984 xhci_get_endpoint_address(i
));
2985 xhci_free_stream_info(xhci
, ep
->stream_info
);
2986 ep
->stream_info
= NULL
;
2987 ep
->ep_state
&= ~EP_HAS_STREAMS
;
2991 /* Called after one or more calls to xhci_add_endpoint() or
2992 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2993 * to call xhci_reset_bandwidth().
2995 * Since we are in the middle of changing either configuration or
2996 * installing a new alt setting, the USB core won't allow URBs to be
2997 * enqueued for any endpoint on the old config or interface. Nothing
2998 * else should be touching the xhci->devs[slot_id] structure, so we
2999 * don't need to take the xhci->lock for manipulating that.
3001 int xhci_check_bandwidth(struct usb_hcd
*hcd
, struct usb_device
*udev
)
3005 struct xhci_hcd
*xhci
;
3006 struct xhci_virt_device
*virt_dev
;
3007 struct xhci_input_control_ctx
*ctrl_ctx
;
3008 struct xhci_slot_ctx
*slot_ctx
;
3009 struct xhci_command
*command
;
3011 ret
= xhci_check_args(hcd
, udev
, NULL
, 0, true, __func__
);
3014 xhci
= hcd_to_xhci(hcd
);
3015 if ((xhci
->xhc_state
& XHCI_STATE_DYING
) ||
3016 (xhci
->xhc_state
& XHCI_STATE_REMOVING
))
3019 xhci_dbg(xhci
, "%s called for udev %p\n", __func__
, udev
);
3020 virt_dev
= xhci
->devs
[udev
->slot_id
];
3022 command
= xhci_alloc_command(xhci
, true, GFP_KERNEL
);
3026 command
->in_ctx
= virt_dev
->in_ctx
;
3028 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
3029 ctrl_ctx
= xhci_get_input_control_ctx(command
->in_ctx
);
3031 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
3034 goto command_cleanup
;
3036 ctrl_ctx
->add_flags
|= cpu_to_le32(SLOT_FLAG
);
3037 ctrl_ctx
->add_flags
&= cpu_to_le32(~EP0_FLAG
);
3038 ctrl_ctx
->drop_flags
&= cpu_to_le32(~(SLOT_FLAG
| EP0_FLAG
));
3040 /* Don't issue the command if there's no endpoints to update. */
3041 if (ctrl_ctx
->add_flags
== cpu_to_le32(SLOT_FLAG
) &&
3042 ctrl_ctx
->drop_flags
== 0) {
3044 goto command_cleanup
;
3046 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
3047 slot_ctx
= xhci_get_slot_ctx(xhci
, virt_dev
->in_ctx
);
3048 for (i
= 31; i
>= 1; i
--) {
3049 __le32 le32
= cpu_to_le32(BIT(i
));
3051 if ((virt_dev
->eps
[i
-1].ring
&& !(ctrl_ctx
->drop_flags
& le32
))
3052 || (ctrl_ctx
->add_flags
& le32
) || i
== 1) {
3053 slot_ctx
->dev_info
&= cpu_to_le32(~LAST_CTX_MASK
);
3054 slot_ctx
->dev_info
|= cpu_to_le32(LAST_CTX(i
));
3059 ret
= xhci_configure_endpoint(xhci
, udev
, command
,
3062 /* Callee should call reset_bandwidth() */
3063 goto command_cleanup
;
3065 /* Free any rings that were dropped, but not changed. */
3066 for (i
= 1; i
< 31; i
++) {
3067 if ((le32_to_cpu(ctrl_ctx
->drop_flags
) & (1 << (i
+ 1))) &&
3068 !(le32_to_cpu(ctrl_ctx
->add_flags
) & (1 << (i
+ 1)))) {
3069 xhci_free_endpoint_ring(xhci
, virt_dev
, i
);
3070 xhci_check_bw_drop_ep_streams(xhci
, virt_dev
, i
);
3073 xhci_zero_in_ctx(xhci
, virt_dev
);
3075 * Install any rings for completely new endpoints or changed endpoints,
3076 * and free any old rings from changed endpoints.
3078 for (i
= 1; i
< 31; i
++) {
3079 if (!virt_dev
->eps
[i
].new_ring
)
3081 /* Only free the old ring if it exists.
3082 * It may not if this is the first add of an endpoint.
3084 if (virt_dev
->eps
[i
].ring
) {
3085 xhci_free_endpoint_ring(xhci
, virt_dev
, i
);
3087 xhci_check_bw_drop_ep_streams(xhci
, virt_dev
, i
);
3088 virt_dev
->eps
[i
].ring
= virt_dev
->eps
[i
].new_ring
;
3089 virt_dev
->eps
[i
].new_ring
= NULL
;
3090 xhci_debugfs_create_endpoint(xhci
, virt_dev
, i
);
3093 kfree(command
->completion
);
3098 EXPORT_SYMBOL_GPL(xhci_check_bandwidth
);
3100 void xhci_reset_bandwidth(struct usb_hcd
*hcd
, struct usb_device
*udev
)
3102 struct xhci_hcd
*xhci
;
3103 struct xhci_virt_device
*virt_dev
;
3106 ret
= xhci_check_args(hcd
, udev
, NULL
, 0, true, __func__
);
3109 xhci
= hcd_to_xhci(hcd
);
3111 xhci_dbg(xhci
, "%s called for udev %p\n", __func__
, udev
);
3112 virt_dev
= xhci
->devs
[udev
->slot_id
];
3113 /* Free any rings allocated for added endpoints */
3114 for (i
= 0; i
< 31; i
++) {
3115 if (virt_dev
->eps
[i
].new_ring
) {
3116 xhci_debugfs_remove_endpoint(xhci
, virt_dev
, i
);
3117 xhci_ring_free(xhci
, virt_dev
->eps
[i
].new_ring
);
3118 virt_dev
->eps
[i
].new_ring
= NULL
;
3121 xhci_zero_in_ctx(xhci
, virt_dev
);
3123 EXPORT_SYMBOL_GPL(xhci_reset_bandwidth
);
3125 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd
*xhci
,
3126 struct xhci_container_ctx
*in_ctx
,
3127 struct xhci_container_ctx
*out_ctx
,
3128 struct xhci_input_control_ctx
*ctrl_ctx
,
3129 u32 add_flags
, u32 drop_flags
)
3131 ctrl_ctx
->add_flags
= cpu_to_le32(add_flags
);
3132 ctrl_ctx
->drop_flags
= cpu_to_le32(drop_flags
);
3133 xhci_slot_copy(xhci
, in_ctx
, out_ctx
);
3134 ctrl_ctx
->add_flags
|= cpu_to_le32(SLOT_FLAG
);
3137 static void xhci_endpoint_disable(struct usb_hcd
*hcd
,
3138 struct usb_host_endpoint
*host_ep
)
3140 struct xhci_hcd
*xhci
;
3141 struct xhci_virt_device
*vdev
;
3142 struct xhci_virt_ep
*ep
;
3143 struct usb_device
*udev
;
3144 unsigned long flags
;
3145 unsigned int ep_index
;
3147 xhci
= hcd_to_xhci(hcd
);
3149 spin_lock_irqsave(&xhci
->lock
, flags
);
3151 udev
= (struct usb_device
*)host_ep
->hcpriv
;
3152 if (!udev
|| !udev
->slot_id
)
3155 vdev
= xhci
->devs
[udev
->slot_id
];
3159 ep_index
= xhci_get_endpoint_index(&host_ep
->desc
);
3160 ep
= &vdev
->eps
[ep_index
];
3164 /* wait for hub_tt_work to finish clearing hub TT */
3165 if (ep
->ep_state
& EP_CLEARING_TT
) {
3166 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3167 schedule_timeout_uninterruptible(1);
3172 xhci_dbg(xhci
, "endpoint disable with ep_state 0x%x\n",
3175 host_ep
->hcpriv
= NULL
;
3176 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3180 * Called after usb core issues a clear halt control message.
3181 * The host side of the halt should already be cleared by a reset endpoint
3182 * command issued when the STALL event was received.
3184 * The reset endpoint command may only be issued to endpoints in the halted
3185 * state. For software that wishes to reset the data toggle or sequence number
3186 * of an endpoint that isn't in the halted state this function will issue a
3187 * configure endpoint command with the Drop and Add bits set for the target
3188 * endpoint. Refer to the additional note in xhci spcification section 4.6.8.
3191 static void xhci_endpoint_reset(struct usb_hcd
*hcd
,
3192 struct usb_host_endpoint
*host_ep
)
3194 struct xhci_hcd
*xhci
;
3195 struct usb_device
*udev
;
3196 struct xhci_virt_device
*vdev
;
3197 struct xhci_virt_ep
*ep
;
3198 struct xhci_input_control_ctx
*ctrl_ctx
;
3199 struct xhci_command
*stop_cmd
, *cfg_cmd
;
3200 unsigned int ep_index
;
3201 unsigned long flags
;
3205 xhci
= hcd_to_xhci(hcd
);
3206 if (!host_ep
->hcpriv
)
3208 udev
= (struct usb_device
*) host_ep
->hcpriv
;
3209 vdev
= xhci
->devs
[udev
->slot_id
];
3212 * vdev may be lost due to xHC restore error and re-initialization
3213 * during S3/S4 resume. A new vdev will be allocated later by
3214 * xhci_discover_or_reset_device()
3216 if (!udev
->slot_id
|| !vdev
)
3218 ep_index
= xhci_get_endpoint_index(&host_ep
->desc
);
3219 ep
= &vdev
->eps
[ep_index
];
3223 /* Bail out if toggle is already being cleared by a endpoint reset */
3224 spin_lock_irqsave(&xhci
->lock
, flags
);
3225 if (ep
->ep_state
& EP_HARD_CLEAR_TOGGLE
) {
3226 ep
->ep_state
&= ~EP_HARD_CLEAR_TOGGLE
;
3227 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3230 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3231 /* Only interrupt and bulk ep's use data toggle, USB2 spec 5.5.4-> */
3232 if (usb_endpoint_xfer_control(&host_ep
->desc
) ||
3233 usb_endpoint_xfer_isoc(&host_ep
->desc
))
3236 ep_flag
= xhci_get_endpoint_flag(&host_ep
->desc
);
3238 if (ep_flag
== SLOT_FLAG
|| ep_flag
== EP0_FLAG
)
3241 stop_cmd
= xhci_alloc_command(xhci
, true, GFP_NOWAIT
);
3245 cfg_cmd
= xhci_alloc_command_with_ctx(xhci
, true, GFP_NOWAIT
);
3249 spin_lock_irqsave(&xhci
->lock
, flags
);
3251 /* block queuing new trbs and ringing ep doorbell */
3252 ep
->ep_state
|= EP_SOFT_CLEAR_TOGGLE
;
3255 * Make sure endpoint ring is empty before resetting the toggle/seq.
3256 * Driver is required to synchronously cancel all transfer request.
3257 * Stop the endpoint to force xHC to update the output context
3260 if (!list_empty(&ep
->ring
->td_list
)) {
3261 dev_err(&udev
->dev
, "EP not empty, refuse reset\n");
3262 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3263 xhci_free_command(xhci
, cfg_cmd
);
3267 err
= xhci_queue_stop_endpoint(xhci
, stop_cmd
, udev
->slot_id
,
3270 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3271 xhci_free_command(xhci
, cfg_cmd
);
3272 xhci_dbg(xhci
, "%s: Failed to queue stop ep command, %d ",
3277 xhci_ring_cmd_db(xhci
);
3278 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3280 wait_for_completion(stop_cmd
->completion
);
3282 spin_lock_irqsave(&xhci
->lock
, flags
);
3284 /* config ep command clears toggle if add and drop ep flags are set */
3285 ctrl_ctx
= xhci_get_input_control_ctx(cfg_cmd
->in_ctx
);
3287 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3288 xhci_free_command(xhci
, cfg_cmd
);
3289 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
3294 xhci_setup_input_ctx_for_config_ep(xhci
, cfg_cmd
->in_ctx
, vdev
->out_ctx
,
3295 ctrl_ctx
, ep_flag
, ep_flag
);
3296 xhci_endpoint_copy(xhci
, cfg_cmd
->in_ctx
, vdev
->out_ctx
, ep_index
);
3298 err
= xhci_queue_configure_endpoint(xhci
, cfg_cmd
, cfg_cmd
->in_ctx
->dma
,
3299 udev
->slot_id
, false);
3301 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3302 xhci_free_command(xhci
, cfg_cmd
);
3303 xhci_dbg(xhci
, "%s: Failed to queue config ep command, %d ",
3308 xhci_ring_cmd_db(xhci
);
3309 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3311 wait_for_completion(cfg_cmd
->completion
);
3313 xhci_free_command(xhci
, cfg_cmd
);
3315 xhci_free_command(xhci
, stop_cmd
);
3316 spin_lock_irqsave(&xhci
->lock
, flags
);
3317 if (ep
->ep_state
& EP_SOFT_CLEAR_TOGGLE
)
3318 ep
->ep_state
&= ~EP_SOFT_CLEAR_TOGGLE
;
3319 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3322 static int xhci_check_streams_endpoint(struct xhci_hcd
*xhci
,
3323 struct usb_device
*udev
, struct usb_host_endpoint
*ep
,
3324 unsigned int slot_id
)
3327 unsigned int ep_index
;
3328 unsigned int ep_state
;
3332 ret
= xhci_check_args(xhci_to_hcd(xhci
), udev
, ep
, 1, true, __func__
);
3334 return ret
? ret
: -EINVAL
;
3335 if (usb_ss_max_streams(&ep
->ss_ep_comp
) == 0) {
3336 xhci_warn(xhci
, "WARN: SuperSpeed Endpoint Companion"
3337 " descriptor for ep 0x%x does not support streams\n",
3338 ep
->desc
.bEndpointAddress
);
3342 ep_index
= xhci_get_endpoint_index(&ep
->desc
);
3343 ep_state
= xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
;
3344 if (ep_state
& EP_HAS_STREAMS
||
3345 ep_state
& EP_GETTING_STREAMS
) {
3346 xhci_warn(xhci
, "WARN: SuperSpeed bulk endpoint 0x%x "
3347 "already has streams set up.\n",
3348 ep
->desc
.bEndpointAddress
);
3349 xhci_warn(xhci
, "Send email to xHCI maintainer and ask for "
3350 "dynamic stream context array reallocation.\n");
3353 if (!list_empty(&xhci
->devs
[slot_id
]->eps
[ep_index
].ring
->td_list
)) {
3354 xhci_warn(xhci
, "Cannot setup streams for SuperSpeed bulk "
3355 "endpoint 0x%x; URBs are pending.\n",
3356 ep
->desc
.bEndpointAddress
);
3362 static void xhci_calculate_streams_entries(struct xhci_hcd
*xhci
,
3363 unsigned int *num_streams
, unsigned int *num_stream_ctxs
)
3365 unsigned int max_streams
;
3367 /* The stream context array size must be a power of two */
3368 *num_stream_ctxs
= roundup_pow_of_two(*num_streams
);
3370 * Find out how many primary stream array entries the host controller
3371 * supports. Later we may use secondary stream arrays (similar to 2nd
3372 * level page entries), but that's an optional feature for xHCI host
3373 * controllers. xHCs must support at least 4 stream IDs.
3375 max_streams
= HCC_MAX_PSA(xhci
->hcc_params
);
3376 if (*num_stream_ctxs
> max_streams
) {
3377 xhci_dbg(xhci
, "xHCI HW only supports %u stream ctx entries.\n",
3379 *num_stream_ctxs
= max_streams
;
3380 *num_streams
= max_streams
;
3384 /* Returns an error code if one of the endpoint already has streams.
3385 * This does not change any data structures, it only checks and gathers
3388 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd
*xhci
,
3389 struct usb_device
*udev
,
3390 struct usb_host_endpoint
**eps
, unsigned int num_eps
,
3391 unsigned int *num_streams
, u32
*changed_ep_bitmask
)
3393 unsigned int max_streams
;
3394 unsigned int endpoint_flag
;
3398 for (i
= 0; i
< num_eps
; i
++) {
3399 ret
= xhci_check_streams_endpoint(xhci
, udev
,
3400 eps
[i
], udev
->slot_id
);
3404 max_streams
= usb_ss_max_streams(&eps
[i
]->ss_ep_comp
);
3405 if (max_streams
< (*num_streams
- 1)) {
3406 xhci_dbg(xhci
, "Ep 0x%x only supports %u stream IDs.\n",
3407 eps
[i
]->desc
.bEndpointAddress
,
3409 *num_streams
= max_streams
+1;
3412 endpoint_flag
= xhci_get_endpoint_flag(&eps
[i
]->desc
);
3413 if (*changed_ep_bitmask
& endpoint_flag
)
3415 *changed_ep_bitmask
|= endpoint_flag
;
3420 static u32
xhci_calculate_no_streams_bitmask(struct xhci_hcd
*xhci
,
3421 struct usb_device
*udev
,
3422 struct usb_host_endpoint
**eps
, unsigned int num_eps
)
3424 u32 changed_ep_bitmask
= 0;
3425 unsigned int slot_id
;
3426 unsigned int ep_index
;
3427 unsigned int ep_state
;
3430 slot_id
= udev
->slot_id
;
3431 if (!xhci
->devs
[slot_id
])
3434 for (i
= 0; i
< num_eps
; i
++) {
3435 ep_index
= xhci_get_endpoint_index(&eps
[i
]->desc
);
3436 ep_state
= xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
;
3437 /* Are streams already being freed for the endpoint? */
3438 if (ep_state
& EP_GETTING_NO_STREAMS
) {
3439 xhci_warn(xhci
, "WARN Can't disable streams for "
3441 "streams are being disabled already\n",
3442 eps
[i
]->desc
.bEndpointAddress
);
3445 /* Are there actually any streams to free? */
3446 if (!(ep_state
& EP_HAS_STREAMS
) &&
3447 !(ep_state
& EP_GETTING_STREAMS
)) {
3448 xhci_warn(xhci
, "WARN Can't disable streams for "
3450 "streams are already disabled!\n",
3451 eps
[i
]->desc
.bEndpointAddress
);
3452 xhci_warn(xhci
, "WARN xhci_free_streams() called "
3453 "with non-streams endpoint\n");
3456 changed_ep_bitmask
|= xhci_get_endpoint_flag(&eps
[i
]->desc
);
3458 return changed_ep_bitmask
;
3462 * The USB device drivers use this function (through the HCD interface in USB
3463 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3464 * coordinate mass storage command queueing across multiple endpoints (basically
3465 * a stream ID == a task ID).
3467 * Setting up streams involves allocating the same size stream context array
3468 * for each endpoint and issuing a configure endpoint command for all endpoints.
3470 * Don't allow the call to succeed if one endpoint only supports one stream
3471 * (which means it doesn't support streams at all).
3473 * Drivers may get less stream IDs than they asked for, if the host controller
3474 * hardware or endpoints claim they can't support the number of requested
3477 static int xhci_alloc_streams(struct usb_hcd
*hcd
, struct usb_device
*udev
,
3478 struct usb_host_endpoint
**eps
, unsigned int num_eps
,
3479 unsigned int num_streams
, gfp_t mem_flags
)
3482 struct xhci_hcd
*xhci
;
3483 struct xhci_virt_device
*vdev
;
3484 struct xhci_command
*config_cmd
;
3485 struct xhci_input_control_ctx
*ctrl_ctx
;
3486 unsigned int ep_index
;
3487 unsigned int num_stream_ctxs
;
3488 unsigned int max_packet
;
3489 unsigned long flags
;
3490 u32 changed_ep_bitmask
= 0;
3495 /* Add one to the number of streams requested to account for
3496 * stream 0 that is reserved for xHCI usage.
3499 xhci
= hcd_to_xhci(hcd
);
3500 xhci_dbg(xhci
, "Driver wants %u stream IDs (including stream 0).\n",
3503 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3504 if ((xhci
->quirks
& XHCI_BROKEN_STREAMS
) ||
3505 HCC_MAX_PSA(xhci
->hcc_params
) < 4) {
3506 xhci_dbg(xhci
, "xHCI controller does not support streams.\n");
3510 config_cmd
= xhci_alloc_command_with_ctx(xhci
, true, mem_flags
);
3514 ctrl_ctx
= xhci_get_input_control_ctx(config_cmd
->in_ctx
);
3516 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
3518 xhci_free_command(xhci
, config_cmd
);
3522 /* Check to make sure all endpoints are not already configured for
3523 * streams. While we're at it, find the maximum number of streams that
3524 * all the endpoints will support and check for duplicate endpoints.
3526 spin_lock_irqsave(&xhci
->lock
, flags
);
3527 ret
= xhci_calculate_streams_and_bitmask(xhci
, udev
, eps
,
3528 num_eps
, &num_streams
, &changed_ep_bitmask
);
3530 xhci_free_command(xhci
, config_cmd
);
3531 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3534 if (num_streams
<= 1) {
3535 xhci_warn(xhci
, "WARN: endpoints can't handle "
3536 "more than one stream.\n");
3537 xhci_free_command(xhci
, config_cmd
);
3538 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3541 vdev
= xhci
->devs
[udev
->slot_id
];
3542 /* Mark each endpoint as being in transition, so
3543 * xhci_urb_enqueue() will reject all URBs.
3545 for (i
= 0; i
< num_eps
; i
++) {
3546 ep_index
= xhci_get_endpoint_index(&eps
[i
]->desc
);
3547 vdev
->eps
[ep_index
].ep_state
|= EP_GETTING_STREAMS
;
3549 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3551 /* Setup internal data structures and allocate HW data structures for
3552 * streams (but don't install the HW structures in the input context
3553 * until we're sure all memory allocation succeeded).
3555 xhci_calculate_streams_entries(xhci
, &num_streams
, &num_stream_ctxs
);
3556 xhci_dbg(xhci
, "Need %u stream ctx entries for %u stream IDs.\n",
3557 num_stream_ctxs
, num_streams
);
3559 for (i
= 0; i
< num_eps
; i
++) {
3560 ep_index
= xhci_get_endpoint_index(&eps
[i
]->desc
);
3561 max_packet
= usb_endpoint_maxp(&eps
[i
]->desc
);
3562 vdev
->eps
[ep_index
].stream_info
= xhci_alloc_stream_info(xhci
,
3565 max_packet
, mem_flags
);
3566 if (!vdev
->eps
[ep_index
].stream_info
)
3568 /* Set maxPstreams in endpoint context and update deq ptr to
3569 * point to stream context array. FIXME
3573 /* Set up the input context for a configure endpoint command. */
3574 for (i
= 0; i
< num_eps
; i
++) {
3575 struct xhci_ep_ctx
*ep_ctx
;
3577 ep_index
= xhci_get_endpoint_index(&eps
[i
]->desc
);
3578 ep_ctx
= xhci_get_ep_ctx(xhci
, config_cmd
->in_ctx
, ep_index
);
3580 xhci_endpoint_copy(xhci
, config_cmd
->in_ctx
,
3581 vdev
->out_ctx
, ep_index
);
3582 xhci_setup_streams_ep_input_ctx(xhci
, ep_ctx
,
3583 vdev
->eps
[ep_index
].stream_info
);
3585 /* Tell the HW to drop its old copy of the endpoint context info
3586 * and add the updated copy from the input context.
3588 xhci_setup_input_ctx_for_config_ep(xhci
, config_cmd
->in_ctx
,
3589 vdev
->out_ctx
, ctrl_ctx
,
3590 changed_ep_bitmask
, changed_ep_bitmask
);
3592 /* Issue and wait for the configure endpoint command */
3593 ret
= xhci_configure_endpoint(xhci
, udev
, config_cmd
,
3596 /* xHC rejected the configure endpoint command for some reason, so we
3597 * leave the old ring intact and free our internal streams data
3603 spin_lock_irqsave(&xhci
->lock
, flags
);
3604 for (i
= 0; i
< num_eps
; i
++) {
3605 ep_index
= xhci_get_endpoint_index(&eps
[i
]->desc
);
3606 vdev
->eps
[ep_index
].ep_state
&= ~EP_GETTING_STREAMS
;
3607 xhci_dbg(xhci
, "Slot %u ep ctx %u now has streams.\n",
3608 udev
->slot_id
, ep_index
);
3609 vdev
->eps
[ep_index
].ep_state
|= EP_HAS_STREAMS
;
3611 xhci_free_command(xhci
, config_cmd
);
3612 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3614 for (i
= 0; i
< num_eps
; i
++) {
3615 ep_index
= xhci_get_endpoint_index(&eps
[i
]->desc
);
3616 xhci_debugfs_create_stream_files(xhci
, vdev
, ep_index
);
3618 /* Subtract 1 for stream 0, which drivers can't use */
3619 return num_streams
- 1;
3622 /* If it didn't work, free the streams! */
3623 for (i
= 0; i
< num_eps
; i
++) {
3624 ep_index
= xhci_get_endpoint_index(&eps
[i
]->desc
);
3625 xhci_free_stream_info(xhci
, vdev
->eps
[ep_index
].stream_info
);
3626 vdev
->eps
[ep_index
].stream_info
= NULL
;
3627 /* FIXME Unset maxPstreams in endpoint context and
3628 * update deq ptr to point to normal string ring.
3630 vdev
->eps
[ep_index
].ep_state
&= ~EP_GETTING_STREAMS
;
3631 vdev
->eps
[ep_index
].ep_state
&= ~EP_HAS_STREAMS
;
3632 xhci_endpoint_zero(xhci
, vdev
, eps
[i
]);
3634 xhci_free_command(xhci
, config_cmd
);
3638 /* Transition the endpoint from using streams to being a "normal" endpoint
3641 * Modify the endpoint context state, submit a configure endpoint command,
3642 * and free all endpoint rings for streams if that completes successfully.
3644 static int xhci_free_streams(struct usb_hcd
*hcd
, struct usb_device
*udev
,
3645 struct usb_host_endpoint
**eps
, unsigned int num_eps
,
3649 struct xhci_hcd
*xhci
;
3650 struct xhci_virt_device
*vdev
;
3651 struct xhci_command
*command
;
3652 struct xhci_input_control_ctx
*ctrl_ctx
;
3653 unsigned int ep_index
;
3654 unsigned long flags
;
3655 u32 changed_ep_bitmask
;
3657 xhci
= hcd_to_xhci(hcd
);
3658 vdev
= xhci
->devs
[udev
->slot_id
];
3660 /* Set up a configure endpoint command to remove the streams rings */
3661 spin_lock_irqsave(&xhci
->lock
, flags
);
3662 changed_ep_bitmask
= xhci_calculate_no_streams_bitmask(xhci
,
3663 udev
, eps
, num_eps
);
3664 if (changed_ep_bitmask
== 0) {
3665 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3669 /* Use the xhci_command structure from the first endpoint. We may have
3670 * allocated too many, but the driver may call xhci_free_streams() for
3671 * each endpoint it grouped into one call to xhci_alloc_streams().
3673 ep_index
= xhci_get_endpoint_index(&eps
[0]->desc
);
3674 command
= vdev
->eps
[ep_index
].stream_info
->free_streams_command
;
3675 ctrl_ctx
= xhci_get_input_control_ctx(command
->in_ctx
);
3677 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3678 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
3683 for (i
= 0; i
< num_eps
; i
++) {
3684 struct xhci_ep_ctx
*ep_ctx
;
3686 ep_index
= xhci_get_endpoint_index(&eps
[i
]->desc
);
3687 ep_ctx
= xhci_get_ep_ctx(xhci
, command
->in_ctx
, ep_index
);
3688 xhci
->devs
[udev
->slot_id
]->eps
[ep_index
].ep_state
|=
3689 EP_GETTING_NO_STREAMS
;
3691 xhci_endpoint_copy(xhci
, command
->in_ctx
,
3692 vdev
->out_ctx
, ep_index
);
3693 xhci_setup_no_streams_ep_input_ctx(ep_ctx
,
3694 &vdev
->eps
[ep_index
]);
3696 xhci_setup_input_ctx_for_config_ep(xhci
, command
->in_ctx
,
3697 vdev
->out_ctx
, ctrl_ctx
,
3698 changed_ep_bitmask
, changed_ep_bitmask
);
3699 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3701 /* Issue and wait for the configure endpoint command,
3702 * which must succeed.
3704 ret
= xhci_configure_endpoint(xhci
, udev
, command
,
3707 /* xHC rejected the configure endpoint command for some reason, so we
3708 * leave the streams rings intact.
3713 spin_lock_irqsave(&xhci
->lock
, flags
);
3714 for (i
= 0; i
< num_eps
; i
++) {
3715 ep_index
= xhci_get_endpoint_index(&eps
[i
]->desc
);
3716 xhci_free_stream_info(xhci
, vdev
->eps
[ep_index
].stream_info
);
3717 vdev
->eps
[ep_index
].stream_info
= NULL
;
3718 /* FIXME Unset maxPstreams in endpoint context and
3719 * update deq ptr to point to normal string ring.
3721 vdev
->eps
[ep_index
].ep_state
&= ~EP_GETTING_NO_STREAMS
;
3722 vdev
->eps
[ep_index
].ep_state
&= ~EP_HAS_STREAMS
;
3724 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3730 * Deletes endpoint resources for endpoints that were active before a Reset
3731 * Device command, or a Disable Slot command. The Reset Device command leaves
3732 * the control endpoint intact, whereas the Disable Slot command deletes it.
3734 * Must be called with xhci->lock held.
3736 void xhci_free_device_endpoint_resources(struct xhci_hcd
*xhci
,
3737 struct xhci_virt_device
*virt_dev
, bool drop_control_ep
)
3740 unsigned int num_dropped_eps
= 0;
3741 unsigned int drop_flags
= 0;
3743 for (i
= (drop_control_ep
? 0 : 1); i
< 31; i
++) {
3744 if (virt_dev
->eps
[i
].ring
) {
3745 drop_flags
|= 1 << i
;
3749 xhci
->num_active_eps
-= num_dropped_eps
;
3750 if (num_dropped_eps
)
3751 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
3752 "Dropped %u ep ctxs, flags = 0x%x, "
3754 num_dropped_eps
, drop_flags
,
3755 xhci
->num_active_eps
);
3759 * This submits a Reset Device Command, which will set the device state to 0,
3760 * set the device address to 0, and disable all the endpoints except the default
3761 * control endpoint. The USB core should come back and call
3762 * xhci_address_device(), and then re-set up the configuration. If this is
3763 * called because of a usb_reset_and_verify_device(), then the old alternate
3764 * settings will be re-installed through the normal bandwidth allocation
3767 * Wait for the Reset Device command to finish. Remove all structures
3768 * associated with the endpoints that were disabled. Clear the input device
3769 * structure? Reset the control endpoint 0 max packet size?
3771 * If the virt_dev to be reset does not exist or does not match the udev,
3772 * it means the device is lost, possibly due to the xHC restore error and
3773 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3774 * re-allocate the device.
3776 static int xhci_discover_or_reset_device(struct usb_hcd
*hcd
,
3777 struct usb_device
*udev
)
3780 unsigned long flags
;
3781 struct xhci_hcd
*xhci
;
3782 unsigned int slot_id
;
3783 struct xhci_virt_device
*virt_dev
;
3784 struct xhci_command
*reset_device_cmd
;
3785 struct xhci_slot_ctx
*slot_ctx
;
3786 int old_active_eps
= 0;
3788 ret
= xhci_check_args(hcd
, udev
, NULL
, 0, false, __func__
);
3791 xhci
= hcd_to_xhci(hcd
);
3792 slot_id
= udev
->slot_id
;
3793 virt_dev
= xhci
->devs
[slot_id
];
3795 xhci_dbg(xhci
, "The device to be reset with slot ID %u does "
3796 "not exist. Re-allocate the device\n", slot_id
);
3797 ret
= xhci_alloc_dev(hcd
, udev
);
3804 if (virt_dev
->tt_info
)
3805 old_active_eps
= virt_dev
->tt_info
->active_eps
;
3807 if (virt_dev
->udev
!= udev
) {
3808 /* If the virt_dev and the udev does not match, this virt_dev
3809 * may belong to another udev.
3810 * Re-allocate the device.
3812 xhci_dbg(xhci
, "The device to be reset with slot ID %u does "
3813 "not match the udev. Re-allocate the device\n",
3815 ret
= xhci_alloc_dev(hcd
, udev
);
3822 /* If device is not setup, there is no point in resetting it */
3823 slot_ctx
= xhci_get_slot_ctx(xhci
, virt_dev
->out_ctx
);
3824 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx
->dev_state
)) ==
3825 SLOT_STATE_DISABLED
)
3828 trace_xhci_discover_or_reset_device(slot_ctx
);
3830 xhci_dbg(xhci
, "Resetting device with slot ID %u\n", slot_id
);
3831 /* Allocate the command structure that holds the struct completion.
3832 * Assume we're in process context, since the normal device reset
3833 * process has to wait for the device anyway. Storage devices are
3834 * reset as part of error handling, so use GFP_NOIO instead of
3837 reset_device_cmd
= xhci_alloc_command(xhci
, true, GFP_NOIO
);
3838 if (!reset_device_cmd
) {
3839 xhci_dbg(xhci
, "Couldn't allocate command structure.\n");
3843 /* Attempt to submit the Reset Device command to the command ring */
3844 spin_lock_irqsave(&xhci
->lock
, flags
);
3846 ret
= xhci_queue_reset_device(xhci
, reset_device_cmd
, slot_id
);
3848 xhci_dbg(xhci
, "FIXME: allocate a command ring segment\n");
3849 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3850 goto command_cleanup
;
3852 xhci_ring_cmd_db(xhci
);
3853 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3855 /* Wait for the Reset Device command to finish */
3856 wait_for_completion(reset_device_cmd
->completion
);
3858 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3859 * unless we tried to reset a slot ID that wasn't enabled,
3860 * or the device wasn't in the addressed or configured state.
3862 ret
= reset_device_cmd
->status
;
3864 case COMP_COMMAND_ABORTED
:
3865 case COMP_COMMAND_RING_STOPPED
:
3866 xhci_warn(xhci
, "Timeout waiting for reset device command\n");
3868 goto command_cleanup
;
3869 case COMP_SLOT_NOT_ENABLED_ERROR
: /* 0.95 completion for bad slot ID */
3870 case COMP_CONTEXT_STATE_ERROR
: /* 0.96 completion code for same thing */
3871 xhci_dbg(xhci
, "Can't reset device (slot ID %u) in %s state\n",
3873 xhci_get_slot_state(xhci
, virt_dev
->out_ctx
));
3874 xhci_dbg(xhci
, "Not freeing device rings.\n");
3875 /* Don't treat this as an error. May change my mind later. */
3877 goto command_cleanup
;
3879 xhci_dbg(xhci
, "Successful reset device command.\n");
3882 if (xhci_is_vendor_info_code(xhci
, ret
))
3884 xhci_warn(xhci
, "Unknown completion code %u for "
3885 "reset device command.\n", ret
);
3887 goto command_cleanup
;
3890 /* Free up host controller endpoint resources */
3891 if ((xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
)) {
3892 spin_lock_irqsave(&xhci
->lock
, flags
);
3893 /* Don't delete the default control endpoint resources */
3894 xhci_free_device_endpoint_resources(xhci
, virt_dev
, false);
3895 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3898 /* Everything but endpoint 0 is disabled, so free the rings. */
3899 for (i
= 1; i
< 31; i
++) {
3900 struct xhci_virt_ep
*ep
= &virt_dev
->eps
[i
];
3902 if (ep
->ep_state
& EP_HAS_STREAMS
) {
3903 xhci_warn(xhci
, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3904 xhci_get_endpoint_address(i
));
3905 xhci_free_stream_info(xhci
, ep
->stream_info
);
3906 ep
->stream_info
= NULL
;
3907 ep
->ep_state
&= ~EP_HAS_STREAMS
;
3911 xhci_debugfs_remove_endpoint(xhci
, virt_dev
, i
);
3912 xhci_free_endpoint_ring(xhci
, virt_dev
, i
);
3914 if (!list_empty(&virt_dev
->eps
[i
].bw_endpoint_list
))
3915 xhci_drop_ep_from_interval_table(xhci
,
3916 &virt_dev
->eps
[i
].bw_info
,
3921 xhci_clear_endpoint_bw_info(&virt_dev
->eps
[i
].bw_info
);
3923 /* If necessary, update the number of active TTs on this root port */
3924 xhci_update_tt_active_eps(xhci
, virt_dev
, old_active_eps
);
3925 virt_dev
->flags
= 0;
3929 xhci_free_command(xhci
, reset_device_cmd
);
3934 * At this point, the struct usb_device is about to go away, the device has
3935 * disconnected, and all traffic has been stopped and the endpoints have been
3936 * disabled. Free any HC data structures associated with that device.
3938 static void xhci_free_dev(struct usb_hcd
*hcd
, struct usb_device
*udev
)
3940 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
3941 struct xhci_virt_device
*virt_dev
;
3942 struct xhci_slot_ctx
*slot_ctx
;
3946 * We called pm_runtime_get_noresume when the device was attached.
3947 * Decrement the counter here to allow controller to runtime suspend
3948 * if no devices remain.
3950 if (xhci
->quirks
& XHCI_RESET_ON_RESUME
)
3951 pm_runtime_put_noidle(hcd
->self
.controller
);
3953 ret
= xhci_check_args(hcd
, udev
, NULL
, 0, true, __func__
);
3954 /* If the host is halted due to driver unload, we still need to free the
3957 if (ret
<= 0 && ret
!= -ENODEV
)
3960 virt_dev
= xhci
->devs
[udev
->slot_id
];
3961 slot_ctx
= xhci_get_slot_ctx(xhci
, virt_dev
->out_ctx
);
3962 trace_xhci_free_dev(slot_ctx
);
3964 /* Stop any wayward timer functions (which may grab the lock) */
3965 for (i
= 0; i
< 31; i
++) {
3966 virt_dev
->eps
[i
].ep_state
&= ~EP_STOP_CMD_PENDING
;
3967 del_timer_sync(&virt_dev
->eps
[i
].stop_cmd_timer
);
3969 virt_dev
->udev
= NULL
;
3970 xhci_disable_slot(xhci
, udev
->slot_id
);
3971 xhci_free_virt_device(xhci
, udev
->slot_id
);
3974 int xhci_disable_slot(struct xhci_hcd
*xhci
, u32 slot_id
)
3976 struct xhci_command
*command
;
3977 unsigned long flags
;
3981 command
= xhci_alloc_command(xhci
, true, GFP_KERNEL
);
3985 xhci_debugfs_remove_slot(xhci
, slot_id
);
3987 spin_lock_irqsave(&xhci
->lock
, flags
);
3988 /* Don't disable the slot if the host controller is dead. */
3989 state
= readl(&xhci
->op_regs
->status
);
3990 if (state
== 0xffffffff || (xhci
->xhc_state
& XHCI_STATE_DYING
) ||
3991 (xhci
->xhc_state
& XHCI_STATE_HALTED
)) {
3992 spin_unlock_irqrestore(&xhci
->lock
, flags
);
3997 ret
= xhci_queue_slot_control(xhci
, command
, TRB_DISABLE_SLOT
,
4000 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4004 xhci_ring_cmd_db(xhci
);
4005 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4007 wait_for_completion(command
->completion
);
4009 if (command
->status
!= COMP_SUCCESS
)
4010 xhci_warn(xhci
, "Unsuccessful disable slot %u command, status %d\n",
4011 slot_id
, command
->status
);
4013 xhci_free_command(xhci
, command
);
4019 * Checks if we have enough host controller resources for the default control
4022 * Must be called with xhci->lock held.
4024 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd
*xhci
)
4026 if (xhci
->num_active_eps
+ 1 > xhci
->limit_active_eps
) {
4027 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
4028 "Not enough ep ctxs: "
4029 "%u active, need to add 1, limit is %u.",
4030 xhci
->num_active_eps
, xhci
->limit_active_eps
);
4033 xhci
->num_active_eps
+= 1;
4034 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
4035 "Adding 1 ep ctx, %u now active.",
4036 xhci
->num_active_eps
);
4042 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
4043 * timed out, or allocating memory failed. Returns 1 on success.
4045 int xhci_alloc_dev(struct usb_hcd
*hcd
, struct usb_device
*udev
)
4047 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
4048 struct xhci_virt_device
*vdev
;
4049 struct xhci_slot_ctx
*slot_ctx
;
4050 unsigned long flags
;
4052 struct xhci_command
*command
;
4054 command
= xhci_alloc_command(xhci
, true, GFP_KERNEL
);
4058 spin_lock_irqsave(&xhci
->lock
, flags
);
4059 ret
= xhci_queue_slot_control(xhci
, command
, TRB_ENABLE_SLOT
, 0);
4061 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4062 xhci_dbg(xhci
, "FIXME: allocate a command ring segment\n");
4063 xhci_free_command(xhci
, command
);
4066 xhci_ring_cmd_db(xhci
);
4067 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4069 wait_for_completion(command
->completion
);
4070 slot_id
= command
->slot_id
;
4072 if (!slot_id
|| command
->status
!= COMP_SUCCESS
) {
4073 xhci_err(xhci
, "Error while assigning device slot ID\n");
4074 xhci_err(xhci
, "Max number of devices this xHCI host supports is %u.\n",
4076 readl(&xhci
->cap_regs
->hcs_params1
)));
4077 xhci_free_command(xhci
, command
);
4081 xhci_free_command(xhci
, command
);
4083 if ((xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
)) {
4084 spin_lock_irqsave(&xhci
->lock
, flags
);
4085 ret
= xhci_reserve_host_control_ep_resources(xhci
);
4087 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4088 xhci_warn(xhci
, "Not enough host resources, "
4089 "active endpoint contexts = %u\n",
4090 xhci
->num_active_eps
);
4093 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4095 /* Use GFP_NOIO, since this function can be called from
4096 * xhci_discover_or_reset_device(), which may be called as part of
4097 * mass storage driver error handling.
4099 if (!xhci_alloc_virt_device(xhci
, slot_id
, udev
, GFP_NOIO
)) {
4100 xhci_warn(xhci
, "Could not allocate xHCI USB device data structures\n");
4103 vdev
= xhci
->devs
[slot_id
];
4104 slot_ctx
= xhci_get_slot_ctx(xhci
, vdev
->out_ctx
);
4105 trace_xhci_alloc_dev(slot_ctx
);
4107 udev
->slot_id
= slot_id
;
4109 xhci_debugfs_create_slot(xhci
, slot_id
);
4112 * If resetting upon resume, we can't put the controller into runtime
4113 * suspend if there is a device attached.
4115 if (xhci
->quirks
& XHCI_RESET_ON_RESUME
)
4116 pm_runtime_get_noresume(hcd
->self
.controller
);
4118 /* Is this a LS or FS device under a HS hub? */
4119 /* Hub or peripherial? */
4123 xhci_disable_slot(xhci
, udev
->slot_id
);
4124 xhci_free_virt_device(xhci
, udev
->slot_id
);
4130 * Issue an Address Device command and optionally send a corresponding
4131 * SetAddress request to the device.
4133 static int xhci_setup_device(struct usb_hcd
*hcd
, struct usb_device
*udev
,
4134 enum xhci_setup_dev setup
)
4136 const char *act
= setup
== SETUP_CONTEXT_ONLY
? "context" : "address";
4137 unsigned long flags
;
4138 struct xhci_virt_device
*virt_dev
;
4140 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
4141 struct xhci_slot_ctx
*slot_ctx
;
4142 struct xhci_input_control_ctx
*ctrl_ctx
;
4144 struct xhci_command
*command
= NULL
;
4146 mutex_lock(&xhci
->mutex
);
4148 if (xhci
->xhc_state
) { /* dying, removing or halted */
4153 if (!udev
->slot_id
) {
4154 xhci_dbg_trace(xhci
, trace_xhci_dbg_address
,
4155 "Bad Slot ID %d", udev
->slot_id
);
4160 virt_dev
= xhci
->devs
[udev
->slot_id
];
4162 if (WARN_ON(!virt_dev
)) {
4164 * In plug/unplug torture test with an NEC controller,
4165 * a zero-dereference was observed once due to virt_dev = 0.
4166 * Print useful debug rather than crash if it is observed again!
4168 xhci_warn(xhci
, "Virt dev invalid for slot_id 0x%x!\n",
4173 slot_ctx
= xhci_get_slot_ctx(xhci
, virt_dev
->out_ctx
);
4174 trace_xhci_setup_device_slot(slot_ctx
);
4176 if (setup
== SETUP_CONTEXT_ONLY
) {
4177 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx
->dev_state
)) ==
4178 SLOT_STATE_DEFAULT
) {
4179 xhci_dbg(xhci
, "Slot already in default state\n");
4184 command
= xhci_alloc_command(xhci
, true, GFP_KERNEL
);
4190 command
->in_ctx
= virt_dev
->in_ctx
;
4192 slot_ctx
= xhci_get_slot_ctx(xhci
, virt_dev
->in_ctx
);
4193 ctrl_ctx
= xhci_get_input_control_ctx(virt_dev
->in_ctx
);
4195 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
4201 * If this is the first Set Address since device plug-in or
4202 * virt_device realloaction after a resume with an xHCI power loss,
4203 * then set up the slot context.
4205 if (!slot_ctx
->dev_info
)
4206 xhci_setup_addressable_virt_dev(xhci
, udev
);
4207 /* Otherwise, update the control endpoint ring enqueue pointer. */
4209 xhci_copy_ep0_dequeue_into_input_ctx(xhci
, udev
);
4210 ctrl_ctx
->add_flags
= cpu_to_le32(SLOT_FLAG
| EP0_FLAG
);
4211 ctrl_ctx
->drop_flags
= 0;
4213 trace_xhci_address_ctx(xhci
, virt_dev
->in_ctx
,
4214 le32_to_cpu(slot_ctx
->dev_info
) >> 27);
4216 trace_xhci_address_ctrl_ctx(ctrl_ctx
);
4217 spin_lock_irqsave(&xhci
->lock
, flags
);
4218 trace_xhci_setup_device(virt_dev
);
4219 ret
= xhci_queue_address_device(xhci
, command
, virt_dev
->in_ctx
->dma
,
4220 udev
->slot_id
, setup
);
4222 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4223 xhci_dbg_trace(xhci
, trace_xhci_dbg_address
,
4224 "FIXME: allocate a command ring segment");
4227 xhci_ring_cmd_db(xhci
);
4228 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4230 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
4231 wait_for_completion(command
->completion
);
4233 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
4234 * the SetAddress() "recovery interval" required by USB and aborting the
4235 * command on a timeout.
4237 switch (command
->status
) {
4238 case COMP_COMMAND_ABORTED
:
4239 case COMP_COMMAND_RING_STOPPED
:
4240 xhci_warn(xhci
, "Timeout while waiting for setup device command\n");
4243 case COMP_CONTEXT_STATE_ERROR
:
4244 case COMP_SLOT_NOT_ENABLED_ERROR
:
4245 xhci_err(xhci
, "Setup ERROR: setup %s command for slot %d.\n",
4246 act
, udev
->slot_id
);
4249 case COMP_USB_TRANSACTION_ERROR
:
4250 dev_warn(&udev
->dev
, "Device not responding to setup %s.\n", act
);
4252 mutex_unlock(&xhci
->mutex
);
4253 ret
= xhci_disable_slot(xhci
, udev
->slot_id
);
4254 xhci_free_virt_device(xhci
, udev
->slot_id
);
4256 xhci_alloc_dev(hcd
, udev
);
4257 kfree(command
->completion
);
4260 case COMP_INCOMPATIBLE_DEVICE_ERROR
:
4261 dev_warn(&udev
->dev
,
4262 "ERROR: Incompatible device for setup %s command\n", act
);
4266 xhci_dbg_trace(xhci
, trace_xhci_dbg_address
,
4267 "Successful setup %s command", act
);
4271 "ERROR: unexpected setup %s command completion code 0x%x.\n",
4272 act
, command
->status
);
4273 trace_xhci_address_ctx(xhci
, virt_dev
->out_ctx
, 1);
4279 temp_64
= xhci_read_64(xhci
, &xhci
->op_regs
->dcbaa_ptr
);
4280 xhci_dbg_trace(xhci
, trace_xhci_dbg_address
,
4281 "Op regs DCBAA ptr = %#016llx", temp_64
);
4282 xhci_dbg_trace(xhci
, trace_xhci_dbg_address
,
4283 "Slot ID %d dcbaa entry @%p = %#016llx",
4285 &xhci
->dcbaa
->dev_context_ptrs
[udev
->slot_id
],
4286 (unsigned long long)
4287 le64_to_cpu(xhci
->dcbaa
->dev_context_ptrs
[udev
->slot_id
]));
4288 xhci_dbg_trace(xhci
, trace_xhci_dbg_address
,
4289 "Output Context DMA address = %#08llx",
4290 (unsigned long long)virt_dev
->out_ctx
->dma
);
4291 trace_xhci_address_ctx(xhci
, virt_dev
->in_ctx
,
4292 le32_to_cpu(slot_ctx
->dev_info
) >> 27);
4294 * USB core uses address 1 for the roothubs, so we add one to the
4295 * address given back to us by the HC.
4297 trace_xhci_address_ctx(xhci
, virt_dev
->out_ctx
,
4298 le32_to_cpu(slot_ctx
->dev_info
) >> 27);
4299 /* Zero the input context control for later use */
4300 ctrl_ctx
->add_flags
= 0;
4301 ctrl_ctx
->drop_flags
= 0;
4302 slot_ctx
= xhci_get_slot_ctx(xhci
, virt_dev
->out_ctx
);
4303 udev
->devaddr
= (u8
)(le32_to_cpu(slot_ctx
->dev_state
) & DEV_ADDR_MASK
);
4305 xhci_dbg_trace(xhci
, trace_xhci_dbg_address
,
4306 "Internal device address = %d",
4307 le32_to_cpu(slot_ctx
->dev_state
) & DEV_ADDR_MASK
);
4309 mutex_unlock(&xhci
->mutex
);
4311 kfree(command
->completion
);
4317 static int xhci_address_device(struct usb_hcd
*hcd
, struct usb_device
*udev
)
4319 return xhci_setup_device(hcd
, udev
, SETUP_CONTEXT_ADDRESS
);
4322 static int xhci_enable_device(struct usb_hcd
*hcd
, struct usb_device
*udev
)
4324 return xhci_setup_device(hcd
, udev
, SETUP_CONTEXT_ONLY
);
4328 * Transfer the port index into real index in the HW port status
4329 * registers. Caculate offset between the port's PORTSC register
4330 * and port status base. Divide the number of per port register
4331 * to get the real index. The raw port number bases 1.
4333 int xhci_find_raw_port_number(struct usb_hcd
*hcd
, int port1
)
4335 struct xhci_hub
*rhub
;
4337 rhub
= xhci_get_rhub(hcd
);
4338 return rhub
->ports
[port1
- 1]->hw_portnum
+ 1;
4342 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4343 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4345 static int __maybe_unused
xhci_change_max_exit_latency(struct xhci_hcd
*xhci
,
4346 struct usb_device
*udev
, u16 max_exit_latency
)
4348 struct xhci_virt_device
*virt_dev
;
4349 struct xhci_command
*command
;
4350 struct xhci_input_control_ctx
*ctrl_ctx
;
4351 struct xhci_slot_ctx
*slot_ctx
;
4352 unsigned long flags
;
4355 spin_lock_irqsave(&xhci
->lock
, flags
);
4357 virt_dev
= xhci
->devs
[udev
->slot_id
];
4360 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4361 * xHC was re-initialized. Exit latency will be set later after
4362 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4365 if (!virt_dev
|| max_exit_latency
== virt_dev
->current_mel
) {
4366 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4370 /* Attempt to issue an Evaluate Context command to change the MEL. */
4371 command
= xhci
->lpm_command
;
4372 ctrl_ctx
= xhci_get_input_control_ctx(command
->in_ctx
);
4374 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4375 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
4380 xhci_slot_copy(xhci
, command
->in_ctx
, virt_dev
->out_ctx
);
4381 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4383 ctrl_ctx
->add_flags
|= cpu_to_le32(SLOT_FLAG
);
4384 slot_ctx
= xhci_get_slot_ctx(xhci
, command
->in_ctx
);
4385 slot_ctx
->dev_info2
&= cpu_to_le32(~((u32
) MAX_EXIT
));
4386 slot_ctx
->dev_info2
|= cpu_to_le32(max_exit_latency
);
4387 slot_ctx
->dev_state
= 0;
4389 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
4390 "Set up evaluate context for LPM MEL change.");
4392 /* Issue and wait for the evaluate context command. */
4393 ret
= xhci_configure_endpoint(xhci
, udev
, command
,
4397 spin_lock_irqsave(&xhci
->lock
, flags
);
4398 virt_dev
->current_mel
= max_exit_latency
;
4399 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4406 /* BESL to HIRD Encoding array for USB2 LPM */
4407 static int xhci_besl_encoding
[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4408 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4410 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4411 static int xhci_calculate_hird_besl(struct xhci_hcd
*xhci
,
4412 struct usb_device
*udev
)
4414 int u2del
, besl
, besl_host
;
4415 int besl_device
= 0;
4418 u2del
= HCS_U2_LATENCY(xhci
->hcs_params3
);
4419 field
= le32_to_cpu(udev
->bos
->ext_cap
->bmAttributes
);
4421 if (field
& USB_BESL_SUPPORT
) {
4422 for (besl_host
= 0; besl_host
< 16; besl_host
++) {
4423 if (xhci_besl_encoding
[besl_host
] >= u2del
)
4426 /* Use baseline BESL value as default */
4427 if (field
& USB_BESL_BASELINE_VALID
)
4428 besl_device
= USB_GET_BESL_BASELINE(field
);
4429 else if (field
& USB_BESL_DEEP_VALID
)
4430 besl_device
= USB_GET_BESL_DEEP(field
);
4435 besl_host
= (u2del
- 51) / 75 + 1;
4438 besl
= besl_host
+ besl_device
;
4445 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4446 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device
*udev
)
4453 field
= le32_to_cpu(udev
->bos
->ext_cap
->bmAttributes
);
4455 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4456 l1
= udev
->l1_params
.timeout
/ 256;
4458 /* device has preferred BESLD */
4459 if (field
& USB_BESL_DEEP_VALID
) {
4460 besld
= USB_GET_BESL_DEEP(field
);
4464 return PORT_BESLD(besld
) | PORT_L1_TIMEOUT(l1
) | PORT_HIRDM(hirdm
);
4467 static int xhci_set_usb2_hardware_lpm(struct usb_hcd
*hcd
,
4468 struct usb_device
*udev
, int enable
)
4470 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
4471 struct xhci_port
**ports
;
4472 __le32 __iomem
*pm_addr
, *hlpm_addr
;
4473 u32 pm_val
, hlpm_val
, field
;
4474 unsigned int port_num
;
4475 unsigned long flags
;
4476 int hird
, exit_latency
;
4479 if (xhci
->quirks
& XHCI_HW_LPM_DISABLE
)
4482 if (hcd
->speed
>= HCD_USB3
|| !xhci
->hw_lpm_support
||
4486 if (!udev
->parent
|| udev
->parent
->parent
||
4487 udev
->descriptor
.bDeviceClass
== USB_CLASS_HUB
)
4490 if (udev
->usb2_hw_lpm_capable
!= 1)
4493 spin_lock_irqsave(&xhci
->lock
, flags
);
4495 ports
= xhci
->usb2_rhub
.ports
;
4496 port_num
= udev
->portnum
- 1;
4497 pm_addr
= ports
[port_num
]->addr
+ PORTPMSC
;
4498 pm_val
= readl(pm_addr
);
4499 hlpm_addr
= ports
[port_num
]->addr
+ PORTHLPMC
;
4501 xhci_dbg(xhci
, "%s port %d USB2 hardware LPM\n",
4502 enable
? "enable" : "disable", port_num
+ 1);
4505 /* Host supports BESL timeout instead of HIRD */
4506 if (udev
->usb2_hw_lpm_besl_capable
) {
4507 /* if device doesn't have a preferred BESL value use a
4508 * default one which works with mixed HIRD and BESL
4509 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4511 field
= le32_to_cpu(udev
->bos
->ext_cap
->bmAttributes
);
4512 if ((field
& USB_BESL_SUPPORT
) &&
4513 (field
& USB_BESL_BASELINE_VALID
))
4514 hird
= USB_GET_BESL_BASELINE(field
);
4516 hird
= udev
->l1_params
.besl
;
4518 exit_latency
= xhci_besl_encoding
[hird
];
4519 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4521 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4522 * input context for link powermanagement evaluate
4523 * context commands. It is protected by hcd->bandwidth
4524 * mutex and is shared by all devices. We need to set
4525 * the max ext latency in USB 2 BESL LPM as well, so
4526 * use the same mutex and xhci_change_max_exit_latency()
4528 mutex_lock(hcd
->bandwidth_mutex
);
4529 ret
= xhci_change_max_exit_latency(xhci
, udev
,
4531 mutex_unlock(hcd
->bandwidth_mutex
);
4535 spin_lock_irqsave(&xhci
->lock
, flags
);
4537 hlpm_val
= xhci_calculate_usb2_hw_lpm_params(udev
);
4538 writel(hlpm_val
, hlpm_addr
);
4542 hird
= xhci_calculate_hird_besl(xhci
, udev
);
4545 pm_val
&= ~PORT_HIRD_MASK
;
4546 pm_val
|= PORT_HIRD(hird
) | PORT_RWE
| PORT_L1DS(udev
->slot_id
);
4547 writel(pm_val
, pm_addr
);
4548 pm_val
= readl(pm_addr
);
4550 writel(pm_val
, pm_addr
);
4554 pm_val
&= ~(PORT_HLE
| PORT_RWE
| PORT_HIRD_MASK
| PORT_L1DS_MASK
);
4555 writel(pm_val
, pm_addr
);
4558 if (udev
->usb2_hw_lpm_besl_capable
) {
4559 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4560 mutex_lock(hcd
->bandwidth_mutex
);
4561 xhci_change_max_exit_latency(xhci
, udev
, 0);
4562 mutex_unlock(hcd
->bandwidth_mutex
);
4563 readl_poll_timeout(ports
[port_num
]->addr
, pm_val
,
4564 (pm_val
& PORT_PLS_MASK
) == XDEV_U0
,
4570 spin_unlock_irqrestore(&xhci
->lock
, flags
);
4574 /* check if a usb2 port supports a given extened capability protocol
4575 * only USB2 ports extended protocol capability values are cached.
4576 * Return 1 if capability is supported
4578 static int xhci_check_usb2_port_capability(struct xhci_hcd
*xhci
, int port
,
4579 unsigned capability
)
4581 u32 port_offset
, port_count
;
4584 for (i
= 0; i
< xhci
->num_ext_caps
; i
++) {
4585 if (xhci
->ext_caps
[i
] & capability
) {
4586 /* port offsets starts at 1 */
4587 port_offset
= XHCI_EXT_PORT_OFF(xhci
->ext_caps
[i
]) - 1;
4588 port_count
= XHCI_EXT_PORT_COUNT(xhci
->ext_caps
[i
]);
4589 if (port
>= port_offset
&&
4590 port
< port_offset
+ port_count
)
4597 static int xhci_update_device(struct usb_hcd
*hcd
, struct usb_device
*udev
)
4599 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
4600 int portnum
= udev
->portnum
- 1;
4602 if (hcd
->speed
>= HCD_USB3
|| !udev
->lpm_capable
)
4605 /* we only support lpm for non-hub device connected to root hub yet */
4606 if (!udev
->parent
|| udev
->parent
->parent
||
4607 udev
->descriptor
.bDeviceClass
== USB_CLASS_HUB
)
4610 if (xhci
->hw_lpm_support
== 1 &&
4611 xhci_check_usb2_port_capability(
4612 xhci
, portnum
, XHCI_HLC
)) {
4613 udev
->usb2_hw_lpm_capable
= 1;
4614 udev
->l1_params
.timeout
= XHCI_L1_TIMEOUT
;
4615 udev
->l1_params
.besl
= XHCI_DEFAULT_BESL
;
4616 if (xhci_check_usb2_port_capability(xhci
, portnum
,
4618 udev
->usb2_hw_lpm_besl_capable
= 1;
4624 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4626 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4627 static unsigned long long xhci_service_interval_to_ns(
4628 struct usb_endpoint_descriptor
*desc
)
4630 return (1ULL << (desc
->bInterval
- 1)) * 125 * 1000;
4633 static u16
xhci_get_timeout_no_hub_lpm(struct usb_device
*udev
,
4634 enum usb3_link_state state
)
4636 unsigned long long sel
;
4637 unsigned long long pel
;
4638 unsigned int max_sel_pel
;
4643 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4644 sel
= DIV_ROUND_UP(udev
->u1_params
.sel
, 1000);
4645 pel
= DIV_ROUND_UP(udev
->u1_params
.pel
, 1000);
4646 max_sel_pel
= USB3_LPM_MAX_U1_SEL_PEL
;
4650 sel
= DIV_ROUND_UP(udev
->u2_params
.sel
, 1000);
4651 pel
= DIV_ROUND_UP(udev
->u2_params
.pel
, 1000);
4652 max_sel_pel
= USB3_LPM_MAX_U2_SEL_PEL
;
4656 dev_warn(&udev
->dev
, "%s: Can't get timeout for non-U1 or U2 state.\n",
4658 return USB3_LPM_DISABLED
;
4661 if (sel
<= max_sel_pel
&& pel
<= max_sel_pel
)
4662 return USB3_LPM_DEVICE_INITIATED
;
4664 if (sel
> max_sel_pel
)
4665 dev_dbg(&udev
->dev
, "Device-initiated %s disabled "
4666 "due to long SEL %llu ms\n",
4669 dev_dbg(&udev
->dev
, "Device-initiated %s disabled "
4670 "due to long PEL %llu ms\n",
4672 return USB3_LPM_DISABLED
;
4675 /* The U1 timeout should be the maximum of the following values:
4676 * - For control endpoints, U1 system exit latency (SEL) * 3
4677 * - For bulk endpoints, U1 SEL * 5
4678 * - For interrupt endpoints:
4679 * - Notification EPs, U1 SEL * 3
4680 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4681 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4683 static unsigned long long xhci_calculate_intel_u1_timeout(
4684 struct usb_device
*udev
,
4685 struct usb_endpoint_descriptor
*desc
)
4687 unsigned long long timeout_ns
;
4691 ep_type
= usb_endpoint_type(desc
);
4693 case USB_ENDPOINT_XFER_CONTROL
:
4694 timeout_ns
= udev
->u1_params
.sel
* 3;
4696 case USB_ENDPOINT_XFER_BULK
:
4697 timeout_ns
= udev
->u1_params
.sel
* 5;
4699 case USB_ENDPOINT_XFER_INT
:
4700 intr_type
= usb_endpoint_interrupt_type(desc
);
4701 if (intr_type
== USB_ENDPOINT_INTR_NOTIFICATION
) {
4702 timeout_ns
= udev
->u1_params
.sel
* 3;
4705 /* Otherwise the calculation is the same as isoc eps */
4707 case USB_ENDPOINT_XFER_ISOC
:
4708 timeout_ns
= xhci_service_interval_to_ns(desc
);
4709 timeout_ns
= DIV_ROUND_UP_ULL(timeout_ns
* 105, 100);
4710 if (timeout_ns
< udev
->u1_params
.sel
* 2)
4711 timeout_ns
= udev
->u1_params
.sel
* 2;
4720 /* Returns the hub-encoded U1 timeout value. */
4721 static u16
xhci_calculate_u1_timeout(struct xhci_hcd
*xhci
,
4722 struct usb_device
*udev
,
4723 struct usb_endpoint_descriptor
*desc
)
4725 unsigned long long timeout_ns
;
4727 /* Prevent U1 if service interval is shorter than U1 exit latency */
4728 if (usb_endpoint_xfer_int(desc
) || usb_endpoint_xfer_isoc(desc
)) {
4729 if (xhci_service_interval_to_ns(desc
) <= udev
->u1_params
.mel
) {
4730 dev_dbg(&udev
->dev
, "Disable U1, ESIT shorter than exit latency\n");
4731 return USB3_LPM_DISABLED
;
4735 if (xhci
->quirks
& XHCI_INTEL_HOST
)
4736 timeout_ns
= xhci_calculate_intel_u1_timeout(udev
, desc
);
4738 timeout_ns
= udev
->u1_params
.sel
;
4740 /* The U1 timeout is encoded in 1us intervals.
4741 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4743 if (timeout_ns
== USB3_LPM_DISABLED
)
4746 timeout_ns
= DIV_ROUND_UP_ULL(timeout_ns
, 1000);
4748 /* If the necessary timeout value is bigger than what we can set in the
4749 * USB 3.0 hub, we have to disable hub-initiated U1.
4751 if (timeout_ns
<= USB3_LPM_U1_MAX_TIMEOUT
)
4753 dev_dbg(&udev
->dev
, "Hub-initiated U1 disabled "
4754 "due to long timeout %llu ms\n", timeout_ns
);
4755 return xhci_get_timeout_no_hub_lpm(udev
, USB3_LPM_U1
);
4758 /* The U2 timeout should be the maximum of:
4759 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4760 * - largest bInterval of any active periodic endpoint (to avoid going
4761 * into lower power link states between intervals).
4762 * - the U2 Exit Latency of the device
4764 static unsigned long long xhci_calculate_intel_u2_timeout(
4765 struct usb_device
*udev
,
4766 struct usb_endpoint_descriptor
*desc
)
4768 unsigned long long timeout_ns
;
4769 unsigned long long u2_del_ns
;
4771 timeout_ns
= 10 * 1000 * 1000;
4773 if ((usb_endpoint_xfer_int(desc
) || usb_endpoint_xfer_isoc(desc
)) &&
4774 (xhci_service_interval_to_ns(desc
) > timeout_ns
))
4775 timeout_ns
= xhci_service_interval_to_ns(desc
);
4777 u2_del_ns
= le16_to_cpu(udev
->bos
->ss_cap
->bU2DevExitLat
) * 1000ULL;
4778 if (u2_del_ns
> timeout_ns
)
4779 timeout_ns
= u2_del_ns
;
4784 /* Returns the hub-encoded U2 timeout value. */
4785 static u16
xhci_calculate_u2_timeout(struct xhci_hcd
*xhci
,
4786 struct usb_device
*udev
,
4787 struct usb_endpoint_descriptor
*desc
)
4789 unsigned long long timeout_ns
;
4791 /* Prevent U2 if service interval is shorter than U2 exit latency */
4792 if (usb_endpoint_xfer_int(desc
) || usb_endpoint_xfer_isoc(desc
)) {
4793 if (xhci_service_interval_to_ns(desc
) <= udev
->u2_params
.mel
) {
4794 dev_dbg(&udev
->dev
, "Disable U2, ESIT shorter than exit latency\n");
4795 return USB3_LPM_DISABLED
;
4799 if (xhci
->quirks
& XHCI_INTEL_HOST
)
4800 timeout_ns
= xhci_calculate_intel_u2_timeout(udev
, desc
);
4802 timeout_ns
= udev
->u2_params
.sel
;
4804 /* The U2 timeout is encoded in 256us intervals */
4805 timeout_ns
= DIV_ROUND_UP_ULL(timeout_ns
, 256 * 1000);
4806 /* If the necessary timeout value is bigger than what we can set in the
4807 * USB 3.0 hub, we have to disable hub-initiated U2.
4809 if (timeout_ns
<= USB3_LPM_U2_MAX_TIMEOUT
)
4811 dev_dbg(&udev
->dev
, "Hub-initiated U2 disabled "
4812 "due to long timeout %llu ms\n", timeout_ns
);
4813 return xhci_get_timeout_no_hub_lpm(udev
, USB3_LPM_U2
);
4816 static u16
xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd
*xhci
,
4817 struct usb_device
*udev
,
4818 struct usb_endpoint_descriptor
*desc
,
4819 enum usb3_link_state state
,
4822 if (state
== USB3_LPM_U1
)
4823 return xhci_calculate_u1_timeout(xhci
, udev
, desc
);
4824 else if (state
== USB3_LPM_U2
)
4825 return xhci_calculate_u2_timeout(xhci
, udev
, desc
);
4827 return USB3_LPM_DISABLED
;
4830 static int xhci_update_timeout_for_endpoint(struct xhci_hcd
*xhci
,
4831 struct usb_device
*udev
,
4832 struct usb_endpoint_descriptor
*desc
,
4833 enum usb3_link_state state
,
4838 alt_timeout
= xhci_call_host_update_timeout_for_endpoint(xhci
, udev
,
4839 desc
, state
, timeout
);
4841 /* If we found we can't enable hub-initiated LPM, and
4842 * the U1 or U2 exit latency was too high to allow
4843 * device-initiated LPM as well, then we will disable LPM
4844 * for this device, so stop searching any further.
4846 if (alt_timeout
== USB3_LPM_DISABLED
) {
4847 *timeout
= alt_timeout
;
4850 if (alt_timeout
> *timeout
)
4851 *timeout
= alt_timeout
;
4855 static int xhci_update_timeout_for_interface(struct xhci_hcd
*xhci
,
4856 struct usb_device
*udev
,
4857 struct usb_host_interface
*alt
,
4858 enum usb3_link_state state
,
4863 for (j
= 0; j
< alt
->desc
.bNumEndpoints
; j
++) {
4864 if (xhci_update_timeout_for_endpoint(xhci
, udev
,
4865 &alt
->endpoint
[j
].desc
, state
, timeout
))
4871 static int xhci_check_intel_tier_policy(struct usb_device
*udev
,
4872 enum usb3_link_state state
)
4874 struct usb_device
*parent
;
4875 unsigned int num_hubs
;
4877 if (state
== USB3_LPM_U2
)
4880 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4881 for (parent
= udev
->parent
, num_hubs
= 0; parent
->parent
;
4882 parent
= parent
->parent
)
4888 dev_dbg(&udev
->dev
, "Disabling U1 link state for device"
4889 " below second-tier hub.\n");
4890 dev_dbg(&udev
->dev
, "Plug device into first-tier hub "
4891 "to decrease power consumption.\n");
4895 static int xhci_check_tier_policy(struct xhci_hcd
*xhci
,
4896 struct usb_device
*udev
,
4897 enum usb3_link_state state
)
4899 if (xhci
->quirks
& XHCI_INTEL_HOST
)
4900 return xhci_check_intel_tier_policy(udev
, state
);
4905 /* Returns the U1 or U2 timeout that should be enabled.
4906 * If the tier check or timeout setting functions return with a non-zero exit
4907 * code, that means the timeout value has been finalized and we shouldn't look
4908 * at any more endpoints.
4910 static u16
xhci_calculate_lpm_timeout(struct usb_hcd
*hcd
,
4911 struct usb_device
*udev
, enum usb3_link_state state
)
4913 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
4914 struct usb_host_config
*config
;
4917 u16 timeout
= USB3_LPM_DISABLED
;
4919 if (state
== USB3_LPM_U1
)
4921 else if (state
== USB3_LPM_U2
)
4924 dev_warn(&udev
->dev
, "Can't enable unknown link state %i\n",
4929 if (xhci_check_tier_policy(xhci
, udev
, state
) < 0)
4932 /* Gather some information about the currently installed configuration
4933 * and alternate interface settings.
4935 if (xhci_update_timeout_for_endpoint(xhci
, udev
, &udev
->ep0
.desc
,
4939 config
= udev
->actconfig
;
4943 for (i
= 0; i
< config
->desc
.bNumInterfaces
; i
++) {
4944 struct usb_driver
*driver
;
4945 struct usb_interface
*intf
= config
->interface
[i
];
4950 /* Check if any currently bound drivers want hub-initiated LPM
4953 if (intf
->dev
.driver
) {
4954 driver
= to_usb_driver(intf
->dev
.driver
);
4955 if (driver
&& driver
->disable_hub_initiated_lpm
) {
4956 dev_dbg(&udev
->dev
, "Hub-initiated %s disabled at request of driver %s\n",
4957 state_name
, driver
->name
);
4958 timeout
= xhci_get_timeout_no_hub_lpm(udev
,
4960 if (timeout
== USB3_LPM_DISABLED
)
4965 /* Not sure how this could happen... */
4966 if (!intf
->cur_altsetting
)
4969 if (xhci_update_timeout_for_interface(xhci
, udev
,
4970 intf
->cur_altsetting
,
4977 static int calculate_max_exit_latency(struct usb_device
*udev
,
4978 enum usb3_link_state state_changed
,
4979 u16 hub_encoded_timeout
)
4981 unsigned long long u1_mel_us
= 0;
4982 unsigned long long u2_mel_us
= 0;
4983 unsigned long long mel_us
= 0;
4989 disabling_u1
= (state_changed
== USB3_LPM_U1
&&
4990 hub_encoded_timeout
== USB3_LPM_DISABLED
);
4991 disabling_u2
= (state_changed
== USB3_LPM_U2
&&
4992 hub_encoded_timeout
== USB3_LPM_DISABLED
);
4994 enabling_u1
= (state_changed
== USB3_LPM_U1
&&
4995 hub_encoded_timeout
!= USB3_LPM_DISABLED
);
4996 enabling_u2
= (state_changed
== USB3_LPM_U2
&&
4997 hub_encoded_timeout
!= USB3_LPM_DISABLED
);
4999 /* If U1 was already enabled and we're not disabling it,
5000 * or we're going to enable U1, account for the U1 max exit latency.
5002 if ((udev
->u1_params
.timeout
!= USB3_LPM_DISABLED
&& !disabling_u1
) ||
5004 u1_mel_us
= DIV_ROUND_UP(udev
->u1_params
.mel
, 1000);
5005 if ((udev
->u2_params
.timeout
!= USB3_LPM_DISABLED
&& !disabling_u2
) ||
5007 u2_mel_us
= DIV_ROUND_UP(udev
->u2_params
.mel
, 1000);
5009 if (u1_mel_us
> u2_mel_us
)
5013 /* xHCI host controller max exit latency field is only 16 bits wide. */
5014 if (mel_us
> MAX_EXIT
) {
5015 dev_warn(&udev
->dev
, "Link PM max exit latency of %lluus "
5016 "is too big.\n", mel_us
);
5022 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
5023 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd
*hcd
,
5024 struct usb_device
*udev
, enum usb3_link_state state
)
5026 struct xhci_hcd
*xhci
;
5027 u16 hub_encoded_timeout
;
5031 xhci
= hcd_to_xhci(hcd
);
5032 /* The LPM timeout values are pretty host-controller specific, so don't
5033 * enable hub-initiated timeouts unless the vendor has provided
5034 * information about their timeout algorithm.
5036 if (!xhci
|| !(xhci
->quirks
& XHCI_LPM_SUPPORT
) ||
5037 !xhci
->devs
[udev
->slot_id
])
5038 return USB3_LPM_DISABLED
;
5040 hub_encoded_timeout
= xhci_calculate_lpm_timeout(hcd
, udev
, state
);
5041 mel
= calculate_max_exit_latency(udev
, state
, hub_encoded_timeout
);
5043 /* Max Exit Latency is too big, disable LPM. */
5044 hub_encoded_timeout
= USB3_LPM_DISABLED
;
5048 ret
= xhci_change_max_exit_latency(xhci
, udev
, mel
);
5051 return hub_encoded_timeout
;
5054 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd
*hcd
,
5055 struct usb_device
*udev
, enum usb3_link_state state
)
5057 struct xhci_hcd
*xhci
;
5060 xhci
= hcd_to_xhci(hcd
);
5061 if (!xhci
|| !(xhci
->quirks
& XHCI_LPM_SUPPORT
) ||
5062 !xhci
->devs
[udev
->slot_id
])
5065 mel
= calculate_max_exit_latency(udev
, state
, USB3_LPM_DISABLED
);
5066 return xhci_change_max_exit_latency(xhci
, udev
, mel
);
5068 #else /* CONFIG_PM */
5070 static int xhci_set_usb2_hardware_lpm(struct usb_hcd
*hcd
,
5071 struct usb_device
*udev
, int enable
)
5076 static int xhci_update_device(struct usb_hcd
*hcd
, struct usb_device
*udev
)
5081 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd
*hcd
,
5082 struct usb_device
*udev
, enum usb3_link_state state
)
5084 return USB3_LPM_DISABLED
;
5087 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd
*hcd
,
5088 struct usb_device
*udev
, enum usb3_link_state state
)
5092 #endif /* CONFIG_PM */
5094 /*-------------------------------------------------------------------------*/
5096 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
5097 * internal data structures for the device.
5099 static int xhci_update_hub_device(struct usb_hcd
*hcd
, struct usb_device
*hdev
,
5100 struct usb_tt
*tt
, gfp_t mem_flags
)
5102 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
5103 struct xhci_virt_device
*vdev
;
5104 struct xhci_command
*config_cmd
;
5105 struct xhci_input_control_ctx
*ctrl_ctx
;
5106 struct xhci_slot_ctx
*slot_ctx
;
5107 unsigned long flags
;
5108 unsigned think_time
;
5111 /* Ignore root hubs */
5115 vdev
= xhci
->devs
[hdev
->slot_id
];
5117 xhci_warn(xhci
, "Cannot update hub desc for unknown device.\n");
5121 config_cmd
= xhci_alloc_command_with_ctx(xhci
, true, mem_flags
);
5125 ctrl_ctx
= xhci_get_input_control_ctx(config_cmd
->in_ctx
);
5127 xhci_warn(xhci
, "%s: Could not get input context, bad type.\n",
5129 xhci_free_command(xhci
, config_cmd
);
5133 spin_lock_irqsave(&xhci
->lock
, flags
);
5134 if (hdev
->speed
== USB_SPEED_HIGH
&&
5135 xhci_alloc_tt_info(xhci
, vdev
, hdev
, tt
, GFP_ATOMIC
)) {
5136 xhci_dbg(xhci
, "Could not allocate xHCI TT structure.\n");
5137 xhci_free_command(xhci
, config_cmd
);
5138 spin_unlock_irqrestore(&xhci
->lock
, flags
);
5142 xhci_slot_copy(xhci
, config_cmd
->in_ctx
, vdev
->out_ctx
);
5143 ctrl_ctx
->add_flags
|= cpu_to_le32(SLOT_FLAG
);
5144 slot_ctx
= xhci_get_slot_ctx(xhci
, config_cmd
->in_ctx
);
5145 slot_ctx
->dev_info
|= cpu_to_le32(DEV_HUB
);
5147 * refer to section 6.2.2: MTT should be 0 for full speed hub,
5148 * but it may be already set to 1 when setup an xHCI virtual
5149 * device, so clear it anyway.
5152 slot_ctx
->dev_info
|= cpu_to_le32(DEV_MTT
);
5153 else if (hdev
->speed
== USB_SPEED_FULL
)
5154 slot_ctx
->dev_info
&= cpu_to_le32(~DEV_MTT
);
5156 if (xhci
->hci_version
> 0x95) {
5157 xhci_dbg(xhci
, "xHCI version %x needs hub "
5158 "TT think time and number of ports\n",
5159 (unsigned int) xhci
->hci_version
);
5160 slot_ctx
->dev_info2
|= cpu_to_le32(XHCI_MAX_PORTS(hdev
->maxchild
));
5161 /* Set TT think time - convert from ns to FS bit times.
5162 * 0 = 8 FS bit times, 1 = 16 FS bit times,
5163 * 2 = 24 FS bit times, 3 = 32 FS bit times.
5165 * xHCI 1.0: this field shall be 0 if the device is not a
5168 think_time
= tt
->think_time
;
5169 if (think_time
!= 0)
5170 think_time
= (think_time
/ 666) - 1;
5171 if (xhci
->hci_version
< 0x100 || hdev
->speed
== USB_SPEED_HIGH
)
5172 slot_ctx
->tt_info
|=
5173 cpu_to_le32(TT_THINK_TIME(think_time
));
5175 xhci_dbg(xhci
, "xHCI version %x doesn't need hub "
5176 "TT think time or number of ports\n",
5177 (unsigned int) xhci
->hci_version
);
5179 slot_ctx
->dev_state
= 0;
5180 spin_unlock_irqrestore(&xhci
->lock
, flags
);
5182 xhci_dbg(xhci
, "Set up %s for hub device.\n",
5183 (xhci
->hci_version
> 0x95) ?
5184 "configure endpoint" : "evaluate context");
5186 /* Issue and wait for the configure endpoint or
5187 * evaluate context command.
5189 if (xhci
->hci_version
> 0x95)
5190 ret
= xhci_configure_endpoint(xhci
, hdev
, config_cmd
,
5193 ret
= xhci_configure_endpoint(xhci
, hdev
, config_cmd
,
5196 xhci_free_command(xhci
, config_cmd
);
5200 static int xhci_get_frame(struct usb_hcd
*hcd
)
5202 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
5203 /* EHCI mods by the periodic size. Why? */
5204 return readl(&xhci
->run_regs
->microframe_index
) >> 3;
5207 int xhci_gen_setup(struct usb_hcd
*hcd
, xhci_get_quirks_t get_quirks
)
5209 struct xhci_hcd
*xhci
;
5211 * TODO: Check with DWC3 clients for sysdev according to
5214 struct device
*dev
= hcd
->self
.sysdev
;
5215 unsigned int minor_rev
;
5218 /* Accept arbitrarily long scatter-gather lists */
5219 hcd
->self
.sg_tablesize
= ~0;
5221 /* support to build packet from discontinuous buffers */
5222 hcd
->self
.no_sg_constraint
= 1;
5224 /* XHCI controllers don't stop the ep queue on short packets :| */
5225 hcd
->self
.no_stop_on_short
= 1;
5227 xhci
= hcd_to_xhci(hcd
);
5229 if (usb_hcd_is_primary_hcd(hcd
)) {
5230 xhci
->main_hcd
= hcd
;
5231 xhci
->usb2_rhub
.hcd
= hcd
;
5232 /* Mark the first roothub as being USB 2.0.
5233 * The xHCI driver will register the USB 3.0 roothub.
5235 hcd
->speed
= HCD_USB2
;
5236 hcd
->self
.root_hub
->speed
= USB_SPEED_HIGH
;
5238 * USB 2.0 roothub under xHCI has an integrated TT,
5239 * (rate matching hub) as opposed to having an OHCI/UHCI
5240 * companion controller.
5245 * Early xHCI 1.1 spec did not mention USB 3.1 capable hosts
5246 * should return 0x31 for sbrn, or that the minor revision
5247 * is a two digit BCD containig minor and sub-minor numbers.
5248 * This was later clarified in xHCI 1.2.
5250 * Some USB 3.1 capable hosts therefore have sbrn 0x30, and
5251 * minor revision set to 0x1 instead of 0x10.
5253 if (xhci
->usb3_rhub
.min_rev
== 0x1)
5256 minor_rev
= xhci
->usb3_rhub
.min_rev
/ 0x10;
5258 switch (minor_rev
) {
5260 hcd
->speed
= HCD_USB32
;
5261 hcd
->self
.root_hub
->speed
= USB_SPEED_SUPER_PLUS
;
5262 hcd
->self
.root_hub
->rx_lanes
= 2;
5263 hcd
->self
.root_hub
->tx_lanes
= 2;
5264 hcd
->self
.root_hub
->ssp_rate
= USB_SSP_GEN_2x2
;
5267 hcd
->speed
= HCD_USB31
;
5268 hcd
->self
.root_hub
->speed
= USB_SPEED_SUPER_PLUS
;
5269 hcd
->self
.root_hub
->ssp_rate
= USB_SSP_GEN_2x1
;
5272 xhci_info(xhci
, "Host supports USB 3.%x %sSuperSpeed\n",
5274 minor_rev
? "Enhanced " : "");
5276 xhci
->usb3_rhub
.hcd
= hcd
;
5277 /* xHCI private pointer was set in xhci_pci_probe for the second
5278 * registered roothub.
5283 mutex_init(&xhci
->mutex
);
5284 xhci
->cap_regs
= hcd
->regs
;
5285 xhci
->op_regs
= hcd
->regs
+
5286 HC_LENGTH(readl(&xhci
->cap_regs
->hc_capbase
));
5287 xhci
->run_regs
= hcd
->regs
+
5288 (readl(&xhci
->cap_regs
->run_regs_off
) & RTSOFF_MASK
);
5289 /* Cache read-only capability registers */
5290 xhci
->hcs_params1
= readl(&xhci
->cap_regs
->hcs_params1
);
5291 xhci
->hcs_params2
= readl(&xhci
->cap_regs
->hcs_params2
);
5292 xhci
->hcs_params3
= readl(&xhci
->cap_regs
->hcs_params3
);
5293 xhci
->hcc_params
= readl(&xhci
->cap_regs
->hc_capbase
);
5294 xhci
->hci_version
= HC_VERSION(xhci
->hcc_params
);
5295 xhci
->hcc_params
= readl(&xhci
->cap_regs
->hcc_params
);
5296 if (xhci
->hci_version
> 0x100)
5297 xhci
->hcc_params2
= readl(&xhci
->cap_regs
->hcc_params2
);
5299 xhci
->quirks
|= quirks
;
5301 get_quirks(dev
, xhci
);
5303 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
5304 * success event after a short transfer. This quirk will ignore such
5307 if (xhci
->hci_version
> 0x96)
5308 xhci
->quirks
|= XHCI_SPURIOUS_SUCCESS
;
5310 /* Make sure the HC is halted. */
5311 retval
= xhci_halt(xhci
);
5315 xhci_zero_64b_regs(xhci
);
5317 xhci_dbg(xhci
, "Resetting HCD\n");
5318 /* Reset the internal HC memory state and registers. */
5319 retval
= xhci_reset(xhci
, XHCI_RESET_LONG_USEC
);
5322 xhci_dbg(xhci
, "Reset complete\n");
5325 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
5326 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
5327 * address memory pointers actually. So, this driver clears the AC64
5328 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
5329 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
5331 if (xhci
->quirks
& XHCI_NO_64BIT_SUPPORT
)
5332 xhci
->hcc_params
&= ~BIT(0);
5334 /* Set dma_mask and coherent_dma_mask to 64-bits,
5335 * if xHC supports 64-bit addressing */
5336 if (HCC_64BIT_ADDR(xhci
->hcc_params
) &&
5337 !dma_set_mask(dev
, DMA_BIT_MASK(64))) {
5338 xhci_dbg(xhci
, "Enabling 64-bit DMA addresses.\n");
5339 dma_set_coherent_mask(dev
, DMA_BIT_MASK(64));
5342 * This is to avoid error in cases where a 32-bit USB
5343 * controller is used on a 64-bit capable system.
5345 retval
= dma_set_mask(dev
, DMA_BIT_MASK(32));
5348 xhci_dbg(xhci
, "Enabling 32-bit DMA addresses.\n");
5349 dma_set_coherent_mask(dev
, DMA_BIT_MASK(32));
5352 xhci_dbg(xhci
, "Calling HCD init\n");
5353 /* Initialize HCD and host controller data structures. */
5354 retval
= xhci_init(hcd
);
5357 xhci_dbg(xhci
, "Called HCD init\n");
5359 xhci_info(xhci
, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
5360 xhci
->hcc_params
, xhci
->hci_version
, xhci
->quirks
);
5364 EXPORT_SYMBOL_GPL(xhci_gen_setup
);
5366 static void xhci_clear_tt_buffer_complete(struct usb_hcd
*hcd
,
5367 struct usb_host_endpoint
*ep
)
5369 struct xhci_hcd
*xhci
;
5370 struct usb_device
*udev
;
5371 unsigned int slot_id
;
5372 unsigned int ep_index
;
5373 unsigned long flags
;
5375 xhci
= hcd_to_xhci(hcd
);
5377 spin_lock_irqsave(&xhci
->lock
, flags
);
5378 udev
= (struct usb_device
*)ep
->hcpriv
;
5379 slot_id
= udev
->slot_id
;
5380 ep_index
= xhci_get_endpoint_index(&ep
->desc
);
5382 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&= ~EP_CLEARING_TT
;
5383 xhci_ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
5384 spin_unlock_irqrestore(&xhci
->lock
, flags
);
5387 static const struct hc_driver xhci_hc_driver
= {
5388 .description
= "xhci-hcd",
5389 .product_desc
= "xHCI Host Controller",
5390 .hcd_priv_size
= sizeof(struct xhci_hcd
),
5393 * generic hardware linkage
5396 .flags
= HCD_MEMORY
| HCD_DMA
| HCD_USB3
| HCD_SHARED
|
5400 * basic lifecycle operations
5402 .reset
= NULL
, /* set in xhci_init_driver() */
5405 .shutdown
= xhci_shutdown
,
5408 * managing i/o requests and associated device resources
5410 .map_urb_for_dma
= xhci_map_urb_for_dma
,
5411 .unmap_urb_for_dma
= xhci_unmap_urb_for_dma
,
5412 .urb_enqueue
= xhci_urb_enqueue
,
5413 .urb_dequeue
= xhci_urb_dequeue
,
5414 .alloc_dev
= xhci_alloc_dev
,
5415 .free_dev
= xhci_free_dev
,
5416 .alloc_streams
= xhci_alloc_streams
,
5417 .free_streams
= xhci_free_streams
,
5418 .add_endpoint
= xhci_add_endpoint
,
5419 .drop_endpoint
= xhci_drop_endpoint
,
5420 .endpoint_disable
= xhci_endpoint_disable
,
5421 .endpoint_reset
= xhci_endpoint_reset
,
5422 .check_bandwidth
= xhci_check_bandwidth
,
5423 .reset_bandwidth
= xhci_reset_bandwidth
,
5424 .address_device
= xhci_address_device
,
5425 .enable_device
= xhci_enable_device
,
5426 .update_hub_device
= xhci_update_hub_device
,
5427 .reset_device
= xhci_discover_or_reset_device
,
5430 * scheduling support
5432 .get_frame_number
= xhci_get_frame
,
5437 .hub_control
= xhci_hub_control
,
5438 .hub_status_data
= xhci_hub_status_data
,
5439 .bus_suspend
= xhci_bus_suspend
,
5440 .bus_resume
= xhci_bus_resume
,
5441 .get_resuming_ports
= xhci_get_resuming_ports
,
5444 * call back when device connected and addressed
5446 .update_device
= xhci_update_device
,
5447 .set_usb2_hw_lpm
= xhci_set_usb2_hardware_lpm
,
5448 .enable_usb3_lpm_timeout
= xhci_enable_usb3_lpm_timeout
,
5449 .disable_usb3_lpm_timeout
= xhci_disable_usb3_lpm_timeout
,
5450 .find_raw_port_number
= xhci_find_raw_port_number
,
5451 .clear_tt_buffer_complete
= xhci_clear_tt_buffer_complete
,
5454 void xhci_init_driver(struct hc_driver
*drv
,
5455 const struct xhci_driver_overrides
*over
)
5459 /* Copy the generic table to drv then apply the overrides */
5460 *drv
= xhci_hc_driver
;
5463 drv
->hcd_priv_size
+= over
->extra_priv_size
;
5465 drv
->reset
= over
->reset
;
5467 drv
->start
= over
->start
;
5468 if (over
->add_endpoint
)
5469 drv
->add_endpoint
= over
->add_endpoint
;
5470 if (over
->drop_endpoint
)
5471 drv
->drop_endpoint
= over
->drop_endpoint
;
5472 if (over
->check_bandwidth
)
5473 drv
->check_bandwidth
= over
->check_bandwidth
;
5474 if (over
->reset_bandwidth
)
5475 drv
->reset_bandwidth
= over
->reset_bandwidth
;
5478 EXPORT_SYMBOL_GPL(xhci_init_driver
);
5480 MODULE_DESCRIPTION(DRIVER_DESC
);
5481 MODULE_AUTHOR(DRIVER_AUTHOR
);
5482 MODULE_LICENSE("GPL");
5484 static int __init
xhci_hcd_init(void)
5487 * Check the compiler generated sizes of structures that must be laid
5488 * out in specific ways for hardware access.
5490 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array
) != 256*32/8);
5491 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx
) != 8*32/8);
5492 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx
) != 8*32/8);
5493 /* xhci_device_control has eight fields, and also
5494 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5496 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx
) != 4*32/8);
5497 BUILD_BUG_ON(sizeof(union xhci_trb
) != 4*32/8);
5498 BUILD_BUG_ON(sizeof(struct xhci_erst_entry
) != 4*32/8);
5499 BUILD_BUG_ON(sizeof(struct xhci_cap_regs
) != 8*32/8);
5500 BUILD_BUG_ON(sizeof(struct xhci_intr_reg
) != 8*32/8);
5501 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5502 BUILD_BUG_ON(sizeof(struct xhci_run_regs
) != (8+8*128)*32/8);
5507 xhci_debugfs_create_root();
5513 * If an init function is provided, an exit function must also be provided
5514 * to allow module unload.
5516 static void __exit
xhci_hcd_fini(void)
5518 xhci_debugfs_remove_root();
5521 module_init(xhci_hcd_init
);
5522 module_exit(xhci_hcd_fini
);