drivers/usb/musb/am35x.c

   1
   2 /*
   3  * Texas Instruments AM35x "glue layer"
   4  *
   5  * Copyright (c) 2010, by Texas Instruments
   6  *
   7  * Based on the DA8xx "glue layer" code.
   8  * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
   9  *
  10  * This file is part of the Inventra Controller Driver for Linux.
  11  *
  12  * The Inventra Controller Driver for Linux is free software; you
  13  * can redistribute it and/or modify it under the terms of the GNU
  14  * General Public License version 2 as published by the Free Software
  15  * Foundation.
  16  *
  17  * The Inventra Controller Driver for Linux is distributed in
  18  * the hope that it will be useful, but WITHOUT ANY WARRANTY;
  19  * without even the implied warranty of MERCHANTABILITY or
  20  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  21  * License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with The Inventra Controller Driver for Linux ; if not,
  25  * write to the Free Software Foundation, Inc., 59 Temple Place,
  26  * Suite 330, Boston, MA  02111-1307  USA
  27  *
  28  */
  29
  30 #include <linux/module.h>
  31 #include <linux/clk.h>
  32 #include <linux/err.h>
  33 #include <linux/io.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/usb/usb_phy_generic.h>
  37 #include <linux/platform_data/usb-omap.h>
  38
  39 #include "musb_core.h"
  40
  41 /*
  42  * AM35x specific definitions
  43  */
  44 /* USB 2.0 OTG module registers */
  45 #define USB_REVISION_REG        0x00
  46 #define USB_CTRL_REG            0x04
  47 #define USB_STAT_REG            0x08
  48 #define USB_EMULATION_REG       0x0c
  49 /* 0x10 Reserved */
  50 #define USB_AUTOREQ_REG         0x14
  51 #define USB_SRP_FIX_TIME_REG    0x18
  52 #define USB_TEARDOWN_REG        0x1c
  53 #define EP_INTR_SRC_REG         0x20
  54 #define EP_INTR_SRC_SET_REG     0x24
  55 #define EP_INTR_SRC_CLEAR_REG   0x28
  56 #define EP_INTR_MASK_REG        0x2c
  57 #define EP_INTR_MASK_SET_REG    0x30
  58 #define EP_INTR_MASK_CLEAR_REG  0x34
  59 #define EP_INTR_SRC_MASKED_REG  0x38
  60 #define CORE_INTR_SRC_REG       0x40
  61 #define CORE_INTR_SRC_SET_REG   0x44
  62 #define CORE_INTR_SRC_CLEAR_REG 0x48
  63 #define CORE_INTR_MASK_REG      0x4c
  64 #define CORE_INTR_MASK_SET_REG  0x50
  65 #define CORE_INTR_MASK_CLEAR_REG 0x54
  66 #define CORE_INTR_SRC_MASKED_REG 0x58
  67 /* 0x5c Reserved */
  68 #define USB_END_OF_INTR_REG     0x60
  69
  70 /* Control register bits */
  71 #define AM35X_SOFT_RESET_MASK   1
  72
  73 /* USB interrupt register bits */
  74 #define AM35X_INTR_USB_SHIFT    16
  75 #define AM35X_INTR_USB_MASK     (0x1ff << AM35X_INTR_USB_SHIFT)
  76 #define AM35X_INTR_DRVVBUS      0x100
  77 #define AM35X_INTR_RX_SHIFT     16
  78 #define AM35X_INTR_TX_SHIFT     0
  79 #define AM35X_TX_EP_MASK        0xffff          /* EP0 + 15 Tx EPs */
  80 #define AM35X_RX_EP_MASK        0xfffe          /* 15 Rx EPs */
  81 #define AM35X_TX_INTR_MASK      (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
  82 #define AM35X_RX_INTR_MASK      (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
  83
  84 #define USB_MENTOR_CORE_OFFSET  0x400
  85
  86 struct am35x_glue {
  87         struct device           *dev;
  88         struct platform_device  *musb;
  89         struct platform_device  *phy;
  90         struct clk              *phy_clk;
  91         struct clk              *clk;
  92 };
  93
  94 /*
  95  * am35x_musb_enable - enable interrupts
  96  */
  97 static void am35x_musb_enable(struct musb *musb)
  98 {
  99         void __iomem *reg_base = musb->ctrl_base;
 100         u32 epmask;
 101
 102         /* Workaround: setup IRQs through both register sets. */
 103         epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) |
 104                ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);
 105
 106         musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
 107         musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);
 108
 109         /* Force the DRVVBUS IRQ so we can start polling for ID change. */
 110         musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
 111                         AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
 112 }
 113
 114 /*
 115  * am35x_musb_disable - disable HDRC and flush interrupts
 116  */
 117 static void am35x_musb_disable(struct musb *musb)
 118 {
 119         void __iomem *reg_base = musb->ctrl_base;
 120
 121         musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
 122         musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
 123                          AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK);
 124         musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
 125 }
 126
 127 #define portstate(stmt)         stmt
 128
 129 static void am35x_musb_set_vbus(struct musb *musb, int is_on)
 130 {
 131         WARN_ON(is_on && is_peripheral_active(musb));
 132 }
 133
 134 #define POLL_SECONDS    2
 135
 136 static struct timer_list otg_workaround;
 137
 138 static void otg_timer(unsigned long _musb)
 139 {
 140         struct musb             *musb = (void *)_musb;
 141         void __iomem            *mregs = musb->mregs;
 142         u8                      devctl;
 143         unsigned long           flags;
 144
 145         /*
 146          * We poll because AM35x's won't expose several OTG-critical
 147          * status change events (from the transceiver) otherwise.
 148          */
 149         devctl = musb_readb(mregs, MUSB_DEVCTL);
 150         dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
 151                 usb_otg_state_string(musb->xceiv->otg->state));
 152
 153         spin_lock_irqsave(&musb->lock, flags);
 154         switch (musb->xceiv->otg->state) {
 155         case OTG_STATE_A_WAIT_BCON:
 156                 devctl &= ~MUSB_DEVCTL_SESSION;
 157                 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
 158
 159                 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 160                 if (devctl & MUSB_DEVCTL_BDEVICE) {
 161                         musb->xceiv->otg->state = OTG_STATE_B_IDLE;
 162                         MUSB_DEV_MODE(musb);
 163                 } else {
 164                         musb->xceiv->otg->state = OTG_STATE_A_IDLE;
 165                         MUSB_HST_MODE(musb);
 166                 }
 167                 break;
 168         case OTG_STATE_A_WAIT_VFALL:
 169                 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
 170                 musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
 171                             MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
 172                 break;
 173         case OTG_STATE_B_IDLE:
 174                 devctl = musb_readb(mregs, MUSB_DEVCTL);
 175                 if (devctl & MUSB_DEVCTL_BDEVICE)
 176                         mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
 177                 else
 178                         musb->xceiv->otg->state = OTG_STATE_A_IDLE;
 179                 break;
 180         default:
 181                 break;
 182         }
 183         spin_unlock_irqrestore(&musb->lock, flags);
 184 }
 185
 186 static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
 187 {
 188         static unsigned long last_timer;
 189
 190         if (timeout == 0)
 191                 timeout = jiffies + msecs_to_jiffies(3);
 192
 193         /* Never idle if active, or when VBUS timeout is not set as host */
 194         if (musb->is_active || (musb->a_wait_bcon == 0 &&
 195                                 musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)) {
 196                 dev_dbg(musb->controller, "%s active, deleting timer\n",
 197                         usb_otg_state_string(musb->xceiv->otg->state));
 198                 del_timer(&otg_workaround);
 199                 last_timer = jiffies;
 200                 return;
 201         }
 202
 203         if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
 204                 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
 205                 return;
 206         }
 207         last_timer = timeout;
 208
 209         dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
 210                 usb_otg_state_string(musb->xceiv->otg->state),
 211                 jiffies_to_msecs(timeout - jiffies));
 212         mod_timer(&otg_workaround, timeout);
 213 }
 214
 215 static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
 216 {
 217         struct musb  *musb = hci;
 218         void __iomem *reg_base = musb->ctrl_base;
 219         struct device *dev = musb->controller;
 220         struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
 221         struct omap_musb_board_data *data = plat->board_data;
 222         struct usb_otg *otg = musb->xceiv->otg;
 223         unsigned long flags;
 224         irqreturn_t ret = IRQ_NONE;
 225         u32 epintr, usbintr;
 226
 227         spin_lock_irqsave(&musb->lock, flags);
 228
 229         /* Get endpoint interrupts */
 230         epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
 231
 232         if (epintr) {
 233                 musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);
 234
 235                 musb->int_rx =
 236                         (epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
 237                 musb->int_tx =
 238                         (epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
 239         }
 240
 241         /* Get usb core interrupts */
 242         usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
 243         if (!usbintr && !epintr)
 244                 goto eoi;
 245
 246         if (usbintr) {
 247                 musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);
 248
 249                 musb->int_usb =
 250                         (usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
 251         }
 252         /*
 253          * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
 254          * AM35x's missing ID change IRQ.  We need an ID change IRQ to
 255          * switch appropriately between halves of the OTG state machine.
 256          * Managing DEVCTL.SESSION per Mentor docs requires that we know its
 257          * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
 258          * Also, DRVVBUS pulses for SRP (but not at 5V) ...
 259          */
 260         if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
 261                 int drvvbus = musb_readl(reg_base, USB_STAT_REG);
 262                 void __iomem *mregs = musb->mregs;
 263                 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
 264                 int err;
 265
 266                 err = musb->int_usb & MUSB_INTR_VBUSERROR;
 267                 if (err) {
 268                         /*
 269                          * The Mentor core doesn't debounce VBUS as needed
 270                          * to cope with device connect current spikes. This
 271                          * means it's not uncommon for bus-powered devices
 272                          * to get VBUS errors during enumeration.
 273                          *
 274                          * This is a workaround, but newer RTL from Mentor
 275                          * seems to allow a better one: "re"-starting sessions
 276                          * without waiting for VBUS to stop registering in
 277                          * devctl.
 278                          */
 279                         musb->int_usb &= ~MUSB_INTR_VBUSERROR;
 280                         musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
 281                         mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
 282                         WARNING("VBUS error workaround (delay coming)\n");
 283                 } else if (drvvbus) {
 284                         MUSB_HST_MODE(musb);
 285                         otg->default_a = 1;
 286                         musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
 287                         portstate(musb->port1_status |= USB_PORT_STAT_POWER);
 288                         del_timer(&otg_workaround);
 289                 } else {
 290                         musb->is_active = 0;
 291                         MUSB_DEV_MODE(musb);
 292                         otg->default_a = 0;
 293                         musb->xceiv->otg->state = OTG_STATE_B_IDLE;
 294                         portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
 295                 }
 296
 297                 /* NOTE: this must complete power-on within 100 ms. */
 298                 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
 299                                 drvvbus ? "on" : "off",
 300                                 usb_otg_state_string(musb->xceiv->otg->state),
 301                                 err ? " ERROR" : "",
 302                                 devctl);
 303                 ret = IRQ_HANDLED;
 304         }
 305
 306         /* Drop spurious RX and TX if device is disconnected */
 307         if (musb->int_usb & MUSB_INTR_DISCONNECT) {
 308                 musb->int_tx = 0;
 309                 musb->int_rx = 0;
 310         }
 311
 312         if (musb->int_tx || musb->int_rx || musb->int_usb)
 313                 ret |= musb_interrupt(musb);
 314
 315 eoi:
 316         /* EOI needs to be written for the IRQ to be re-asserted. */
 317         if (ret == IRQ_HANDLED || epintr || usbintr) {
 318                 /* clear level interrupt */
 319                 if (data->clear_irq)
 320                         data->clear_irq();
 321                 /* write EOI */
 322                 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
 323         }
 324
 325         /* Poll for ID change */
 326         if (musb->xceiv->otg->state == OTG_STATE_B_IDLE)
 327                 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
 328
 329         spin_unlock_irqrestore(&musb->lock, flags);
 330
 331         return ret;
 332 }
 333
 334 static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
 335 {
 336         struct device *dev = musb->controller;
 337         struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
 338         struct omap_musb_board_data *data = plat->board_data;
 339         int     retval = 0;
 340
 341         if (data->set_mode)
 342                 data->set_mode(musb_mode);
 343         else
 344                 retval = -EIO;
 345
 346         return retval;
 347 }
 348
 349 static int am35x_musb_init(struct musb *musb)
 350 {
 351         struct device *dev = musb->controller;
 352         struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
 353         struct omap_musb_board_data *data = plat->board_data;
 354         void __iomem *reg_base = musb->ctrl_base;
 355         u32 rev;
 356
 357         musb->mregs += USB_MENTOR_CORE_OFFSET;
 358
 359         /* Returns zero if e.g. not clocked */
 360         rev = musb_readl(reg_base, USB_REVISION_REG);
 361         if (!rev)
 362                 return -ENODEV;
 363
 364         musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
 365         if (IS_ERR_OR_NULL(musb->xceiv))
 366                 return -EPROBE_DEFER;
 367
 368         setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
 369
 370         /* Reset the musb */
 371         if (data->reset)
 372                 data->reset();
 373
 374         /* Reset the controller */
 375         musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
 376
 377         /* Start the on-chip PHY and its PLL. */
 378         if (data->set_phy_power)
 379                 data->set_phy_power(1);
 380
 381         msleep(5);
 382
 383         musb->isr = am35x_musb_interrupt;
 384
 385         /* clear level interrupt */
 386         if (data->clear_irq)
 387                 data->clear_irq();
 388
 389         return 0;
 390 }
 391
 392 static int am35x_musb_exit(struct musb *musb)
 393 {
 394         struct device *dev = musb->controller;
 395         struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
 396         struct omap_musb_board_data *data = plat->board_data;
 397
 398         del_timer_sync(&otg_workaround);
 399
 400         /* Shutdown the on-chip PHY and its PLL. */
 401         if (data->set_phy_power)
 402                 data->set_phy_power(0);
 403
 404         usb_put_phy(musb->xceiv);
 405
 406         return 0;
 407 }
 408
 409 /* AM35x supports only 32bit read operation */
 410 static void am35x_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
 411 {
 412         void __iomem *fifo = hw_ep->fifo;
 413         u32             val;
 414         int             i;
 415
 416         /* Read for 32bit-aligned destination address */
 417         if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
 418                 readsl(fifo, dst, len >> 2);
 419                 dst += len & ~0x03;
 420                 len &= 0x03;
 421         }
 422         /*
 423          * Now read the remaining 1 to 3 byte or complete length if
 424          * unaligned address.
 425          */
 426         if (len > 4) {
 427                 for (i = 0; i < (len >> 2); i++) {
 428                         *(u32 *) dst = musb_readl(fifo, 0);
 429                         dst += 4;
 430                 }
 431                 len &= 0x03;
 432         }
 433         if (len > 0) {
 434                 val = musb_readl(fifo, 0);
 435                 memcpy(dst, &val, len);
 436         }
 437 }
 438
 439 static const struct musb_platform_ops am35x_ops = {
 440         .quirks         = MUSB_DMA_INVENTRA | MUSB_INDEXED_EP,
 441         .init           = am35x_musb_init,
 442         .exit           = am35x_musb_exit,
 443
 444         .read_fifo      = am35x_read_fifo,
 445 #ifdef CONFIG_USB_INVENTRA_DMA
 446         .dma_init       = musbhs_dma_controller_create,
 447         .dma_exit       = musbhs_dma_controller_destroy,
 448 #endif
 449         .enable         = am35x_musb_enable,
 450         .disable        = am35x_musb_disable,
 451
 452         .set_mode       = am35x_musb_set_mode,
 453         .try_idle       = am35x_musb_try_idle,
 454
 455         .set_vbus       = am35x_musb_set_vbus,
 456 };
 457
 458 static const struct platform_device_info am35x_dev_info = {
 459         .name           = "musb-hdrc",
 460         .id             = PLATFORM_DEVID_AUTO,
 461         .dma_mask       = DMA_BIT_MASK(32),
 462 };
 463
 464 static int am35x_probe(struct platform_device *pdev)
 465 {
 466         struct musb_hdrc_platform_data  *pdata = dev_get_platdata(&pdev->dev);
 467         struct platform_device          *musb;
 468         struct am35x_glue               *glue;
 469         struct platform_device_info     pinfo;
 470         struct clk                      *phy_clk;
 471         struct clk                      *clk;
 472
 473         int                             ret = -ENOMEM;
 474
 475         glue = kzalloc(sizeof(*glue), GFP_KERNEL);
 476         if (!glue)
 477                 goto err0;
 478
 479         phy_clk = clk_get(&pdev->dev, "fck");
 480         if (IS_ERR(phy_clk)) {
 481                 dev_err(&pdev->dev, "failed to get PHY clock\n");
 482                 ret = PTR_ERR(phy_clk);
 483                 goto err3;
 484         }
 485
 486         clk = clk_get(&pdev->dev, "ick");
 487         if (IS_ERR(clk)) {
 488                 dev_err(&pdev->dev, "failed to get clock\n");
 489                 ret = PTR_ERR(clk);
 490                 goto err4;
 491         }
 492
 493         ret = clk_enable(phy_clk);
 494         if (ret) {
 495                 dev_err(&pdev->dev, "failed to enable PHY clock\n");
 496                 goto err5;
 497         }
 498
 499         ret = clk_enable(clk);
 500         if (ret) {
 501                 dev_err(&pdev->dev, "failed to enable clock\n");
 502                 goto err6;
 503         }
 504
 505         glue->dev                       = &pdev->dev;
 506         glue->phy_clk                   = phy_clk;
 507         glue->clk                       = clk;
 508
 509         pdata->platform_ops             = &am35x_ops;
 510
 511         glue->phy = usb_phy_generic_register();
 512         if (IS_ERR(glue->phy)) {
 513                 ret = PTR_ERR(glue->phy);
 514                 goto err7;
 515         }
 516         platform_set_drvdata(pdev, glue);
 517
 518         pinfo = am35x_dev_info;
 519         pinfo.parent = &pdev->dev;
 520         pinfo.res = pdev->resource;
 521         pinfo.num_res = pdev->num_resources;
 522         pinfo.data = pdata;
 523         pinfo.size_data = sizeof(*pdata);
 524
 525         glue->musb = musb = platform_device_register_full(&pinfo);
 526         if (IS_ERR(musb)) {
 527                 ret = PTR_ERR(musb);
 528                 dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
 529                 goto err8;
 530         }
 531
 532         return 0;
 533
 534 err8:
 535         usb_phy_generic_unregister(glue->phy);
 536
 537 err7:
 538         clk_disable(clk);
 539
 540 err6:
 541         clk_disable(phy_clk);
 542
 543 err5:
 544         clk_put(clk);
 545
 546 err4:
 547         clk_put(phy_clk);
 548
 549 err3:
 550         kfree(glue);
 551
 552 err0:
 553         return ret;
 554 }
 555
 556 static int am35x_remove(struct platform_device *pdev)
 557 {
 558         struct am35x_glue       *glue = platform_get_drvdata(pdev);
 559
 560         platform_device_unregister(glue->musb);
 561         usb_phy_generic_unregister(glue->phy);
 562         clk_disable(glue->clk);
 563         clk_disable(glue->phy_clk);
 564         clk_put(glue->clk);
 565         clk_put(glue->phy_clk);
 566         kfree(glue);
 567
 568         return 0;
 569 }
 570
 571 #ifdef CONFIG_PM_SLEEP
 572 static int am35x_suspend(struct device *dev)
 573 {
 574         struct am35x_glue       *glue = dev_get_drvdata(dev);
 575         struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
 576         struct omap_musb_board_data *data = plat->board_data;
 577
 578         /* Shutdown the on-chip PHY and its PLL. */
 579         if (data->set_phy_power)
 580                 data->set_phy_power(0);
 581
 582         clk_disable(glue->phy_clk);
 583         clk_disable(glue->clk);
 584
 585         return 0;
 586 }
 587
 588 static int am35x_resume(struct device *dev)
 589 {
 590         struct am35x_glue       *glue = dev_get_drvdata(dev);
 591         struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
 592         struct omap_musb_board_data *data = plat->board_data;
 593         int                     ret;
 594
 595         /* Start the on-chip PHY and its PLL. */
 596         if (data->set_phy_power)
 597                 data->set_phy_power(1);
 598
 599         ret = clk_enable(glue->phy_clk);
 600         if (ret) {
 601                 dev_err(dev, "failed to enable PHY clock\n");
 602                 return ret;
 603         }
 604
 605         ret = clk_enable(glue->clk);
 606         if (ret) {
 607                 dev_err(dev, "failed to enable clock\n");
 608                 return ret;
 609         }
 610
 611         return 0;
 612 }
 613 #endif
 614
 615 static SIMPLE_DEV_PM_OPS(am35x_pm_ops, am35x_suspend, am35x_resume);
 616
 617 static struct platform_driver am35x_driver = {
 618         .probe          = am35x_probe,
 619         .remove         = am35x_remove,
 620         .driver         = {
 621                 .name   = "musb-am35x",
 622                 .pm     = &am35x_pm_ops,
 623         },
 624 };
 625
 626 MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
 627 MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
 628 MODULE_LICENSE("GPL v2");
 629 module_platform_driver(am35x_driver);