2 * Texas Instruments AM35x "glue layer"
4 * Copyright (c) 2010, by Texas Instruments
6 * Based on the DA8xx "glue layer" code.
7 * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
9 * This file is part of the Inventra Controller Driver for Linux.
11 * The Inventra Controller Driver for Linux is free software; you
12 * can redistribute it and/or modify it under the terms of the GNU
13 * General Public License version 2 as published by the Free Software
16 * The Inventra Controller Driver for Linux is distributed in
17 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
18 * without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 * License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with The Inventra Controller Driver for Linux ; if not,
24 * write to the Free Software Foundation, Inc., 59 Temple Place,
25 * Suite 330, Boston, MA 02111-1307 USA
29 #include <linux/init.h>
30 #include <linux/module.h>
31 #include <linux/clk.h>
32 #include <linux/err.h>
34 #include <linux/platform_device.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/usb/nop-usb-xceiv.h>
40 #include "musb_core.h"
43 * AM35x specific definitions
45 /* USB 2.0 OTG module registers */
46 #define USB_REVISION_REG 0x00
47 #define USB_CTRL_REG 0x04
48 #define USB_STAT_REG 0x08
49 #define USB_EMULATION_REG 0x0c
51 #define USB_AUTOREQ_REG 0x14
52 #define USB_SRP_FIX_TIME_REG 0x18
53 #define USB_TEARDOWN_REG 0x1c
54 #define EP_INTR_SRC_REG 0x20
55 #define EP_INTR_SRC_SET_REG 0x24
56 #define EP_INTR_SRC_CLEAR_REG 0x28
57 #define EP_INTR_MASK_REG 0x2c
58 #define EP_INTR_MASK_SET_REG 0x30
59 #define EP_INTR_MASK_CLEAR_REG 0x34
60 #define EP_INTR_SRC_MASKED_REG 0x38
61 #define CORE_INTR_SRC_REG 0x40
62 #define CORE_INTR_SRC_SET_REG 0x44
63 #define CORE_INTR_SRC_CLEAR_REG 0x48
64 #define CORE_INTR_MASK_REG 0x4c
65 #define CORE_INTR_MASK_SET_REG 0x50
66 #define CORE_INTR_MASK_CLEAR_REG 0x54
67 #define CORE_INTR_SRC_MASKED_REG 0x58
69 #define USB_END_OF_INTR_REG 0x60
71 /* Control register bits */
72 #define AM35X_SOFT_RESET_MASK 1
74 /* USB interrupt register bits */
75 #define AM35X_INTR_USB_SHIFT 16
76 #define AM35X_INTR_USB_MASK (0x1ff << AM35X_INTR_USB_SHIFT)
77 #define AM35X_INTR_DRVVBUS 0x100
78 #define AM35X_INTR_RX_SHIFT 16
79 #define AM35X_INTR_TX_SHIFT 0
80 #define AM35X_TX_EP_MASK 0xffff /* EP0 + 15 Tx EPs */
81 #define AM35X_RX_EP_MASK 0xfffe /* 15 Rx EPs */
82 #define AM35X_TX_INTR_MASK (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
83 #define AM35X_RX_INTR_MASK (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
85 #define USB_MENTOR_CORE_OFFSET 0x400
89 struct platform_device
*musb
;
93 #define glue_to_musb(g) platform_get_drvdata(g->musb)
96 * am35x_musb_enable - enable interrupts
98 static void am35x_musb_enable(struct musb
*musb
)
100 void __iomem
*reg_base
= musb
->ctrl_base
;
103 /* Workaround: setup IRQs through both register sets. */
104 epmask
= ((musb
->epmask
& AM35X_TX_EP_MASK
) << AM35X_INTR_TX_SHIFT
) |
105 ((musb
->epmask
& AM35X_RX_EP_MASK
) << AM35X_INTR_RX_SHIFT
);
107 musb_writel(reg_base
, EP_INTR_MASK_SET_REG
, epmask
);
108 musb_writel(reg_base
, CORE_INTR_MASK_SET_REG
, AM35X_INTR_USB_MASK
);
110 /* Force the DRVVBUS IRQ so we can start polling for ID change. */
111 musb_writel(reg_base
, CORE_INTR_SRC_SET_REG
,
112 AM35X_INTR_DRVVBUS
<< AM35X_INTR_USB_SHIFT
);
116 * am35x_musb_disable - disable HDRC and flush interrupts
118 static void am35x_musb_disable(struct musb
*musb
)
120 void __iomem
*reg_base
= musb
->ctrl_base
;
122 musb_writel(reg_base
, CORE_INTR_MASK_CLEAR_REG
, AM35X_INTR_USB_MASK
);
123 musb_writel(reg_base
, EP_INTR_MASK_CLEAR_REG
,
124 AM35X_TX_INTR_MASK
| AM35X_RX_INTR_MASK
);
125 musb_writeb(musb
->mregs
, MUSB_DEVCTL
, 0);
126 musb_writel(reg_base
, USB_END_OF_INTR_REG
, 0);
129 #define portstate(stmt) stmt
131 static void am35x_musb_set_vbus(struct musb
*musb
, int is_on
)
133 WARN_ON(is_on
&& is_peripheral_active(musb
));
136 #define POLL_SECONDS 2
138 static struct timer_list otg_workaround
;
140 static void otg_timer(unsigned long _musb
)
142 struct musb
*musb
= (void *)_musb
;
143 void __iomem
*mregs
= musb
->mregs
;
148 * We poll because AM35x's won't expose several OTG-critical
149 * status change events (from the transceiver) otherwise.
151 devctl
= musb_readb(mregs
, MUSB_DEVCTL
);
152 dev_dbg(musb
->controller
, "Poll devctl %02x (%s)\n", devctl
,
153 otg_state_string(musb
->xceiv
->state
));
155 spin_lock_irqsave(&musb
->lock
, flags
);
156 switch (musb
->xceiv
->state
) {
157 case OTG_STATE_A_WAIT_BCON
:
158 devctl
&= ~MUSB_DEVCTL_SESSION
;
159 musb_writeb(musb
->mregs
, MUSB_DEVCTL
, devctl
);
161 devctl
= musb_readb(musb
->mregs
, MUSB_DEVCTL
);
162 if (devctl
& MUSB_DEVCTL_BDEVICE
) {
163 musb
->xceiv
->state
= OTG_STATE_B_IDLE
;
166 musb
->xceiv
->state
= OTG_STATE_A_IDLE
;
170 case OTG_STATE_A_WAIT_VFALL
:
171 musb
->xceiv
->state
= OTG_STATE_A_WAIT_VRISE
;
172 musb_writel(musb
->ctrl_base
, CORE_INTR_SRC_SET_REG
,
173 MUSB_INTR_VBUSERROR
<< AM35X_INTR_USB_SHIFT
);
175 case OTG_STATE_B_IDLE
:
176 devctl
= musb_readb(mregs
, MUSB_DEVCTL
);
177 if (devctl
& MUSB_DEVCTL_BDEVICE
)
178 mod_timer(&otg_workaround
, jiffies
+ POLL_SECONDS
* HZ
);
180 musb
->xceiv
->state
= OTG_STATE_A_IDLE
;
185 spin_unlock_irqrestore(&musb
->lock
, flags
);
188 static void am35x_musb_try_idle(struct musb
*musb
, unsigned long timeout
)
190 static unsigned long last_timer
;
193 timeout
= jiffies
+ msecs_to_jiffies(3);
195 /* Never idle if active, or when VBUS timeout is not set as host */
196 if (musb
->is_active
|| (musb
->a_wait_bcon
== 0 &&
197 musb
->xceiv
->state
== OTG_STATE_A_WAIT_BCON
)) {
198 dev_dbg(musb
->controller
, "%s active, deleting timer\n",
199 otg_state_string(musb
->xceiv
->state
));
200 del_timer(&otg_workaround
);
201 last_timer
= jiffies
;
205 if (time_after(last_timer
, timeout
) && timer_pending(&otg_workaround
)) {
206 dev_dbg(musb
->controller
, "Longer idle timer already pending, ignoring...\n");
209 last_timer
= timeout
;
211 dev_dbg(musb
->controller
, "%s inactive, starting idle timer for %u ms\n",
212 otg_state_string(musb
->xceiv
->state
),
213 jiffies_to_msecs(timeout
- jiffies
));
214 mod_timer(&otg_workaround
, timeout
);
217 static irqreturn_t
am35x_musb_interrupt(int irq
, void *hci
)
219 struct musb
*musb
= hci
;
220 void __iomem
*reg_base
= musb
->ctrl_base
;
221 struct device
*dev
= musb
->controller
;
222 struct musb_hdrc_platform_data
*plat
= dev
->platform_data
;
223 struct omap_musb_board_data
*data
= plat
->board_data
;
224 struct usb_otg
*otg
= musb
->xceiv
->otg
;
226 irqreturn_t ret
= IRQ_NONE
;
229 spin_lock_irqsave(&musb
->lock
, flags
);
231 /* Get endpoint interrupts */
232 epintr
= musb_readl(reg_base
, EP_INTR_SRC_MASKED_REG
);
235 musb_writel(reg_base
, EP_INTR_SRC_CLEAR_REG
, epintr
);
238 (epintr
& AM35X_RX_INTR_MASK
) >> AM35X_INTR_RX_SHIFT
;
240 (epintr
& AM35X_TX_INTR_MASK
) >> AM35X_INTR_TX_SHIFT
;
243 /* Get usb core interrupts */
244 usbintr
= musb_readl(reg_base
, CORE_INTR_SRC_MASKED_REG
);
245 if (!usbintr
&& !epintr
)
249 musb_writel(reg_base
, CORE_INTR_SRC_CLEAR_REG
, usbintr
);
252 (usbintr
& AM35X_INTR_USB_MASK
) >> AM35X_INTR_USB_SHIFT
;
255 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
256 * AM35x's missing ID change IRQ. We need an ID change IRQ to
257 * switch appropriately between halves of the OTG state machine.
258 * Managing DEVCTL.SESSION per Mentor docs requires that we know its
259 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
260 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
262 if (usbintr
& (AM35X_INTR_DRVVBUS
<< AM35X_INTR_USB_SHIFT
)) {
263 int drvvbus
= musb_readl(reg_base
, USB_STAT_REG
);
264 void __iomem
*mregs
= musb
->mregs
;
265 u8 devctl
= musb_readb(mregs
, MUSB_DEVCTL
);
268 err
= musb
->int_usb
& MUSB_INTR_VBUSERROR
;
271 * The Mentor core doesn't debounce VBUS as needed
272 * to cope with device connect current spikes. This
273 * means it's not uncommon for bus-powered devices
274 * to get VBUS errors during enumeration.
276 * This is a workaround, but newer RTL from Mentor
277 * seems to allow a better one: "re"-starting sessions
278 * without waiting for VBUS to stop registering in
281 musb
->int_usb
&= ~MUSB_INTR_VBUSERROR
;
282 musb
->xceiv
->state
= OTG_STATE_A_WAIT_VFALL
;
283 mod_timer(&otg_workaround
, jiffies
+ POLL_SECONDS
* HZ
);
284 WARNING("VBUS error workaround (delay coming)\n");
285 } else if (drvvbus
) {
288 musb
->xceiv
->state
= OTG_STATE_A_WAIT_VRISE
;
289 portstate(musb
->port1_status
|= USB_PORT_STAT_POWER
);
290 del_timer(&otg_workaround
);
295 musb
->xceiv
->state
= OTG_STATE_B_IDLE
;
296 portstate(musb
->port1_status
&= ~USB_PORT_STAT_POWER
);
299 /* NOTE: this must complete power-on within 100 ms. */
300 dev_dbg(musb
->controller
, "VBUS %s (%s)%s, devctl %02x\n",
301 drvvbus
? "on" : "off",
302 otg_state_string(musb
->xceiv
->state
),
308 if (musb
->int_tx
|| musb
->int_rx
|| musb
->int_usb
)
309 ret
|= musb_interrupt(musb
);
312 /* EOI needs to be written for the IRQ to be re-asserted. */
313 if (ret
== IRQ_HANDLED
|| epintr
|| usbintr
) {
314 /* clear level interrupt */
318 musb_writel(reg_base
, USB_END_OF_INTR_REG
, 0);
321 /* Poll for ID change */
322 if (musb
->xceiv
->state
== OTG_STATE_B_IDLE
)
323 mod_timer(&otg_workaround
, jiffies
+ POLL_SECONDS
* HZ
);
325 spin_unlock_irqrestore(&musb
->lock
, flags
);
330 static int am35x_musb_set_mode(struct musb
*musb
, u8 musb_mode
)
332 struct device
*dev
= musb
->controller
;
333 struct musb_hdrc_platform_data
*plat
= dev
->platform_data
;
334 struct omap_musb_board_data
*data
= plat
->board_data
;
338 data
->set_mode(musb_mode
);
345 static int am35x_musb_init(struct musb
*musb
)
347 struct device
*dev
= musb
->controller
;
348 struct musb_hdrc_platform_data
*plat
= dev
->platform_data
;
349 struct omap_musb_board_data
*data
= plat
->board_data
;
350 void __iomem
*reg_base
= musb
->ctrl_base
;
353 musb
->mregs
+= USB_MENTOR_CORE_OFFSET
;
355 /* Returns zero if e.g. not clocked */
356 rev
= musb_readl(reg_base
, USB_REVISION_REG
);
360 usb_nop_xceiv_register();
361 musb
->xceiv
= usb_get_phy(USB_PHY_TYPE_USB2
);
362 if (IS_ERR_OR_NULL(musb
->xceiv
))
365 setup_timer(&otg_workaround
, otg_timer
, (unsigned long) musb
);
371 /* Reset the controller */
372 musb_writel(reg_base
, USB_CTRL_REG
, AM35X_SOFT_RESET_MASK
);
374 /* Start the on-chip PHY and its PLL. */
375 if (data
->set_phy_power
)
376 data
->set_phy_power(1);
380 musb
->isr
= am35x_musb_interrupt
;
382 /* clear level interrupt */
389 static int am35x_musb_exit(struct musb
*musb
)
391 struct device
*dev
= musb
->controller
;
392 struct musb_hdrc_platform_data
*plat
= dev
->platform_data
;
393 struct omap_musb_board_data
*data
= plat
->board_data
;
395 del_timer_sync(&otg_workaround
);
397 /* Shutdown the on-chip PHY and its PLL. */
398 if (data
->set_phy_power
)
399 data
->set_phy_power(0);
401 usb_put_phy(musb
->xceiv
);
402 usb_nop_xceiv_unregister();
407 /* AM35x supports only 32bit read operation */
408 void musb_read_fifo(struct musb_hw_ep
*hw_ep
, u16 len
, u8
*dst
)
410 void __iomem
*fifo
= hw_ep
->fifo
;
414 /* Read for 32bit-aligned destination address */
415 if (likely((0x03 & (unsigned long) dst
) == 0) && len
>= 4) {
416 readsl(fifo
, dst
, len
>> 2);
421 * Now read the remaining 1 to 3 byte or complete length if
425 for (i
= 0; i
< (len
>> 2); i
++) {
426 *(u32
*) dst
= musb_readl(fifo
, 0);
432 val
= musb_readl(fifo
, 0);
433 memcpy(dst
, &val
, len
);
437 static const struct musb_platform_ops am35x_ops
= {
438 .init
= am35x_musb_init
,
439 .exit
= am35x_musb_exit
,
441 .enable
= am35x_musb_enable
,
442 .disable
= am35x_musb_disable
,
444 .set_mode
= am35x_musb_set_mode
,
445 .try_idle
= am35x_musb_try_idle
,
447 .set_vbus
= am35x_musb_set_vbus
,
450 static u64 am35x_dmamask
= DMA_BIT_MASK(32);
452 static int __devinit
am35x_probe(struct platform_device
*pdev
)
454 struct musb_hdrc_platform_data
*pdata
= pdev
->dev
.platform_data
;
455 struct platform_device
*musb
;
456 struct am35x_glue
*glue
;
464 glue
= kzalloc(sizeof(*glue
), GFP_KERNEL
);
466 dev_err(&pdev
->dev
, "failed to allocate glue context\n");
470 /* get the musb id */
471 musbid
= musb_get_id(&pdev
->dev
, GFP_KERNEL
);
473 dev_err(&pdev
->dev
, "failed to allocate musb id\n");
478 musb
= platform_device_alloc("musb-hdrc", musbid
);
480 dev_err(&pdev
->dev
, "failed to allocate musb device\n");
484 phy_clk
= clk_get(&pdev
->dev
, "fck");
485 if (IS_ERR(phy_clk
)) {
486 dev_err(&pdev
->dev
, "failed to get PHY clock\n");
487 ret
= PTR_ERR(phy_clk
);
491 clk
= clk_get(&pdev
->dev
, "ick");
493 dev_err(&pdev
->dev
, "failed to get clock\n");
498 ret
= clk_enable(phy_clk
);
500 dev_err(&pdev
->dev
, "failed to enable PHY clock\n");
504 ret
= clk_enable(clk
);
506 dev_err(&pdev
->dev
, "failed to enable clock\n");
511 musb
->dev
.parent
= &pdev
->dev
;
512 musb
->dev
.dma_mask
= &am35x_dmamask
;
513 musb
->dev
.coherent_dma_mask
= am35x_dmamask
;
515 glue
->dev
= &pdev
->dev
;
517 glue
->phy_clk
= phy_clk
;
520 pdata
->platform_ops
= &am35x_ops
;
522 platform_set_drvdata(pdev
, glue
);
524 ret
= platform_device_add_resources(musb
, pdev
->resource
,
525 pdev
->num_resources
);
527 dev_err(&pdev
->dev
, "failed to add resources\n");
531 ret
= platform_device_add_data(musb
, pdata
, sizeof(*pdata
));
533 dev_err(&pdev
->dev
, "failed to add platform_data\n");
537 ret
= platform_device_add(musb
);
539 dev_err(&pdev
->dev
, "failed to register musb device\n");
549 clk_disable(phy_clk
);
558 platform_device_put(musb
);
561 musb_put_id(&pdev
->dev
, musbid
);
570 static int __devexit
am35x_remove(struct platform_device
*pdev
)
572 struct am35x_glue
*glue
= platform_get_drvdata(pdev
);
574 musb_put_id(&pdev
->dev
, glue
->musb
->id
);
575 platform_device_del(glue
->musb
);
576 platform_device_put(glue
->musb
);
577 clk_disable(glue
->clk
);
578 clk_disable(glue
->phy_clk
);
580 clk_put(glue
->phy_clk
);
587 static int am35x_suspend(struct device
*dev
)
589 struct am35x_glue
*glue
= dev_get_drvdata(dev
);
590 struct musb_hdrc_platform_data
*plat
= dev
->platform_data
;
591 struct omap_musb_board_data
*data
= plat
->board_data
;
593 /* Shutdown the on-chip PHY and its PLL. */
594 if (data
->set_phy_power
)
595 data
->set_phy_power(0);
597 clk_disable(glue
->phy_clk
);
598 clk_disable(glue
->clk
);
603 static int am35x_resume(struct device
*dev
)
605 struct am35x_glue
*glue
= dev_get_drvdata(dev
);
606 struct musb_hdrc_platform_data
*plat
= dev
->platform_data
;
607 struct omap_musb_board_data
*data
= plat
->board_data
;
610 /* Start the on-chip PHY and its PLL. */
611 if (data
->set_phy_power
)
612 data
->set_phy_power(1);
614 ret
= clk_enable(glue
->phy_clk
);
616 dev_err(dev
, "failed to enable PHY clock\n");
620 ret
= clk_enable(glue
->clk
);
622 dev_err(dev
, "failed to enable clock\n");
629 static struct dev_pm_ops am35x_pm_ops
= {
630 .suspend
= am35x_suspend
,
631 .resume
= am35x_resume
,
634 #define DEV_PM_OPS &am35x_pm_ops
636 #define DEV_PM_OPS NULL
639 static struct platform_driver am35x_driver
= {
640 .probe
= am35x_probe
,
641 .remove
= __devexit_p(am35x_remove
),
643 .name
= "musb-am35x",
648 MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
649 MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
650 MODULE_LICENSE("GPL v2");
652 static int __init
am35x_init(void)
654 return platform_driver_register(&am35x_driver
);
656 module_init(am35x_init
);
658 static void __exit
am35x_exit(void)
660 platform_driver_unregister(&am35x_driver
);
662 module_exit(am35x_exit
);