drivers/usb/musb/blackfin.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * MUSB OTG controller driver for Blackfin Processors
   4  *
   5  * Copyright 2006-2008 Analog Devices Inc.
   6  *
   7  * Enter bugs at http://blackfin.uclinux.org/
   8  *
   9  * Licensed under the GPL-2 or later.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/kernel.h>
  14 #include <linux/sched.h>
  15 #include <linux/list.h>
  16 #include <linux/gpio.h>
  17 #include <linux/io.h>
  18 #include <linux/err.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/prefetch.h>
  22 #include <linux/usb/usb_phy_generic.h>
  23
  24 #include <asm/cacheflush.h>
  25
  26 #include "musb_core.h"
  27 #include "musbhsdma.h"
  28 #include "blackfin.h"
  29
  30 struct bfin_glue {
  31         struct device           *dev;
  32         struct platform_device  *musb;
  33         struct platform_device  *phy;
  34 };
  35 #define glue_to_musb(g)         platform_get_drvdata(g->musb)
  36
  37 static u32 bfin_fifo_offset(u8 epnum)
  38 {
  39         return USB_OFFSET(USB_EP0_FIFO) + (epnum * 8);
  40 }
  41
  42 static u8 bfin_readb(const void __iomem *addr, unsigned offset)
  43 {
  44         return (u8)(bfin_read16(addr + offset));
  45 }
  46
  47 static u16 bfin_readw(const void __iomem *addr, unsigned offset)
  48 {
  49         return bfin_read16(addr + offset);
  50 }
  51
  52 static u32 bfin_readl(const void __iomem *addr, unsigned offset)
  53 {
  54         return (u32)(bfin_read16(addr + offset));
  55 }
  56
  57 static void bfin_writeb(void __iomem *addr, unsigned offset, u8 data)
  58 {
  59         bfin_write16(addr + offset, (u16)data);
  60 }
  61
  62 static void bfin_writew(void __iomem *addr, unsigned offset, u16 data)
  63 {
  64         bfin_write16(addr + offset, data);
  65 }
  66
  67 static void bfin_writel(void __iomem *addr, unsigned offset, u32 data)
  68 {
  69         bfin_write16(addr + offset, (u16)data);
  70 }
  71
  72 /*
  73  * Load an endpoint's FIFO
  74  */
  75 static void bfin_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
  76 {
  77         struct musb *musb = hw_ep->musb;
  78         void __iomem *fifo = hw_ep->fifo;
  79         void __iomem *epio = hw_ep->regs;
  80         u8 epnum = hw_ep->epnum;
  81
  82         prefetch((u8 *)src);
  83
  84         musb_writew(epio, MUSB_TXCOUNT, len);
  85
  86         dev_dbg(musb->controller, "TX ep%d fifo %p count %d buf %p, epio %p\n",
  87                         hw_ep->epnum, fifo, len, src, epio);
  88
  89         dump_fifo_data(src, len);
  90
  91         if (!ANOMALY_05000380 && epnum != 0) {
  92                 u16 dma_reg;
  93
  94                 flush_dcache_range((unsigned long)src,
  95                         (unsigned long)(src + len));
  96
  97                 /* Setup DMA address register */
  98                 dma_reg = (u32)src;
  99                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
 100                 SSYNC();
 101
 102                 dma_reg = (u32)src >> 16;
 103                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
 104                 SSYNC();
 105
 106                 /* Setup DMA count register */
 107                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
 108                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
 109                 SSYNC();
 110
 111                 /* Enable the DMA */
 112                 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA | DIRECTION;
 113                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
 114                 SSYNC();
 115
 116                 /* Wait for complete */
 117                 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
 118                         cpu_relax();
 119
 120                 /* acknowledge dma interrupt */
 121                 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
 122                 SSYNC();
 123
 124                 /* Reset DMA */
 125                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
 126                 SSYNC();
 127         } else {
 128                 SSYNC();
 129
 130                 if (unlikely((unsigned long)src & 0x01))
 131                         outsw_8((unsigned long)fifo, src, (len + 1) >> 1);
 132                 else
 133                         outsw((unsigned long)fifo, src, (len + 1) >> 1);
 134         }
 135 }
 136 /*
 137  * Unload an endpoint's FIFO
 138  */
 139 static void bfin_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
 140 {
 141         struct musb *musb = hw_ep->musb;
 142         void __iomem *fifo = hw_ep->fifo;
 143         u8 epnum = hw_ep->epnum;
 144
 145         if (ANOMALY_05000467 && epnum != 0) {
 146                 u16 dma_reg;
 147
 148                 invalidate_dcache_range((unsigned long)dst,
 149                         (unsigned long)(dst + len));
 150
 151                 /* Setup DMA address register */
 152                 dma_reg = (u32)dst;
 153                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
 154                 SSYNC();
 155
 156                 dma_reg = (u32)dst >> 16;
 157                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
 158                 SSYNC();
 159
 160                 /* Setup DMA count register */
 161                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
 162                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
 163                 SSYNC();
 164
 165                 /* Enable the DMA */
 166                 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA;
 167                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
 168                 SSYNC();
 169
 170                 /* Wait for complete */
 171                 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
 172                         cpu_relax();
 173
 174                 /* acknowledge dma interrupt */
 175                 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
 176                 SSYNC();
 177
 178                 /* Reset DMA */
 179                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
 180                 SSYNC();
 181         } else {
 182                 SSYNC();
 183                 /* Read the last byte of packet with odd size from address fifo + 4
 184                  * to trigger 1 byte access to EP0 FIFO.
 185                  */
 186                 if (len == 1)
 187                         *dst = (u8)inw((unsigned long)fifo + 4);
 188                 else {
 189                         if (unlikely((unsigned long)dst & 0x01))
 190                                 insw_8((unsigned long)fifo, dst, len >> 1);
 191                         else
 192                                 insw((unsigned long)fifo, dst, len >> 1);
 193
 194                         if (len & 0x01)
 195                                 *(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
 196                 }
 197         }
 198         dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
 199                         'R', hw_ep->epnum, fifo, len, dst);
 200
 201         dump_fifo_data(dst, len);
 202 }
 203
 204 static irqreturn_t blackfin_interrupt(int irq, void *__hci)
 205 {
 206         unsigned long   flags;
 207         irqreturn_t     retval = IRQ_NONE;
 208         struct musb     *musb = __hci;
 209
 210         spin_lock_irqsave(&musb->lock, flags);
 211
 212         musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
 213         musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
 214         musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
 215
 216         if (musb->int_usb || musb->int_tx || musb->int_rx) {
 217                 musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
 218                 musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
 219                 musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
 220                 retval = musb_interrupt(musb);
 221         }
 222
 223         /* Start sampling ID pin, when plug is removed from MUSB */
 224         if ((musb->xceiv->otg->state == OTG_STATE_B_IDLE
 225                 || musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON) ||
 226                 (musb->int_usb & MUSB_INTR_DISCONNECT && is_host_active(musb))) {
 227                 mod_timer(&musb->dev_timer, jiffies + TIMER_DELAY);
 228                 musb->a_wait_bcon = TIMER_DELAY;
 229         }
 230
 231         spin_unlock_irqrestore(&musb->lock, flags);
 232
 233         return retval;
 234 }
 235
 236 static void musb_conn_timer_handler(struct timer_list *t)
 237 {
 238         struct musb *musb = from_timer(musb, t, dev_timer);
 239         unsigned long flags;
 240         u16 val;
 241         static u8 toggle;
 242
 243         spin_lock_irqsave(&musb->lock, flags);
 244         switch (musb->xceiv->otg->state) {
 245         case OTG_STATE_A_IDLE:
 246         case OTG_STATE_A_WAIT_BCON:
 247                 /* Start a new session */
 248                 val = musb_readw(musb->mregs, MUSB_DEVCTL);
 249                 val &= ~MUSB_DEVCTL_SESSION;
 250                 musb_writew(musb->mregs, MUSB_DEVCTL, val);
 251                 val |= MUSB_DEVCTL_SESSION;
 252                 musb_writew(musb->mregs, MUSB_DEVCTL, val);
 253                 /* Check if musb is host or peripheral. */
 254                 val = musb_readw(musb->mregs, MUSB_DEVCTL);
 255
 256                 if (!(val & MUSB_DEVCTL_BDEVICE)) {
 257                         gpio_set_value(musb->config->gpio_vrsel, 1);
 258                         musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
 259                 } else {
 260                         gpio_set_value(musb->config->gpio_vrsel, 0);
 261                         /* Ignore VBUSERROR and SUSPEND IRQ */
 262                         val = musb_readb(musb->mregs, MUSB_INTRUSBE);
 263                         val &= ~MUSB_INTR_VBUSERROR;
 264                         musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
 265
 266                         val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
 267                         musb_writeb(musb->mregs, MUSB_INTRUSB, val);
 268                         musb->xceiv->otg->state = OTG_STATE_B_IDLE;
 269                 }
 270                 mod_timer(&musb->dev_timer, jiffies + TIMER_DELAY);
 271                 break;
 272         case OTG_STATE_B_IDLE:
 273                 /*
 274                  * Start a new session.  It seems that MUSB needs taking
 275                  * some time to recognize the type of the plug inserted?
 276                  */
 277                 val = musb_readw(musb->mregs, MUSB_DEVCTL);
 278                 val |= MUSB_DEVCTL_SESSION;
 279                 musb_writew(musb->mregs, MUSB_DEVCTL, val);
 280                 val = musb_readw(musb->mregs, MUSB_DEVCTL);
 281
 282                 if (!(val & MUSB_DEVCTL_BDEVICE)) {
 283                         gpio_set_value(musb->config->gpio_vrsel, 1);
 284                         musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
 285                 } else {
 286                         gpio_set_value(musb->config->gpio_vrsel, 0);
 287
 288                         /* Ignore VBUSERROR and SUSPEND IRQ */
 289                         val = musb_readb(musb->mregs, MUSB_INTRUSBE);
 290                         val &= ~MUSB_INTR_VBUSERROR;
 291                         musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
 292
 293                         val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
 294                         musb_writeb(musb->mregs, MUSB_INTRUSB, val);
 295
 296                         /* Toggle the Soft Conn bit, so that we can response to
 297                          * the inserting of either A-plug or B-plug.
 298                          */
 299                         if (toggle) {
 300                                 val = musb_readb(musb->mregs, MUSB_POWER);
 301                                 val &= ~MUSB_POWER_SOFTCONN;
 302                                 musb_writeb(musb->mregs, MUSB_POWER, val);
 303                                 toggle = 0;
 304                         } else {
 305                                 val = musb_readb(musb->mregs, MUSB_POWER);
 306                                 val |= MUSB_POWER_SOFTCONN;
 307                                 musb_writeb(musb->mregs, MUSB_POWER, val);
 308                                 toggle = 1;
 309                         }
 310                         /* The delay time is set to 1/4 second by default,
 311                          * shortening it, if accelerating A-plug detection
 312                          * is needed in OTG mode.
 313                          */
 314                         mod_timer(&musb->dev_timer, jiffies + TIMER_DELAY / 4);
 315                 }
 316                 break;
 317         default:
 318                 dev_dbg(musb->controller, "%s state not handled\n",
 319                         usb_otg_state_string(musb->xceiv->otg->state));
 320                 break;
 321         }
 322         spin_unlock_irqrestore(&musb->lock, flags);
 323
 324         dev_dbg(musb->controller, "state is %s\n",
 325                 usb_otg_state_string(musb->xceiv->otg->state));
 326 }
 327
 328 static void bfin_musb_enable(struct musb *musb)
 329 {
 330         /* REVISIT is this really correct ? */
 331 }
 332
 333 static void bfin_musb_disable(struct musb *musb)
 334 {
 335 }
 336
 337 static void bfin_musb_set_vbus(struct musb *musb, int is_on)
 338 {
 339         int value = musb->config->gpio_vrsel_active;
 340         if (!is_on)
 341                 value = !value;
 342         gpio_set_value(musb->config->gpio_vrsel, value);
 343
 344         dev_dbg(musb->controller, "VBUS %s, devctl %02x "
 345                 /* otg %3x conf %08x prcm %08x */ "\n",
 346                 usb_otg_state_string(musb->xceiv->otg->state),
 347                 musb_readb(musb->mregs, MUSB_DEVCTL));
 348 }
 349
 350 static int bfin_musb_set_power(struct usb_phy *x, unsigned mA)
 351 {
 352         return 0;
 353 }
 354
 355 static int bfin_musb_vbus_status(struct musb *musb)
 356 {
 357         return 0;
 358 }
 359
 360 static int bfin_musb_set_mode(struct musb *musb, u8 musb_mode)
 361 {
 362         return -EIO;
 363 }
 364
 365 static int bfin_musb_adjust_channel_params(struct dma_channel *channel,
 366                                 u16 packet_sz, u8 *mode,
 367                                 dma_addr_t *dma_addr, u32 *len)
 368 {
 369         struct musb_dma_channel *musb_channel = channel->private_data;
 370
 371         /*
 372          * Anomaly 05000450 might cause data corruption when using DMA
 373          * MODE 1 transmits with short packet.  So to work around this,
 374          * we truncate all MODE 1 transfers down to a multiple of the
 375          * max packet size, and then do the last short packet transfer
 376          * (if there is any) using MODE 0.
 377          */
 378         if (ANOMALY_05000450) {
 379                 if (musb_channel->transmit && *mode == 1)
 380                         *len = *len - (*len % packet_sz);
 381         }
 382
 383         return 0;
 384 }
 385
 386 static void bfin_musb_reg_init(struct musb *musb)
 387 {
 388         if (ANOMALY_05000346) {
 389                 bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
 390                 SSYNC();
 391         }
 392
 393         if (ANOMALY_05000347) {
 394                 bfin_write_USB_APHY_CNTRL(0x0);
 395                 SSYNC();
 396         }
 397
 398         /* Configure PLL oscillator register */
 399         bfin_write_USB_PLLOSC_CTRL(0x3080 |
 400                         ((480/musb->config->clkin) << 1));
 401         SSYNC();
 402
 403         bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
 404         SSYNC();
 405
 406         bfin_write_USB_EP_NI0_RXMAXP(64);
 407         SSYNC();
 408
 409         bfin_write_USB_EP_NI0_TXMAXP(64);
 410         SSYNC();
 411
 412         /* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
 413         bfin_write_USB_GLOBINTR(0x7);
 414         SSYNC();
 415
 416         bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
 417                                 EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
 418                                 EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
 419                                 EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
 420                                 EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
 421         SSYNC();
 422 }
 423
 424 static int bfin_musb_init(struct musb *musb)
 425 {
 426
 427         /*
 428          * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
 429          * and OTG HOST modes, while rev 1.1 and greater require PE7 to
 430          * be low for DEVICE mode and high for HOST mode. We set it high
 431          * here because we are in host mode
 432          */
 433
 434         if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
 435                 printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d\n",
 436                         musb->config->gpio_vrsel);
 437                 return -ENODEV;
 438         }
 439         gpio_direction_output(musb->config->gpio_vrsel, 0);
 440
 441         musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
 442         if (IS_ERR_OR_NULL(musb->xceiv)) {
 443                 gpio_free(musb->config->gpio_vrsel);
 444                 return -EPROBE_DEFER;
 445         }
 446
 447         bfin_musb_reg_init(musb);
 448
 449         timer_setup(&musb->dev_timer, musb_conn_timer_handler, 0);
 450
 451         musb->xceiv->set_power = bfin_musb_set_power;
 452
 453         musb->isr = blackfin_interrupt;
 454         musb->double_buffer_not_ok = true;
 455
 456         return 0;
 457 }
 458
 459 static int bfin_musb_exit(struct musb *musb)
 460 {
 461         gpio_free(musb->config->gpio_vrsel);
 462         usb_put_phy(musb->xceiv);
 463
 464         return 0;
 465 }
 466
 467 static const struct musb_platform_ops bfin_ops = {
 468         .quirks         = MUSB_DMA_INVENTRA,
 469         .init           = bfin_musb_init,
 470         .exit           = bfin_musb_exit,
 471
 472         .fifo_offset    = bfin_fifo_offset,
 473         .readb          = bfin_readb,
 474         .writeb         = bfin_writeb,
 475         .readw          = bfin_readw,
 476         .writew         = bfin_writew,
 477         .readl          = bfin_readl,
 478         .writel         = bfin_writel,
 479         .fifo_mode      = 2,
 480         .read_fifo      = bfin_read_fifo,
 481         .write_fifo     = bfin_write_fifo,
 482 #ifdef CONFIG_USB_INVENTRA_DMA
 483         .dma_init       = musbhs_dma_controller_create,
 484         .dma_exit       = musbhs_dma_controller_destroy,
 485 #endif
 486         .enable         = bfin_musb_enable,
 487         .disable        = bfin_musb_disable,
 488
 489         .set_mode       = bfin_musb_set_mode,
 490
 491         .vbus_status    = bfin_musb_vbus_status,
 492         .set_vbus       = bfin_musb_set_vbus,
 493
 494         .adjust_channel_params = bfin_musb_adjust_channel_params,
 495 };
 496
 497 static u64 bfin_dmamask = DMA_BIT_MASK(32);
 498
 499 static int bfin_probe(struct platform_device *pdev)
 500 {
 501         struct resource musb_resources[2];
 502         struct musb_hdrc_platform_data  *pdata = dev_get_platdata(&pdev->dev);
 503         struct platform_device          *musb;
 504         struct bfin_glue                *glue;
 505
 506         int                             ret = -ENOMEM;
 507
 508         glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
 509         if (!glue)
 510                 goto err0;
 511
 512         musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO);
 513         if (!musb)
 514                 goto err0;
 515
 516         musb->dev.parent                = &pdev->dev;
 517         musb->dev.dma_mask              = &bfin_dmamask;
 518         musb->dev.coherent_dma_mask     = bfin_dmamask;
 519
 520         glue->dev                       = &pdev->dev;
 521         glue->musb                      = musb;
 522
 523         pdata->platform_ops             = &bfin_ops;
 524
 525         glue->phy = usb_phy_generic_register();
 526         if (IS_ERR(glue->phy))
 527                 goto err1;
 528         platform_set_drvdata(pdev, glue);
 529
 530         memset(musb_resources, 0x00, sizeof(*musb_resources) *
 531                         ARRAY_SIZE(musb_resources));
 532
 533         musb_resources[0].name = pdev->resource[0].name;
 534         musb_resources[0].start = pdev->resource[0].start;
 535         musb_resources[0].end = pdev->resource[0].end;
 536         musb_resources[0].flags = pdev->resource[0].flags;
 537
 538         musb_resources[1].name = pdev->resource[1].name;
 539         musb_resources[1].start = pdev->resource[1].start;
 540         musb_resources[1].end = pdev->resource[1].end;
 541         musb_resources[1].flags = pdev->resource[1].flags;
 542
 543         ret = platform_device_add_resources(musb, musb_resources,
 544                         ARRAY_SIZE(musb_resources));
 545         if (ret) {
 546                 dev_err(&pdev->dev, "failed to add resources\n");
 547                 goto err2;
 548         }
 549
 550         ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
 551         if (ret) {
 552                 dev_err(&pdev->dev, "failed to add platform_data\n");
 553                 goto err2;
 554         }
 555
 556         ret = platform_device_add(musb);
 557         if (ret) {
 558                 dev_err(&pdev->dev, "failed to register musb device\n");
 559                 goto err2;
 560         }
 561
 562         return 0;
 563
 564 err2:
 565         usb_phy_generic_unregister(glue->phy);
 566
 567 err1:
 568         platform_device_put(musb);
 569
 570 err0:
 571         return ret;
 572 }
 573
 574 static int bfin_remove(struct platform_device *pdev)
 575 {
 576         struct bfin_glue                *glue = platform_get_drvdata(pdev);
 577
 578         platform_device_unregister(glue->musb);
 579         usb_phy_generic_unregister(glue->phy);
 580
 581         return 0;
 582 }
 583
 584 static int __maybe_unused bfin_suspend(struct device *dev)
 585 {
 586         struct bfin_glue        *glue = dev_get_drvdata(dev);
 587         struct musb             *musb = glue_to_musb(glue);
 588
 589         if (is_host_active(musb))
 590                 /*
 591                  * During hibernate gpio_vrsel will change from high to low
 592                  * low which will generate wakeup event resume the system
 593                  * immediately.  Set it to 0 before hibernate to avoid this
 594                  * wakeup event.
 595                  */
 596                 gpio_set_value(musb->config->gpio_vrsel, 0);
 597
 598         return 0;
 599 }
 600
 601 static int __maybe_unused bfin_resume(struct device *dev)
 602 {
 603         struct bfin_glue        *glue = dev_get_drvdata(dev);
 604         struct musb             *musb = glue_to_musb(glue);
 605
 606         bfin_musb_reg_init(musb);
 607
 608         return 0;
 609 }
 610
 611 static SIMPLE_DEV_PM_OPS(bfin_pm_ops, bfin_suspend, bfin_resume);
 612
 613 static struct platform_driver bfin_driver = {
 614         .probe          = bfin_probe,
 615         .remove         = bfin_remove,
 616         .driver         = {
 617                 .name   = "musb-blackfin",
 618                 .pm     = &bfin_pm_ops,
 619         },
 620 };
 621
 622 MODULE_DESCRIPTION("Blackfin MUSB Glue Layer");
 623 MODULE_AUTHOR("Bryan Wy <cooloney@kernel.org>");
 624 MODULE_LICENSE("GPL v2");
 625 module_platform_driver(bfin_driver);