drivers/usb/musb/blackfin.c

   1 /*
   2  * MUSB OTG controller driver for Blackfin Processors
   3  *
   4  * Copyright 2006-2008 Analog Devices Inc.
   5  *
   6  * Enter bugs at http://blackfin.uclinux.org/
   7  *
   8  * Licensed under the GPL-2 or later.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/sched.h>
  14 #include <linux/slab.h>
  15 #include <linux/init.h>
  16 #include <linux/list.h>
  17 #include <linux/gpio.h>
  18 #include <linux/io.h>
  19
  20 #include <asm/cacheflush.h>
  21
  22 #include "musb_core.h"
  23 #include "blackfin.h"
  24
  25 /*
  26  * Load an endpoint's FIFO
  27  */
  28 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
  29 {
  30         void __iomem *fifo = hw_ep->fifo;
  31         void __iomem *epio = hw_ep->regs;
  32         u8 epnum = hw_ep->epnum;
  33
  34         prefetch((u8 *)src);
  35
  36         musb_writew(epio, MUSB_TXCOUNT, len);
  37
  38         DBG(4, "TX ep%d fifo %p count %d buf %p, epio %p\n",
  39                         hw_ep->epnum, fifo, len, src, epio);
  40
  41         dump_fifo_data(src, len);
  42
  43         if (!ANOMALY_05000380 && epnum != 0) {
  44                 u16 dma_reg;
  45
  46                 flush_dcache_range((unsigned long)src,
  47                         (unsigned long)(src + len));
  48
  49                 /* Setup DMA address register */
  50                 dma_reg = (u32)src;
  51                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
  52                 SSYNC();
  53
  54                 dma_reg = (u32)src >> 16;
  55                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
  56                 SSYNC();
  57
  58                 /* Setup DMA count register */
  59                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
  60                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
  61                 SSYNC();
  62
  63                 /* Enable the DMA */
  64                 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA | DIRECTION;
  65                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
  66                 SSYNC();
  67
  68                 /* Wait for compelete */
  69                 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
  70                         cpu_relax();
  71
  72                 /* acknowledge dma interrupt */
  73                 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
  74                 SSYNC();
  75
  76                 /* Reset DMA */
  77                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
  78                 SSYNC();
  79         } else {
  80                 SSYNC();
  81
  82                 if (unlikely((unsigned long)src & 0x01))
  83                         outsw_8((unsigned long)fifo, src, (len + 1) >> 1);
  84                 else
  85                         outsw((unsigned long)fifo, src, (len + 1) >> 1);
  86         }
  87 }
  88 /*
  89  * Unload an endpoint's FIFO
  90  */
  91 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
  92 {
  93         void __iomem *fifo = hw_ep->fifo;
  94         u8 epnum = hw_ep->epnum;
  95
  96         if (ANOMALY_05000467 && epnum != 0) {
  97                 u16 dma_reg;
  98
  99                 invalidate_dcache_range((unsigned long)dst,
 100                         (unsigned long)(dst + len));
 101
 102                 /* Setup DMA address register */
 103                 dma_reg = (u32)dst;
 104                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
 105                 SSYNC();
 106
 107                 dma_reg = (u32)dst >> 16;
 108                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
 109                 SSYNC();
 110
 111                 /* Setup DMA count register */
 112                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
 113                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
 114                 SSYNC();
 115
 116                 /* Enable the DMA */
 117                 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA;
 118                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
 119                 SSYNC();
 120
 121                 /* Wait for compelete */
 122                 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
 123                         cpu_relax();
 124
 125                 /* acknowledge dma interrupt */
 126                 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
 127                 SSYNC();
 128
 129                 /* Reset DMA */
 130                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
 131                 SSYNC();
 132         } else {
 133                 SSYNC();
 134                 /* Read the last byte of packet with odd size from address fifo + 4
 135                  * to trigger 1 byte access to EP0 FIFO.
 136                  */
 137                 if (len == 1)
 138                         *dst = (u8)inw((unsigned long)fifo + 4);
 139                 else {
 140                         if (unlikely((unsigned long)dst & 0x01))
 141                                 insw_8((unsigned long)fifo, dst, len >> 1);
 142                         else
 143                                 insw((unsigned long)fifo, dst, len >> 1);
 144
 145                         if (len & 0x01)
 146                                 *(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
 147                 }
 148         }
 149         DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
 150                         'R', hw_ep->epnum, fifo, len, dst);
 151
 152         dump_fifo_data(dst, len);
 153 }
 154
 155 static irqreturn_t blackfin_interrupt(int irq, void *__hci)
 156 {
 157         unsigned long   flags;
 158         irqreturn_t     retval = IRQ_NONE;
 159         struct musb     *musb = __hci;
 160
 161         spin_lock_irqsave(&musb->lock, flags);
 162
 163         musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
 164         musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
 165         musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
 166
 167         if (musb->int_usb || musb->int_tx || musb->int_rx) {
 168                 musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
 169                 musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
 170                 musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
 171                 retval = musb_interrupt(musb);
 172         }
 173
 174         spin_unlock_irqrestore(&musb->lock, flags);
 175
 176         /* REVISIT we sometimes get spurious IRQs on g_ep0
 177          * not clear why... fall in BF54x too.
 178          */
 179         if (retval != IRQ_HANDLED)
 180                 DBG(5, "spurious?\n");
 181
 182         return IRQ_HANDLED;
 183 }
 184
 185 static void musb_conn_timer_handler(unsigned long _musb)
 186 {
 187         struct musb *musb = (void *)_musb;
 188         unsigned long flags;
 189         u16 val;
 190
 191         spin_lock_irqsave(&musb->lock, flags);
 192         switch (musb->xceiv->state) {
 193         case OTG_STATE_A_IDLE:
 194         case OTG_STATE_A_WAIT_BCON:
 195                 /* Start a new session */
 196                 val = musb_readw(musb->mregs, MUSB_DEVCTL);
 197                 val |= MUSB_DEVCTL_SESSION;
 198                 musb_writew(musb->mregs, MUSB_DEVCTL, val);
 199
 200                 val = musb_readw(musb->mregs, MUSB_DEVCTL);
 201                 if (!(val & MUSB_DEVCTL_BDEVICE)) {
 202                         gpio_set_value(musb->config->gpio_vrsel, 1);
 203                         musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
 204                 } else {
 205                         gpio_set_value(musb->config->gpio_vrsel, 0);
 206
 207                         /* Ignore VBUSERROR and SUSPEND IRQ */
 208                         val = musb_readb(musb->mregs, MUSB_INTRUSBE);
 209                         val &= ~MUSB_INTR_VBUSERROR;
 210                         musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
 211
 212                         val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
 213                         musb_writeb(musb->mregs, MUSB_INTRUSB, val);
 214
 215                         val = MUSB_POWER_HSENAB;
 216                         musb_writeb(musb->mregs, MUSB_POWER, val);
 217                 }
 218                 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
 219                 break;
 220
 221         default:
 222                 DBG(1, "%s state not handled\n", otg_state_string(musb));
 223                 break;
 224         }
 225         spin_unlock_irqrestore(&musb->lock, flags);
 226
 227         DBG(4, "state is %s\n", otg_state_string(musb));
 228 }
 229
 230 void musb_platform_enable(struct musb *musb)
 231 {
 232         if (is_host_enabled(musb)) {
 233                 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
 234                 musb->a_wait_bcon = TIMER_DELAY;
 235         }
 236 }
 237
 238 void musb_platform_disable(struct musb *musb)
 239 {
 240 }
 241
 242 static void bfin_vbus_power(struct musb *musb, int is_on, int sleeping)
 243 {
 244 }
 245
 246 static void bfin_set_vbus(struct musb *musb, int is_on)
 247 {
 248         if (is_on)
 249                 gpio_set_value(musb->config->gpio_vrsel, 1);
 250         else
 251                 gpio_set_value(musb->config->gpio_vrsel, 0);
 252
 253         DBG(1, "VBUS %s, devctl %02x "
 254                 /* otg %3x conf %08x prcm %08x */ "\n",
 255                 otg_state_string(musb),
 256                 musb_readb(musb->mregs, MUSB_DEVCTL));
 257 }
 258
 259 static int bfin_set_power(struct otg_transceiver *x, unsigned mA)
 260 {
 261         return 0;
 262 }
 263
 264 void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
 265 {
 266         if (is_host_enabled(musb))
 267                 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
 268 }
 269
 270 int musb_platform_get_vbus_status(struct musb *musb)
 271 {
 272         return 0;
 273 }
 274
 275 int musb_platform_set_mode(struct musb *musb, u8 musb_mode)
 276 {
 277         return -EIO;
 278 }
 279
 280 int __init musb_platform_init(struct musb *musb)
 281 {
 282
 283         /*
 284          * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
 285          * and OTG HOST modes, while rev 1.1 and greater require PE7 to
 286          * be low for DEVICE mode and high for HOST mode. We set it high
 287          * here because we are in host mode
 288          */
 289
 290         if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
 291                 printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d \n",
 292                         musb->config->gpio_vrsel);
 293                 return -ENODEV;
 294         }
 295         gpio_direction_output(musb->config->gpio_vrsel, 0);
 296
 297         usb_nop_xceiv_register();
 298         musb->xceiv = otg_get_transceiver();
 299         if (!musb->xceiv)
 300                 return -ENODEV;
 301
 302         if (ANOMALY_05000346) {
 303                 bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
 304                 SSYNC();
 305         }
 306
 307         if (ANOMALY_05000347) {
 308                 bfin_write_USB_APHY_CNTRL(0x0);
 309                 SSYNC();
 310         }
 311
 312         /* Configure PLL oscillator register */
 313         bfin_write_USB_PLLOSC_CTRL(0x30a8);
 314         SSYNC();
 315
 316         bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
 317         SSYNC();
 318
 319         bfin_write_USB_EP_NI0_RXMAXP(64);
 320         SSYNC();
 321
 322         bfin_write_USB_EP_NI0_TXMAXP(64);
 323         SSYNC();
 324
 325         /* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
 326         bfin_write_USB_GLOBINTR(0x7);
 327         SSYNC();
 328
 329         bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
 330                                 EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
 331                                 EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
 332                                 EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
 333                                 EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
 334         SSYNC();
 335
 336         if (is_host_enabled(musb)) {
 337                 musb->board_set_vbus = bfin_set_vbus;
 338                 setup_timer(&musb_conn_timer,
 339                         musb_conn_timer_handler, (unsigned long) musb);
 340         }
 341         if (is_peripheral_enabled(musb))
 342                 musb->xceiv->set_power = bfin_set_power;
 343
 344         musb->isr = blackfin_interrupt;
 345
 346         return 0;
 347 }
 348
 349 int musb_platform_suspend(struct musb *musb)
 350 {
 351         return 0;
 352 }
 353
 354 int musb_platform_resume(struct musb *musb)
 355 {
 356         return 0;
 357 }
 358
 359
 360 int musb_platform_exit(struct musb *musb)
 361 {
 362
 363         bfin_vbus_power(musb, 0 /*off*/, 1);
 364         gpio_free(musb->config->gpio_vrsel);
 365         musb_platform_suspend(musb);
 366
 367         return 0;
 368 }