drivers/usb/musb/blackfin.c

   1 /*
   2  * MUSB OTG controller driver for Blackfin Processors
   3  *
   4  * Copyright 2006-2008 Analog Devices Inc.
   5  *
   6  * Enter bugs at http://blackfin.uclinux.org/
   7  *
   8  * Licensed under the GPL-2 or later.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/sched.h>
  14 #include <linux/slab.h>
  15 #include <linux/init.h>
  16 #include <linux/list.h>
  17 #include <linux/gpio.h>
  18 #include <linux/io.h>
  19
  20 #include <asm/cacheflush.h>
  21
  22 #include "musb_core.h"
  23 #include "blackfin.h"
  24
  25 /*
  26  * Load an endpoint's FIFO
  27  */
  28 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
  29 {
  30         void __iomem *fifo = hw_ep->fifo;
  31         void __iomem *epio = hw_ep->regs;
  32         u8 epnum = hw_ep->epnum;
  33         u16 dma_reg = 0;
  34
  35         prefetch((u8 *)src);
  36
  37         musb_writew(epio, MUSB_TXCOUNT, len);
  38
  39         DBG(4, "TX ep%d fifo %p count %d buf %p, epio %p\n",
  40                         hw_ep->epnum, fifo, len, src, epio);
  41
  42         dump_fifo_data(src, len);
  43
  44         if (!ANOMALY_05000380 && epnum != 0) {
  45                 flush_dcache_range((unsigned int)src,
  46                         (unsigned int)(src + len));
  47
  48                 /* Setup DMA address register */
  49                 dma_reg = (u16) ((u32) src & 0xFFFF);
  50                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
  51                 SSYNC();
  52
  53                 dma_reg = (u16) (((u32) src >> 16) & 0xFFFF);
  54                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
  55                 SSYNC();
  56
  57                 /* Setup DMA count register */
  58                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
  59                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
  60                 SSYNC();
  61
  62                 /* Enable the DMA */
  63                 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA | DIRECTION;
  64                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
  65                 SSYNC();
  66
  67                 /* Wait for compelete */
  68                 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
  69                         cpu_relax();
  70
  71                 /* acknowledge dma interrupt */
  72                 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
  73                 SSYNC();
  74
  75                 /* Reset DMA */
  76                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
  77                 SSYNC();
  78         } else {
  79                 SSYNC();
  80
  81                 if (unlikely((unsigned long)src & 0x01))
  82                         outsw_8((unsigned long)fifo, src,
  83                                 len & 0x01 ? (len >> 1) + 1 : len >> 1);
  84                 else
  85                         outsw((unsigned long)fifo, src,
  86                                 len & 0x01 ? (len >> 1) + 1 : len >> 1);
  87
  88         }
  89 }
  90 /*
  91  * Unload an endpoint's FIFO
  92  */
  93 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
  94 {
  95         void __iomem *fifo = hw_ep->fifo;
  96         u8 epnum = hw_ep->epnum;
  97         u16 dma_reg = 0;
  98
  99         if (ANOMALY_05000467 && epnum != 0) {
 100
 101                 invalidate_dcache_range((unsigned int)dst,
 102                         (unsigned int)(dst + len));
 103
 104                 /* Setup DMA address register */
 105                 dma_reg = (u16) ((u32) dst & 0xFFFF);
 106                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
 107                 SSYNC();
 108
 109                 dma_reg = (u16) (((u32) dst >> 16) & 0xFFFF);
 110                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
 111                 SSYNC();
 112
 113                 /* Setup DMA count register */
 114                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
 115                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
 116                 SSYNC();
 117
 118                 /* Enable the DMA */
 119                 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA;
 120                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
 121                 SSYNC();
 122
 123                 /* Wait for compelete */
 124                 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
 125                         cpu_relax();
 126
 127                 /* acknowledge dma interrupt */
 128                 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
 129                 SSYNC();
 130
 131                 /* Reset DMA */
 132                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
 133                 SSYNC();
 134         } else {
 135                 SSYNC();
 136                 /* Read the last byte of packet with odd size from address fifo + 4
 137                  * to trigger 1 byte access to EP0 FIFO.
 138                  */
 139                 if (len == 1)
 140                         *dst = (u8)inw((unsigned long)fifo + 4);
 141                 else {
 142                         if (unlikely((unsigned long)dst & 0x01))
 143                                 insw_8((unsigned long)fifo, dst, len >> 1);
 144                         else
 145                                 insw((unsigned long)fifo, dst, len >> 1);
 146
 147                         if (len & 0x01)
 148                                 *(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
 149                 }
 150         }
 151         DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
 152                         'R', hw_ep->epnum, fifo, len, dst);
 153
 154         dump_fifo_data(dst, len);
 155 }
 156
 157 static irqreturn_t blackfin_interrupt(int irq, void *__hci)
 158 {
 159         unsigned long   flags;
 160         irqreturn_t     retval = IRQ_NONE;
 161         struct musb     *musb = __hci;
 162
 163         spin_lock_irqsave(&musb->lock, flags);
 164
 165         musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
 166         musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
 167         musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
 168
 169         if (musb->int_usb || musb->int_tx || musb->int_rx) {
 170                 musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
 171                 musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
 172                 musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
 173                 retval = musb_interrupt(musb);
 174         }
 175
 176         spin_unlock_irqrestore(&musb->lock, flags);
 177
 178         /* REVISIT we sometimes get spurious IRQs on g_ep0
 179          * not clear why... fall in BF54x too.
 180          */
 181         if (retval != IRQ_HANDLED)
 182                 DBG(5, "spurious?\n");
 183
 184         return IRQ_HANDLED;
 185 }
 186
 187 static void musb_conn_timer_handler(unsigned long _musb)
 188 {
 189         struct musb *musb = (void *)_musb;
 190         unsigned long flags;
 191         u16 val;
 192
 193         spin_lock_irqsave(&musb->lock, flags);
 194         switch (musb->xceiv->state) {
 195         case OTG_STATE_A_IDLE:
 196         case OTG_STATE_A_WAIT_BCON:
 197                 /* Start a new session */
 198                 val = musb_readw(musb->mregs, MUSB_DEVCTL);
 199                 val |= MUSB_DEVCTL_SESSION;
 200                 musb_writew(musb->mregs, MUSB_DEVCTL, val);
 201
 202                 val = musb_readw(musb->mregs, MUSB_DEVCTL);
 203                 if (!(val & MUSB_DEVCTL_BDEVICE)) {
 204                         gpio_set_value(musb->config->gpio_vrsel, 1);
 205                         musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
 206                 } else {
 207                         gpio_set_value(musb->config->gpio_vrsel, 0);
 208
 209                         /* Ignore VBUSERROR and SUSPEND IRQ */
 210                         val = musb_readb(musb->mregs, MUSB_INTRUSBE);
 211                         val &= ~MUSB_INTR_VBUSERROR;
 212                         musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
 213
 214                         val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
 215                         musb_writeb(musb->mregs, MUSB_INTRUSB, val);
 216
 217                         val = MUSB_POWER_HSENAB;
 218                         musb_writeb(musb->mregs, MUSB_POWER, val);
 219                 }
 220                 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
 221                 break;
 222
 223         default:
 224                 DBG(1, "%s state not handled\n", otg_state_string(musb));
 225                 break;
 226         }
 227         spin_unlock_irqrestore(&musb->lock, flags);
 228
 229         DBG(4, "state is %s\n", otg_state_string(musb));
 230 }
 231
 232 void musb_platform_enable(struct musb *musb)
 233 {
 234         if (is_host_enabled(musb)) {
 235                 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
 236                 musb->a_wait_bcon = TIMER_DELAY;
 237         }
 238 }
 239
 240 void musb_platform_disable(struct musb *musb)
 241 {
 242 }
 243
 244 static void bfin_vbus_power(struct musb *musb, int is_on, int sleeping)
 245 {
 246 }
 247
 248 static void bfin_set_vbus(struct musb *musb, int is_on)
 249 {
 250         if (is_on)
 251                 gpio_set_value(musb->config->gpio_vrsel, 1);
 252         else
 253                 gpio_set_value(musb->config->gpio_vrsel, 0);
 254
 255         DBG(1, "VBUS %s, devctl %02x "
 256                 /* otg %3x conf %08x prcm %08x */ "\n",
 257                 otg_state_string(musb),
 258                 musb_readb(musb->mregs, MUSB_DEVCTL));
 259 }
 260
 261 static int bfin_set_power(struct otg_transceiver *x, unsigned mA)
 262 {
 263         return 0;
 264 }
 265
 266 void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
 267 {
 268         if (is_host_enabled(musb))
 269                 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
 270 }
 271
 272 int musb_platform_get_vbus_status(struct musb *musb)
 273 {
 274         return 0;
 275 }
 276
 277 int musb_platform_set_mode(struct musb *musb, u8 musb_mode)
 278 {
 279         return -EIO;
 280 }
 281
 282 int __init musb_platform_init(struct musb *musb)
 283 {
 284
 285         /*
 286          * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
 287          * and OTG HOST modes, while rev 1.1 and greater require PE7 to
 288          * be low for DEVICE mode and high for HOST mode. We set it high
 289          * here because we are in host mode
 290          */
 291
 292         if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
 293                 printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d \n",
 294                         musb->config->gpio_vrsel);
 295                 return -ENODEV;
 296         }
 297         gpio_direction_output(musb->config->gpio_vrsel, 0);
 298
 299         usb_nop_xceiv_register();
 300         musb->xceiv = otg_get_transceiver();
 301         if (!musb->xceiv)
 302                 return -ENODEV;
 303
 304         if (ANOMALY_05000346) {
 305                 bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
 306                 SSYNC();
 307         }
 308
 309         if (ANOMALY_05000347) {
 310                 bfin_write_USB_APHY_CNTRL(0x0);
 311                 SSYNC();
 312         }
 313
 314         /* Configure PLL oscillator register */
 315         bfin_write_USB_PLLOSC_CTRL(0x30a8);
 316         SSYNC();
 317
 318         bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
 319         SSYNC();
 320
 321         bfin_write_USB_EP_NI0_RXMAXP(64);
 322         SSYNC();
 323
 324         bfin_write_USB_EP_NI0_TXMAXP(64);
 325         SSYNC();
 326
 327         /* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
 328         bfin_write_USB_GLOBINTR(0x7);
 329         SSYNC();
 330
 331         bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
 332                                 EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
 333                                 EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
 334                                 EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
 335                                 EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
 336         SSYNC();
 337
 338         if (is_host_enabled(musb)) {
 339                 musb->board_set_vbus = bfin_set_vbus;
 340                 setup_timer(&musb_conn_timer,
 341                         musb_conn_timer_handler, (unsigned long) musb);
 342         }
 343         if (is_peripheral_enabled(musb))
 344                 musb->xceiv->set_power = bfin_set_power;
 345
 346         musb->isr = blackfin_interrupt;
 347
 348         return 0;
 349 }
 350
 351 int musb_platform_suspend(struct musb *musb)
 352 {
 353         return 0;
 354 }
 355
 356 int musb_platform_resume(struct musb *musb)
 357 {
 358         return 0;
 359 }
 360
 361
 362 int musb_platform_exit(struct musb *musb)
 363 {
 364
 365         bfin_vbus_power(musb, 0 /*off*/, 1);
 366         gpio_free(musb->config->gpio_vrsel);
 367         musb_platform_suspend(musb);
 368
 369         return 0;
 370 }