2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/prefetch.h>
100 #include <linux/platform_device.h>
101 #include <linux/io.h>
102 #include <linux/dma-mapping.h>
104 #include "musb_core.h"
106 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
109 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
110 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
112 #define MUSB_VERSION "6.0"
114 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
116 #define MUSB_DRIVER_NAME "musb-hdrc"
117 const char musb_driver_name
[] = MUSB_DRIVER_NAME
;
119 MODULE_DESCRIPTION(DRIVER_INFO
);
120 MODULE_AUTHOR(DRIVER_AUTHOR
);
121 MODULE_LICENSE("GPL");
122 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME
);
125 /*-------------------------------------------------------------------------*/
127 static inline struct musb
*dev_to_musb(struct device
*dev
)
129 return dev_get_drvdata(dev
);
132 /*-------------------------------------------------------------------------*/
134 #ifndef CONFIG_BLACKFIN
135 static int musb_ulpi_read(struct usb_phy
*phy
, u32 offset
)
137 void __iomem
*addr
= phy
->io_priv
;
143 pm_runtime_get_sync(phy
->io_dev
);
145 /* Make sure the transceiver is not in low power mode */
146 power
= musb_readb(addr
, MUSB_POWER
);
147 power
&= ~MUSB_POWER_SUSPENDM
;
148 musb_writeb(addr
, MUSB_POWER
, power
);
150 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
151 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
154 musb_writeb(addr
, MUSB_ULPI_REG_ADDR
, (u8
)offset
);
155 musb_writeb(addr
, MUSB_ULPI_REG_CONTROL
,
156 MUSB_ULPI_REG_REQ
| MUSB_ULPI_RDN_WR
);
158 while (!(musb_readb(addr
, MUSB_ULPI_REG_CONTROL
)
159 & MUSB_ULPI_REG_CMPLT
)) {
167 r
= musb_readb(addr
, MUSB_ULPI_REG_CONTROL
);
168 r
&= ~MUSB_ULPI_REG_CMPLT
;
169 musb_writeb(addr
, MUSB_ULPI_REG_CONTROL
, r
);
171 ret
= musb_readb(addr
, MUSB_ULPI_REG_DATA
);
174 pm_runtime_put(phy
->io_dev
);
179 static int musb_ulpi_write(struct usb_phy
*phy
, u32 offset
, u32 data
)
181 void __iomem
*addr
= phy
->io_priv
;
187 pm_runtime_get_sync(phy
->io_dev
);
189 /* Make sure the transceiver is not in low power mode */
190 power
= musb_readb(addr
, MUSB_POWER
);
191 power
&= ~MUSB_POWER_SUSPENDM
;
192 musb_writeb(addr
, MUSB_POWER
, power
);
194 musb_writeb(addr
, MUSB_ULPI_REG_ADDR
, (u8
)offset
);
195 musb_writeb(addr
, MUSB_ULPI_REG_DATA
, (u8
)data
);
196 musb_writeb(addr
, MUSB_ULPI_REG_CONTROL
, MUSB_ULPI_REG_REQ
);
198 while (!(musb_readb(addr
, MUSB_ULPI_REG_CONTROL
)
199 & MUSB_ULPI_REG_CMPLT
)) {
207 r
= musb_readb(addr
, MUSB_ULPI_REG_CONTROL
);
208 r
&= ~MUSB_ULPI_REG_CMPLT
;
209 musb_writeb(addr
, MUSB_ULPI_REG_CONTROL
, r
);
212 pm_runtime_put(phy
->io_dev
);
217 #define musb_ulpi_read NULL
218 #define musb_ulpi_write NULL
221 static struct usb_phy_io_ops musb_ulpi_access
= {
222 .read
= musb_ulpi_read
,
223 .write
= musb_ulpi_write
,
226 /*-------------------------------------------------------------------------*/
228 #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
231 * Load an endpoint's FIFO
233 void musb_write_fifo(struct musb_hw_ep
*hw_ep
, u16 len
, const u8
*src
)
235 struct musb
*musb
= hw_ep
->musb
;
236 void __iomem
*fifo
= hw_ep
->fifo
;
238 if (unlikely(len
== 0))
243 dev_dbg(musb
->controller
, "%cX ep%d fifo %p count %d buf %p\n",
244 'T', hw_ep
->epnum
, fifo
, len
, src
);
246 /* we can't assume unaligned reads work */
247 if (likely((0x01 & (unsigned long) src
) == 0)) {
250 /* best case is 32bit-aligned source address */
251 if ((0x02 & (unsigned long) src
) == 0) {
253 iowrite32_rep(fifo
, src
+ index
, len
>> 2);
254 index
+= len
& ~0x03;
257 musb_writew(fifo
, 0, *(u16
*)&src
[index
]);
262 iowrite16_rep(fifo
, src
+ index
, len
>> 1);
263 index
+= len
& ~0x01;
267 musb_writeb(fifo
, 0, src
[index
]);
270 iowrite8_rep(fifo
, src
, len
);
274 #if !defined(CONFIG_USB_MUSB_AM35X)
276 * Unload an endpoint's FIFO
278 void musb_read_fifo(struct musb_hw_ep
*hw_ep
, u16 len
, u8
*dst
)
280 struct musb
*musb
= hw_ep
->musb
;
281 void __iomem
*fifo
= hw_ep
->fifo
;
283 if (unlikely(len
== 0))
286 dev_dbg(musb
->controller
, "%cX ep%d fifo %p count %d buf %p\n",
287 'R', hw_ep
->epnum
, fifo
, len
, dst
);
289 /* we can't assume unaligned writes work */
290 if (likely((0x01 & (unsigned long) dst
) == 0)) {
293 /* best case is 32bit-aligned destination address */
294 if ((0x02 & (unsigned long) dst
) == 0) {
296 ioread32_rep(fifo
, dst
, len
>> 2);
300 *(u16
*)&dst
[index
] = musb_readw(fifo
, 0);
305 ioread16_rep(fifo
, dst
, len
>> 1);
310 dst
[index
] = musb_readb(fifo
, 0);
313 ioread8_rep(fifo
, dst
, len
);
318 #endif /* normal PIO */
321 /*-------------------------------------------------------------------------*/
323 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
324 static const u8 musb_test_packet
[53] = {
325 /* implicit SYNC then DATA0 to start */
328 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
330 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
332 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
333 /* JJJJJJJKKKKKKK x8 */
334 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
336 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
337 /* JKKKKKKK x10, JK */
338 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
340 /* implicit CRC16 then EOP to end */
343 void musb_load_testpacket(struct musb
*musb
)
345 void __iomem
*regs
= musb
->endpoints
[0].regs
;
347 musb_ep_select(musb
->mregs
, 0);
348 musb_write_fifo(musb
->control_ep
,
349 sizeof(musb_test_packet
), musb_test_packet
);
350 musb_writew(regs
, MUSB_CSR0
, MUSB_CSR0_TXPKTRDY
);
353 /*-------------------------------------------------------------------------*/
356 * Handles OTG hnp timeouts, such as b_ase0_brst
358 static void musb_otg_timer_func(unsigned long data
)
360 struct musb
*musb
= (struct musb
*)data
;
363 spin_lock_irqsave(&musb
->lock
, flags
);
364 switch (musb
->xceiv
->state
) {
365 case OTG_STATE_B_WAIT_ACON
:
366 dev_dbg(musb
->controller
, "HNP: b_wait_acon timeout; back to b_peripheral\n");
367 musb_g_disconnect(musb
);
368 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
371 case OTG_STATE_A_SUSPEND
:
372 case OTG_STATE_A_WAIT_BCON
:
373 dev_dbg(musb
->controller
, "HNP: %s timeout\n",
374 usb_otg_state_string(musb
->xceiv
->state
));
375 musb_platform_set_vbus(musb
, 0);
376 musb
->xceiv
->state
= OTG_STATE_A_WAIT_VFALL
;
379 dev_dbg(musb
->controller
, "HNP: Unhandled mode %s\n",
380 usb_otg_state_string(musb
->xceiv
->state
));
382 spin_unlock_irqrestore(&musb
->lock
, flags
);
386 * Stops the HNP transition. Caller must take care of locking.
388 void musb_hnp_stop(struct musb
*musb
)
390 struct usb_hcd
*hcd
= musb
->hcd
;
391 void __iomem
*mbase
= musb
->mregs
;
394 dev_dbg(musb
->controller
, "HNP: stop from %s\n",
395 usb_otg_state_string(musb
->xceiv
->state
));
397 switch (musb
->xceiv
->state
) {
398 case OTG_STATE_A_PERIPHERAL
:
399 musb_g_disconnect(musb
);
400 dev_dbg(musb
->controller
, "HNP: back to %s\n",
401 usb_otg_state_string(musb
->xceiv
->state
));
403 case OTG_STATE_B_HOST
:
404 dev_dbg(musb
->controller
, "HNP: Disabling HR\n");
406 hcd
->self
.is_b_host
= 0;
407 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
409 reg
= musb_readb(mbase
, MUSB_POWER
);
410 reg
|= MUSB_POWER_SUSPENDM
;
411 musb_writeb(mbase
, MUSB_POWER
, reg
);
412 /* REVISIT: Start SESSION_REQUEST here? */
415 dev_dbg(musb
->controller
, "HNP: Stopping in unknown state %s\n",
416 usb_otg_state_string(musb
->xceiv
->state
));
420 * When returning to A state after HNP, avoid hub_port_rebounce(),
421 * which cause occasional OPT A "Did not receive reset after connect"
424 musb
->port1_status
&= ~(USB_PORT_STAT_C_CONNECTION
<< 16);
428 * Interrupt Service Routine to record USB "global" interrupts.
429 * Since these do not happen often and signify things of
430 * paramount importance, it seems OK to check them individually;
431 * the order of the tests is specified in the manual
433 * @param musb instance pointer
434 * @param int_usb register contents
439 static irqreturn_t
musb_stage0_irq(struct musb
*musb
, u8 int_usb
,
442 struct usb_otg
*otg
= musb
->xceiv
->otg
;
443 irqreturn_t handled
= IRQ_NONE
;
445 dev_dbg(musb
->controller
, "<== DevCtl=%02x, int_usb=0x%x\n", devctl
,
448 /* in host mode, the peripheral may issue remote wakeup.
449 * in peripheral mode, the host may resume the link.
450 * spurious RESUME irqs happen too, paired with SUSPEND.
452 if (int_usb
& MUSB_INTR_RESUME
) {
453 handled
= IRQ_HANDLED
;
454 dev_dbg(musb
->controller
, "RESUME (%s)\n", usb_otg_state_string(musb
->xceiv
->state
));
456 if (devctl
& MUSB_DEVCTL_HM
) {
457 void __iomem
*mbase
= musb
->mregs
;
460 switch (musb
->xceiv
->state
) {
461 case OTG_STATE_A_SUSPEND
:
462 /* remote wakeup? later, GetPortStatus
463 * will stop RESUME signaling
466 power
= musb_readb(musb
->mregs
, MUSB_POWER
);
467 if (power
& MUSB_POWER_SUSPENDM
) {
469 musb
->int_usb
&= ~MUSB_INTR_SUSPEND
;
470 dev_dbg(musb
->controller
, "Spurious SUSPENDM\n");
474 power
&= ~MUSB_POWER_SUSPENDM
;
475 musb_writeb(mbase
, MUSB_POWER
,
476 power
| MUSB_POWER_RESUME
);
478 musb
->port1_status
|=
479 (USB_PORT_STAT_C_SUSPEND
<< 16)
480 | MUSB_PORT_STAT_RESUME
;
481 musb
->rh_timer
= jiffies
482 + msecs_to_jiffies(20);
484 musb
->xceiv
->state
= OTG_STATE_A_HOST
;
486 musb_host_resume_root_hub(musb
);
488 case OTG_STATE_B_WAIT_ACON
:
489 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
494 WARNING("bogus %s RESUME (%s)\n",
496 usb_otg_state_string(musb
->xceiv
->state
));
499 switch (musb
->xceiv
->state
) {
500 case OTG_STATE_A_SUSPEND
:
501 /* possibly DISCONNECT is upcoming */
502 musb
->xceiv
->state
= OTG_STATE_A_HOST
;
503 musb_host_resume_root_hub(musb
);
505 case OTG_STATE_B_WAIT_ACON
:
506 case OTG_STATE_B_PERIPHERAL
:
507 /* disconnect while suspended? we may
508 * not get a disconnect irq...
510 if ((devctl
& MUSB_DEVCTL_VBUS
)
511 != (3 << MUSB_DEVCTL_VBUS_SHIFT
)
513 musb
->int_usb
|= MUSB_INTR_DISCONNECT
;
514 musb
->int_usb
&= ~MUSB_INTR_SUSPEND
;
519 case OTG_STATE_B_IDLE
:
520 musb
->int_usb
&= ~MUSB_INTR_SUSPEND
;
523 WARNING("bogus %s RESUME (%s)\n",
525 usb_otg_state_string(musb
->xceiv
->state
));
530 /* see manual for the order of the tests */
531 if (int_usb
& MUSB_INTR_SESSREQ
) {
532 void __iomem
*mbase
= musb
->mregs
;
534 if ((devctl
& MUSB_DEVCTL_VBUS
) == MUSB_DEVCTL_VBUS
535 && (devctl
& MUSB_DEVCTL_BDEVICE
)) {
536 dev_dbg(musb
->controller
, "SessReq while on B state\n");
540 dev_dbg(musb
->controller
, "SESSION_REQUEST (%s)\n",
541 usb_otg_state_string(musb
->xceiv
->state
));
543 /* IRQ arrives from ID pin sense or (later, if VBUS power
544 * is removed) SRP. responses are time critical:
545 * - turn on VBUS (with silicon-specific mechanism)
546 * - go through A_WAIT_VRISE
547 * - ... to A_WAIT_BCON.
548 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
550 musb_writeb(mbase
, MUSB_DEVCTL
, MUSB_DEVCTL_SESSION
);
551 musb
->ep0_stage
= MUSB_EP0_START
;
552 musb
->xceiv
->state
= OTG_STATE_A_IDLE
;
554 musb_platform_set_vbus(musb
, 1);
556 handled
= IRQ_HANDLED
;
559 if (int_usb
& MUSB_INTR_VBUSERROR
) {
562 /* During connection as an A-Device, we may see a short
563 * current spikes causing voltage drop, because of cable
564 * and peripheral capacitance combined with vbus draw.
565 * (So: less common with truly self-powered devices, where
566 * vbus doesn't act like a power supply.)
568 * Such spikes are short; usually less than ~500 usec, max
569 * of ~2 msec. That is, they're not sustained overcurrent
570 * errors, though they're reported using VBUSERROR irqs.
572 * Workarounds: (a) hardware: use self powered devices.
573 * (b) software: ignore non-repeated VBUS errors.
575 * REVISIT: do delays from lots of DEBUG_KERNEL checks
576 * make trouble here, keeping VBUS < 4.4V ?
578 switch (musb
->xceiv
->state
) {
579 case OTG_STATE_A_HOST
:
580 /* recovery is dicey once we've gotten past the
581 * initial stages of enumeration, but if VBUS
582 * stayed ok at the other end of the link, and
583 * another reset is due (at least for high speed,
584 * to redo the chirp etc), it might work OK...
586 case OTG_STATE_A_WAIT_BCON
:
587 case OTG_STATE_A_WAIT_VRISE
:
588 if (musb
->vbuserr_retry
) {
589 void __iomem
*mbase
= musb
->mregs
;
591 musb
->vbuserr_retry
--;
593 devctl
|= MUSB_DEVCTL_SESSION
;
594 musb_writeb(mbase
, MUSB_DEVCTL
, devctl
);
596 musb
->port1_status
|=
597 USB_PORT_STAT_OVERCURRENT
598 | (USB_PORT_STAT_C_OVERCURRENT
<< 16);
605 dev_printk(ignore
? KERN_DEBUG
: KERN_ERR
, musb
->controller
,
606 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
607 usb_otg_state_string(musb
->xceiv
->state
),
610 switch (devctl
& MUSB_DEVCTL_VBUS
) {
611 case 0 << MUSB_DEVCTL_VBUS_SHIFT
:
612 s
= "<SessEnd"; break;
613 case 1 << MUSB_DEVCTL_VBUS_SHIFT
:
614 s
= "<AValid"; break;
615 case 2 << MUSB_DEVCTL_VBUS_SHIFT
:
616 s
= "<VBusValid"; break;
617 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
621 VBUSERR_RETRY_COUNT
- musb
->vbuserr_retry
,
624 /* go through A_WAIT_VFALL then start a new session */
626 musb_platform_set_vbus(musb
, 0);
627 handled
= IRQ_HANDLED
;
630 if (int_usb
& MUSB_INTR_SUSPEND
) {
631 dev_dbg(musb
->controller
, "SUSPEND (%s) devctl %02x\n",
632 usb_otg_state_string(musb
->xceiv
->state
), devctl
);
633 handled
= IRQ_HANDLED
;
635 switch (musb
->xceiv
->state
) {
636 case OTG_STATE_A_PERIPHERAL
:
637 /* We also come here if the cable is removed, since
638 * this silicon doesn't report ID-no-longer-grounded.
640 * We depend on T(a_wait_bcon) to shut us down, and
641 * hope users don't do anything dicey during this
642 * undesired detour through A_WAIT_BCON.
645 musb_host_resume_root_hub(musb
);
646 musb_root_disconnect(musb
);
647 musb_platform_try_idle(musb
, jiffies
648 + msecs_to_jiffies(musb
->a_wait_bcon
649 ? : OTG_TIME_A_WAIT_BCON
));
652 case OTG_STATE_B_IDLE
:
653 if (!musb
->is_active
)
655 case OTG_STATE_B_PERIPHERAL
:
656 musb_g_suspend(musb
);
657 musb
->is_active
= otg
->gadget
->b_hnp_enable
;
658 if (musb
->is_active
) {
659 musb
->xceiv
->state
= OTG_STATE_B_WAIT_ACON
;
660 dev_dbg(musb
->controller
, "HNP: Setting timer for b_ase0_brst\n");
661 mod_timer(&musb
->otg_timer
, jiffies
663 OTG_TIME_B_ASE0_BRST
));
666 case OTG_STATE_A_WAIT_BCON
:
667 if (musb
->a_wait_bcon
!= 0)
668 musb_platform_try_idle(musb
, jiffies
669 + msecs_to_jiffies(musb
->a_wait_bcon
));
671 case OTG_STATE_A_HOST
:
672 musb
->xceiv
->state
= OTG_STATE_A_SUSPEND
;
673 musb
->is_active
= otg
->host
->b_hnp_enable
;
675 case OTG_STATE_B_HOST
:
676 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
677 dev_dbg(musb
->controller
, "REVISIT: SUSPEND as B_HOST\n");
680 /* "should not happen" */
686 if (int_usb
& MUSB_INTR_CONNECT
) {
687 struct usb_hcd
*hcd
= musb
->hcd
;
689 handled
= IRQ_HANDLED
;
692 musb
->ep0_stage
= MUSB_EP0_START
;
694 /* flush endpoints when transitioning from Device Mode */
695 if (is_peripheral_active(musb
)) {
696 /* REVISIT HNP; just force disconnect */
698 musb
->intrtxe
= musb
->epmask
;
699 musb_writew(musb
->mregs
, MUSB_INTRTXE
, musb
->intrtxe
);
700 musb
->intrrxe
= musb
->epmask
& 0xfffe;
701 musb_writew(musb
->mregs
, MUSB_INTRRXE
, musb
->intrrxe
);
702 musb_writeb(musb
->mregs
, MUSB_INTRUSBE
, 0xf7);
703 musb
->port1_status
&= ~(USB_PORT_STAT_LOW_SPEED
704 |USB_PORT_STAT_HIGH_SPEED
705 |USB_PORT_STAT_ENABLE
707 musb
->port1_status
|= USB_PORT_STAT_CONNECTION
708 |(USB_PORT_STAT_C_CONNECTION
<< 16);
710 /* high vs full speed is just a guess until after reset */
711 if (devctl
& MUSB_DEVCTL_LSDEV
)
712 musb
->port1_status
|= USB_PORT_STAT_LOW_SPEED
;
714 /* indicate new connection to OTG machine */
715 switch (musb
->xceiv
->state
) {
716 case OTG_STATE_B_PERIPHERAL
:
717 if (int_usb
& MUSB_INTR_SUSPEND
) {
718 dev_dbg(musb
->controller
, "HNP: SUSPEND+CONNECT, now b_host\n");
719 int_usb
&= ~MUSB_INTR_SUSPEND
;
722 dev_dbg(musb
->controller
, "CONNECT as b_peripheral???\n");
724 case OTG_STATE_B_WAIT_ACON
:
725 dev_dbg(musb
->controller
, "HNP: CONNECT, now b_host\n");
727 musb
->xceiv
->state
= OTG_STATE_B_HOST
;
729 musb
->hcd
->self
.is_b_host
= 1;
730 del_timer(&musb
->otg_timer
);
733 if ((devctl
& MUSB_DEVCTL_VBUS
)
734 == (3 << MUSB_DEVCTL_VBUS_SHIFT
)) {
735 musb
->xceiv
->state
= OTG_STATE_A_HOST
;
737 hcd
->self
.is_b_host
= 0;
742 musb_host_poke_root_hub(musb
);
744 dev_dbg(musb
->controller
, "CONNECT (%s) devctl %02x\n",
745 usb_otg_state_string(musb
->xceiv
->state
), devctl
);
748 if (int_usb
& MUSB_INTR_DISCONNECT
) {
749 dev_dbg(musb
->controller
, "DISCONNECT (%s) as %s, devctl %02x\n",
750 usb_otg_state_string(musb
->xceiv
->state
),
751 MUSB_MODE(musb
), devctl
);
752 handled
= IRQ_HANDLED
;
754 switch (musb
->xceiv
->state
) {
755 case OTG_STATE_A_HOST
:
756 case OTG_STATE_A_SUSPEND
:
757 musb_host_resume_root_hub(musb
);
758 musb_root_disconnect(musb
);
759 if (musb
->a_wait_bcon
!= 0)
760 musb_platform_try_idle(musb
, jiffies
761 + msecs_to_jiffies(musb
->a_wait_bcon
));
763 case OTG_STATE_B_HOST
:
764 /* REVISIT this behaves for "real disconnect"
765 * cases; make sure the other transitions from
766 * from B_HOST act right too. The B_HOST code
767 * in hnp_stop() is currently not used...
769 musb_root_disconnect(musb
);
771 musb
->hcd
->self
.is_b_host
= 0;
772 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
774 musb_g_disconnect(musb
);
776 case OTG_STATE_A_PERIPHERAL
:
778 musb_root_disconnect(musb
);
780 case OTG_STATE_B_WAIT_ACON
:
782 case OTG_STATE_B_PERIPHERAL
:
783 case OTG_STATE_B_IDLE
:
784 musb_g_disconnect(musb
);
787 WARNING("unhandled DISCONNECT transition (%s)\n",
788 usb_otg_state_string(musb
->xceiv
->state
));
793 /* mentor saves a bit: bus reset and babble share the same irq.
794 * only host sees babble; only peripheral sees bus reset.
796 if (int_usb
& MUSB_INTR_RESET
) {
797 handled
= IRQ_HANDLED
;
798 if ((devctl
& MUSB_DEVCTL_HM
) != 0) {
800 * Looks like non-HS BABBLE can be ignored, but
801 * HS BABBLE is an error condition. For HS the solution
802 * is to avoid babble in the first place and fix what
803 * caused BABBLE. When HS BABBLE happens we can only
806 if (devctl
& (MUSB_DEVCTL_FSDEV
| MUSB_DEVCTL_LSDEV
))
807 dev_dbg(musb
->controller
, "BABBLE devctl: %02x\n", devctl
);
809 ERR("Stopping host session -- babble\n");
810 musb_writeb(musb
->mregs
, MUSB_DEVCTL
, 0);
813 dev_dbg(musb
->controller
, "BUS RESET as %s\n",
814 usb_otg_state_string(musb
->xceiv
->state
));
815 switch (musb
->xceiv
->state
) {
816 case OTG_STATE_A_SUSPEND
:
819 case OTG_STATE_A_WAIT_BCON
: /* OPT TD.4.7-900ms */
820 /* never use invalid T(a_wait_bcon) */
821 dev_dbg(musb
->controller
, "HNP: in %s, %d msec timeout\n",
822 usb_otg_state_string(musb
->xceiv
->state
),
824 mod_timer(&musb
->otg_timer
, jiffies
825 + msecs_to_jiffies(TA_WAIT_BCON(musb
)));
827 case OTG_STATE_A_PERIPHERAL
:
828 del_timer(&musb
->otg_timer
);
831 case OTG_STATE_B_WAIT_ACON
:
832 dev_dbg(musb
->controller
, "HNP: RESET (%s), to b_peripheral\n",
833 usb_otg_state_string(musb
->xceiv
->state
));
834 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
837 case OTG_STATE_B_IDLE
:
838 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
840 case OTG_STATE_B_PERIPHERAL
:
844 dev_dbg(musb
->controller
, "Unhandled BUS RESET as %s\n",
845 usb_otg_state_string(musb
->xceiv
->state
));
851 /* REVISIT ... this would be for multiplexing periodic endpoints, or
852 * supporting transfer phasing to prevent exceeding ISO bandwidth
853 * limits of a given frame or microframe.
855 * It's not needed for peripheral side, which dedicates endpoints;
856 * though it _might_ use SOF irqs for other purposes.
858 * And it's not currently needed for host side, which also dedicates
859 * endpoints, relies on TX/RX interval registers, and isn't claimed
860 * to support ISO transfers yet.
862 if (int_usb
& MUSB_INTR_SOF
) {
863 void __iomem
*mbase
= musb
->mregs
;
864 struct musb_hw_ep
*ep
;
868 dev_dbg(musb
->controller
, "START_OF_FRAME\n");
869 handled
= IRQ_HANDLED
;
871 /* start any periodic Tx transfers waiting for current frame */
872 frame
= musb_readw(mbase
, MUSB_FRAME
);
873 ep
= musb
->endpoints
;
874 for (epnum
= 1; (epnum
< musb
->nr_endpoints
)
875 && (musb
->epmask
>= (1 << epnum
));
878 * FIXME handle framecounter wraps (12 bits)
879 * eliminate duplicated StartUrb logic
881 if (ep
->dwWaitFrame
>= frame
) {
883 pr_debug("SOF --> periodic TX%s on %d\n",
884 ep
->tx_channel
? " DMA" : "",
887 musb_h_tx_start(musb
, epnum
);
889 cppi_hostdma_start(musb
, epnum
);
891 } /* end of for loop */
895 schedule_work(&musb
->irq_work
);
900 /*-------------------------------------------------------------------------*/
902 static void musb_generic_disable(struct musb
*musb
)
904 void __iomem
*mbase
= musb
->mregs
;
907 /* disable interrupts */
908 musb_writeb(mbase
, MUSB_INTRUSBE
, 0);
910 musb_writew(mbase
, MUSB_INTRTXE
, 0);
912 musb_writew(mbase
, MUSB_INTRRXE
, 0);
915 musb_writeb(mbase
, MUSB_DEVCTL
, 0);
917 /* flush pending interrupts */
918 temp
= musb_readb(mbase
, MUSB_INTRUSB
);
919 temp
= musb_readw(mbase
, MUSB_INTRTX
);
920 temp
= musb_readw(mbase
, MUSB_INTRRX
);
925 * Program the HDRC to start (enable interrupts, dma, etc.).
927 void musb_start(struct musb
*musb
)
929 void __iomem
*regs
= musb
->mregs
;
930 u8 devctl
= musb_readb(regs
, MUSB_DEVCTL
);
932 dev_dbg(musb
->controller
, "<== devctl %02x\n", devctl
);
934 /* Set INT enable registers, enable interrupts */
935 musb
->intrtxe
= musb
->epmask
;
936 musb_writew(regs
, MUSB_INTRTXE
, musb
->intrtxe
);
937 musb
->intrrxe
= musb
->epmask
& 0xfffe;
938 musb_writew(regs
, MUSB_INTRRXE
, musb
->intrrxe
);
939 musb_writeb(regs
, MUSB_INTRUSBE
, 0xf7);
941 musb_writeb(regs
, MUSB_TESTMODE
, 0);
943 /* put into basic highspeed mode and start session */
944 musb_writeb(regs
, MUSB_POWER
, MUSB_POWER_ISOUPDATE
946 /* ENSUSPEND wedges tusb */
947 /* | MUSB_POWER_ENSUSPEND */
951 devctl
= musb_readb(regs
, MUSB_DEVCTL
);
952 devctl
&= ~MUSB_DEVCTL_SESSION
;
954 /* session started after:
955 * (a) ID-grounded irq, host mode;
956 * (b) vbus present/connect IRQ, peripheral mode;
957 * (c) peripheral initiates, using SRP
959 if (musb
->port_mode
!= MUSB_PORT_MODE_HOST
&&
960 (devctl
& MUSB_DEVCTL_VBUS
) == MUSB_DEVCTL_VBUS
) {
963 devctl
|= MUSB_DEVCTL_SESSION
;
966 musb_platform_enable(musb
);
967 musb_writeb(regs
, MUSB_DEVCTL
, devctl
);
971 * Make the HDRC stop (disable interrupts, etc.);
972 * reversible by musb_start
973 * called on gadget driver unregister
974 * with controller locked, irqs blocked
975 * acts as a NOP unless some role activated the hardware
977 void musb_stop(struct musb
*musb
)
979 /* stop IRQs, timers, ... */
980 musb_platform_disable(musb
);
981 musb_generic_disable(musb
);
982 dev_dbg(musb
->controller
, "HDRC disabled\n");
985 * - mark host and/or peripheral drivers unusable/inactive
986 * - disable DMA (and enable it in HdrcStart)
987 * - make sure we can musb_start() after musb_stop(); with
988 * OTG mode, gadget driver module rmmod/modprobe cycles that
991 musb_platform_try_idle(musb
, 0);
994 static void musb_shutdown(struct platform_device
*pdev
)
996 struct musb
*musb
= dev_to_musb(&pdev
->dev
);
999 pm_runtime_get_sync(musb
->controller
);
1001 musb_host_cleanup(musb
);
1002 musb_gadget_cleanup(musb
);
1004 spin_lock_irqsave(&musb
->lock
, flags
);
1005 musb_platform_disable(musb
);
1006 musb_generic_disable(musb
);
1007 spin_unlock_irqrestore(&musb
->lock
, flags
);
1009 musb_writeb(musb
->mregs
, MUSB_DEVCTL
, 0);
1010 musb_platform_exit(musb
);
1012 pm_runtime_put(musb
->controller
);
1013 /* FIXME power down */
1017 /*-------------------------------------------------------------------------*/
1020 * The silicon either has hard-wired endpoint configurations, or else
1021 * "dynamic fifo" sizing. The driver has support for both, though at this
1022 * writing only the dynamic sizing is very well tested. Since we switched
1023 * away from compile-time hardware parameters, we can no longer rely on
1024 * dead code elimination to leave only the relevant one in the object file.
1026 * We don't currently use dynamic fifo setup capability to do anything
1027 * more than selecting one of a bunch of predefined configurations.
1029 #if defined(CONFIG_USB_MUSB_TUSB6010) \
1030 || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \
1031 || defined(CONFIG_USB_MUSB_OMAP2PLUS) \
1032 || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \
1033 || defined(CONFIG_USB_MUSB_AM35X) \
1034 || defined(CONFIG_USB_MUSB_AM35X_MODULE) \
1035 || defined(CONFIG_USB_MUSB_DSPS) \
1036 || defined(CONFIG_USB_MUSB_DSPS_MODULE)
1037 static ushort fifo_mode
= 4;
1038 #elif defined(CONFIG_USB_MUSB_UX500) \
1039 || defined(CONFIG_USB_MUSB_UX500_MODULE)
1040 static ushort fifo_mode
= 5;
1042 static ushort fifo_mode
= 2;
1045 /* "modprobe ... fifo_mode=1" etc */
1046 module_param(fifo_mode
, ushort
, 0);
1047 MODULE_PARM_DESC(fifo_mode
, "initial endpoint configuration");
1050 * tables defining fifo_mode values. define more if you like.
1051 * for host side, make sure both halves of ep1 are set up.
1054 /* mode 0 - fits in 2KB */
1055 static struct musb_fifo_cfg mode_0_cfg
[] = {
1056 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, },
1057 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, },
1058 { .hw_ep_num
= 2, .style
= FIFO_RXTX
, .maxpacket
= 512, },
1059 { .hw_ep_num
= 3, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1060 { .hw_ep_num
= 4, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1063 /* mode 1 - fits in 4KB */
1064 static struct musb_fifo_cfg mode_1_cfg
[] = {
1065 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, .mode
= BUF_DOUBLE
, },
1066 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, .mode
= BUF_DOUBLE
, },
1067 { .hw_ep_num
= 2, .style
= FIFO_RXTX
, .maxpacket
= 512, .mode
= BUF_DOUBLE
, },
1068 { .hw_ep_num
= 3, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1069 { .hw_ep_num
= 4, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1072 /* mode 2 - fits in 4KB */
1073 static struct musb_fifo_cfg mode_2_cfg
[] = {
1074 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, },
1075 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, },
1076 { .hw_ep_num
= 2, .style
= FIFO_TX
, .maxpacket
= 512, },
1077 { .hw_ep_num
= 2, .style
= FIFO_RX
, .maxpacket
= 512, },
1078 { .hw_ep_num
= 3, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1079 { .hw_ep_num
= 4, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1082 /* mode 3 - fits in 4KB */
1083 static struct musb_fifo_cfg mode_3_cfg
[] = {
1084 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, .mode
= BUF_DOUBLE
, },
1085 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, .mode
= BUF_DOUBLE
, },
1086 { .hw_ep_num
= 2, .style
= FIFO_TX
, .maxpacket
= 512, },
1087 { .hw_ep_num
= 2, .style
= FIFO_RX
, .maxpacket
= 512, },
1088 { .hw_ep_num
= 3, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1089 { .hw_ep_num
= 4, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1092 /* mode 4 - fits in 16KB */
1093 static struct musb_fifo_cfg mode_4_cfg
[] = {
1094 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, },
1095 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, },
1096 { .hw_ep_num
= 2, .style
= FIFO_TX
, .maxpacket
= 512, },
1097 { .hw_ep_num
= 2, .style
= FIFO_RX
, .maxpacket
= 512, },
1098 { .hw_ep_num
= 3, .style
= FIFO_TX
, .maxpacket
= 512, },
1099 { .hw_ep_num
= 3, .style
= FIFO_RX
, .maxpacket
= 512, },
1100 { .hw_ep_num
= 4, .style
= FIFO_TX
, .maxpacket
= 512, },
1101 { .hw_ep_num
= 4, .style
= FIFO_RX
, .maxpacket
= 512, },
1102 { .hw_ep_num
= 5, .style
= FIFO_TX
, .maxpacket
= 512, },
1103 { .hw_ep_num
= 5, .style
= FIFO_RX
, .maxpacket
= 512, },
1104 { .hw_ep_num
= 6, .style
= FIFO_TX
, .maxpacket
= 512, },
1105 { .hw_ep_num
= 6, .style
= FIFO_RX
, .maxpacket
= 512, },
1106 { .hw_ep_num
= 7, .style
= FIFO_TX
, .maxpacket
= 512, },
1107 { .hw_ep_num
= 7, .style
= FIFO_RX
, .maxpacket
= 512, },
1108 { .hw_ep_num
= 8, .style
= FIFO_TX
, .maxpacket
= 512, },
1109 { .hw_ep_num
= 8, .style
= FIFO_RX
, .maxpacket
= 512, },
1110 { .hw_ep_num
= 9, .style
= FIFO_TX
, .maxpacket
= 512, },
1111 { .hw_ep_num
= 9, .style
= FIFO_RX
, .maxpacket
= 512, },
1112 { .hw_ep_num
= 10, .style
= FIFO_TX
, .maxpacket
= 256, },
1113 { .hw_ep_num
= 10, .style
= FIFO_RX
, .maxpacket
= 64, },
1114 { .hw_ep_num
= 11, .style
= FIFO_TX
, .maxpacket
= 256, },
1115 { .hw_ep_num
= 11, .style
= FIFO_RX
, .maxpacket
= 64, },
1116 { .hw_ep_num
= 12, .style
= FIFO_TX
, .maxpacket
= 256, },
1117 { .hw_ep_num
= 12, .style
= FIFO_RX
, .maxpacket
= 64, },
1118 { .hw_ep_num
= 13, .style
= FIFO_RXTX
, .maxpacket
= 4096, },
1119 { .hw_ep_num
= 14, .style
= FIFO_RXTX
, .maxpacket
= 1024, },
1120 { .hw_ep_num
= 15, .style
= FIFO_RXTX
, .maxpacket
= 1024, },
1123 /* mode 5 - fits in 8KB */
1124 static struct musb_fifo_cfg mode_5_cfg
[] = {
1125 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, },
1126 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, },
1127 { .hw_ep_num
= 2, .style
= FIFO_TX
, .maxpacket
= 512, },
1128 { .hw_ep_num
= 2, .style
= FIFO_RX
, .maxpacket
= 512, },
1129 { .hw_ep_num
= 3, .style
= FIFO_TX
, .maxpacket
= 512, },
1130 { .hw_ep_num
= 3, .style
= FIFO_RX
, .maxpacket
= 512, },
1131 { .hw_ep_num
= 4, .style
= FIFO_TX
, .maxpacket
= 512, },
1132 { .hw_ep_num
= 4, .style
= FIFO_RX
, .maxpacket
= 512, },
1133 { .hw_ep_num
= 5, .style
= FIFO_TX
, .maxpacket
= 512, },
1134 { .hw_ep_num
= 5, .style
= FIFO_RX
, .maxpacket
= 512, },
1135 { .hw_ep_num
= 6, .style
= FIFO_TX
, .maxpacket
= 32, },
1136 { .hw_ep_num
= 6, .style
= FIFO_RX
, .maxpacket
= 32, },
1137 { .hw_ep_num
= 7, .style
= FIFO_TX
, .maxpacket
= 32, },
1138 { .hw_ep_num
= 7, .style
= FIFO_RX
, .maxpacket
= 32, },
1139 { .hw_ep_num
= 8, .style
= FIFO_TX
, .maxpacket
= 32, },
1140 { .hw_ep_num
= 8, .style
= FIFO_RX
, .maxpacket
= 32, },
1141 { .hw_ep_num
= 9, .style
= FIFO_TX
, .maxpacket
= 32, },
1142 { .hw_ep_num
= 9, .style
= FIFO_RX
, .maxpacket
= 32, },
1143 { .hw_ep_num
= 10, .style
= FIFO_TX
, .maxpacket
= 32, },
1144 { .hw_ep_num
= 10, .style
= FIFO_RX
, .maxpacket
= 32, },
1145 { .hw_ep_num
= 11, .style
= FIFO_TX
, .maxpacket
= 32, },
1146 { .hw_ep_num
= 11, .style
= FIFO_RX
, .maxpacket
= 32, },
1147 { .hw_ep_num
= 12, .style
= FIFO_TX
, .maxpacket
= 32, },
1148 { .hw_ep_num
= 12, .style
= FIFO_RX
, .maxpacket
= 32, },
1149 { .hw_ep_num
= 13, .style
= FIFO_RXTX
, .maxpacket
= 512, },
1150 { .hw_ep_num
= 14, .style
= FIFO_RXTX
, .maxpacket
= 1024, },
1151 { .hw_ep_num
= 15, .style
= FIFO_RXTX
, .maxpacket
= 1024, },
1155 * configure a fifo; for non-shared endpoints, this may be called
1156 * once for a tx fifo and once for an rx fifo.
1158 * returns negative errno or offset for next fifo.
1161 fifo_setup(struct musb
*musb
, struct musb_hw_ep
*hw_ep
,
1162 const struct musb_fifo_cfg
*cfg
, u16 offset
)
1164 void __iomem
*mbase
= musb
->mregs
;
1166 u16 maxpacket
= cfg
->maxpacket
;
1167 u16 c_off
= offset
>> 3;
1170 /* expect hw_ep has already been zero-initialized */
1172 size
= ffs(max(maxpacket
, (u16
) 8)) - 1;
1173 maxpacket
= 1 << size
;
1176 if (cfg
->mode
== BUF_DOUBLE
) {
1177 if ((offset
+ (maxpacket
<< 1)) >
1178 (1 << (musb
->config
->ram_bits
+ 2)))
1180 c_size
|= MUSB_FIFOSZ_DPB
;
1182 if ((offset
+ maxpacket
) > (1 << (musb
->config
->ram_bits
+ 2)))
1186 /* configure the FIFO */
1187 musb_writeb(mbase
, MUSB_INDEX
, hw_ep
->epnum
);
1189 /* EP0 reserved endpoint for control, bidirectional;
1190 * EP1 reserved for bulk, two unidirection halves.
1192 if (hw_ep
->epnum
== 1)
1193 musb
->bulk_ep
= hw_ep
;
1194 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1195 switch (cfg
->style
) {
1197 musb_write_txfifosz(mbase
, c_size
);
1198 musb_write_txfifoadd(mbase
, c_off
);
1199 hw_ep
->tx_double_buffered
= !!(c_size
& MUSB_FIFOSZ_DPB
);
1200 hw_ep
->max_packet_sz_tx
= maxpacket
;
1203 musb_write_rxfifosz(mbase
, c_size
);
1204 musb_write_rxfifoadd(mbase
, c_off
);
1205 hw_ep
->rx_double_buffered
= !!(c_size
& MUSB_FIFOSZ_DPB
);
1206 hw_ep
->max_packet_sz_rx
= maxpacket
;
1209 musb_write_txfifosz(mbase
, c_size
);
1210 musb_write_txfifoadd(mbase
, c_off
);
1211 hw_ep
->rx_double_buffered
= !!(c_size
& MUSB_FIFOSZ_DPB
);
1212 hw_ep
->max_packet_sz_rx
= maxpacket
;
1214 musb_write_rxfifosz(mbase
, c_size
);
1215 musb_write_rxfifoadd(mbase
, c_off
);
1216 hw_ep
->tx_double_buffered
= hw_ep
->rx_double_buffered
;
1217 hw_ep
->max_packet_sz_tx
= maxpacket
;
1219 hw_ep
->is_shared_fifo
= true;
1223 /* NOTE rx and tx endpoint irqs aren't managed separately,
1224 * which happens to be ok
1226 musb
->epmask
|= (1 << hw_ep
->epnum
);
1228 return offset
+ (maxpacket
<< ((c_size
& MUSB_FIFOSZ_DPB
) ? 1 : 0));
1231 static struct musb_fifo_cfg ep0_cfg
= {
1232 .style
= FIFO_RXTX
, .maxpacket
= 64,
1235 static int ep_config_from_table(struct musb
*musb
)
1237 const struct musb_fifo_cfg
*cfg
;
1240 struct musb_hw_ep
*hw_ep
= musb
->endpoints
;
1242 if (musb
->config
->fifo_cfg
) {
1243 cfg
= musb
->config
->fifo_cfg
;
1244 n
= musb
->config
->fifo_cfg_size
;
1248 switch (fifo_mode
) {
1254 n
= ARRAY_SIZE(mode_0_cfg
);
1258 n
= ARRAY_SIZE(mode_1_cfg
);
1262 n
= ARRAY_SIZE(mode_2_cfg
);
1266 n
= ARRAY_SIZE(mode_3_cfg
);
1270 n
= ARRAY_SIZE(mode_4_cfg
);
1274 n
= ARRAY_SIZE(mode_5_cfg
);
1278 printk(KERN_DEBUG
"%s: setup fifo_mode %d\n",
1279 musb_driver_name
, fifo_mode
);
1283 offset
= fifo_setup(musb
, hw_ep
, &ep0_cfg
, 0);
1284 /* assert(offset > 0) */
1286 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1287 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1290 for (i
= 0; i
< n
; i
++) {
1291 u8 epn
= cfg
->hw_ep_num
;
1293 if (epn
>= musb
->config
->num_eps
) {
1294 pr_debug("%s: invalid ep %d\n",
1295 musb_driver_name
, epn
);
1298 offset
= fifo_setup(musb
, hw_ep
+ epn
, cfg
++, offset
);
1300 pr_debug("%s: mem overrun, ep %d\n",
1301 musb_driver_name
, epn
);
1305 musb
->nr_endpoints
= max(epn
, musb
->nr_endpoints
);
1308 printk(KERN_DEBUG
"%s: %d/%d max ep, %d/%d memory\n",
1310 n
+ 1, musb
->config
->num_eps
* 2 - 1,
1311 offset
, (1 << (musb
->config
->ram_bits
+ 2)));
1313 if (!musb
->bulk_ep
) {
1314 pr_debug("%s: missing bulk\n", musb_driver_name
);
1323 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1324 * @param musb the controller
1326 static int ep_config_from_hw(struct musb
*musb
)
1329 struct musb_hw_ep
*hw_ep
;
1330 void __iomem
*mbase
= musb
->mregs
;
1333 dev_dbg(musb
->controller
, "<== static silicon ep config\n");
1335 /* FIXME pick up ep0 maxpacket size */
1337 for (epnum
= 1; epnum
< musb
->config
->num_eps
; epnum
++) {
1338 musb_ep_select(mbase
, epnum
);
1339 hw_ep
= musb
->endpoints
+ epnum
;
1341 ret
= musb_read_fifosize(musb
, hw_ep
, epnum
);
1345 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1347 /* pick an RX/TX endpoint for bulk */
1348 if (hw_ep
->max_packet_sz_tx
< 512
1349 || hw_ep
->max_packet_sz_rx
< 512)
1352 /* REVISIT: this algorithm is lazy, we should at least
1353 * try to pick a double buffered endpoint.
1357 musb
->bulk_ep
= hw_ep
;
1360 if (!musb
->bulk_ep
) {
1361 pr_debug("%s: missing bulk\n", musb_driver_name
);
1368 enum { MUSB_CONTROLLER_MHDRC
, MUSB_CONTROLLER_HDRC
, };
1370 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1371 * configure endpoints, or take their config from silicon
1373 static int musb_core_init(u16 musb_type
, struct musb
*musb
)
1377 char aInfo
[90], aRevision
[32], aDate
[12];
1378 void __iomem
*mbase
= musb
->mregs
;
1382 /* log core options (read using indexed model) */
1383 reg
= musb_read_configdata(mbase
);
1385 strcpy(aInfo
, (reg
& MUSB_CONFIGDATA_UTMIDW
) ? "UTMI-16" : "UTMI-8");
1386 if (reg
& MUSB_CONFIGDATA_DYNFIFO
) {
1387 strcat(aInfo
, ", dyn FIFOs");
1388 musb
->dyn_fifo
= true;
1390 if (reg
& MUSB_CONFIGDATA_MPRXE
) {
1391 strcat(aInfo
, ", bulk combine");
1392 musb
->bulk_combine
= true;
1394 if (reg
& MUSB_CONFIGDATA_MPTXE
) {
1395 strcat(aInfo
, ", bulk split");
1396 musb
->bulk_split
= true;
1398 if (reg
& MUSB_CONFIGDATA_HBRXE
) {
1399 strcat(aInfo
, ", HB-ISO Rx");
1400 musb
->hb_iso_rx
= true;
1402 if (reg
& MUSB_CONFIGDATA_HBTXE
) {
1403 strcat(aInfo
, ", HB-ISO Tx");
1404 musb
->hb_iso_tx
= true;
1406 if (reg
& MUSB_CONFIGDATA_SOFTCONE
)
1407 strcat(aInfo
, ", SoftConn");
1409 printk(KERN_DEBUG
"%s: ConfigData=0x%02x (%s)\n",
1410 musb_driver_name
, reg
, aInfo
);
1413 if (MUSB_CONTROLLER_MHDRC
== musb_type
) {
1414 musb
->is_multipoint
= 1;
1417 musb
->is_multipoint
= 0;
1419 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1421 "%s: kernel must blacklist external hubs\n",
1426 /* log release info */
1427 musb
->hwvers
= musb_read_hwvers(mbase
);
1428 snprintf(aRevision
, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb
->hwvers
),
1429 MUSB_HWVERS_MINOR(musb
->hwvers
),
1430 (musb
->hwvers
& MUSB_HWVERS_RC
) ? "RC" : "");
1431 printk(KERN_DEBUG
"%s: %sHDRC RTL version %s %s\n",
1432 musb_driver_name
, type
, aRevision
, aDate
);
1435 musb_configure_ep0(musb
);
1437 /* discover endpoint configuration */
1438 musb
->nr_endpoints
= 1;
1442 status
= ep_config_from_table(musb
);
1444 status
= ep_config_from_hw(musb
);
1449 /* finish init, and print endpoint config */
1450 for (i
= 0; i
< musb
->nr_endpoints
; i
++) {
1451 struct musb_hw_ep
*hw_ep
= musb
->endpoints
+ i
;
1453 hw_ep
->fifo
= MUSB_FIFO_OFFSET(i
) + mbase
;
1454 #if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE)
1455 hw_ep
->fifo_async
= musb
->async
+ 0x400 + MUSB_FIFO_OFFSET(i
);
1456 hw_ep
->fifo_sync
= musb
->sync
+ 0x400 + MUSB_FIFO_OFFSET(i
);
1457 hw_ep
->fifo_sync_va
=
1458 musb
->sync_va
+ 0x400 + MUSB_FIFO_OFFSET(i
);
1461 hw_ep
->conf
= mbase
- 0x400 + TUSB_EP0_CONF
;
1463 hw_ep
->conf
= mbase
+ 0x400 + (((i
- 1) & 0xf) << 2);
1466 hw_ep
->regs
= MUSB_EP_OFFSET(i
, 0) + mbase
;
1467 hw_ep
->target_regs
= musb_read_target_reg_base(i
, mbase
);
1468 hw_ep
->rx_reinit
= 1;
1469 hw_ep
->tx_reinit
= 1;
1471 if (hw_ep
->max_packet_sz_tx
) {
1472 dev_dbg(musb
->controller
,
1473 "%s: hw_ep %d%s, %smax %d\n",
1474 musb_driver_name
, i
,
1475 hw_ep
->is_shared_fifo
? "shared" : "tx",
1476 hw_ep
->tx_double_buffered
1477 ? "doublebuffer, " : "",
1478 hw_ep
->max_packet_sz_tx
);
1480 if (hw_ep
->max_packet_sz_rx
&& !hw_ep
->is_shared_fifo
) {
1481 dev_dbg(musb
->controller
,
1482 "%s: hw_ep %d%s, %smax %d\n",
1483 musb_driver_name
, i
,
1485 hw_ep
->rx_double_buffered
1486 ? "doublebuffer, " : "",
1487 hw_ep
->max_packet_sz_rx
);
1489 if (!(hw_ep
->max_packet_sz_tx
|| hw_ep
->max_packet_sz_rx
))
1490 dev_dbg(musb
->controller
, "hw_ep %d not configured\n", i
);
1496 /*-------------------------------------------------------------------------*/
1499 * handle all the irqs defined by the HDRC core. for now we expect: other
1500 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1501 * will be assigned, and the irq will already have been acked.
1503 * called in irq context with spinlock held, irqs blocked
1505 irqreturn_t
musb_interrupt(struct musb
*musb
)
1507 irqreturn_t retval
= IRQ_NONE
;
1512 devctl
= musb_readb(musb
->mregs
, MUSB_DEVCTL
);
1514 dev_dbg(musb
->controller
, "** IRQ %s usb%04x tx%04x rx%04x\n",
1515 (devctl
& MUSB_DEVCTL_HM
) ? "host" : "peripheral",
1516 musb
->int_usb
, musb
->int_tx
, musb
->int_rx
);
1518 /* the core can interrupt us for multiple reasons; docs have
1519 * a generic interrupt flowchart to follow
1522 retval
|= musb_stage0_irq(musb
, musb
->int_usb
,
1525 /* "stage 1" is handling endpoint irqs */
1527 /* handle endpoint 0 first */
1528 if (musb
->int_tx
& 1) {
1529 if (devctl
& MUSB_DEVCTL_HM
)
1530 retval
|= musb_h_ep0_irq(musb
);
1532 retval
|= musb_g_ep0_irq(musb
);
1535 /* RX on endpoints 1-15 */
1536 reg
= musb
->int_rx
>> 1;
1540 /* musb_ep_select(musb->mregs, ep_num); */
1541 /* REVISIT just retval = ep->rx_irq(...) */
1542 retval
= IRQ_HANDLED
;
1543 if (devctl
& MUSB_DEVCTL_HM
)
1544 musb_host_rx(musb
, ep_num
);
1546 musb_g_rx(musb
, ep_num
);
1553 /* TX on endpoints 1-15 */
1554 reg
= musb
->int_tx
>> 1;
1558 /* musb_ep_select(musb->mregs, ep_num); */
1559 /* REVISIT just retval |= ep->tx_irq(...) */
1560 retval
= IRQ_HANDLED
;
1561 if (devctl
& MUSB_DEVCTL_HM
)
1562 musb_host_tx(musb
, ep_num
);
1564 musb_g_tx(musb
, ep_num
);
1572 EXPORT_SYMBOL_GPL(musb_interrupt
);
1574 #ifndef CONFIG_MUSB_PIO_ONLY
1575 static bool use_dma
= 1;
1577 /* "modprobe ... use_dma=0" etc */
1578 module_param(use_dma
, bool, 0);
1579 MODULE_PARM_DESC(use_dma
, "enable/disable use of DMA");
1581 void musb_dma_completion(struct musb
*musb
, u8 epnum
, u8 transmit
)
1583 u8 devctl
= musb_readb(musb
->mregs
, MUSB_DEVCTL
);
1585 /* called with controller lock already held */
1588 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1589 if (!is_cppi_enabled()) {
1591 if (devctl
& MUSB_DEVCTL_HM
)
1592 musb_h_ep0_irq(musb
);
1594 musb_g_ep0_irq(musb
);
1598 /* endpoints 1..15 */
1600 if (devctl
& MUSB_DEVCTL_HM
)
1601 musb_host_tx(musb
, epnum
);
1603 musb_g_tx(musb
, epnum
);
1606 if (devctl
& MUSB_DEVCTL_HM
)
1607 musb_host_rx(musb
, epnum
);
1609 musb_g_rx(musb
, epnum
);
1613 EXPORT_SYMBOL_GPL(musb_dma_completion
);
1619 /*-------------------------------------------------------------------------*/
1622 musb_mode_show(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1624 struct musb
*musb
= dev_to_musb(dev
);
1625 unsigned long flags
;
1628 spin_lock_irqsave(&musb
->lock
, flags
);
1629 ret
= sprintf(buf
, "%s\n", usb_otg_state_string(musb
->xceiv
->state
));
1630 spin_unlock_irqrestore(&musb
->lock
, flags
);
1636 musb_mode_store(struct device
*dev
, struct device_attribute
*attr
,
1637 const char *buf
, size_t n
)
1639 struct musb
*musb
= dev_to_musb(dev
);
1640 unsigned long flags
;
1643 spin_lock_irqsave(&musb
->lock
, flags
);
1644 if (sysfs_streq(buf
, "host"))
1645 status
= musb_platform_set_mode(musb
, MUSB_HOST
);
1646 else if (sysfs_streq(buf
, "peripheral"))
1647 status
= musb_platform_set_mode(musb
, MUSB_PERIPHERAL
);
1648 else if (sysfs_streq(buf
, "otg"))
1649 status
= musb_platform_set_mode(musb
, MUSB_OTG
);
1652 spin_unlock_irqrestore(&musb
->lock
, flags
);
1654 return (status
== 0) ? n
: status
;
1656 static DEVICE_ATTR(mode
, 0644, musb_mode_show
, musb_mode_store
);
1659 musb_vbus_store(struct device
*dev
, struct device_attribute
*attr
,
1660 const char *buf
, size_t n
)
1662 struct musb
*musb
= dev_to_musb(dev
);
1663 unsigned long flags
;
1666 if (sscanf(buf
, "%lu", &val
) < 1) {
1667 dev_err(dev
, "Invalid VBUS timeout ms value\n");
1671 spin_lock_irqsave(&musb
->lock
, flags
);
1672 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1673 musb
->a_wait_bcon
= val
? max_t(int, val
, OTG_TIME_A_WAIT_BCON
) : 0 ;
1674 if (musb
->xceiv
->state
== OTG_STATE_A_WAIT_BCON
)
1675 musb
->is_active
= 0;
1676 musb_platform_try_idle(musb
, jiffies
+ msecs_to_jiffies(val
));
1677 spin_unlock_irqrestore(&musb
->lock
, flags
);
1683 musb_vbus_show(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1685 struct musb
*musb
= dev_to_musb(dev
);
1686 unsigned long flags
;
1690 spin_lock_irqsave(&musb
->lock
, flags
);
1691 val
= musb
->a_wait_bcon
;
1692 /* FIXME get_vbus_status() is normally #defined as false...
1693 * and is effectively TUSB-specific.
1695 vbus
= musb_platform_get_vbus_status(musb
);
1696 spin_unlock_irqrestore(&musb
->lock
, flags
);
1698 return sprintf(buf
, "Vbus %s, timeout %lu msec\n",
1699 vbus
? "on" : "off", val
);
1701 static DEVICE_ATTR(vbus
, 0644, musb_vbus_show
, musb_vbus_store
);
1703 /* Gadget drivers can't know that a host is connected so they might want
1704 * to start SRP, but users can. This allows userspace to trigger SRP.
1707 musb_srp_store(struct device
*dev
, struct device_attribute
*attr
,
1708 const char *buf
, size_t n
)
1710 struct musb
*musb
= dev_to_musb(dev
);
1713 if (sscanf(buf
, "%hu", &srp
) != 1
1715 dev_err(dev
, "SRP: Value must be 1\n");
1720 musb_g_wakeup(musb
);
1724 static DEVICE_ATTR(srp
, 0644, NULL
, musb_srp_store
);
1726 static struct attribute
*musb_attributes
[] = {
1727 &dev_attr_mode
.attr
,
1728 &dev_attr_vbus
.attr
,
1733 static const struct attribute_group musb_attr_group
= {
1734 .attrs
= musb_attributes
,
1737 /* Only used to provide driver mode change events */
1738 static void musb_irq_work(struct work_struct
*data
)
1740 struct musb
*musb
= container_of(data
, struct musb
, irq_work
);
1742 if (musb
->xceiv
->state
!= musb
->xceiv_old_state
) {
1743 musb
->xceiv_old_state
= musb
->xceiv
->state
;
1744 sysfs_notify(&musb
->controller
->kobj
, NULL
, "mode");
1748 /* --------------------------------------------------------------------------
1752 static struct musb
*allocate_instance(struct device
*dev
,
1753 struct musb_hdrc_config
*config
, void __iomem
*mbase
)
1756 struct musb_hw_ep
*ep
;
1760 musb
= devm_kzalloc(dev
, sizeof(*musb
), GFP_KERNEL
);
1764 INIT_LIST_HEAD(&musb
->control
);
1765 INIT_LIST_HEAD(&musb
->in_bulk
);
1766 INIT_LIST_HEAD(&musb
->out_bulk
);
1768 musb
->vbuserr_retry
= VBUSERR_RETRY_COUNT
;
1769 musb
->a_wait_bcon
= OTG_TIME_A_WAIT_BCON
;
1770 musb
->mregs
= mbase
;
1771 musb
->ctrl_base
= mbase
;
1772 musb
->nIrq
= -ENODEV
;
1773 musb
->config
= config
;
1774 BUG_ON(musb
->config
->num_eps
> MUSB_C_NUM_EPS
);
1775 for (epnum
= 0, ep
= musb
->endpoints
;
1776 epnum
< musb
->config
->num_eps
;
1782 musb
->controller
= dev
;
1784 ret
= musb_host_alloc(musb
);
1788 dev_set_drvdata(dev
, musb
);
1796 static void musb_free(struct musb
*musb
)
1798 /* this has multiple entry modes. it handles fault cleanup after
1799 * probe(), where things may be partially set up, as well as rmmod
1800 * cleanup after everything's been de-activated.
1804 sysfs_remove_group(&musb
->controller
->kobj
, &musb_attr_group
);
1807 if (musb
->nIrq
>= 0) {
1809 disable_irq_wake(musb
->nIrq
);
1810 free_irq(musb
->nIrq
, musb
);
1812 cancel_work_sync(&musb
->irq_work
);
1814 musb_host_free(musb
);
1818 * Perform generic per-controller initialization.
1820 * @dev: the controller (already clocked, etc)
1822 * @ctrl: virtual address of controller registers,
1823 * not yet corrected for platform-specific offsets
1826 musb_init_controller(struct device
*dev
, int nIrq
, void __iomem
*ctrl
)
1830 struct musb_hdrc_platform_data
*plat
= dev_get_platdata(dev
);
1832 /* The driver might handle more features than the board; OK.
1833 * Fail when the board needs a feature that's not enabled.
1836 dev_dbg(dev
, "no platform_data?\n");
1842 musb
= allocate_instance(dev
, plat
->config
, ctrl
);
1848 pm_runtime_use_autosuspend(musb
->controller
);
1849 pm_runtime_set_autosuspend_delay(musb
->controller
, 200);
1850 pm_runtime_enable(musb
->controller
);
1852 spin_lock_init(&musb
->lock
);
1853 musb
->board_set_power
= plat
->set_power
;
1854 musb
->min_power
= plat
->min_power
;
1855 musb
->ops
= plat
->platform_ops
;
1856 musb
->port_mode
= plat
->mode
;
1858 /* The musb_platform_init() call:
1859 * - adjusts musb->mregs
1860 * - sets the musb->isr
1861 * - may initialize an integrated tranceiver
1862 * - initializes musb->xceiv, usually by otg_get_phy()
1863 * - stops powering VBUS
1865 * There are various transceiver configurations. Blackfin,
1866 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1867 * external/discrete ones in various flavors (twl4030 family,
1868 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1870 status
= musb_platform_init(musb
);
1879 if (!musb
->xceiv
->io_ops
) {
1880 musb
->xceiv
->io_dev
= musb
->controller
;
1881 musb
->xceiv
->io_priv
= musb
->mregs
;
1882 musb
->xceiv
->io_ops
= &musb_ulpi_access
;
1885 pm_runtime_get_sync(musb
->controller
);
1887 if (use_dma
&& dev
->dma_mask
) {
1888 musb
->dma_controller
= dma_controller_create(musb
, musb
->mregs
);
1889 if (IS_ERR(musb
->dma_controller
)) {
1890 status
= PTR_ERR(musb
->dma_controller
);
1895 /* be sure interrupts are disabled before connecting ISR */
1896 musb_platform_disable(musb
);
1897 musb_generic_disable(musb
);
1899 /* setup musb parts of the core (especially endpoints) */
1900 status
= musb_core_init(plat
->config
->multipoint
1901 ? MUSB_CONTROLLER_MHDRC
1902 : MUSB_CONTROLLER_HDRC
, musb
);
1906 setup_timer(&musb
->otg_timer
, musb_otg_timer_func
, (unsigned long) musb
);
1908 /* Init IRQ workqueue before request_irq */
1909 INIT_WORK(&musb
->irq_work
, musb_irq_work
);
1911 /* attach to the IRQ */
1912 if (request_irq(nIrq
, musb
->isr
, 0, dev_name(dev
), musb
)) {
1913 dev_err(dev
, "request_irq %d failed!\n", nIrq
);
1918 /* FIXME this handles wakeup irqs wrong */
1919 if (enable_irq_wake(nIrq
) == 0) {
1921 device_init_wakeup(dev
, 1);
1926 /* program PHY to use external vBus if required */
1927 if (plat
->extvbus
) {
1928 u8 busctl
= musb_read_ulpi_buscontrol(musb
->mregs
);
1929 busctl
|= MUSB_ULPI_USE_EXTVBUS
;
1930 musb_write_ulpi_buscontrol(musb
->mregs
, busctl
);
1933 if (musb
->xceiv
->otg
->default_a
) {
1934 MUSB_HST_MODE(musb
);
1935 musb
->xceiv
->state
= OTG_STATE_A_IDLE
;
1937 MUSB_DEV_MODE(musb
);
1938 musb
->xceiv
->state
= OTG_STATE_B_IDLE
;
1941 switch (musb
->port_mode
) {
1942 case MUSB_PORT_MODE_HOST
:
1943 status
= musb_host_setup(musb
, plat
->power
);
1945 case MUSB_PORT_MODE_GADGET
:
1946 status
= musb_gadget_setup(musb
);
1948 case MUSB_PORT_MODE_DUAL_ROLE
:
1949 status
= musb_host_setup(musb
, plat
->power
);
1952 status
= musb_gadget_setup(musb
);
1954 musb_host_cleanup(musb
);
1957 dev_err(dev
, "unsupported port mode %d\n", musb
->port_mode
);
1964 status
= musb_init_debugfs(musb
);
1968 status
= sysfs_create_group(&musb
->controller
->kobj
, &musb_attr_group
);
1972 pm_runtime_put(musb
->controller
);
1977 musb_exit_debugfs(musb
);
1980 musb_gadget_cleanup(musb
);
1981 musb_host_cleanup(musb
);
1984 if (musb
->dma_controller
)
1985 dma_controller_destroy(musb
->dma_controller
);
1987 pm_runtime_put_sync(musb
->controller
);
1991 device_init_wakeup(dev
, 0);
1992 musb_platform_exit(musb
);
1995 pm_runtime_disable(musb
->controller
);
1996 dev_err(musb
->controller
,
1997 "musb_init_controller failed with status %d\n", status
);
2007 /*-------------------------------------------------------------------------*/
2009 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2010 * bridge to a platform device; this driver then suffices.
2012 static int musb_probe(struct platform_device
*pdev
)
2014 struct device
*dev
= &pdev
->dev
;
2015 int irq
= platform_get_irq_byname(pdev
, "mc");
2016 struct resource
*iomem
;
2019 iomem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2020 if (!iomem
|| irq
<= 0)
2023 base
= devm_ioremap_resource(dev
, iomem
);
2025 return PTR_ERR(base
);
2027 return musb_init_controller(dev
, irq
, base
);
2030 static int musb_remove(struct platform_device
*pdev
)
2032 struct device
*dev
= &pdev
->dev
;
2033 struct musb
*musb
= dev_to_musb(dev
);
2035 /* this gets called on rmmod.
2036 * - Host mode: host may still be active
2037 * - Peripheral mode: peripheral is deactivated (or never-activated)
2038 * - OTG mode: both roles are deactivated (or never-activated)
2040 musb_exit_debugfs(musb
);
2041 musb_shutdown(pdev
);
2043 if (musb
->dma_controller
)
2044 dma_controller_destroy(musb
->dma_controller
);
2047 device_init_wakeup(dev
, 0);
2053 static void musb_save_context(struct musb
*musb
)
2056 void __iomem
*musb_base
= musb
->mregs
;
2059 musb
->context
.frame
= musb_readw(musb_base
, MUSB_FRAME
);
2060 musb
->context
.testmode
= musb_readb(musb_base
, MUSB_TESTMODE
);
2061 musb
->context
.busctl
= musb_read_ulpi_buscontrol(musb
->mregs
);
2062 musb
->context
.power
= musb_readb(musb_base
, MUSB_POWER
);
2063 musb
->context
.intrusbe
= musb_readb(musb_base
, MUSB_INTRUSBE
);
2064 musb
->context
.index
= musb_readb(musb_base
, MUSB_INDEX
);
2065 musb
->context
.devctl
= musb_readb(musb_base
, MUSB_DEVCTL
);
2067 for (i
= 0; i
< musb
->config
->num_eps
; ++i
) {
2068 struct musb_hw_ep
*hw_ep
;
2070 hw_ep
= &musb
->endpoints
[i
];
2078 musb_writeb(musb_base
, MUSB_INDEX
, i
);
2079 musb
->context
.index_regs
[i
].txmaxp
=
2080 musb_readw(epio
, MUSB_TXMAXP
);
2081 musb
->context
.index_regs
[i
].txcsr
=
2082 musb_readw(epio
, MUSB_TXCSR
);
2083 musb
->context
.index_regs
[i
].rxmaxp
=
2084 musb_readw(epio
, MUSB_RXMAXP
);
2085 musb
->context
.index_regs
[i
].rxcsr
=
2086 musb_readw(epio
, MUSB_RXCSR
);
2088 if (musb
->dyn_fifo
) {
2089 musb
->context
.index_regs
[i
].txfifoadd
=
2090 musb_read_txfifoadd(musb_base
);
2091 musb
->context
.index_regs
[i
].rxfifoadd
=
2092 musb_read_rxfifoadd(musb_base
);
2093 musb
->context
.index_regs
[i
].txfifosz
=
2094 musb_read_txfifosz(musb_base
);
2095 musb
->context
.index_regs
[i
].rxfifosz
=
2096 musb_read_rxfifosz(musb_base
);
2099 musb
->context
.index_regs
[i
].txtype
=
2100 musb_readb(epio
, MUSB_TXTYPE
);
2101 musb
->context
.index_regs
[i
].txinterval
=
2102 musb_readb(epio
, MUSB_TXINTERVAL
);
2103 musb
->context
.index_regs
[i
].rxtype
=
2104 musb_readb(epio
, MUSB_RXTYPE
);
2105 musb
->context
.index_regs
[i
].rxinterval
=
2106 musb_readb(epio
, MUSB_RXINTERVAL
);
2108 musb
->context
.index_regs
[i
].txfunaddr
=
2109 musb_read_txfunaddr(musb_base
, i
);
2110 musb
->context
.index_regs
[i
].txhubaddr
=
2111 musb_read_txhubaddr(musb_base
, i
);
2112 musb
->context
.index_regs
[i
].txhubport
=
2113 musb_read_txhubport(musb_base
, i
);
2115 musb
->context
.index_regs
[i
].rxfunaddr
=
2116 musb_read_rxfunaddr(musb_base
, i
);
2117 musb
->context
.index_regs
[i
].rxhubaddr
=
2118 musb_read_rxhubaddr(musb_base
, i
);
2119 musb
->context
.index_regs
[i
].rxhubport
=
2120 musb_read_rxhubport(musb_base
, i
);
2124 static void musb_restore_context(struct musb
*musb
)
2127 void __iomem
*musb_base
= musb
->mregs
;
2128 void __iomem
*ep_target_regs
;
2131 musb_writew(musb_base
, MUSB_FRAME
, musb
->context
.frame
);
2132 musb_writeb(musb_base
, MUSB_TESTMODE
, musb
->context
.testmode
);
2133 musb_write_ulpi_buscontrol(musb
->mregs
, musb
->context
.busctl
);
2134 musb_writeb(musb_base
, MUSB_POWER
, musb
->context
.power
);
2135 musb_writew(musb_base
, MUSB_INTRTXE
, musb
->intrtxe
);
2136 musb_writew(musb_base
, MUSB_INTRRXE
, musb
->intrrxe
);
2137 musb_writeb(musb_base
, MUSB_INTRUSBE
, musb
->context
.intrusbe
);
2138 musb_writeb(musb_base
, MUSB_DEVCTL
, musb
->context
.devctl
);
2140 for (i
= 0; i
< musb
->config
->num_eps
; ++i
) {
2141 struct musb_hw_ep
*hw_ep
;
2143 hw_ep
= &musb
->endpoints
[i
];
2151 musb_writeb(musb_base
, MUSB_INDEX
, i
);
2152 musb_writew(epio
, MUSB_TXMAXP
,
2153 musb
->context
.index_regs
[i
].txmaxp
);
2154 musb_writew(epio
, MUSB_TXCSR
,
2155 musb
->context
.index_regs
[i
].txcsr
);
2156 musb_writew(epio
, MUSB_RXMAXP
,
2157 musb
->context
.index_regs
[i
].rxmaxp
);
2158 musb_writew(epio
, MUSB_RXCSR
,
2159 musb
->context
.index_regs
[i
].rxcsr
);
2161 if (musb
->dyn_fifo
) {
2162 musb_write_txfifosz(musb_base
,
2163 musb
->context
.index_regs
[i
].txfifosz
);
2164 musb_write_rxfifosz(musb_base
,
2165 musb
->context
.index_regs
[i
].rxfifosz
);
2166 musb_write_txfifoadd(musb_base
,
2167 musb
->context
.index_regs
[i
].txfifoadd
);
2168 musb_write_rxfifoadd(musb_base
,
2169 musb
->context
.index_regs
[i
].rxfifoadd
);
2172 musb_writeb(epio
, MUSB_TXTYPE
,
2173 musb
->context
.index_regs
[i
].txtype
);
2174 musb_writeb(epio
, MUSB_TXINTERVAL
,
2175 musb
->context
.index_regs
[i
].txinterval
);
2176 musb_writeb(epio
, MUSB_RXTYPE
,
2177 musb
->context
.index_regs
[i
].rxtype
);
2178 musb_writeb(epio
, MUSB_RXINTERVAL
,
2180 musb
->context
.index_regs
[i
].rxinterval
);
2181 musb_write_txfunaddr(musb_base
, i
,
2182 musb
->context
.index_regs
[i
].txfunaddr
);
2183 musb_write_txhubaddr(musb_base
, i
,
2184 musb
->context
.index_regs
[i
].txhubaddr
);
2185 musb_write_txhubport(musb_base
, i
,
2186 musb
->context
.index_regs
[i
].txhubport
);
2189 musb_read_target_reg_base(i
, musb_base
);
2191 musb_write_rxfunaddr(ep_target_regs
,
2192 musb
->context
.index_regs
[i
].rxfunaddr
);
2193 musb_write_rxhubaddr(ep_target_regs
,
2194 musb
->context
.index_regs
[i
].rxhubaddr
);
2195 musb_write_rxhubport(ep_target_regs
,
2196 musb
->context
.index_regs
[i
].rxhubport
);
2198 musb_writeb(musb_base
, MUSB_INDEX
, musb
->context
.index
);
2201 static int musb_suspend(struct device
*dev
)
2203 struct musb
*musb
= dev_to_musb(dev
);
2204 unsigned long flags
;
2206 spin_lock_irqsave(&musb
->lock
, flags
);
2208 if (is_peripheral_active(musb
)) {
2209 /* FIXME force disconnect unless we know USB will wake
2210 * the system up quickly enough to respond ...
2212 } else if (is_host_active(musb
)) {
2213 /* we know all the children are suspended; sometimes
2214 * they will even be wakeup-enabled.
2218 spin_unlock_irqrestore(&musb
->lock
, flags
);
2222 static int musb_resume_noirq(struct device
*dev
)
2224 /* for static cmos like DaVinci, register values were preserved
2225 * unless for some reason the whole soc powered down or the USB
2226 * module got reset through the PSC (vs just being disabled).
2231 static int musb_runtime_suspend(struct device
*dev
)
2233 struct musb
*musb
= dev_to_musb(dev
);
2235 musb_save_context(musb
);
2240 static int musb_runtime_resume(struct device
*dev
)
2242 struct musb
*musb
= dev_to_musb(dev
);
2243 static int first
= 1;
2246 * When pm_runtime_get_sync called for the first time in driver
2247 * init, some of the structure is still not initialized which is
2248 * used in restore function. But clock needs to be
2249 * enabled before any register access, so
2250 * pm_runtime_get_sync has to be called.
2251 * Also context restore without save does not make
2255 musb_restore_context(musb
);
2261 static const struct dev_pm_ops musb_dev_pm_ops
= {
2262 .suspend
= musb_suspend
,
2263 .resume_noirq
= musb_resume_noirq
,
2264 .runtime_suspend
= musb_runtime_suspend
,
2265 .runtime_resume
= musb_runtime_resume
,
2268 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2270 #define MUSB_DEV_PM_OPS NULL
2273 static struct platform_driver musb_driver
= {
2275 .name
= (char *)musb_driver_name
,
2276 .bus
= &platform_bus_type
,
2277 .owner
= THIS_MODULE
,
2278 .pm
= MUSB_DEV_PM_OPS
,
2280 .probe
= musb_probe
,
2281 .remove
= musb_remove
,
2282 .shutdown
= musb_shutdown
,
2285 /*-------------------------------------------------------------------------*/
2287 static int __init
musb_init(void)
2292 return platform_driver_register(&musb_driver
);
2294 module_init(musb_init
);
2296 static void __exit
musb_cleanup(void)
2298 platform_driver_unregister(&musb_driver
);
2300 module_exit(musb_cleanup
);