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Merge branch 'for-linus' of git://git.kernel.dk/linux-block
[mirror_ubuntu-bionic-kernel.git] / drivers / usb / musb / musb_core.c
1 /*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35 /*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82 /*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific information
87 * (plus recentrly, SOC or family details)
88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/list.h>
97 #include <linux/kobject.h>
98 #include <linux/prefetch.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
101 #include <linux/dma-mapping.h>
102 #include <linux/usb.h>
103
104 #include "musb_core.h"
105
106 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
107
108
109 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
110 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
111
112 #define MUSB_VERSION "6.0"
113
114 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
115
116 #define MUSB_DRIVER_NAME "musb-hdrc"
117 const char musb_driver_name[] = MUSB_DRIVER_NAME;
118
119 MODULE_DESCRIPTION(DRIVER_INFO);
120 MODULE_AUTHOR(DRIVER_AUTHOR);
121 MODULE_LICENSE("GPL");
122 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
123
124
125 /*-------------------------------------------------------------------------*/
126
127 static inline struct musb *dev_to_musb(struct device *dev)
128 {
129 return dev_get_drvdata(dev);
130 }
131
132 /*-------------------------------------------------------------------------*/
133
134 #ifndef CONFIG_BLACKFIN
135 static int musb_ulpi_read(struct usb_phy *phy, u32 reg)
136 {
137 void __iomem *addr = phy->io_priv;
138 int i = 0;
139 u8 r;
140 u8 power;
141 int ret;
142
143 pm_runtime_get_sync(phy->io_dev);
144
145 /* Make sure the transceiver is not in low power mode */
146 power = musb_readb(addr, MUSB_POWER);
147 power &= ~MUSB_POWER_SUSPENDM;
148 musb_writeb(addr, MUSB_POWER, power);
149
150 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
151 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
152 */
153
154 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
155 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
156 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
157
158 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
159 & MUSB_ULPI_REG_CMPLT)) {
160 i++;
161 if (i == 10000) {
162 ret = -ETIMEDOUT;
163 goto out;
164 }
165
166 }
167 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
168 r &= ~MUSB_ULPI_REG_CMPLT;
169 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
170
171 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
172
173 out:
174 pm_runtime_put(phy->io_dev);
175
176 return ret;
177 }
178
179 static int musb_ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
180 {
181 void __iomem *addr = phy->io_priv;
182 int i = 0;
183 u8 r = 0;
184 u8 power;
185 int ret = 0;
186
187 pm_runtime_get_sync(phy->io_dev);
188
189 /* Make sure the transceiver is not in low power mode */
190 power = musb_readb(addr, MUSB_POWER);
191 power &= ~MUSB_POWER_SUSPENDM;
192 musb_writeb(addr, MUSB_POWER, power);
193
194 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
195 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)val);
196 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
197
198 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
199 & MUSB_ULPI_REG_CMPLT)) {
200 i++;
201 if (i == 10000) {
202 ret = -ETIMEDOUT;
203 goto out;
204 }
205 }
206
207 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
208 r &= ~MUSB_ULPI_REG_CMPLT;
209 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
210
211 out:
212 pm_runtime_put(phy->io_dev);
213
214 return ret;
215 }
216 #else
217 #define musb_ulpi_read NULL
218 #define musb_ulpi_write NULL
219 #endif
220
221 static struct usb_phy_io_ops musb_ulpi_access = {
222 .read = musb_ulpi_read,
223 .write = musb_ulpi_write,
224 };
225
226 /*-------------------------------------------------------------------------*/
227
228 static u32 musb_default_fifo_offset(u8 epnum)
229 {
230 return 0x20 + (epnum * 4);
231 }
232
233 /* "flat" mapping: each endpoint has its own i/o address */
234 static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
235 {
236 }
237
238 static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
239 {
240 return 0x100 + (0x10 * epnum) + offset;
241 }
242
243 /* "indexed" mapping: INDEX register controls register bank select */
244 static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
245 {
246 musb_writeb(mbase, MUSB_INDEX, epnum);
247 }
248
249 static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
250 {
251 return 0x10 + offset;
252 }
253
254 static u32 musb_default_busctl_offset(u8 epnum, u16 offset)
255 {
256 return 0x80 + (0x08 * epnum) + offset;
257 }
258
259 static u8 musb_default_readb(const void __iomem *addr, unsigned offset)
260 {
261 return __raw_readb(addr + offset);
262 }
263
264 static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data)
265 {
266 __raw_writeb(data, addr + offset);
267 }
268
269 static u16 musb_default_readw(const void __iomem *addr, unsigned offset)
270 {
271 return __raw_readw(addr + offset);
272 }
273
274 static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data)
275 {
276 __raw_writew(data, addr + offset);
277 }
278
279 static u32 musb_default_readl(const void __iomem *addr, unsigned offset)
280 {
281 return __raw_readl(addr + offset);
282 }
283
284 static void musb_default_writel(void __iomem *addr, unsigned offset, u32 data)
285 {
286 __raw_writel(data, addr + offset);
287 }
288
289 /*
290 * Load an endpoint's FIFO
291 */
292 static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
293 const u8 *src)
294 {
295 struct musb *musb = hw_ep->musb;
296 void __iomem *fifo = hw_ep->fifo;
297
298 if (unlikely(len == 0))
299 return;
300
301 prefetch((u8 *)src);
302
303 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
304 'T', hw_ep->epnum, fifo, len, src);
305
306 /* we can't assume unaligned reads work */
307 if (likely((0x01 & (unsigned long) src) == 0)) {
308 u16 index = 0;
309
310 /* best case is 32bit-aligned source address */
311 if ((0x02 & (unsigned long) src) == 0) {
312 if (len >= 4) {
313 iowrite32_rep(fifo, src + index, len >> 2);
314 index += len & ~0x03;
315 }
316 if (len & 0x02) {
317 __raw_writew(*(u16 *)&src[index], fifo);
318 index += 2;
319 }
320 } else {
321 if (len >= 2) {
322 iowrite16_rep(fifo, src + index, len >> 1);
323 index += len & ~0x01;
324 }
325 }
326 if (len & 0x01)
327 __raw_writeb(src[index], fifo);
328 } else {
329 /* byte aligned */
330 iowrite8_rep(fifo, src, len);
331 }
332 }
333
334 /*
335 * Unload an endpoint's FIFO
336 */
337 static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
338 {
339 struct musb *musb = hw_ep->musb;
340 void __iomem *fifo = hw_ep->fifo;
341
342 if (unlikely(len == 0))
343 return;
344
345 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
346 'R', hw_ep->epnum, fifo, len, dst);
347
348 /* we can't assume unaligned writes work */
349 if (likely((0x01 & (unsigned long) dst) == 0)) {
350 u16 index = 0;
351
352 /* best case is 32bit-aligned destination address */
353 if ((0x02 & (unsigned long) dst) == 0) {
354 if (len >= 4) {
355 ioread32_rep(fifo, dst, len >> 2);
356 index = len & ~0x03;
357 }
358 if (len & 0x02) {
359 *(u16 *)&dst[index] = __raw_readw(fifo);
360 index += 2;
361 }
362 } else {
363 if (len >= 2) {
364 ioread16_rep(fifo, dst, len >> 1);
365 index = len & ~0x01;
366 }
367 }
368 if (len & 0x01)
369 dst[index] = __raw_readb(fifo);
370 } else {
371 /* byte aligned */
372 ioread8_rep(fifo, dst, len);
373 }
374 }
375
376 /*
377 * Old style IO functions
378 */
379 u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
380 EXPORT_SYMBOL_GPL(musb_readb);
381
382 void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
383 EXPORT_SYMBOL_GPL(musb_writeb);
384
385 u16 (*musb_readw)(const void __iomem *addr, unsigned offset);
386 EXPORT_SYMBOL_GPL(musb_readw);
387
388 void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data);
389 EXPORT_SYMBOL_GPL(musb_writew);
390
391 u32 (*musb_readl)(const void __iomem *addr, unsigned offset);
392 EXPORT_SYMBOL_GPL(musb_readl);
393
394 void (*musb_writel)(void __iomem *addr, unsigned offset, u32 data);
395 EXPORT_SYMBOL_GPL(musb_writel);
396
397 #ifndef CONFIG_MUSB_PIO_ONLY
398 struct dma_controller *
399 (*musb_dma_controller_create)(struct musb *musb, void __iomem *base);
400 EXPORT_SYMBOL(musb_dma_controller_create);
401
402 void (*musb_dma_controller_destroy)(struct dma_controller *c);
403 EXPORT_SYMBOL(musb_dma_controller_destroy);
404 #endif
405
406 /*
407 * New style IO functions
408 */
409 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
410 {
411 return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
412 }
413
414 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
415 {
416 return hw_ep->musb->io.write_fifo(hw_ep, len, src);
417 }
418
419 /*-------------------------------------------------------------------------*/
420
421 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
422 static const u8 musb_test_packet[53] = {
423 /* implicit SYNC then DATA0 to start */
424
425 /* JKJKJKJK x9 */
426 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
427 /* JJKKJJKK x8 */
428 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
429 /* JJJJKKKK x8 */
430 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
431 /* JJJJJJJKKKKKKK x8 */
432 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
433 /* JJJJJJJK x8 */
434 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
435 /* JKKKKKKK x10, JK */
436 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
437
438 /* implicit CRC16 then EOP to end */
439 };
440
441 void musb_load_testpacket(struct musb *musb)
442 {
443 void __iomem *regs = musb->endpoints[0].regs;
444
445 musb_ep_select(musb->mregs, 0);
446 musb_write_fifo(musb->control_ep,
447 sizeof(musb_test_packet), musb_test_packet);
448 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
449 }
450
451 /*-------------------------------------------------------------------------*/
452
453 /*
454 * Handles OTG hnp timeouts, such as b_ase0_brst
455 */
456 static void musb_otg_timer_func(unsigned long data)
457 {
458 struct musb *musb = (struct musb *)data;
459 unsigned long flags;
460
461 spin_lock_irqsave(&musb->lock, flags);
462 switch (musb->xceiv->otg->state) {
463 case OTG_STATE_B_WAIT_ACON:
464 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
465 musb_g_disconnect(musb);
466 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
467 musb->is_active = 0;
468 break;
469 case OTG_STATE_A_SUSPEND:
470 case OTG_STATE_A_WAIT_BCON:
471 dev_dbg(musb->controller, "HNP: %s timeout\n",
472 usb_otg_state_string(musb->xceiv->otg->state));
473 musb_platform_set_vbus(musb, 0);
474 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
475 break;
476 default:
477 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
478 usb_otg_state_string(musb->xceiv->otg->state));
479 }
480 spin_unlock_irqrestore(&musb->lock, flags);
481 }
482
483 /*
484 * Stops the HNP transition. Caller must take care of locking.
485 */
486 void musb_hnp_stop(struct musb *musb)
487 {
488 struct usb_hcd *hcd = musb->hcd;
489 void __iomem *mbase = musb->mregs;
490 u8 reg;
491
492 dev_dbg(musb->controller, "HNP: stop from %s\n",
493 usb_otg_state_string(musb->xceiv->otg->state));
494
495 switch (musb->xceiv->otg->state) {
496 case OTG_STATE_A_PERIPHERAL:
497 musb_g_disconnect(musb);
498 dev_dbg(musb->controller, "HNP: back to %s\n",
499 usb_otg_state_string(musb->xceiv->otg->state));
500 break;
501 case OTG_STATE_B_HOST:
502 dev_dbg(musb->controller, "HNP: Disabling HR\n");
503 if (hcd)
504 hcd->self.is_b_host = 0;
505 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
506 MUSB_DEV_MODE(musb);
507 reg = musb_readb(mbase, MUSB_POWER);
508 reg |= MUSB_POWER_SUSPENDM;
509 musb_writeb(mbase, MUSB_POWER, reg);
510 /* REVISIT: Start SESSION_REQUEST here? */
511 break;
512 default:
513 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
514 usb_otg_state_string(musb->xceiv->otg->state));
515 }
516
517 /*
518 * When returning to A state after HNP, avoid hub_port_rebounce(),
519 * which cause occasional OPT A "Did not receive reset after connect"
520 * errors.
521 */
522 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
523 }
524
525 static void musb_recover_from_babble(struct musb *musb);
526
527 /*
528 * Interrupt Service Routine to record USB "global" interrupts.
529 * Since these do not happen often and signify things of
530 * paramount importance, it seems OK to check them individually;
531 * the order of the tests is specified in the manual
532 *
533 * @param musb instance pointer
534 * @param int_usb register contents
535 * @param devctl
536 * @param power
537 */
538
539 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
540 u8 devctl)
541 {
542 irqreturn_t handled = IRQ_NONE;
543
544 dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl,
545 int_usb);
546
547 /* in host mode, the peripheral may issue remote wakeup.
548 * in peripheral mode, the host may resume the link.
549 * spurious RESUME irqs happen too, paired with SUSPEND.
550 */
551 if (int_usb & MUSB_INTR_RESUME) {
552 handled = IRQ_HANDLED;
553 dev_dbg(musb->controller, "RESUME (%s)\n",
554 usb_otg_state_string(musb->xceiv->otg->state));
555
556 if (devctl & MUSB_DEVCTL_HM) {
557 switch (musb->xceiv->otg->state) {
558 case OTG_STATE_A_SUSPEND:
559 /* remote wakeup? later, GetPortStatus
560 * will stop RESUME signaling
561 */
562
563 musb->port1_status |=
564 (USB_PORT_STAT_C_SUSPEND << 16)
565 | MUSB_PORT_STAT_RESUME;
566 musb->rh_timer = jiffies
567 + msecs_to_jiffies(USB_RESUME_TIMEOUT);
568 musb->need_finish_resume = 1;
569
570 musb->xceiv->otg->state = OTG_STATE_A_HOST;
571 musb->is_active = 1;
572 musb_host_resume_root_hub(musb);
573 break;
574 case OTG_STATE_B_WAIT_ACON:
575 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
576 musb->is_active = 1;
577 MUSB_DEV_MODE(musb);
578 break;
579 default:
580 WARNING("bogus %s RESUME (%s)\n",
581 "host",
582 usb_otg_state_string(musb->xceiv->otg->state));
583 }
584 } else {
585 switch (musb->xceiv->otg->state) {
586 case OTG_STATE_A_SUSPEND:
587 /* possibly DISCONNECT is upcoming */
588 musb->xceiv->otg->state = OTG_STATE_A_HOST;
589 musb_host_resume_root_hub(musb);
590 break;
591 case OTG_STATE_B_WAIT_ACON:
592 case OTG_STATE_B_PERIPHERAL:
593 /* disconnect while suspended? we may
594 * not get a disconnect irq...
595 */
596 if ((devctl & MUSB_DEVCTL_VBUS)
597 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
598 ) {
599 musb->int_usb |= MUSB_INTR_DISCONNECT;
600 musb->int_usb &= ~MUSB_INTR_SUSPEND;
601 break;
602 }
603 musb_g_resume(musb);
604 break;
605 case OTG_STATE_B_IDLE:
606 musb->int_usb &= ~MUSB_INTR_SUSPEND;
607 break;
608 default:
609 WARNING("bogus %s RESUME (%s)\n",
610 "peripheral",
611 usb_otg_state_string(musb->xceiv->otg->state));
612 }
613 }
614 }
615
616 /* see manual for the order of the tests */
617 if (int_usb & MUSB_INTR_SESSREQ) {
618 void __iomem *mbase = musb->mregs;
619
620 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
621 && (devctl & MUSB_DEVCTL_BDEVICE)) {
622 dev_dbg(musb->controller, "SessReq while on B state\n");
623 return IRQ_HANDLED;
624 }
625
626 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
627 usb_otg_state_string(musb->xceiv->otg->state));
628
629 /* IRQ arrives from ID pin sense or (later, if VBUS power
630 * is removed) SRP. responses are time critical:
631 * - turn on VBUS (with silicon-specific mechanism)
632 * - go through A_WAIT_VRISE
633 * - ... to A_WAIT_BCON.
634 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
635 */
636 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
637 musb->ep0_stage = MUSB_EP0_START;
638 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
639 MUSB_HST_MODE(musb);
640 musb_platform_set_vbus(musb, 1);
641
642 handled = IRQ_HANDLED;
643 }
644
645 if (int_usb & MUSB_INTR_VBUSERROR) {
646 int ignore = 0;
647
648 /* During connection as an A-Device, we may see a short
649 * current spikes causing voltage drop, because of cable
650 * and peripheral capacitance combined with vbus draw.
651 * (So: less common with truly self-powered devices, where
652 * vbus doesn't act like a power supply.)
653 *
654 * Such spikes are short; usually less than ~500 usec, max
655 * of ~2 msec. That is, they're not sustained overcurrent
656 * errors, though they're reported using VBUSERROR irqs.
657 *
658 * Workarounds: (a) hardware: use self powered devices.
659 * (b) software: ignore non-repeated VBUS errors.
660 *
661 * REVISIT: do delays from lots of DEBUG_KERNEL checks
662 * make trouble here, keeping VBUS < 4.4V ?
663 */
664 switch (musb->xceiv->otg->state) {
665 case OTG_STATE_A_HOST:
666 /* recovery is dicey once we've gotten past the
667 * initial stages of enumeration, but if VBUS
668 * stayed ok at the other end of the link, and
669 * another reset is due (at least for high speed,
670 * to redo the chirp etc), it might work OK...
671 */
672 case OTG_STATE_A_WAIT_BCON:
673 case OTG_STATE_A_WAIT_VRISE:
674 if (musb->vbuserr_retry) {
675 void __iomem *mbase = musb->mregs;
676
677 musb->vbuserr_retry--;
678 ignore = 1;
679 devctl |= MUSB_DEVCTL_SESSION;
680 musb_writeb(mbase, MUSB_DEVCTL, devctl);
681 } else {
682 musb->port1_status |=
683 USB_PORT_STAT_OVERCURRENT
684 | (USB_PORT_STAT_C_OVERCURRENT << 16);
685 }
686 break;
687 default:
688 break;
689 }
690
691 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
692 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
693 usb_otg_state_string(musb->xceiv->otg->state),
694 devctl,
695 ({ char *s;
696 switch (devctl & MUSB_DEVCTL_VBUS) {
697 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
698 s = "<SessEnd"; break;
699 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
700 s = "<AValid"; break;
701 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
702 s = "<VBusValid"; break;
703 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
704 default:
705 s = "VALID"; break;
706 } s; }),
707 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
708 musb->port1_status);
709
710 /* go through A_WAIT_VFALL then start a new session */
711 if (!ignore)
712 musb_platform_set_vbus(musb, 0);
713 handled = IRQ_HANDLED;
714 }
715
716 if (int_usb & MUSB_INTR_SUSPEND) {
717 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n",
718 usb_otg_state_string(musb->xceiv->otg->state), devctl);
719 handled = IRQ_HANDLED;
720
721 switch (musb->xceiv->otg->state) {
722 case OTG_STATE_A_PERIPHERAL:
723 /* We also come here if the cable is removed, since
724 * this silicon doesn't report ID-no-longer-grounded.
725 *
726 * We depend on T(a_wait_bcon) to shut us down, and
727 * hope users don't do anything dicey during this
728 * undesired detour through A_WAIT_BCON.
729 */
730 musb_hnp_stop(musb);
731 musb_host_resume_root_hub(musb);
732 musb_root_disconnect(musb);
733 musb_platform_try_idle(musb, jiffies
734 + msecs_to_jiffies(musb->a_wait_bcon
735 ? : OTG_TIME_A_WAIT_BCON));
736
737 break;
738 case OTG_STATE_B_IDLE:
739 if (!musb->is_active)
740 break;
741 case OTG_STATE_B_PERIPHERAL:
742 musb_g_suspend(musb);
743 musb->is_active = musb->g.b_hnp_enable;
744 if (musb->is_active) {
745 musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
746 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
747 mod_timer(&musb->otg_timer, jiffies
748 + msecs_to_jiffies(
749 OTG_TIME_B_ASE0_BRST));
750 }
751 break;
752 case OTG_STATE_A_WAIT_BCON:
753 if (musb->a_wait_bcon != 0)
754 musb_platform_try_idle(musb, jiffies
755 + msecs_to_jiffies(musb->a_wait_bcon));
756 break;
757 case OTG_STATE_A_HOST:
758 musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
759 musb->is_active = musb->hcd->self.b_hnp_enable;
760 break;
761 case OTG_STATE_B_HOST:
762 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
763 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
764 break;
765 default:
766 /* "should not happen" */
767 musb->is_active = 0;
768 break;
769 }
770 }
771
772 if (int_usb & MUSB_INTR_CONNECT) {
773 struct usb_hcd *hcd = musb->hcd;
774
775 handled = IRQ_HANDLED;
776 musb->is_active = 1;
777
778 musb->ep0_stage = MUSB_EP0_START;
779
780 musb->intrtxe = musb->epmask;
781 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
782 musb->intrrxe = musb->epmask & 0xfffe;
783 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
784 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
785 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
786 |USB_PORT_STAT_HIGH_SPEED
787 |USB_PORT_STAT_ENABLE
788 );
789 musb->port1_status |= USB_PORT_STAT_CONNECTION
790 |(USB_PORT_STAT_C_CONNECTION << 16);
791
792 /* high vs full speed is just a guess until after reset */
793 if (devctl & MUSB_DEVCTL_LSDEV)
794 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
795
796 /* indicate new connection to OTG machine */
797 switch (musb->xceiv->otg->state) {
798 case OTG_STATE_B_PERIPHERAL:
799 if (int_usb & MUSB_INTR_SUSPEND) {
800 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
801 int_usb &= ~MUSB_INTR_SUSPEND;
802 goto b_host;
803 } else
804 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
805 break;
806 case OTG_STATE_B_WAIT_ACON:
807 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
808 b_host:
809 musb->xceiv->otg->state = OTG_STATE_B_HOST;
810 if (musb->hcd)
811 musb->hcd->self.is_b_host = 1;
812 del_timer(&musb->otg_timer);
813 break;
814 default:
815 if ((devctl & MUSB_DEVCTL_VBUS)
816 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
817 musb->xceiv->otg->state = OTG_STATE_A_HOST;
818 if (hcd)
819 hcd->self.is_b_host = 0;
820 }
821 break;
822 }
823
824 musb_host_poke_root_hub(musb);
825
826 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
827 usb_otg_state_string(musb->xceiv->otg->state), devctl);
828 }
829
830 if (int_usb & MUSB_INTR_DISCONNECT) {
831 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
832 usb_otg_state_string(musb->xceiv->otg->state),
833 MUSB_MODE(musb), devctl);
834 handled = IRQ_HANDLED;
835
836 switch (musb->xceiv->otg->state) {
837 case OTG_STATE_A_HOST:
838 case OTG_STATE_A_SUSPEND:
839 musb_host_resume_root_hub(musb);
840 musb_root_disconnect(musb);
841 if (musb->a_wait_bcon != 0)
842 musb_platform_try_idle(musb, jiffies
843 + msecs_to_jiffies(musb->a_wait_bcon));
844 break;
845 case OTG_STATE_B_HOST:
846 /* REVISIT this behaves for "real disconnect"
847 * cases; make sure the other transitions from
848 * from B_HOST act right too. The B_HOST code
849 * in hnp_stop() is currently not used...
850 */
851 musb_root_disconnect(musb);
852 if (musb->hcd)
853 musb->hcd->self.is_b_host = 0;
854 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
855 MUSB_DEV_MODE(musb);
856 musb_g_disconnect(musb);
857 break;
858 case OTG_STATE_A_PERIPHERAL:
859 musb_hnp_stop(musb);
860 musb_root_disconnect(musb);
861 /* FALLTHROUGH */
862 case OTG_STATE_B_WAIT_ACON:
863 /* FALLTHROUGH */
864 case OTG_STATE_B_PERIPHERAL:
865 case OTG_STATE_B_IDLE:
866 musb_g_disconnect(musb);
867 break;
868 default:
869 WARNING("unhandled DISCONNECT transition (%s)\n",
870 usb_otg_state_string(musb->xceiv->otg->state));
871 break;
872 }
873 }
874
875 /* mentor saves a bit: bus reset and babble share the same irq.
876 * only host sees babble; only peripheral sees bus reset.
877 */
878 if (int_usb & MUSB_INTR_RESET) {
879 handled = IRQ_HANDLED;
880 if (devctl & MUSB_DEVCTL_HM) {
881 /*
882 * When BABBLE happens what we can depends on which
883 * platform MUSB is running, because some platforms
884 * implemented proprietary means for 'recovering' from
885 * Babble conditions. One such platform is AM335x. In
886 * most cases, however, the only thing we can do is
887 * drop the session.
888 */
889 dev_err(musb->controller, "Babble\n");
890
891 if (is_host_active(musb))
892 musb_recover_from_babble(musb);
893 } else {
894 dev_dbg(musb->controller, "BUS RESET as %s\n",
895 usb_otg_state_string(musb->xceiv->otg->state));
896 switch (musb->xceiv->otg->state) {
897 case OTG_STATE_A_SUSPEND:
898 musb_g_reset(musb);
899 /* FALLTHROUGH */
900 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
901 /* never use invalid T(a_wait_bcon) */
902 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
903 usb_otg_state_string(musb->xceiv->otg->state),
904 TA_WAIT_BCON(musb));
905 mod_timer(&musb->otg_timer, jiffies
906 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
907 break;
908 case OTG_STATE_A_PERIPHERAL:
909 del_timer(&musb->otg_timer);
910 musb_g_reset(musb);
911 break;
912 case OTG_STATE_B_WAIT_ACON:
913 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
914 usb_otg_state_string(musb->xceiv->otg->state));
915 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
916 musb_g_reset(musb);
917 break;
918 case OTG_STATE_B_IDLE:
919 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
920 /* FALLTHROUGH */
921 case OTG_STATE_B_PERIPHERAL:
922 musb_g_reset(musb);
923 break;
924 default:
925 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
926 usb_otg_state_string(musb->xceiv->otg->state));
927 }
928 }
929 }
930
931 #if 0
932 /* REVISIT ... this would be for multiplexing periodic endpoints, or
933 * supporting transfer phasing to prevent exceeding ISO bandwidth
934 * limits of a given frame or microframe.
935 *
936 * It's not needed for peripheral side, which dedicates endpoints;
937 * though it _might_ use SOF irqs for other purposes.
938 *
939 * And it's not currently needed for host side, which also dedicates
940 * endpoints, relies on TX/RX interval registers, and isn't claimed
941 * to support ISO transfers yet.
942 */
943 if (int_usb & MUSB_INTR_SOF) {
944 void __iomem *mbase = musb->mregs;
945 struct musb_hw_ep *ep;
946 u8 epnum;
947 u16 frame;
948
949 dev_dbg(musb->controller, "START_OF_FRAME\n");
950 handled = IRQ_HANDLED;
951
952 /* start any periodic Tx transfers waiting for current frame */
953 frame = musb_readw(mbase, MUSB_FRAME);
954 ep = musb->endpoints;
955 for (epnum = 1; (epnum < musb->nr_endpoints)
956 && (musb->epmask >= (1 << epnum));
957 epnum++, ep++) {
958 /*
959 * FIXME handle framecounter wraps (12 bits)
960 * eliminate duplicated StartUrb logic
961 */
962 if (ep->dwWaitFrame >= frame) {
963 ep->dwWaitFrame = 0;
964 pr_debug("SOF --> periodic TX%s on %d\n",
965 ep->tx_channel ? " DMA" : "",
966 epnum);
967 if (!ep->tx_channel)
968 musb_h_tx_start(musb, epnum);
969 else
970 cppi_hostdma_start(musb, epnum);
971 }
972 } /* end of for loop */
973 }
974 #endif
975
976 schedule_work(&musb->irq_work);
977
978 return handled;
979 }
980
981 /*-------------------------------------------------------------------------*/
982
983 static void musb_disable_interrupts(struct musb *musb)
984 {
985 void __iomem *mbase = musb->mregs;
986 u16 temp;
987
988 /* disable interrupts */
989 musb_writeb(mbase, MUSB_INTRUSBE, 0);
990 musb->intrtxe = 0;
991 musb_writew(mbase, MUSB_INTRTXE, 0);
992 musb->intrrxe = 0;
993 musb_writew(mbase, MUSB_INTRRXE, 0);
994
995 /* flush pending interrupts */
996 temp = musb_readb(mbase, MUSB_INTRUSB);
997 temp = musb_readw(mbase, MUSB_INTRTX);
998 temp = musb_readw(mbase, MUSB_INTRRX);
999 }
1000
1001 static void musb_enable_interrupts(struct musb *musb)
1002 {
1003 void __iomem *regs = musb->mregs;
1004
1005 /* Set INT enable registers, enable interrupts */
1006 musb->intrtxe = musb->epmask;
1007 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
1008 musb->intrrxe = musb->epmask & 0xfffe;
1009 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
1010 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
1011
1012 }
1013
1014 static void musb_generic_disable(struct musb *musb)
1015 {
1016 void __iomem *mbase = musb->mregs;
1017
1018 musb_disable_interrupts(musb);
1019
1020 /* off */
1021 musb_writeb(mbase, MUSB_DEVCTL, 0);
1022 }
1023
1024 /*
1025 * Program the HDRC to start (enable interrupts, dma, etc.).
1026 */
1027 void musb_start(struct musb *musb)
1028 {
1029 void __iomem *regs = musb->mregs;
1030 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
1031 u8 power;
1032
1033 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
1034
1035 musb_enable_interrupts(musb);
1036 musb_writeb(regs, MUSB_TESTMODE, 0);
1037
1038 power = MUSB_POWER_ISOUPDATE;
1039 /*
1040 * treating UNKNOWN as unspecified maximum speed, in which case
1041 * we will default to high-speed.
1042 */
1043 if (musb->config->maximum_speed == USB_SPEED_HIGH ||
1044 musb->config->maximum_speed == USB_SPEED_UNKNOWN)
1045 power |= MUSB_POWER_HSENAB;
1046 musb_writeb(regs, MUSB_POWER, power);
1047
1048 musb->is_active = 0;
1049 devctl = musb_readb(regs, MUSB_DEVCTL);
1050 devctl &= ~MUSB_DEVCTL_SESSION;
1051
1052 /* session started after:
1053 * (a) ID-grounded irq, host mode;
1054 * (b) vbus present/connect IRQ, peripheral mode;
1055 * (c) peripheral initiates, using SRP
1056 */
1057 if (musb->port_mode != MUSB_PORT_MODE_HOST &&
1058 musb->xceiv->otg->state != OTG_STATE_A_WAIT_BCON &&
1059 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
1060 musb->is_active = 1;
1061 } else {
1062 devctl |= MUSB_DEVCTL_SESSION;
1063 }
1064
1065 musb_platform_enable(musb);
1066 musb_writeb(regs, MUSB_DEVCTL, devctl);
1067 }
1068
1069 /*
1070 * Make the HDRC stop (disable interrupts, etc.);
1071 * reversible by musb_start
1072 * called on gadget driver unregister
1073 * with controller locked, irqs blocked
1074 * acts as a NOP unless some role activated the hardware
1075 */
1076 void musb_stop(struct musb *musb)
1077 {
1078 /* stop IRQs, timers, ... */
1079 musb_platform_disable(musb);
1080 musb_generic_disable(musb);
1081 dev_dbg(musb->controller, "HDRC disabled\n");
1082
1083 /* FIXME
1084 * - mark host and/or peripheral drivers unusable/inactive
1085 * - disable DMA (and enable it in HdrcStart)
1086 * - make sure we can musb_start() after musb_stop(); with
1087 * OTG mode, gadget driver module rmmod/modprobe cycles that
1088 * - ...
1089 */
1090 musb_platform_try_idle(musb, 0);
1091 }
1092
1093 static void musb_shutdown(struct platform_device *pdev)
1094 {
1095 struct musb *musb = dev_to_musb(&pdev->dev);
1096 unsigned long flags;
1097
1098 pm_runtime_get_sync(musb->controller);
1099
1100 musb_host_cleanup(musb);
1101 musb_gadget_cleanup(musb);
1102
1103 spin_lock_irqsave(&musb->lock, flags);
1104 musb_platform_disable(musb);
1105 musb_generic_disable(musb);
1106 spin_unlock_irqrestore(&musb->lock, flags);
1107
1108 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1109 musb_platform_exit(musb);
1110
1111 pm_runtime_put(musb->controller);
1112 /* FIXME power down */
1113 }
1114
1115
1116 /*-------------------------------------------------------------------------*/
1117
1118 /*
1119 * The silicon either has hard-wired endpoint configurations, or else
1120 * "dynamic fifo" sizing. The driver has support for both, though at this
1121 * writing only the dynamic sizing is very well tested. Since we switched
1122 * away from compile-time hardware parameters, we can no longer rely on
1123 * dead code elimination to leave only the relevant one in the object file.
1124 *
1125 * We don't currently use dynamic fifo setup capability to do anything
1126 * more than selecting one of a bunch of predefined configurations.
1127 */
1128 static ushort fifo_mode;
1129
1130 /* "modprobe ... fifo_mode=1" etc */
1131 module_param(fifo_mode, ushort, 0);
1132 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1133
1134 /*
1135 * tables defining fifo_mode values. define more if you like.
1136 * for host side, make sure both halves of ep1 are set up.
1137 */
1138
1139 /* mode 0 - fits in 2KB */
1140 static struct musb_fifo_cfg mode_0_cfg[] = {
1141 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1142 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1143 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1144 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1145 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1146 };
1147
1148 /* mode 1 - fits in 4KB */
1149 static struct musb_fifo_cfg mode_1_cfg[] = {
1150 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1151 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1152 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1153 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1154 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1155 };
1156
1157 /* mode 2 - fits in 4KB */
1158 static struct musb_fifo_cfg mode_2_cfg[] = {
1159 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1160 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1161 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1162 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1163 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1164 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1165 };
1166
1167 /* mode 3 - fits in 4KB */
1168 static struct musb_fifo_cfg mode_3_cfg[] = {
1169 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1170 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1171 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1172 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1173 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1174 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1175 };
1176
1177 /* mode 4 - fits in 16KB */
1178 static struct musb_fifo_cfg mode_4_cfg[] = {
1179 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1180 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1181 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1182 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1183 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1184 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1185 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1186 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1187 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1188 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1189 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1190 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1191 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1192 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1193 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1194 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1195 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1196 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1197 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1198 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1199 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1200 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1201 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1202 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1203 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1204 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1205 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1206 };
1207
1208 /* mode 5 - fits in 8KB */
1209 static struct musb_fifo_cfg mode_5_cfg[] = {
1210 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1211 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1212 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1213 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1214 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1215 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1216 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1217 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1218 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1219 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1220 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1221 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1222 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1223 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1224 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1225 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1226 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1227 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1228 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1229 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1230 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1231 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1232 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1233 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1234 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1235 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1236 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1237 };
1238
1239 /*
1240 * configure a fifo; for non-shared endpoints, this may be called
1241 * once for a tx fifo and once for an rx fifo.
1242 *
1243 * returns negative errno or offset for next fifo.
1244 */
1245 static int
1246 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1247 const struct musb_fifo_cfg *cfg, u16 offset)
1248 {
1249 void __iomem *mbase = musb->mregs;
1250 int size = 0;
1251 u16 maxpacket = cfg->maxpacket;
1252 u16 c_off = offset >> 3;
1253 u8 c_size;
1254
1255 /* expect hw_ep has already been zero-initialized */
1256
1257 size = ffs(max(maxpacket, (u16) 8)) - 1;
1258 maxpacket = 1 << size;
1259
1260 c_size = size - 3;
1261 if (cfg->mode == BUF_DOUBLE) {
1262 if ((offset + (maxpacket << 1)) >
1263 (1 << (musb->config->ram_bits + 2)))
1264 return -EMSGSIZE;
1265 c_size |= MUSB_FIFOSZ_DPB;
1266 } else {
1267 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1268 return -EMSGSIZE;
1269 }
1270
1271 /* configure the FIFO */
1272 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1273
1274 /* EP0 reserved endpoint for control, bidirectional;
1275 * EP1 reserved for bulk, two unidirectional halves.
1276 */
1277 if (hw_ep->epnum == 1)
1278 musb->bulk_ep = hw_ep;
1279 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1280 switch (cfg->style) {
1281 case FIFO_TX:
1282 musb_write_txfifosz(mbase, c_size);
1283 musb_write_txfifoadd(mbase, c_off);
1284 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1285 hw_ep->max_packet_sz_tx = maxpacket;
1286 break;
1287 case FIFO_RX:
1288 musb_write_rxfifosz(mbase, c_size);
1289 musb_write_rxfifoadd(mbase, c_off);
1290 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1291 hw_ep->max_packet_sz_rx = maxpacket;
1292 break;
1293 case FIFO_RXTX:
1294 musb_write_txfifosz(mbase, c_size);
1295 musb_write_txfifoadd(mbase, c_off);
1296 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1297 hw_ep->max_packet_sz_rx = maxpacket;
1298
1299 musb_write_rxfifosz(mbase, c_size);
1300 musb_write_rxfifoadd(mbase, c_off);
1301 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1302 hw_ep->max_packet_sz_tx = maxpacket;
1303
1304 hw_ep->is_shared_fifo = true;
1305 break;
1306 }
1307
1308 /* NOTE rx and tx endpoint irqs aren't managed separately,
1309 * which happens to be ok
1310 */
1311 musb->epmask |= (1 << hw_ep->epnum);
1312
1313 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1314 }
1315
1316 static struct musb_fifo_cfg ep0_cfg = {
1317 .style = FIFO_RXTX, .maxpacket = 64,
1318 };
1319
1320 static int ep_config_from_table(struct musb *musb)
1321 {
1322 const struct musb_fifo_cfg *cfg;
1323 unsigned i, n;
1324 int offset;
1325 struct musb_hw_ep *hw_ep = musb->endpoints;
1326
1327 if (musb->config->fifo_cfg) {
1328 cfg = musb->config->fifo_cfg;
1329 n = musb->config->fifo_cfg_size;
1330 goto done;
1331 }
1332
1333 switch (fifo_mode) {
1334 default:
1335 fifo_mode = 0;
1336 /* FALLTHROUGH */
1337 case 0:
1338 cfg = mode_0_cfg;
1339 n = ARRAY_SIZE(mode_0_cfg);
1340 break;
1341 case 1:
1342 cfg = mode_1_cfg;
1343 n = ARRAY_SIZE(mode_1_cfg);
1344 break;
1345 case 2:
1346 cfg = mode_2_cfg;
1347 n = ARRAY_SIZE(mode_2_cfg);
1348 break;
1349 case 3:
1350 cfg = mode_3_cfg;
1351 n = ARRAY_SIZE(mode_3_cfg);
1352 break;
1353 case 4:
1354 cfg = mode_4_cfg;
1355 n = ARRAY_SIZE(mode_4_cfg);
1356 break;
1357 case 5:
1358 cfg = mode_5_cfg;
1359 n = ARRAY_SIZE(mode_5_cfg);
1360 break;
1361 }
1362
1363 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1364 musb_driver_name, fifo_mode);
1365
1366
1367 done:
1368 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1369 /* assert(offset > 0) */
1370
1371 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1372 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1373 */
1374
1375 for (i = 0; i < n; i++) {
1376 u8 epn = cfg->hw_ep_num;
1377
1378 if (epn >= musb->config->num_eps) {
1379 pr_debug("%s: invalid ep %d\n",
1380 musb_driver_name, epn);
1381 return -EINVAL;
1382 }
1383 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1384 if (offset < 0) {
1385 pr_debug("%s: mem overrun, ep %d\n",
1386 musb_driver_name, epn);
1387 return offset;
1388 }
1389 epn++;
1390 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1391 }
1392
1393 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1394 musb_driver_name,
1395 n + 1, musb->config->num_eps * 2 - 1,
1396 offset, (1 << (musb->config->ram_bits + 2)));
1397
1398 if (!musb->bulk_ep) {
1399 pr_debug("%s: missing bulk\n", musb_driver_name);
1400 return -EINVAL;
1401 }
1402
1403 return 0;
1404 }
1405
1406
1407 /*
1408 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1409 * @param musb the controller
1410 */
1411 static int ep_config_from_hw(struct musb *musb)
1412 {
1413 u8 epnum = 0;
1414 struct musb_hw_ep *hw_ep;
1415 void __iomem *mbase = musb->mregs;
1416 int ret = 0;
1417
1418 dev_dbg(musb->controller, "<== static silicon ep config\n");
1419
1420 /* FIXME pick up ep0 maxpacket size */
1421
1422 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1423 musb_ep_select(mbase, epnum);
1424 hw_ep = musb->endpoints + epnum;
1425
1426 ret = musb_read_fifosize(musb, hw_ep, epnum);
1427 if (ret < 0)
1428 break;
1429
1430 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1431
1432 /* pick an RX/TX endpoint for bulk */
1433 if (hw_ep->max_packet_sz_tx < 512
1434 || hw_ep->max_packet_sz_rx < 512)
1435 continue;
1436
1437 /* REVISIT: this algorithm is lazy, we should at least
1438 * try to pick a double buffered endpoint.
1439 */
1440 if (musb->bulk_ep)
1441 continue;
1442 musb->bulk_ep = hw_ep;
1443 }
1444
1445 if (!musb->bulk_ep) {
1446 pr_debug("%s: missing bulk\n", musb_driver_name);
1447 return -EINVAL;
1448 }
1449
1450 return 0;
1451 }
1452
1453 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1454
1455 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1456 * configure endpoints, or take their config from silicon
1457 */
1458 static int musb_core_init(u16 musb_type, struct musb *musb)
1459 {
1460 u8 reg;
1461 char *type;
1462 char aInfo[90], aRevision[32], aDate[12];
1463 void __iomem *mbase = musb->mregs;
1464 int status = 0;
1465 int i;
1466
1467 /* log core options (read using indexed model) */
1468 reg = musb_read_configdata(mbase);
1469
1470 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1471 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1472 strcat(aInfo, ", dyn FIFOs");
1473 musb->dyn_fifo = true;
1474 }
1475 if (reg & MUSB_CONFIGDATA_MPRXE) {
1476 strcat(aInfo, ", bulk combine");
1477 musb->bulk_combine = true;
1478 }
1479 if (reg & MUSB_CONFIGDATA_MPTXE) {
1480 strcat(aInfo, ", bulk split");
1481 musb->bulk_split = true;
1482 }
1483 if (reg & MUSB_CONFIGDATA_HBRXE) {
1484 strcat(aInfo, ", HB-ISO Rx");
1485 musb->hb_iso_rx = true;
1486 }
1487 if (reg & MUSB_CONFIGDATA_HBTXE) {
1488 strcat(aInfo, ", HB-ISO Tx");
1489 musb->hb_iso_tx = true;
1490 }
1491 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1492 strcat(aInfo, ", SoftConn");
1493
1494 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1495 musb_driver_name, reg, aInfo);
1496
1497 aDate[0] = 0;
1498 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1499 musb->is_multipoint = 1;
1500 type = "M";
1501 } else {
1502 musb->is_multipoint = 0;
1503 type = "";
1504 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1505 printk(KERN_ERR
1506 "%s: kernel must blacklist external hubs\n",
1507 musb_driver_name);
1508 #endif
1509 }
1510
1511 /* log release info */
1512 musb->hwvers = musb_read_hwvers(mbase);
1513 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1514 MUSB_HWVERS_MINOR(musb->hwvers),
1515 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1516 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1517 musb_driver_name, type, aRevision, aDate);
1518
1519 /* configure ep0 */
1520 musb_configure_ep0(musb);
1521
1522 /* discover endpoint configuration */
1523 musb->nr_endpoints = 1;
1524 musb->epmask = 1;
1525
1526 if (musb->dyn_fifo)
1527 status = ep_config_from_table(musb);
1528 else
1529 status = ep_config_from_hw(musb);
1530
1531 if (status < 0)
1532 return status;
1533
1534 /* finish init, and print endpoint config */
1535 for (i = 0; i < musb->nr_endpoints; i++) {
1536 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1537
1538 hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
1539 #if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
1540 if (musb->io.quirks & MUSB_IN_TUSB) {
1541 hw_ep->fifo_async = musb->async + 0x400 +
1542 musb->io.fifo_offset(i);
1543 hw_ep->fifo_sync = musb->sync + 0x400 +
1544 musb->io.fifo_offset(i);
1545 hw_ep->fifo_sync_va =
1546 musb->sync_va + 0x400 + musb->io.fifo_offset(i);
1547
1548 if (i == 0)
1549 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1550 else
1551 hw_ep->conf = mbase + 0x400 +
1552 (((i - 1) & 0xf) << 2);
1553 }
1554 #endif
1555
1556 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
1557 hw_ep->rx_reinit = 1;
1558 hw_ep->tx_reinit = 1;
1559
1560 if (hw_ep->max_packet_sz_tx) {
1561 dev_dbg(musb->controller,
1562 "%s: hw_ep %d%s, %smax %d\n",
1563 musb_driver_name, i,
1564 hw_ep->is_shared_fifo ? "shared" : "tx",
1565 hw_ep->tx_double_buffered
1566 ? "doublebuffer, " : "",
1567 hw_ep->max_packet_sz_tx);
1568 }
1569 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1570 dev_dbg(musb->controller,
1571 "%s: hw_ep %d%s, %smax %d\n",
1572 musb_driver_name, i,
1573 "rx",
1574 hw_ep->rx_double_buffered
1575 ? "doublebuffer, " : "",
1576 hw_ep->max_packet_sz_rx);
1577 }
1578 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1579 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1580 }
1581
1582 return 0;
1583 }
1584
1585 /*-------------------------------------------------------------------------*/
1586
1587 /*
1588 * handle all the irqs defined by the HDRC core. for now we expect: other
1589 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1590 * will be assigned, and the irq will already have been acked.
1591 *
1592 * called in irq context with spinlock held, irqs blocked
1593 */
1594 irqreturn_t musb_interrupt(struct musb *musb)
1595 {
1596 irqreturn_t retval = IRQ_NONE;
1597 unsigned long status;
1598 unsigned long epnum;
1599 u8 devctl;
1600
1601 if (!musb->int_usb && !musb->int_tx && !musb->int_rx)
1602 return IRQ_NONE;
1603
1604 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1605
1606 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1607 is_host_active(musb) ? "host" : "peripheral",
1608 musb->int_usb, musb->int_tx, musb->int_rx);
1609
1610 /**
1611 * According to Mentor Graphics' documentation, flowchart on page 98,
1612 * IRQ should be handled as follows:
1613 *
1614 * . Resume IRQ
1615 * . Session Request IRQ
1616 * . VBUS Error IRQ
1617 * . Suspend IRQ
1618 * . Connect IRQ
1619 * . Disconnect IRQ
1620 * . Reset/Babble IRQ
1621 * . SOF IRQ (we're not using this one)
1622 * . Endpoint 0 IRQ
1623 * . TX Endpoints
1624 * . RX Endpoints
1625 *
1626 * We will be following that flowchart in order to avoid any problems
1627 * that might arise with internal Finite State Machine.
1628 */
1629
1630 if (musb->int_usb)
1631 retval |= musb_stage0_irq(musb, musb->int_usb, devctl);
1632
1633 if (musb->int_tx & 1) {
1634 if (is_host_active(musb))
1635 retval |= musb_h_ep0_irq(musb);
1636 else
1637 retval |= musb_g_ep0_irq(musb);
1638
1639 /* we have just handled endpoint 0 IRQ, clear it */
1640 musb->int_tx &= ~BIT(0);
1641 }
1642
1643 status = musb->int_tx;
1644
1645 for_each_set_bit(epnum, &status, 16) {
1646 retval = IRQ_HANDLED;
1647 if (is_host_active(musb))
1648 musb_host_tx(musb, epnum);
1649 else
1650 musb_g_tx(musb, epnum);
1651 }
1652
1653 status = musb->int_rx;
1654
1655 for_each_set_bit(epnum, &status, 16) {
1656 retval = IRQ_HANDLED;
1657 if (is_host_active(musb))
1658 musb_host_rx(musb, epnum);
1659 else
1660 musb_g_rx(musb, epnum);
1661 }
1662
1663 return retval;
1664 }
1665 EXPORT_SYMBOL_GPL(musb_interrupt);
1666
1667 #ifndef CONFIG_MUSB_PIO_ONLY
1668 static bool use_dma = 1;
1669
1670 /* "modprobe ... use_dma=0" etc */
1671 module_param(use_dma, bool, 0644);
1672 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1673
1674 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1675 {
1676 /* called with controller lock already held */
1677
1678 if (!epnum) {
1679 if (!is_cppi_enabled(musb)) {
1680 /* endpoint 0 */
1681 if (is_host_active(musb))
1682 musb_h_ep0_irq(musb);
1683 else
1684 musb_g_ep0_irq(musb);
1685 }
1686 } else {
1687 /* endpoints 1..15 */
1688 if (transmit) {
1689 if (is_host_active(musb))
1690 musb_host_tx(musb, epnum);
1691 else
1692 musb_g_tx(musb, epnum);
1693 } else {
1694 /* receive */
1695 if (is_host_active(musb))
1696 musb_host_rx(musb, epnum);
1697 else
1698 musb_g_rx(musb, epnum);
1699 }
1700 }
1701 }
1702 EXPORT_SYMBOL_GPL(musb_dma_completion);
1703
1704 #else
1705 #define use_dma 0
1706 #endif
1707
1708 /*-------------------------------------------------------------------------*/
1709
1710 static ssize_t
1711 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1712 {
1713 struct musb *musb = dev_to_musb(dev);
1714 unsigned long flags;
1715 int ret = -EINVAL;
1716
1717 spin_lock_irqsave(&musb->lock, flags);
1718 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
1719 spin_unlock_irqrestore(&musb->lock, flags);
1720
1721 return ret;
1722 }
1723
1724 static ssize_t
1725 musb_mode_store(struct device *dev, struct device_attribute *attr,
1726 const char *buf, size_t n)
1727 {
1728 struct musb *musb = dev_to_musb(dev);
1729 unsigned long flags;
1730 int status;
1731
1732 spin_lock_irqsave(&musb->lock, flags);
1733 if (sysfs_streq(buf, "host"))
1734 status = musb_platform_set_mode(musb, MUSB_HOST);
1735 else if (sysfs_streq(buf, "peripheral"))
1736 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1737 else if (sysfs_streq(buf, "otg"))
1738 status = musb_platform_set_mode(musb, MUSB_OTG);
1739 else
1740 status = -EINVAL;
1741 spin_unlock_irqrestore(&musb->lock, flags);
1742
1743 return (status == 0) ? n : status;
1744 }
1745 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1746
1747 static ssize_t
1748 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1749 const char *buf, size_t n)
1750 {
1751 struct musb *musb = dev_to_musb(dev);
1752 unsigned long flags;
1753 unsigned long val;
1754
1755 if (sscanf(buf, "%lu", &val) < 1) {
1756 dev_err(dev, "Invalid VBUS timeout ms value\n");
1757 return -EINVAL;
1758 }
1759
1760 spin_lock_irqsave(&musb->lock, flags);
1761 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1762 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1763 if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
1764 musb->is_active = 0;
1765 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1766 spin_unlock_irqrestore(&musb->lock, flags);
1767
1768 return n;
1769 }
1770
1771 static ssize_t
1772 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1773 {
1774 struct musb *musb = dev_to_musb(dev);
1775 unsigned long flags;
1776 unsigned long val;
1777 int vbus;
1778 u8 devctl;
1779
1780 spin_lock_irqsave(&musb->lock, flags);
1781 val = musb->a_wait_bcon;
1782 vbus = musb_platform_get_vbus_status(musb);
1783 if (vbus < 0) {
1784 /* Use default MUSB method by means of DEVCTL register */
1785 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1786 if ((devctl & MUSB_DEVCTL_VBUS)
1787 == (3 << MUSB_DEVCTL_VBUS_SHIFT))
1788 vbus = 1;
1789 else
1790 vbus = 0;
1791 }
1792 spin_unlock_irqrestore(&musb->lock, flags);
1793
1794 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1795 vbus ? "on" : "off", val);
1796 }
1797 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1798
1799 /* Gadget drivers can't know that a host is connected so they might want
1800 * to start SRP, but users can. This allows userspace to trigger SRP.
1801 */
1802 static ssize_t
1803 musb_srp_store(struct device *dev, struct device_attribute *attr,
1804 const char *buf, size_t n)
1805 {
1806 struct musb *musb = dev_to_musb(dev);
1807 unsigned short srp;
1808
1809 if (sscanf(buf, "%hu", &srp) != 1
1810 || (srp != 1)) {
1811 dev_err(dev, "SRP: Value must be 1\n");
1812 return -EINVAL;
1813 }
1814
1815 if (srp == 1)
1816 musb_g_wakeup(musb);
1817
1818 return n;
1819 }
1820 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1821
1822 static struct attribute *musb_attributes[] = {
1823 &dev_attr_mode.attr,
1824 &dev_attr_vbus.attr,
1825 &dev_attr_srp.attr,
1826 NULL
1827 };
1828
1829 static const struct attribute_group musb_attr_group = {
1830 .attrs = musb_attributes,
1831 };
1832
1833 /* Only used to provide driver mode change events */
1834 static void musb_irq_work(struct work_struct *data)
1835 {
1836 struct musb *musb = container_of(data, struct musb, irq_work);
1837
1838 if (musb->xceiv->otg->state != musb->xceiv_old_state) {
1839 musb->xceiv_old_state = musb->xceiv->otg->state;
1840 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1841 }
1842 }
1843
1844 static void musb_recover_from_babble(struct musb *musb)
1845 {
1846 int ret;
1847 u8 devctl;
1848
1849 musb_disable_interrupts(musb);
1850
1851 /*
1852 * wait at least 320 cycles of 60MHz clock. That's 5.3us, we will give
1853 * it some slack and wait for 10us.
1854 */
1855 udelay(10);
1856
1857 ret = musb_platform_recover(musb);
1858 if (ret) {
1859 musb_enable_interrupts(musb);
1860 return;
1861 }
1862
1863 /* drop session bit */
1864 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1865 devctl &= ~MUSB_DEVCTL_SESSION;
1866 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
1867
1868 /* tell usbcore about it */
1869 musb_root_disconnect(musb);
1870
1871 /*
1872 * When a babble condition occurs, the musb controller
1873 * removes the session bit and the endpoint config is lost.
1874 */
1875 if (musb->dyn_fifo)
1876 ret = ep_config_from_table(musb);
1877 else
1878 ret = ep_config_from_hw(musb);
1879
1880 /* restart session */
1881 if (ret == 0)
1882 musb_start(musb);
1883 }
1884
1885 /* --------------------------------------------------------------------------
1886 * Init support
1887 */
1888
1889 static struct musb *allocate_instance(struct device *dev,
1890 struct musb_hdrc_config *config, void __iomem *mbase)
1891 {
1892 struct musb *musb;
1893 struct musb_hw_ep *ep;
1894 int epnum;
1895 int ret;
1896
1897 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
1898 if (!musb)
1899 return NULL;
1900
1901 INIT_LIST_HEAD(&musb->control);
1902 INIT_LIST_HEAD(&musb->in_bulk);
1903 INIT_LIST_HEAD(&musb->out_bulk);
1904
1905 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1906 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1907 musb->mregs = mbase;
1908 musb->ctrl_base = mbase;
1909 musb->nIrq = -ENODEV;
1910 musb->config = config;
1911 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1912 for (epnum = 0, ep = musb->endpoints;
1913 epnum < musb->config->num_eps;
1914 epnum++, ep++) {
1915 ep->musb = musb;
1916 ep->epnum = epnum;
1917 }
1918
1919 musb->controller = dev;
1920
1921 ret = musb_host_alloc(musb);
1922 if (ret < 0)
1923 goto err_free;
1924
1925 dev_set_drvdata(dev, musb);
1926
1927 return musb;
1928
1929 err_free:
1930 return NULL;
1931 }
1932
1933 static void musb_free(struct musb *musb)
1934 {
1935 /* this has multiple entry modes. it handles fault cleanup after
1936 * probe(), where things may be partially set up, as well as rmmod
1937 * cleanup after everything's been de-activated.
1938 */
1939
1940 #ifdef CONFIG_SYSFS
1941 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1942 #endif
1943
1944 if (musb->nIrq >= 0) {
1945 if (musb->irq_wake)
1946 disable_irq_wake(musb->nIrq);
1947 free_irq(musb->nIrq, musb);
1948 }
1949
1950 musb_host_free(musb);
1951 }
1952
1953 static void musb_deassert_reset(struct work_struct *work)
1954 {
1955 struct musb *musb;
1956 unsigned long flags;
1957
1958 musb = container_of(work, struct musb, deassert_reset_work.work);
1959
1960 spin_lock_irqsave(&musb->lock, flags);
1961
1962 if (musb->port1_status & USB_PORT_STAT_RESET)
1963 musb_port_reset(musb, false);
1964
1965 spin_unlock_irqrestore(&musb->lock, flags);
1966 }
1967
1968 /*
1969 * Perform generic per-controller initialization.
1970 *
1971 * @dev: the controller (already clocked, etc)
1972 * @nIrq: IRQ number
1973 * @ctrl: virtual address of controller registers,
1974 * not yet corrected for platform-specific offsets
1975 */
1976 static int
1977 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1978 {
1979 int status;
1980 struct musb *musb;
1981 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
1982
1983 /* The driver might handle more features than the board; OK.
1984 * Fail when the board needs a feature that's not enabled.
1985 */
1986 if (!plat) {
1987 dev_dbg(dev, "no platform_data?\n");
1988 status = -ENODEV;
1989 goto fail0;
1990 }
1991
1992 /* allocate */
1993 musb = allocate_instance(dev, plat->config, ctrl);
1994 if (!musb) {
1995 status = -ENOMEM;
1996 goto fail0;
1997 }
1998
1999 spin_lock_init(&musb->lock);
2000 musb->board_set_power = plat->set_power;
2001 musb->min_power = plat->min_power;
2002 musb->ops = plat->platform_ops;
2003 musb->port_mode = plat->mode;
2004
2005 /*
2006 * Initialize the default IO functions. At least omap2430 needs
2007 * these early. We initialize the platform specific IO functions
2008 * later on.
2009 */
2010 musb_readb = musb_default_readb;
2011 musb_writeb = musb_default_writeb;
2012 musb_readw = musb_default_readw;
2013 musb_writew = musb_default_writew;
2014 musb_readl = musb_default_readl;
2015 musb_writel = musb_default_writel;
2016
2017 /* We need musb_read/write functions initialized for PM */
2018 pm_runtime_use_autosuspend(musb->controller);
2019 pm_runtime_set_autosuspend_delay(musb->controller, 200);
2020 pm_runtime_irq_safe(musb->controller);
2021 pm_runtime_enable(musb->controller);
2022
2023 /* The musb_platform_init() call:
2024 * - adjusts musb->mregs
2025 * - sets the musb->isr
2026 * - may initialize an integrated transceiver
2027 * - initializes musb->xceiv, usually by otg_get_phy()
2028 * - stops powering VBUS
2029 *
2030 * There are various transceiver configurations. Blackfin,
2031 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
2032 * external/discrete ones in various flavors (twl4030 family,
2033 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
2034 */
2035 status = musb_platform_init(musb);
2036 if (status < 0)
2037 goto fail1;
2038
2039 if (!musb->isr) {
2040 status = -ENODEV;
2041 goto fail2;
2042 }
2043
2044 if (musb->ops->quirks)
2045 musb->io.quirks = musb->ops->quirks;
2046
2047 /* Most devices use indexed offset or flat offset */
2048 if (musb->io.quirks & MUSB_INDEXED_EP) {
2049 musb->io.ep_offset = musb_indexed_ep_offset;
2050 musb->io.ep_select = musb_indexed_ep_select;
2051 } else {
2052 musb->io.ep_offset = musb_flat_ep_offset;
2053 musb->io.ep_select = musb_flat_ep_select;
2054 }
2055 /* And override them with platform specific ops if specified. */
2056 if (musb->ops->ep_offset)
2057 musb->io.ep_offset = musb->ops->ep_offset;
2058 if (musb->ops->ep_select)
2059 musb->io.ep_select = musb->ops->ep_select;
2060
2061 /* At least tusb6010 has its own offsets */
2062 if (musb->ops->ep_offset)
2063 musb->io.ep_offset = musb->ops->ep_offset;
2064 if (musb->ops->ep_select)
2065 musb->io.ep_select = musb->ops->ep_select;
2066
2067 if (musb->ops->fifo_mode)
2068 fifo_mode = musb->ops->fifo_mode;
2069 else
2070 fifo_mode = 4;
2071
2072 if (musb->ops->fifo_offset)
2073 musb->io.fifo_offset = musb->ops->fifo_offset;
2074 else
2075 musb->io.fifo_offset = musb_default_fifo_offset;
2076
2077 if (musb->ops->busctl_offset)
2078 musb->io.busctl_offset = musb->ops->busctl_offset;
2079 else
2080 musb->io.busctl_offset = musb_default_busctl_offset;
2081
2082 if (musb->ops->readb)
2083 musb_readb = musb->ops->readb;
2084 if (musb->ops->writeb)
2085 musb_writeb = musb->ops->writeb;
2086 if (musb->ops->readw)
2087 musb_readw = musb->ops->readw;
2088 if (musb->ops->writew)
2089 musb_writew = musb->ops->writew;
2090 if (musb->ops->readl)
2091 musb_readl = musb->ops->readl;
2092 if (musb->ops->writel)
2093 musb_writel = musb->ops->writel;
2094
2095 #ifndef CONFIG_MUSB_PIO_ONLY
2096 if (!musb->ops->dma_init || !musb->ops->dma_exit) {
2097 dev_err(dev, "DMA controller not set\n");
2098 goto fail2;
2099 }
2100 musb_dma_controller_create = musb->ops->dma_init;
2101 musb_dma_controller_destroy = musb->ops->dma_exit;
2102 #endif
2103
2104 if (musb->ops->read_fifo)
2105 musb->io.read_fifo = musb->ops->read_fifo;
2106 else
2107 musb->io.read_fifo = musb_default_read_fifo;
2108
2109 if (musb->ops->write_fifo)
2110 musb->io.write_fifo = musb->ops->write_fifo;
2111 else
2112 musb->io.write_fifo = musb_default_write_fifo;
2113
2114 if (!musb->xceiv->io_ops) {
2115 musb->xceiv->io_dev = musb->controller;
2116 musb->xceiv->io_priv = musb->mregs;
2117 musb->xceiv->io_ops = &musb_ulpi_access;
2118 }
2119
2120 pm_runtime_get_sync(musb->controller);
2121
2122 if (use_dma && dev->dma_mask) {
2123 musb->dma_controller =
2124 musb_dma_controller_create(musb, musb->mregs);
2125 if (IS_ERR(musb->dma_controller)) {
2126 status = PTR_ERR(musb->dma_controller);
2127 goto fail2_5;
2128 }
2129 }
2130
2131 /* be sure interrupts are disabled before connecting ISR */
2132 musb_platform_disable(musb);
2133 musb_generic_disable(musb);
2134
2135 /* Init IRQ workqueue before request_irq */
2136 INIT_WORK(&musb->irq_work, musb_irq_work);
2137 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
2138 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
2139
2140 /* setup musb parts of the core (especially endpoints) */
2141 status = musb_core_init(plat->config->multipoint
2142 ? MUSB_CONTROLLER_MHDRC
2143 : MUSB_CONTROLLER_HDRC, musb);
2144 if (status < 0)
2145 goto fail3;
2146
2147 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
2148
2149 /* attach to the IRQ */
2150 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2151 dev_err(dev, "request_irq %d failed!\n", nIrq);
2152 status = -ENODEV;
2153 goto fail3;
2154 }
2155 musb->nIrq = nIrq;
2156 /* FIXME this handles wakeup irqs wrong */
2157 if (enable_irq_wake(nIrq) == 0) {
2158 musb->irq_wake = 1;
2159 device_init_wakeup(dev, 1);
2160 } else {
2161 musb->irq_wake = 0;
2162 }
2163
2164 /* program PHY to use external vBus if required */
2165 if (plat->extvbus) {
2166 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2167 busctl |= MUSB_ULPI_USE_EXTVBUS;
2168 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2169 }
2170
2171 if (musb->xceiv->otg->default_a) {
2172 MUSB_HST_MODE(musb);
2173 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
2174 } else {
2175 MUSB_DEV_MODE(musb);
2176 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
2177 }
2178
2179 switch (musb->port_mode) {
2180 case MUSB_PORT_MODE_HOST:
2181 status = musb_host_setup(musb, plat->power);
2182 if (status < 0)
2183 goto fail3;
2184 status = musb_platform_set_mode(musb, MUSB_HOST);
2185 break;
2186 case MUSB_PORT_MODE_GADGET:
2187 status = musb_gadget_setup(musb);
2188 if (status < 0)
2189 goto fail3;
2190 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
2191 break;
2192 case MUSB_PORT_MODE_DUAL_ROLE:
2193 status = musb_host_setup(musb, plat->power);
2194 if (status < 0)
2195 goto fail3;
2196 status = musb_gadget_setup(musb);
2197 if (status) {
2198 musb_host_cleanup(musb);
2199 goto fail3;
2200 }
2201 status = musb_platform_set_mode(musb, MUSB_OTG);
2202 break;
2203 default:
2204 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2205 break;
2206 }
2207
2208 if (status < 0)
2209 goto fail3;
2210
2211 status = musb_init_debugfs(musb);
2212 if (status < 0)
2213 goto fail4;
2214
2215 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2216 if (status)
2217 goto fail5;
2218
2219 pm_runtime_put(musb->controller);
2220
2221 return 0;
2222
2223 fail5:
2224 musb_exit_debugfs(musb);
2225
2226 fail4:
2227 musb_gadget_cleanup(musb);
2228 musb_host_cleanup(musb);
2229
2230 fail3:
2231 cancel_work_sync(&musb->irq_work);
2232 cancel_delayed_work_sync(&musb->finish_resume_work);
2233 cancel_delayed_work_sync(&musb->deassert_reset_work);
2234 if (musb->dma_controller)
2235 musb_dma_controller_destroy(musb->dma_controller);
2236 fail2_5:
2237 pm_runtime_put_sync(musb->controller);
2238
2239 fail2:
2240 if (musb->irq_wake)
2241 device_init_wakeup(dev, 0);
2242 musb_platform_exit(musb);
2243
2244 fail1:
2245 pm_runtime_disable(musb->controller);
2246 dev_err(musb->controller,
2247 "musb_init_controller failed with status %d\n", status);
2248
2249 musb_free(musb);
2250
2251 fail0:
2252
2253 return status;
2254
2255 }
2256
2257 /*-------------------------------------------------------------------------*/
2258
2259 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2260 * bridge to a platform device; this driver then suffices.
2261 */
2262 static int musb_probe(struct platform_device *pdev)
2263 {
2264 struct device *dev = &pdev->dev;
2265 int irq = platform_get_irq_byname(pdev, "mc");
2266 struct resource *iomem;
2267 void __iomem *base;
2268
2269 if (irq <= 0)
2270 return -ENODEV;
2271
2272 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2273 base = devm_ioremap_resource(dev, iomem);
2274 if (IS_ERR(base))
2275 return PTR_ERR(base);
2276
2277 return musb_init_controller(dev, irq, base);
2278 }
2279
2280 static int musb_remove(struct platform_device *pdev)
2281 {
2282 struct device *dev = &pdev->dev;
2283 struct musb *musb = dev_to_musb(dev);
2284
2285 /* this gets called on rmmod.
2286 * - Host mode: host may still be active
2287 * - Peripheral mode: peripheral is deactivated (or never-activated)
2288 * - OTG mode: both roles are deactivated (or never-activated)
2289 */
2290 musb_exit_debugfs(musb);
2291 musb_shutdown(pdev);
2292
2293 if (musb->dma_controller)
2294 musb_dma_controller_destroy(musb->dma_controller);
2295
2296 cancel_work_sync(&musb->irq_work);
2297 cancel_delayed_work_sync(&musb->finish_resume_work);
2298 cancel_delayed_work_sync(&musb->deassert_reset_work);
2299 musb_free(musb);
2300 device_init_wakeup(dev, 0);
2301 return 0;
2302 }
2303
2304 #ifdef CONFIG_PM
2305
2306 static void musb_save_context(struct musb *musb)
2307 {
2308 int i;
2309 void __iomem *musb_base = musb->mregs;
2310 void __iomem *epio;
2311
2312 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2313 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2314 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2315 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2316 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2317 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2318 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2319
2320 for (i = 0; i < musb->config->num_eps; ++i) {
2321 struct musb_hw_ep *hw_ep;
2322
2323 hw_ep = &musb->endpoints[i];
2324 if (!hw_ep)
2325 continue;
2326
2327 epio = hw_ep->regs;
2328 if (!epio)
2329 continue;
2330
2331 musb_writeb(musb_base, MUSB_INDEX, i);
2332 musb->context.index_regs[i].txmaxp =
2333 musb_readw(epio, MUSB_TXMAXP);
2334 musb->context.index_regs[i].txcsr =
2335 musb_readw(epio, MUSB_TXCSR);
2336 musb->context.index_regs[i].rxmaxp =
2337 musb_readw(epio, MUSB_RXMAXP);
2338 musb->context.index_regs[i].rxcsr =
2339 musb_readw(epio, MUSB_RXCSR);
2340
2341 if (musb->dyn_fifo) {
2342 musb->context.index_regs[i].txfifoadd =
2343 musb_read_txfifoadd(musb_base);
2344 musb->context.index_regs[i].rxfifoadd =
2345 musb_read_rxfifoadd(musb_base);
2346 musb->context.index_regs[i].txfifosz =
2347 musb_read_txfifosz(musb_base);
2348 musb->context.index_regs[i].rxfifosz =
2349 musb_read_rxfifosz(musb_base);
2350 }
2351
2352 musb->context.index_regs[i].txtype =
2353 musb_readb(epio, MUSB_TXTYPE);
2354 musb->context.index_regs[i].txinterval =
2355 musb_readb(epio, MUSB_TXINTERVAL);
2356 musb->context.index_regs[i].rxtype =
2357 musb_readb(epio, MUSB_RXTYPE);
2358 musb->context.index_regs[i].rxinterval =
2359 musb_readb(epio, MUSB_RXINTERVAL);
2360
2361 musb->context.index_regs[i].txfunaddr =
2362 musb_read_txfunaddr(musb, i);
2363 musb->context.index_regs[i].txhubaddr =
2364 musb_read_txhubaddr(musb, i);
2365 musb->context.index_regs[i].txhubport =
2366 musb_read_txhubport(musb, i);
2367
2368 musb->context.index_regs[i].rxfunaddr =
2369 musb_read_rxfunaddr(musb, i);
2370 musb->context.index_regs[i].rxhubaddr =
2371 musb_read_rxhubaddr(musb, i);
2372 musb->context.index_regs[i].rxhubport =
2373 musb_read_rxhubport(musb, i);
2374 }
2375 }
2376
2377 static void musb_restore_context(struct musb *musb)
2378 {
2379 int i;
2380 void __iomem *musb_base = musb->mregs;
2381 void __iomem *epio;
2382 u8 power;
2383
2384 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2385 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2386 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2387
2388 /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2389 power = musb_readb(musb_base, MUSB_POWER);
2390 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2391 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2392 power |= musb->context.power;
2393 musb_writeb(musb_base, MUSB_POWER, power);
2394
2395 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
2396 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
2397 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2398 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2399
2400 for (i = 0; i < musb->config->num_eps; ++i) {
2401 struct musb_hw_ep *hw_ep;
2402
2403 hw_ep = &musb->endpoints[i];
2404 if (!hw_ep)
2405 continue;
2406
2407 epio = hw_ep->regs;
2408 if (!epio)
2409 continue;
2410
2411 musb_writeb(musb_base, MUSB_INDEX, i);
2412 musb_writew(epio, MUSB_TXMAXP,
2413 musb->context.index_regs[i].txmaxp);
2414 musb_writew(epio, MUSB_TXCSR,
2415 musb->context.index_regs[i].txcsr);
2416 musb_writew(epio, MUSB_RXMAXP,
2417 musb->context.index_regs[i].rxmaxp);
2418 musb_writew(epio, MUSB_RXCSR,
2419 musb->context.index_regs[i].rxcsr);
2420
2421 if (musb->dyn_fifo) {
2422 musb_write_txfifosz(musb_base,
2423 musb->context.index_regs[i].txfifosz);
2424 musb_write_rxfifosz(musb_base,
2425 musb->context.index_regs[i].rxfifosz);
2426 musb_write_txfifoadd(musb_base,
2427 musb->context.index_regs[i].txfifoadd);
2428 musb_write_rxfifoadd(musb_base,
2429 musb->context.index_regs[i].rxfifoadd);
2430 }
2431
2432 musb_writeb(epio, MUSB_TXTYPE,
2433 musb->context.index_regs[i].txtype);
2434 musb_writeb(epio, MUSB_TXINTERVAL,
2435 musb->context.index_regs[i].txinterval);
2436 musb_writeb(epio, MUSB_RXTYPE,
2437 musb->context.index_regs[i].rxtype);
2438 musb_writeb(epio, MUSB_RXINTERVAL,
2439
2440 musb->context.index_regs[i].rxinterval);
2441 musb_write_txfunaddr(musb, i,
2442 musb->context.index_regs[i].txfunaddr);
2443 musb_write_txhubaddr(musb, i,
2444 musb->context.index_regs[i].txhubaddr);
2445 musb_write_txhubport(musb, i,
2446 musb->context.index_regs[i].txhubport);
2447
2448 musb_write_rxfunaddr(musb, i,
2449 musb->context.index_regs[i].rxfunaddr);
2450 musb_write_rxhubaddr(musb, i,
2451 musb->context.index_regs[i].rxhubaddr);
2452 musb_write_rxhubport(musb, i,
2453 musb->context.index_regs[i].rxhubport);
2454 }
2455 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2456 }
2457
2458 static int musb_suspend(struct device *dev)
2459 {
2460 struct musb *musb = dev_to_musb(dev);
2461 unsigned long flags;
2462
2463 musb_platform_disable(musb);
2464 musb_generic_disable(musb);
2465
2466 spin_lock_irqsave(&musb->lock, flags);
2467
2468 if (is_peripheral_active(musb)) {
2469 /* FIXME force disconnect unless we know USB will wake
2470 * the system up quickly enough to respond ...
2471 */
2472 } else if (is_host_active(musb)) {
2473 /* we know all the children are suspended; sometimes
2474 * they will even be wakeup-enabled.
2475 */
2476 }
2477
2478 musb_save_context(musb);
2479
2480 spin_unlock_irqrestore(&musb->lock, flags);
2481 return 0;
2482 }
2483
2484 static int musb_resume(struct device *dev)
2485 {
2486 struct musb *musb = dev_to_musb(dev);
2487 u8 devctl;
2488 u8 mask;
2489
2490 /*
2491 * For static cmos like DaVinci, register values were preserved
2492 * unless for some reason the whole soc powered down or the USB
2493 * module got reset through the PSC (vs just being disabled).
2494 *
2495 * For the DSPS glue layer though, a full register restore has to
2496 * be done. As it shouldn't harm other platforms, we do it
2497 * unconditionally.
2498 */
2499
2500 musb_restore_context(musb);
2501
2502 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2503 mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
2504 if ((devctl & mask) != (musb->context.devctl & mask))
2505 musb->port1_status = 0;
2506 if (musb->need_finish_resume) {
2507 musb->need_finish_resume = 0;
2508 schedule_delayed_work(&musb->finish_resume_work,
2509 msecs_to_jiffies(USB_RESUME_TIMEOUT));
2510 }
2511
2512 /*
2513 * The USB HUB code expects the device to be in RPM_ACTIVE once it came
2514 * out of suspend
2515 */
2516 pm_runtime_disable(dev);
2517 pm_runtime_set_active(dev);
2518 pm_runtime_enable(dev);
2519
2520 musb_start(musb);
2521
2522 return 0;
2523 }
2524
2525 static int musb_runtime_suspend(struct device *dev)
2526 {
2527 struct musb *musb = dev_to_musb(dev);
2528
2529 musb_save_context(musb);
2530
2531 return 0;
2532 }
2533
2534 static int musb_runtime_resume(struct device *dev)
2535 {
2536 struct musb *musb = dev_to_musb(dev);
2537 static int first = 1;
2538
2539 /*
2540 * When pm_runtime_get_sync called for the first time in driver
2541 * init, some of the structure is still not initialized which is
2542 * used in restore function. But clock needs to be
2543 * enabled before any register access, so
2544 * pm_runtime_get_sync has to be called.
2545 * Also context restore without save does not make
2546 * any sense
2547 */
2548 if (!first)
2549 musb_restore_context(musb);
2550 first = 0;
2551
2552 if (musb->need_finish_resume) {
2553 musb->need_finish_resume = 0;
2554 schedule_delayed_work(&musb->finish_resume_work,
2555 msecs_to_jiffies(USB_RESUME_TIMEOUT));
2556 }
2557
2558 return 0;
2559 }
2560
2561 static const struct dev_pm_ops musb_dev_pm_ops = {
2562 .suspend = musb_suspend,
2563 .resume = musb_resume,
2564 .runtime_suspend = musb_runtime_suspend,
2565 .runtime_resume = musb_runtime_resume,
2566 };
2567
2568 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2569 #else
2570 #define MUSB_DEV_PM_OPS NULL
2571 #endif
2572
2573 static struct platform_driver musb_driver = {
2574 .driver = {
2575 .name = (char *)musb_driver_name,
2576 .bus = &platform_bus_type,
2577 .pm = MUSB_DEV_PM_OPS,
2578 },
2579 .probe = musb_probe,
2580 .remove = musb_remove,
2581 .shutdown = musb_shutdown,
2582 };
2583
2584 module_platform_driver(musb_driver);
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