drivers/usb/musb/musb_cppi41.c

   1 #include <linux/device.h>
   2 #include <linux/dma-mapping.h>
   3 #include <linux/dmaengine.h>
   4 #include <linux/sizes.h>
   5 #include <linux/platform_device.h>
   6 #include <linux/of.h>
   7
   8 #include "cppi_dma.h"
   9 #include "musb_core.h"
  10 #include "musb_trace.h"
  11
  12 #define RNDIS_REG(x) (0x80 + ((x - 1) * 4))
  13
  14 #define EP_MODE_AUTOREQ_NONE            0
  15 #define EP_MODE_AUTOREQ_ALL_NEOP        1
  16 #define EP_MODE_AUTOREQ_ALWAYS          3
  17
  18 #define EP_MODE_DMA_TRANSPARENT         0
  19 #define EP_MODE_DMA_RNDIS               1
  20 #define EP_MODE_DMA_GEN_RNDIS           3
  21
  22 #define USB_CTRL_TX_MODE        0x70
  23 #define USB_CTRL_RX_MODE        0x74
  24 #define USB_CTRL_AUTOREQ        0xd0
  25 #define USB_TDOWN               0xd8
  26
  27 #define MUSB_DMA_NUM_CHANNELS 15
  28
  29 #define DA8XX_USB_AUTOREQ       0x14
  30 #define DA8XX_USB_TEARDOWN      0x1c
  31
  32 struct cppi41_dma_controller {
  33         struct dma_controller controller;
  34         struct cppi41_dma_channel rx_channel[MUSB_DMA_NUM_CHANNELS];
  35         struct cppi41_dma_channel tx_channel[MUSB_DMA_NUM_CHANNELS];
  36         struct hrtimer early_tx;
  37         struct list_head early_tx_list;
  38         u32 rx_mode;
  39         u32 tx_mode;
  40         u32 auto_req;
  41
  42         u32 tdown_reg;
  43         u32 autoreq_reg;
  44 };
  45
  46 static void save_rx_toggle(struct cppi41_dma_channel *cppi41_channel)
  47 {
  48         u16 csr;
  49         u8 toggle;
  50
  51         if (cppi41_channel->is_tx)
  52                 return;
  53         if (!is_host_active(cppi41_channel->controller->controller.musb))
  54                 return;
  55
  56         csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR);
  57         toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;
  58
  59         cppi41_channel->usb_toggle = toggle;
  60 }
  61
  62 static void update_rx_toggle(struct cppi41_dma_channel *cppi41_channel)
  63 {
  64         struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
  65         struct musb *musb = hw_ep->musb;
  66         u16 csr;
  67         u8 toggle;
  68
  69         if (cppi41_channel->is_tx)
  70                 return;
  71         if (!is_host_active(musb))
  72                 return;
  73
  74         musb_ep_select(musb->mregs, hw_ep->epnum);
  75         csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
  76         toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;
  77
  78         /*
  79          * AM335x Advisory 1.0.13: Due to internal synchronisation error the
  80          * data toggle may reset from DATA1 to DATA0 during receiving data from
  81          * more than one endpoint.
  82          */
  83         if (!toggle && toggle == cppi41_channel->usb_toggle) {
  84                 csr |= MUSB_RXCSR_H_DATATOGGLE | MUSB_RXCSR_H_WR_DATATOGGLE;
  85                 musb_writew(cppi41_channel->hw_ep->regs, MUSB_RXCSR, csr);
  86                 musb_dbg(musb, "Restoring DATA1 toggle.");
  87         }
  88
  89         cppi41_channel->usb_toggle = toggle;
  90 }
  91
  92 static bool musb_is_tx_fifo_empty(struct musb_hw_ep *hw_ep)
  93 {
  94         u8              epnum = hw_ep->epnum;
  95         struct musb     *musb = hw_ep->musb;
  96         void __iomem    *epio = musb->endpoints[epnum].regs;
  97         u16             csr;
  98
  99         musb_ep_select(musb->mregs, hw_ep->epnum);
 100         csr = musb_readw(epio, MUSB_TXCSR);
 101         if (csr & MUSB_TXCSR_TXPKTRDY)
 102                 return false;
 103         return true;
 104 }
 105
 106 static void cppi41_dma_callback(void *private_data,
 107                                 const struct dmaengine_result *result);
 108
 109 static void cppi41_trans_done(struct cppi41_dma_channel *cppi41_channel)
 110 {
 111         struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
 112         struct musb *musb = hw_ep->musb;
 113         void __iomem *epio = hw_ep->regs;
 114         u16 csr;
 115
 116         if (!cppi41_channel->prog_len ||
 117             (cppi41_channel->channel.status == MUSB_DMA_STATUS_FREE)) {
 118
 119                 /* done, complete */
 120                 cppi41_channel->channel.actual_len =
 121                         cppi41_channel->transferred;
 122                 cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE;
 123                 cppi41_channel->channel.rx_packet_done = true;
 124
 125                 /*
 126                  * transmit ZLP using PIO mode for transfers which size is
 127                  * multiple of EP packet size.
 128                  */
 129                 if (cppi41_channel->tx_zlp && (cppi41_channel->transferred %
 130                                         cppi41_channel->packet_sz) == 0) {
 131                         musb_ep_select(musb->mregs, hw_ep->epnum);
 132                         csr = MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY;
 133                         musb_writew(epio, MUSB_TXCSR, csr);
 134                 }
 135
 136                 trace_musb_cppi41_done(cppi41_channel);
 137                 musb_dma_completion(musb, hw_ep->epnum, cppi41_channel->is_tx);
 138         } else {
 139                 /* next iteration, reload */
 140                 struct dma_chan *dc = cppi41_channel->dc;
 141                 struct dma_async_tx_descriptor *dma_desc;
 142                 enum dma_transfer_direction direction;
 143                 u32 remain_bytes;
 144
 145                 cppi41_channel->buf_addr += cppi41_channel->packet_sz;
 146
 147                 remain_bytes = cppi41_channel->total_len;
 148                 remain_bytes -= cppi41_channel->transferred;
 149                 remain_bytes = min(remain_bytes, cppi41_channel->packet_sz);
 150                 cppi41_channel->prog_len = remain_bytes;
 151
 152                 direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV
 153                         : DMA_DEV_TO_MEM;
 154                 dma_desc = dmaengine_prep_slave_single(dc,
 155                                 cppi41_channel->buf_addr,
 156                                 remain_bytes,
 157                                 direction,
 158                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 159                 if (WARN_ON(!dma_desc))
 160                         return;
 161
 162                 dma_desc->callback_result = cppi41_dma_callback;
 163                 dma_desc->callback_param = &cppi41_channel->channel;
 164                 cppi41_channel->cookie = dma_desc->tx_submit(dma_desc);
 165                 trace_musb_cppi41_cont(cppi41_channel);
 166                 dma_async_issue_pending(dc);
 167
 168                 if (!cppi41_channel->is_tx) {
 169                         musb_ep_select(musb->mregs, hw_ep->epnum);
 170                         csr = musb_readw(epio, MUSB_RXCSR);
 171                         csr |= MUSB_RXCSR_H_REQPKT;
 172                         musb_writew(epio, MUSB_RXCSR, csr);
 173                 }
 174         }
 175 }
 176
 177 static enum hrtimer_restart cppi41_recheck_tx_req(struct hrtimer *timer)
 178 {
 179         struct cppi41_dma_controller *controller;
 180         struct cppi41_dma_channel *cppi41_channel, *n;
 181         struct musb *musb;
 182         unsigned long flags;
 183         enum hrtimer_restart ret = HRTIMER_NORESTART;
 184
 185         controller = container_of(timer, struct cppi41_dma_controller,
 186                         early_tx);
 187         musb = controller->controller.musb;
 188
 189         spin_lock_irqsave(&musb->lock, flags);
 190         list_for_each_entry_safe(cppi41_channel, n, &controller->early_tx_list,
 191                         tx_check) {
 192                 bool empty;
 193                 struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
 194
 195                 empty = musb_is_tx_fifo_empty(hw_ep);
 196                 if (empty) {
 197                         list_del_init(&cppi41_channel->tx_check);
 198                         cppi41_trans_done(cppi41_channel);
 199                 }
 200         }
 201
 202         if (!list_empty(&controller->early_tx_list) &&
 203             !hrtimer_is_queued(&controller->early_tx)) {
 204                 ret = HRTIMER_RESTART;
 205                 hrtimer_forward_now(&controller->early_tx, 20 * NSEC_PER_USEC);
 206         }
 207
 208         spin_unlock_irqrestore(&musb->lock, flags);
 209         return ret;
 210 }
 211
 212 static void cppi41_dma_callback(void *private_data,
 213                                 const struct dmaengine_result *result)
 214 {
 215         struct dma_channel *channel = private_data;
 216         struct cppi41_dma_channel *cppi41_channel = channel->private_data;
 217         struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
 218         struct cppi41_dma_controller *controller;
 219         struct musb *musb = hw_ep->musb;
 220         unsigned long flags;
 221         struct dma_tx_state txstate;
 222         u32 transferred;
 223         int is_hs = 0;
 224         bool empty;
 225
 226         controller = cppi41_channel->controller;
 227         if (controller->controller.dma_callback)
 228                 controller->controller.dma_callback(&controller->controller);
 229
 230         if (result->result == DMA_TRANS_ABORTED)
 231                 return;
 232
 233         spin_lock_irqsave(&musb->lock, flags);
 234
 235         dmaengine_tx_status(cppi41_channel->dc, cppi41_channel->cookie,
 236                         &txstate);
 237         transferred = cppi41_channel->prog_len - txstate.residue;
 238         cppi41_channel->transferred += transferred;
 239
 240         trace_musb_cppi41_gb(cppi41_channel);
 241         update_rx_toggle(cppi41_channel);
 242
 243         if (cppi41_channel->transferred == cppi41_channel->total_len ||
 244                         transferred < cppi41_channel->packet_sz)
 245                 cppi41_channel->prog_len = 0;
 246
 247         if (cppi41_channel->is_tx) {
 248                 u8 type;
 249
 250                 if (is_host_active(musb))
 251                         type = hw_ep->out_qh->type;
 252                 else
 253                         type = hw_ep->ep_in.type;
 254
 255                 if (type == USB_ENDPOINT_XFER_ISOC)
 256                         /*
 257                          * Don't use the early-TX-interrupt workaround below
 258                          * for Isoch transfter. Since Isoch are periodic
 259                          * transfer, by the time the next transfer is
 260                          * scheduled, the current one should be done already.
 261                          *
 262                          * This avoids audio playback underrun issue.
 263                          */
 264                         empty = true;
 265                 else
 266                         empty = musb_is_tx_fifo_empty(hw_ep);
 267         }
 268
 269         if (!cppi41_channel->is_tx || empty) {
 270                 cppi41_trans_done(cppi41_channel);
 271                 goto out;
 272         }
 273
 274         /*
 275          * On AM335x it has been observed that the TX interrupt fires
 276          * too early that means the TXFIFO is not yet empty but the DMA
 277          * engine says that it is done with the transfer. We don't
 278          * receive a FIFO empty interrupt so the only thing we can do is
 279          * to poll for the bit. On HS it usually takes 2us, on FS around
 280          * 110us - 150us depending on the transfer size.
 281          * We spin on HS (no longer than than 25us and setup a timer on
 282          * FS to check for the bit and complete the transfer.
 283          */
 284         if (is_host_active(musb)) {
 285                 if (musb->port1_status & USB_PORT_STAT_HIGH_SPEED)
 286                         is_hs = 1;
 287         } else {
 288                 if (musb->g.speed == USB_SPEED_HIGH)
 289                         is_hs = 1;
 290         }
 291         if (is_hs) {
 292                 unsigned wait = 25;
 293
 294                 do {
 295                         empty = musb_is_tx_fifo_empty(hw_ep);
 296                         if (empty) {
 297                                 cppi41_trans_done(cppi41_channel);
 298                                 goto out;
 299                         }
 300                         wait--;
 301                         if (!wait)
 302                                 break;
 303                         cpu_relax();
 304                 } while (1);
 305         }
 306         list_add_tail(&cppi41_channel->tx_check,
 307                         &controller->early_tx_list);
 308         if (!hrtimer_is_queued(&controller->early_tx)) {
 309                 unsigned long usecs = cppi41_channel->total_len / 10;
 310
 311                 hrtimer_start_range_ns(&controller->early_tx,
 312                                        usecs * NSEC_PER_USEC,
 313                                        20 * NSEC_PER_USEC,
 314                                        HRTIMER_MODE_REL);
 315         }
 316
 317 out:
 318         spin_unlock_irqrestore(&musb->lock, flags);
 319 }
 320
 321 static u32 update_ep_mode(unsigned ep, unsigned mode, u32 old)
 322 {
 323         unsigned shift;
 324
 325         shift = (ep - 1) * 2;
 326         old &= ~(3 << shift);
 327         old |= mode << shift;
 328         return old;
 329 }
 330
 331 static void cppi41_set_dma_mode(struct cppi41_dma_channel *cppi41_channel,
 332                 unsigned mode)
 333 {
 334         struct cppi41_dma_controller *controller = cppi41_channel->controller;
 335         struct musb *musb = controller->controller.musb;
 336         u32 port;
 337         u32 new_mode;
 338         u32 old_mode;
 339
 340         if (cppi41_channel->is_tx)
 341                 old_mode = controller->tx_mode;
 342         else
 343                 old_mode = controller->rx_mode;
 344         port = cppi41_channel->port_num;
 345         new_mode = update_ep_mode(port, mode, old_mode);
 346
 347         if (new_mode == old_mode)
 348                 return;
 349         if (cppi41_channel->is_tx) {
 350                 controller->tx_mode = new_mode;
 351                 musb_writel(musb->ctrl_base, USB_CTRL_TX_MODE, new_mode);
 352         } else {
 353                 controller->rx_mode = new_mode;
 354                 musb_writel(musb->ctrl_base, USB_CTRL_RX_MODE, new_mode);
 355         }
 356 }
 357
 358 static void cppi41_set_autoreq_mode(struct cppi41_dma_channel *cppi41_channel,
 359                 unsigned mode)
 360 {
 361         struct cppi41_dma_controller *controller = cppi41_channel->controller;
 362         u32 port;
 363         u32 new_mode;
 364         u32 old_mode;
 365
 366         old_mode = controller->auto_req;
 367         port = cppi41_channel->port_num;
 368         new_mode = update_ep_mode(port, mode, old_mode);
 369
 370         if (new_mode == old_mode)
 371                 return;
 372         controller->auto_req = new_mode;
 373         musb_writel(controller->controller.musb->ctrl_base,
 374                     controller->autoreq_reg, new_mode);
 375 }
 376
 377 static bool cppi41_configure_channel(struct dma_channel *channel,
 378                                 u16 packet_sz, u8 mode,
 379                                 dma_addr_t dma_addr, u32 len)
 380 {
 381         struct cppi41_dma_channel *cppi41_channel = channel->private_data;
 382         struct dma_chan *dc = cppi41_channel->dc;
 383         struct dma_async_tx_descriptor *dma_desc;
 384         enum dma_transfer_direction direction;
 385         struct musb *musb = cppi41_channel->controller->controller.musb;
 386         unsigned use_gen_rndis = 0;
 387
 388         cppi41_channel->buf_addr = dma_addr;
 389         cppi41_channel->total_len = len;
 390         cppi41_channel->transferred = 0;
 391         cppi41_channel->packet_sz = packet_sz;
 392         cppi41_channel->tx_zlp = (cppi41_channel->is_tx && mode) ? 1 : 0;
 393
 394         /*
 395          * Due to AM335x' Advisory 1.0.13 we are not allowed to transfer more
 396          * than max packet size at a time.
 397          */
 398         if (cppi41_channel->is_tx)
 399                 use_gen_rndis = 1;
 400
 401         if (use_gen_rndis) {
 402                 /* RNDIS mode */
 403                 if (len > packet_sz) {
 404                         musb_writel(musb->ctrl_base,
 405                                 RNDIS_REG(cppi41_channel->port_num), len);
 406                         /* gen rndis */
 407                         cppi41_set_dma_mode(cppi41_channel,
 408                                         EP_MODE_DMA_GEN_RNDIS);
 409
 410                         /* auto req */
 411                         cppi41_set_autoreq_mode(cppi41_channel,
 412                                         EP_MODE_AUTOREQ_ALL_NEOP);
 413                 } else {
 414                         musb_writel(musb->ctrl_base,
 415                                         RNDIS_REG(cppi41_channel->port_num), 0);
 416                         cppi41_set_dma_mode(cppi41_channel,
 417                                         EP_MODE_DMA_TRANSPARENT);
 418                         cppi41_set_autoreq_mode(cppi41_channel,
 419                                         EP_MODE_AUTOREQ_NONE);
 420                 }
 421         } else {
 422                 /* fallback mode */
 423                 cppi41_set_dma_mode(cppi41_channel, EP_MODE_DMA_TRANSPARENT);
 424                 cppi41_set_autoreq_mode(cppi41_channel, EP_MODE_AUTOREQ_NONE);
 425                 len = min_t(u32, packet_sz, len);
 426         }
 427         cppi41_channel->prog_len = len;
 428         direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
 429         dma_desc = dmaengine_prep_slave_single(dc, dma_addr, len, direction,
 430                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 431         if (!dma_desc)
 432                 return false;
 433
 434         dma_desc->callback_result = cppi41_dma_callback;
 435         dma_desc->callback_param = channel;
 436         cppi41_channel->cookie = dma_desc->tx_submit(dma_desc);
 437         cppi41_channel->channel.rx_packet_done = false;
 438
 439         trace_musb_cppi41_config(cppi41_channel);
 440
 441         save_rx_toggle(cppi41_channel);
 442         dma_async_issue_pending(dc);
 443         return true;
 444 }
 445
 446 static struct dma_channel *cppi41_dma_channel_allocate(struct dma_controller *c,
 447                                 struct musb_hw_ep *hw_ep, u8 is_tx)
 448 {
 449         struct cppi41_dma_controller *controller = container_of(c,
 450                         struct cppi41_dma_controller, controller);
 451         struct cppi41_dma_channel *cppi41_channel = NULL;
 452         u8 ch_num = hw_ep->epnum - 1;
 453
 454         if (ch_num >= MUSB_DMA_NUM_CHANNELS)
 455                 return NULL;
 456
 457         if (is_tx)
 458                 cppi41_channel = &controller->tx_channel[ch_num];
 459         else
 460                 cppi41_channel = &controller->rx_channel[ch_num];
 461
 462         if (!cppi41_channel->dc)
 463                 return NULL;
 464
 465         if (cppi41_channel->is_allocated)
 466                 return NULL;
 467
 468         cppi41_channel->hw_ep = hw_ep;
 469         cppi41_channel->is_allocated = 1;
 470
 471         trace_musb_cppi41_alloc(cppi41_channel);
 472         return &cppi41_channel->channel;
 473 }
 474
 475 static void cppi41_dma_channel_release(struct dma_channel *channel)
 476 {
 477         struct cppi41_dma_channel *cppi41_channel = channel->private_data;
 478
 479         trace_musb_cppi41_free(cppi41_channel);
 480         if (cppi41_channel->is_allocated) {
 481                 cppi41_channel->is_allocated = 0;
 482                 channel->status = MUSB_DMA_STATUS_FREE;
 483                 channel->actual_len = 0;
 484         }
 485 }
 486
 487 static int cppi41_dma_channel_program(struct dma_channel *channel,
 488                                 u16 packet_sz, u8 mode,
 489                                 dma_addr_t dma_addr, u32 len)
 490 {
 491         int ret;
 492         struct cppi41_dma_channel *cppi41_channel = channel->private_data;
 493         int hb_mult = 0;
 494
 495         BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
 496                 channel->status == MUSB_DMA_STATUS_BUSY);
 497
 498         if (is_host_active(cppi41_channel->controller->controller.musb)) {
 499                 if (cppi41_channel->is_tx)
 500                         hb_mult = cppi41_channel->hw_ep->out_qh->hb_mult;
 501                 else
 502                         hb_mult = cppi41_channel->hw_ep->in_qh->hb_mult;
 503         }
 504
 505         channel->status = MUSB_DMA_STATUS_BUSY;
 506         channel->actual_len = 0;
 507
 508         if (hb_mult)
 509                 packet_sz = hb_mult * (packet_sz & 0x7FF);
 510
 511         ret = cppi41_configure_channel(channel, packet_sz, mode, dma_addr, len);
 512         if (!ret)
 513                 channel->status = MUSB_DMA_STATUS_FREE;
 514
 515         return ret;
 516 }
 517
 518 static int cppi41_is_compatible(struct dma_channel *channel, u16 maxpacket,
 519                 void *buf, u32 length)
 520 {
 521         struct cppi41_dma_channel *cppi41_channel = channel->private_data;
 522         struct cppi41_dma_controller *controller = cppi41_channel->controller;
 523         struct musb *musb = controller->controller.musb;
 524
 525         if (is_host_active(musb)) {
 526                 WARN_ON(1);
 527                 return 1;
 528         }
 529         if (cppi41_channel->hw_ep->ep_in.type != USB_ENDPOINT_XFER_BULK)
 530                 return 0;
 531         if (cppi41_channel->is_tx)
 532                 return 1;
 533         /* AM335x Advisory 1.0.13. No workaround for device RX mode */
 534         return 0;
 535 }
 536
 537 static int cppi41_dma_channel_abort(struct dma_channel *channel)
 538 {
 539         struct cppi41_dma_channel *cppi41_channel = channel->private_data;
 540         struct cppi41_dma_controller *controller = cppi41_channel->controller;
 541         struct musb *musb = controller->controller.musb;
 542         void __iomem *epio = cppi41_channel->hw_ep->regs;
 543         int tdbit;
 544         int ret;
 545         unsigned is_tx;
 546         u16 csr;
 547
 548         is_tx = cppi41_channel->is_tx;
 549         trace_musb_cppi41_abort(cppi41_channel);
 550
 551         if (cppi41_channel->channel.status == MUSB_DMA_STATUS_FREE)
 552                 return 0;
 553
 554         list_del_init(&cppi41_channel->tx_check);
 555         if (is_tx) {
 556                 csr = musb_readw(epio, MUSB_TXCSR);
 557                 csr &= ~MUSB_TXCSR_DMAENAB;
 558                 musb_writew(epio, MUSB_TXCSR, csr);
 559         } else {
 560                 cppi41_set_autoreq_mode(cppi41_channel, EP_MODE_AUTOREQ_NONE);
 561
 562                 /* delay to drain to cppi dma pipeline for isoch */
 563                 udelay(250);
 564
 565                 csr = musb_readw(epio, MUSB_RXCSR);
 566                 csr &= ~(MUSB_RXCSR_H_REQPKT | MUSB_RXCSR_DMAENAB);
 567                 musb_writew(epio, MUSB_RXCSR, csr);
 568
 569                 /* wait to drain cppi dma pipe line */
 570                 udelay(50);
 571
 572                 csr = musb_readw(epio, MUSB_RXCSR);
 573                 if (csr & MUSB_RXCSR_RXPKTRDY) {
 574                         csr |= MUSB_RXCSR_FLUSHFIFO;
 575                         musb_writew(epio, MUSB_RXCSR, csr);
 576                         musb_writew(epio, MUSB_RXCSR, csr);
 577                 }
 578         }
 579
 580         /* DA8xx Advisory 2.3.27: wait 250 ms before to start the teardown */
 581         if (musb->io.quirks & MUSB_DA8XX)
 582                 mdelay(250);
 583
 584         tdbit = 1 << cppi41_channel->port_num;
 585         if (is_tx)
 586                 tdbit <<= 16;
 587
 588         do {
 589                 if (is_tx)
 590                         musb_writel(musb->ctrl_base, controller->tdown_reg,
 591                                     tdbit);
 592                 ret = dmaengine_terminate_all(cppi41_channel->dc);
 593         } while (ret == -EAGAIN);
 594
 595         if (is_tx) {
 596                 musb_writel(musb->ctrl_base, controller->tdown_reg, tdbit);
 597
 598                 csr = musb_readw(epio, MUSB_TXCSR);
 599                 if (csr & MUSB_TXCSR_TXPKTRDY) {
 600                         csr |= MUSB_TXCSR_FLUSHFIFO;
 601                         musb_writew(epio, MUSB_TXCSR, csr);
 602                 }
 603         }
 604
 605         cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE;
 606         return 0;
 607 }
 608
 609 static void cppi41_release_all_dma_chans(struct cppi41_dma_controller *ctrl)
 610 {
 611         struct dma_chan *dc;
 612         int i;
 613
 614         for (i = 0; i < MUSB_DMA_NUM_CHANNELS; i++) {
 615                 dc = ctrl->tx_channel[i].dc;
 616                 if (dc)
 617                         dma_release_channel(dc);
 618                 dc = ctrl->rx_channel[i].dc;
 619                 if (dc)
 620                         dma_release_channel(dc);
 621         }
 622 }
 623
 624 static void cppi41_dma_controller_stop(struct cppi41_dma_controller *controller)
 625 {
 626         cppi41_release_all_dma_chans(controller);
 627 }
 628
 629 static int cppi41_dma_controller_start(struct cppi41_dma_controller *controller)
 630 {
 631         struct musb *musb = controller->controller.musb;
 632         struct device *dev = musb->controller;
 633         struct device_node *np = dev->parent->of_node;
 634         struct cppi41_dma_channel *cppi41_channel;
 635         int count;
 636         int i;
 637         int ret;
 638
 639         count = of_property_count_strings(np, "dma-names");
 640         if (count < 0)
 641                 return count;
 642
 643         for (i = 0; i < count; i++) {
 644                 struct dma_chan *dc;
 645                 struct dma_channel *musb_dma;
 646                 const char *str;
 647                 unsigned is_tx;
 648                 unsigned int port;
 649
 650                 ret = of_property_read_string_index(np, "dma-names", i, &str);
 651                 if (ret)
 652                         goto err;
 653                 if (strstarts(str, "tx"))
 654                         is_tx = 1;
 655                 else if (strstarts(str, "rx"))
 656                         is_tx = 0;
 657                 else {
 658                         dev_err(dev, "Wrong dmatype %s\n", str);
 659                         goto err;
 660                 }
 661                 ret = kstrtouint(str + 2, 0, &port);
 662                 if (ret)
 663                         goto err;
 664
 665                 ret = -EINVAL;
 666                 if (port > MUSB_DMA_NUM_CHANNELS || !port)
 667                         goto err;
 668                 if (is_tx)
 669                         cppi41_channel = &controller->tx_channel[port - 1];
 670                 else
 671                         cppi41_channel = &controller->rx_channel[port - 1];
 672
 673                 cppi41_channel->controller = controller;
 674                 cppi41_channel->port_num = port;
 675                 cppi41_channel->is_tx = is_tx;
 676                 INIT_LIST_HEAD(&cppi41_channel->tx_check);
 677
 678                 musb_dma = &cppi41_channel->channel;
 679                 musb_dma->private_data = cppi41_channel;
 680                 musb_dma->status = MUSB_DMA_STATUS_FREE;
 681                 musb_dma->max_len = SZ_4M;
 682
 683                 dc = dma_request_chan(dev->parent, str);
 684                 if (IS_ERR(dc)) {
 685                         ret = PTR_ERR(dc);
 686                         if (ret != -EPROBE_DEFER)
 687                                 dev_err(dev, "Failed to request %s: %d.\n",
 688                                         str, ret);
 689                         goto err;
 690                 }
 691
 692                 cppi41_channel->dc = dc;
 693         }
 694         return 0;
 695 err:
 696         cppi41_release_all_dma_chans(controller);
 697         return ret;
 698 }
 699
 700 void cppi41_dma_controller_destroy(struct dma_controller *c)
 701 {
 702         struct cppi41_dma_controller *controller = container_of(c,
 703                         struct cppi41_dma_controller, controller);
 704
 705         hrtimer_cancel(&controller->early_tx);
 706         cppi41_dma_controller_stop(controller);
 707         kfree(controller);
 708 }
 709 EXPORT_SYMBOL_GPL(cppi41_dma_controller_destroy);
 710
 711 struct dma_controller *
 712 cppi41_dma_controller_create(struct musb *musb, void __iomem *base)
 713 {
 714         struct cppi41_dma_controller *controller;
 715         int ret = 0;
 716
 717         if (!musb->controller->parent->of_node) {
 718                 dev_err(musb->controller, "Need DT for the DMA engine.\n");
 719                 return NULL;
 720         }
 721
 722         controller = kzalloc(sizeof(*controller), GFP_KERNEL);
 723         if (!controller)
 724                 goto kzalloc_fail;
 725
 726         hrtimer_init(&controller->early_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
 727         controller->early_tx.function = cppi41_recheck_tx_req;
 728         INIT_LIST_HEAD(&controller->early_tx_list);
 729
 730         controller->controller.channel_alloc = cppi41_dma_channel_allocate;
 731         controller->controller.channel_release = cppi41_dma_channel_release;
 732         controller->controller.channel_program = cppi41_dma_channel_program;
 733         controller->controller.channel_abort = cppi41_dma_channel_abort;
 734         controller->controller.is_compatible = cppi41_is_compatible;
 735         controller->controller.musb = musb;
 736
 737         if (musb->io.quirks & MUSB_DA8XX) {
 738                 controller->tdown_reg = DA8XX_USB_TEARDOWN;
 739                 controller->autoreq_reg = DA8XX_USB_AUTOREQ;
 740         } else {
 741                 controller->tdown_reg = USB_TDOWN;
 742                 controller->autoreq_reg = USB_CTRL_AUTOREQ;
 743         }
 744
 745         ret = cppi41_dma_controller_start(controller);
 746         if (ret)
 747                 goto plat_get_fail;
 748         return &controller->controller;
 749
 750 plat_get_fail:
 751         kfree(controller);
 752 kzalloc_fail:
 753         if (ret == -EPROBE_DEFER)
 754                 return ERR_PTR(ret);
 755         return NULL;
 756 }
 757 EXPORT_SYMBOL_GPL(cppi41_dma_controller_create);