2 * Copyright (C) 2005-2007 by Texas Instruments
3 * Some code has been taken from tusb6010.c
4 * Copyrights for that are attributable to:
5 * Copyright (C) 2006 Nokia Corporation
6 * Tony Lindgren <tony@atomide.com>
8 * This file is part of the Inventra Controller Driver for Linux.
10 * The Inventra Controller Driver for Linux is free software; you
11 * can redistribute it and/or modify it under the terms of the GNU
12 * General Public License version 2 as published by the Free Software
15 * The Inventra Controller Driver for Linux is distributed in
16 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
17 * without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 * License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with The Inventra Controller Driver for Linux ; if not,
23 * write to the Free Software Foundation, Inc., 59 Temple Place,
24 * Suite 330, Boston, MA 02111-1307 USA
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/sched.h>
30 #include <linux/slab.h>
31 #include <linux/init.h>
32 #include <linux/list.h>
33 #include <linux/clk.h>
36 #include <asm/mach-types.h>
37 #include <mach/hardware.h>
40 #include "musb_core.h"
43 #ifdef CONFIG_ARCH_OMAP3430
44 #define get_cpu_rev() 2
47 #define MUSB_TIMEOUT_A_WAIT_BCON 1100
49 static struct timer_list musb_idle_timer
;
51 static void musb_do_idle(unsigned long _musb
)
53 struct musb
*musb
= (void *)_musb
;
55 #ifdef CONFIG_USB_MUSB_HDRC_HCD
60 spin_lock_irqsave(&musb
->lock
, flags
);
62 devctl
= musb_readb(musb
->mregs
, MUSB_DEVCTL
);
64 switch (musb
->xceiv
.state
) {
65 case OTG_STATE_A_WAIT_BCON
:
66 devctl
&= ~MUSB_DEVCTL_SESSION
;
67 musb_writeb(musb
->mregs
, MUSB_DEVCTL
, devctl
);
69 devctl
= musb_readb(musb
->mregs
, MUSB_DEVCTL
);
70 if (devctl
& MUSB_DEVCTL_BDEVICE
) {
71 musb
->xceiv
.state
= OTG_STATE_B_IDLE
;
74 musb
->xceiv
.state
= OTG_STATE_A_IDLE
;
78 #ifdef CONFIG_USB_MUSB_HDRC_HCD
79 case OTG_STATE_A_SUSPEND
:
80 /* finish RESUME signaling? */
81 if (musb
->port1_status
& MUSB_PORT_STAT_RESUME
) {
82 power
= musb_readb(musb
->mregs
, MUSB_POWER
);
83 power
&= ~MUSB_POWER_RESUME
;
84 DBG(1, "root port resume stopped, power %02x\n", power
);
85 musb_writeb(musb
->mregs
, MUSB_POWER
, power
);
87 musb
->port1_status
&= ~(USB_PORT_STAT_SUSPEND
88 | MUSB_PORT_STAT_RESUME
);
89 musb
->port1_status
|= USB_PORT_STAT_C_SUSPEND
<< 16;
90 usb_hcd_poll_rh_status(musb_to_hcd(musb
));
91 /* NOTE: it might really be A_WAIT_BCON ... */
92 musb
->xceiv
.state
= OTG_STATE_A_HOST
;
96 #ifdef CONFIG_USB_MUSB_HDRC_HCD
97 case OTG_STATE_A_HOST
:
98 devctl
= musb_readb(musb
->mregs
, MUSB_DEVCTL
);
99 if (devctl
& MUSB_DEVCTL_BDEVICE
)
100 musb
->xceiv
.state
= OTG_STATE_B_IDLE
;
102 musb
->xceiv
.state
= OTG_STATE_A_WAIT_BCON
;
107 spin_unlock_irqrestore(&musb
->lock
, flags
);
111 void musb_platform_try_idle(struct musb
*musb
, unsigned long timeout
)
113 unsigned long default_timeout
= jiffies
+ msecs_to_jiffies(3);
114 static unsigned long last_timer
;
117 timeout
= default_timeout
;
119 /* Never idle if active, or when VBUS timeout is not set as host */
120 if (musb
->is_active
|| ((musb
->a_wait_bcon
== 0)
121 && (musb
->xceiv
.state
== OTG_STATE_A_WAIT_BCON
))) {
122 DBG(4, "%s active, deleting timer\n", otg_state_string(musb
));
123 del_timer(&musb_idle_timer
);
124 last_timer
= jiffies
;
128 if (time_after(last_timer
, timeout
)) {
129 if (!timer_pending(&musb_idle_timer
))
130 last_timer
= timeout
;
132 DBG(4, "Longer idle timer already pending, ignoring\n");
136 last_timer
= timeout
;
138 DBG(4, "%s inactive, for idle timer for %lu ms\n",
139 otg_state_string(musb
),
140 (unsigned long)jiffies_to_msecs(timeout
- jiffies
));
141 mod_timer(&musb_idle_timer
, timeout
);
144 void musb_platform_enable(struct musb
*musb
)
147 void musb_platform_disable(struct musb
*musb
)
150 static void omap_vbus_power(struct musb
*musb
, int is_on
, int sleeping
)
154 static void omap_set_vbus(struct musb
*musb
, int is_on
)
157 /* HDRC controls CPEN, but beware current surges during device
158 * connect. They can trigger transient overcurrent conditions
159 * that must be ignored.
162 devctl
= musb_readb(musb
->mregs
, MUSB_DEVCTL
);
166 musb
->xceiv
.default_a
= 1;
167 musb
->xceiv
.state
= OTG_STATE_A_WAIT_VRISE
;
168 devctl
|= MUSB_DEVCTL_SESSION
;
174 /* NOTE: we're skipping A_WAIT_VFALL -> A_IDLE and
175 * jumping right to B_IDLE...
178 musb
->xceiv
.default_a
= 0;
179 musb
->xceiv
.state
= OTG_STATE_B_IDLE
;
180 devctl
&= ~MUSB_DEVCTL_SESSION
;
184 musb_writeb(musb
->mregs
, MUSB_DEVCTL
, devctl
);
186 DBG(1, "VBUS %s, devctl %02x "
187 /* otg %3x conf %08x prcm %08x */ "\n",
188 otg_state_string(musb
),
189 musb_readb(musb
->mregs
, MUSB_DEVCTL
));
191 static int omap_set_power(struct otg_transceiver
*x
, unsigned mA
)
196 static int musb_platform_resume(struct musb
*musb
);
198 int musb_platform_set_mode(struct musb
*musb
, u8 musb_mode
)
200 u8 devctl
= musb_readb(musb
->mregs
, MUSB_DEVCTL
);
202 devctl
|= MUSB_DEVCTL_SESSION
;
203 musb_writeb(musb
->mregs
, MUSB_DEVCTL
, devctl
);
206 #ifdef CONFIG_USB_MUSB_HDRC_HCD
208 otg_set_host(&musb
->xceiv
, musb
->xceiv
.host
);
211 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
212 case MUSB_PERIPHERAL
:
213 otg_set_peripheral(&musb
->xceiv
, musb
->xceiv
.gadget
);
216 #ifdef CONFIG_USB_MUSB_OTG
226 int __init
musb_platform_init(struct musb
*musb
)
230 #if defined(CONFIG_ARCH_OMAP2430)
231 omap_cfg_reg(AE5_2430_USB0HS_STP
);
234 musb_platform_resume(musb
);
236 l
= omap_readl(OTG_SYSCONFIG
);
237 l
&= ~ENABLEWAKEUP
; /* disable wakeup */
238 l
&= ~NOSTDBY
; /* remove possible nostdby */
239 l
|= SMARTSTDBY
; /* enable smart standby */
240 l
&= ~AUTOIDLE
; /* disable auto idle */
241 l
&= ~NOIDLE
; /* remove possible noidle */
242 l
|= SMARTIDLE
; /* enable smart idle */
243 l
|= AUTOIDLE
; /* enable auto idle */
244 omap_writel(l
, OTG_SYSCONFIG
);
246 l
= omap_readl(OTG_INTERFSEL
);
248 omap_writel(l
, OTG_INTERFSEL
);
250 pr_debug("HS USB OTG: revision 0x%x, sysconfig 0x%02x, "
251 "sysstatus 0x%x, intrfsel 0x%x, simenable 0x%x\n",
252 omap_readl(OTG_REVISION
), omap_readl(OTG_SYSCONFIG
),
253 omap_readl(OTG_SYSSTATUS
), omap_readl(OTG_INTERFSEL
),
254 omap_readl(OTG_SIMENABLE
));
256 omap_vbus_power(musb
, musb
->board_mode
== MUSB_HOST
, 1);
258 if (is_host_enabled(musb
))
259 musb
->board_set_vbus
= omap_set_vbus
;
260 if (is_peripheral_enabled(musb
))
261 musb
->xceiv
.set_power
= omap_set_power
;
262 musb
->a_wait_bcon
= MUSB_TIMEOUT_A_WAIT_BCON
;
264 setup_timer(&musb_idle_timer
, musb_do_idle
, (unsigned long) musb
);
269 int musb_platform_suspend(struct musb
*musb
)
277 l
= omap_readl(OTG_FORCESTDBY
);
278 l
|= ENABLEFORCE
; /* enable MSTANDBY */
279 omap_writel(l
, OTG_FORCESTDBY
);
281 l
= omap_readl(OTG_SYSCONFIG
);
282 l
|= ENABLEWAKEUP
; /* enable wakeup */
283 omap_writel(l
, OTG_SYSCONFIG
);
285 if (musb
->xceiv
.set_suspend
)
286 musb
->xceiv
.set_suspend(&musb
->xceiv
, 1);
289 musb
->set_clock(musb
->clock
, 0);
291 clk_disable(musb
->clock
);
296 static int musb_platform_resume(struct musb
*musb
)
303 if (musb
->xceiv
.set_suspend
)
304 musb
->xceiv
.set_suspend(&musb
->xceiv
, 0);
307 musb
->set_clock(musb
->clock
, 1);
309 clk_enable(musb
->clock
);
311 l
= omap_readl(OTG_SYSCONFIG
);
312 l
&= ~ENABLEWAKEUP
; /* disable wakeup */
313 omap_writel(l
, OTG_SYSCONFIG
);
315 l
= omap_readl(OTG_FORCESTDBY
);
316 l
&= ~ENABLEFORCE
; /* disable MSTANDBY */
317 omap_writel(l
, OTG_FORCESTDBY
);
323 int musb_platform_exit(struct musb
*musb
)
326 omap_vbus_power(musb
, 0 /*off*/, 1);
328 musb_platform_suspend(musb
);
330 clk_put(musb
->clock
);