]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blob - drivers/usb/musb/tusb6010.c
projects / mirror_ubuntu-jammy-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge tag 'xceiv-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi...
[mirror_ubuntu-jammy-kernel.git] / drivers / usb / musb / tusb6010.c
1 /*
2 * TUSB6010 USB 2.0 OTG Dual Role controller
3 *
4 * Copyright (C) 2006 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Notes:
12 * - Driver assumes that interface to external host (main CPU) is
13 * configured for NOR FLASH interface instead of VLYNQ serial
14 * interface.
15 */
16
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/errno.h>
20 #include <linux/err.h>
21 #include <linux/init.h>
22 #include <linux/prefetch.h>
23 #include <linux/usb.h>
24 #include <linux/irq.h>
25 #include <linux/platform_device.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/usb/nop-usb-xceiv.h>
28
29 #include "musb_core.h"
30
31 struct tusb6010_glue {
32 struct device *dev;
33 struct platform_device *musb;
34 };
35
36 static void tusb_musb_set_vbus(struct musb *musb, int is_on);
37
38 #define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf)
39 #define TUSB_REV_MINOR(reg_val) (reg_val & 0xf)
40
41 /*
42 * Checks the revision. We need to use the DMA register as 3.0 does not
43 * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
44 */
45 u8 tusb_get_revision(struct musb *musb)
46 {
47 void __iomem *tbase = musb->ctrl_base;
48 u32 die_id;
49 u8 rev;
50
51 rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
52 if (TUSB_REV_MAJOR(rev) == 3) {
53 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,
54 TUSB_DIDR1_HI));
55 if (die_id >= TUSB_DIDR1_HI_REV_31)
56 rev |= 1;
57 }
58
59 return rev;
60 }
61 EXPORT_SYMBOL_GPL(tusb_get_revision);
62
63 static int tusb_print_revision(struct musb *musb)
64 {
65 void __iomem *tbase = musb->ctrl_base;
66 u8 rev;
67
68 rev = tusb_get_revision(musb);
69
70 pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n",
71 "prcm",
72 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),
73 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),
74 "int",
75 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
76 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
77 "gpio",
78 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),
79 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),
80 "dma",
81 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
82 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
83 "dieid",
84 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),
85 "rev",
86 TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev));
87
88 return tusb_get_revision(musb);
89 }
90
91 #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \
92 | TUSB_PHY_OTG_CTRL_TESTM0)
93
94 /*
95 * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
96 * Disables power detection in PHY for the duration of idle.
97 */
98 static void tusb_wbus_quirk(struct musb *musb, int enabled)
99 {
100 void __iomem *tbase = musb->ctrl_base;
101 static u32 phy_otg_ctrl, phy_otg_ena;
102 u32 tmp;
103
104 if (enabled) {
105 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
106 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
107 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT
108 | phy_otg_ena | WBUS_QUIRK_MASK;
109 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
110 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
111 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
112 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
113 dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
114 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
115 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
116 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
117 & TUSB_PHY_OTG_CTRL_TESTM2) {
118 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl;
119 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
120 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
121 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
122 dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
123 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
124 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
125 phy_otg_ctrl = 0;
126 phy_otg_ena = 0;
127 }
128 }
129
130 /*
131 * TUSB 6010 may use a parallel bus that doesn't support byte ops;
132 * so both loading and unloading FIFOs need explicit byte counts.
133 */
134
135 static inline void
136 tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len)
137 {
138 u32 val;
139 int i;
140
141 if (len > 4) {
142 for (i = 0; i < (len >> 2); i++) {
143 memcpy(&val, buf, 4);
144 musb_writel(fifo, 0, val);
145 buf += 4;
146 }
147 len %= 4;
148 }
149 if (len > 0) {
150 /* Write the rest 1 - 3 bytes to FIFO */
151 memcpy(&val, buf, len);
152 musb_writel(fifo, 0, val);
153 }
154 }
155
156 static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
157 void __iomem *buf, u16 len)
158 {
159 u32 val;
160 int i;
161
162 if (len > 4) {
163 for (i = 0; i < (len >> 2); i++) {
164 val = musb_readl(fifo, 0);
165 memcpy(buf, &val, 4);
166 buf += 4;
167 }
168 len %= 4;
169 }
170 if (len > 0) {
171 /* Read the rest 1 - 3 bytes from FIFO */
172 val = musb_readl(fifo, 0);
173 memcpy(buf, &val, len);
174 }
175 }
176
177 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
178 {
179 struct musb *musb = hw_ep->musb;
180 void __iomem *ep_conf = hw_ep->conf;
181 void __iomem *fifo = hw_ep->fifo;
182 u8 epnum = hw_ep->epnum;
183
184 prefetch(buf);
185
186 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
187 'T', epnum, fifo, len, buf);
188
189 if (epnum)
190 musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
191 TUSB_EP_CONFIG_XFR_SIZE(len));
192 else
193 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX |
194 TUSB_EP0_CONFIG_XFR_SIZE(len));
195
196 if (likely((0x01 & (unsigned long) buf) == 0)) {
197
198 /* Best case is 32bit-aligned destination address */
199 if ((0x02 & (unsigned long) buf) == 0) {
200 if (len >= 4) {
201 writesl(fifo, buf, len >> 2);
202 buf += (len & ~0x03);
203 len &= 0x03;
204 }
205 } else {
206 if (len >= 2) {
207 u32 val;
208 int i;
209
210 /* Cannot use writesw, fifo is 32-bit */
211 for (i = 0; i < (len >> 2); i++) {
212 val = (u32)(*(u16 *)buf);
213 buf += 2;
214 val |= (*(u16 *)buf) << 16;
215 buf += 2;
216 musb_writel(fifo, 0, val);
217 }
218 len &= 0x03;
219 }
220 }
221 }
222
223 if (len > 0)
224 tusb_fifo_write_unaligned(fifo, buf, len);
225 }
226
227 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
228 {
229 struct musb *musb = hw_ep->musb;
230 void __iomem *ep_conf = hw_ep->conf;
231 void __iomem *fifo = hw_ep->fifo;
232 u8 epnum = hw_ep->epnum;
233
234 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
235 'R', epnum, fifo, len, buf);
236
237 if (epnum)
238 musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
239 TUSB_EP_CONFIG_XFR_SIZE(len));
240 else
241 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len));
242
243 if (likely((0x01 & (unsigned long) buf) == 0)) {
244
245 /* Best case is 32bit-aligned destination address */
246 if ((0x02 & (unsigned long) buf) == 0) {
247 if (len >= 4) {
248 readsl(fifo, buf, len >> 2);
249 buf += (len & ~0x03);
250 len &= 0x03;
251 }
252 } else {
253 if (len >= 2) {
254 u32 val;
255 int i;
256
257 /* Cannot use readsw, fifo is 32-bit */
258 for (i = 0; i < (len >> 2); i++) {
259 val = musb_readl(fifo, 0);
260 *(u16 *)buf = (u16)(val & 0xffff);
261 buf += 2;
262 *(u16 *)buf = (u16)(val >> 16);
263 buf += 2;
264 }
265 len &= 0x03;
266 }
267 }
268 }
269
270 if (len > 0)
271 tusb_fifo_read_unaligned(fifo, buf, len);
272 }
273
274 static struct musb *the_musb;
275
276 /* This is used by gadget drivers, and OTG transceiver logic, allowing
277 * at most mA current to be drawn from VBUS during a Default-B session
278 * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host
279 * mode), or low power Default-B sessions, something else supplies power.
280 * Caller must take care of locking.
281 */
282 static int tusb_draw_power(struct usb_phy *x, unsigned mA)
283 {
284 struct musb *musb = the_musb;
285 void __iomem *tbase = musb->ctrl_base;
286 u32 reg;
287
288 /* tps65030 seems to consume max 100mA, with maybe 60mA available
289 * (measured on one board) for things other than tps and tusb.
290 *
291 * Boards sharing the CPU clock with CLKIN will need to prevent
292 * certain idle sleep states while the USB link is active.
293 *
294 * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }.
295 * The actual current usage would be very board-specific. For now,
296 * it's simpler to just use an aggregate (also board-specific).
297 */
298 if (x->otg->default_a || mA < (musb->min_power << 1))
299 mA = 0;
300
301 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
302 if (mA) {
303 musb->is_bus_powered = 1;
304 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN;
305 } else {
306 musb->is_bus_powered = 0;
307 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
308 }
309 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
310
311 dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA);
312 return 0;
313 }
314
315 /* workaround for issue 13: change clock during chip idle
316 * (to be fixed in rev3 silicon) ... symptoms include disconnect
317 * or looping suspend/resume cycles
318 */
319 static void tusb_set_clock_source(struct musb *musb, unsigned mode)
320 {
321 void __iomem *tbase = musb->ctrl_base;
322 u32 reg;
323
324 reg = musb_readl(tbase, TUSB_PRCM_CONF);
325 reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3);
326
327 /* 0 = refclk (clkin, XI)
328 * 1 = PHY 60 MHz (internal PLL)
329 * 2 = not supported
330 * 3 = what?
331 */
332 if (mode > 0)
333 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3);
334
335 musb_writel(tbase, TUSB_PRCM_CONF, reg);
336
337 /* FIXME tusb6010_platform_retime(mode == 0); */
338 }
339
340 /*
341 * Idle TUSB6010 until next wake-up event; NOR access always wakes.
342 * Other code ensures that we idle unless we're connected _and_ the
343 * USB link is not suspended ... and tells us the relevant wakeup
344 * events. SW_EN for voltage is handled separately.
345 */
346 static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
347 {
348 void __iomem *tbase = musb->ctrl_base;
349 u32 reg;
350
351 if ((wakeup_enables & TUSB_PRCM_WBUS)
352 && (tusb_get_revision(musb) == TUSB_REV_30))
353 tusb_wbus_quirk(musb, 1);
354
355 tusb_set_clock_source(musb, 0);
356
357 wakeup_enables |= TUSB_PRCM_WNORCS;
358 musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
359
360 /* REVISIT writeup of WID implies that if WID set and ID is grounded,
361 * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared.
362 * Presumably that's mostly to save power, hence WID is immaterial ...
363 */
364
365 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
366 /* issue 4: when driving vbus, use hipower (vbus_det) comparator */
367 if (is_host_active(musb)) {
368 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
369 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
370 } else {
371 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
372 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
373 }
374 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
375 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
376
377 dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables);
378 }
379
380 /*
381 * Updates cable VBUS status. Caller must take care of locking.
382 */
383 static int tusb_musb_vbus_status(struct musb *musb)
384 {
385 void __iomem *tbase = musb->ctrl_base;
386 u32 otg_stat, prcm_mngmt;
387 int ret = 0;
388
389 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
390 prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);
391
392 /* Temporarily enable VBUS detection if it was disabled for
393 * suspend mode. Unless it's enabled otg_stat and devctl will
394 * not show correct VBUS state.
395 */
396 if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) {
397 u32 tmp = prcm_mngmt;
398 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
399 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp);
400 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
401 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt);
402 }
403
404 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID)
405 ret = 1;
406
407 return ret;
408 }
409
410 static struct timer_list musb_idle_timer;
411
412 static void musb_do_idle(unsigned long _musb)
413 {
414 struct musb *musb = (void *)_musb;
415 unsigned long flags;
416
417 spin_lock_irqsave(&musb->lock, flags);
418
419 switch (musb->xceiv->state) {
420 case OTG_STATE_A_WAIT_BCON:
421 if ((musb->a_wait_bcon != 0)
422 && (musb->idle_timeout == 0
423 || time_after(jiffies, musb->idle_timeout))) {
424 dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n",
425 otg_state_string(musb->xceiv->state));
426 }
427 /* FALLTHROUGH */
428 case OTG_STATE_A_IDLE:
429 tusb_musb_set_vbus(musb, 0);
430 default:
431 break;
432 }
433
434 if (!musb->is_active) {
435 u32 wakeups;
436
437 /* wait until khubd handles port change status */
438 if (is_host_active(musb) && (musb->port1_status >> 16))
439 goto done;
440
441 if (is_peripheral_enabled(musb) && !musb->gadget_driver) {
442 wakeups = 0;
443 } else {
444 wakeups = TUSB_PRCM_WHOSTDISCON
445 | TUSB_PRCM_WBUS
446 | TUSB_PRCM_WVBUS;
447 if (is_otg_enabled(musb))
448 wakeups |= TUSB_PRCM_WID;
449 }
450 tusb_allow_idle(musb, wakeups);
451 }
452 done:
453 spin_unlock_irqrestore(&musb->lock, flags);
454 }
455
456 /*
457 * Maybe put TUSB6010 into idle mode mode depending on USB link status,
458 * like "disconnected" or "suspended". We'll be woken out of it by
459 * connect, resume, or disconnect.
460 *
461 * Needs to be called as the last function everywhere where there is
462 * register access to TUSB6010 because of NOR flash wake-up.
463 * Caller should own controller spinlock.
464 *
465 * Delay because peripheral enables D+ pullup 3msec after SE0, and
466 * we don't want to treat that full speed J as a wakeup event.
467 * ... peripherals must draw only suspend current after 10 msec.
468 */
469 static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout)
470 {
471 unsigned long default_timeout = jiffies + msecs_to_jiffies(3);
472 static unsigned long last_timer;
473
474 if (timeout == 0)
475 timeout = default_timeout;
476
477 /* Never idle if active, or when VBUS timeout is not set as host */
478 if (musb->is_active || ((musb->a_wait_bcon == 0)
479 && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
480 dev_dbg(musb->controller, "%s active, deleting timer\n",
481 otg_state_string(musb->xceiv->state));
482 del_timer(&musb_idle_timer);
483 last_timer = jiffies;
484 return;
485 }
486
487 if (time_after(last_timer, timeout)) {
488 if (!timer_pending(&musb_idle_timer))
489 last_timer = timeout;
490 else {
491 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
492 return;
493 }
494 }
495 last_timer = timeout;
496
497 dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
498 otg_state_string(musb->xceiv->state),
499 (unsigned long)jiffies_to_msecs(timeout - jiffies));
500 mod_timer(&musb_idle_timer, timeout);
501 }
502
503 /* ticks of 60 MHz clock */
504 #define DEVCLOCK 60000000
505 #define OTG_TIMER_MS(msecs) ((msecs) \
506 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \
507 | TUSB_DEV_OTG_TIMER_ENABLE) \
508 : 0)
509
510 static void tusb_musb_set_vbus(struct musb *musb, int is_on)
511 {
512 void __iomem *tbase = musb->ctrl_base;
513 u32 conf, prcm, timer;
514 u8 devctl;
515 struct usb_otg *otg = musb->xceiv->otg;
516
517 /* HDRC controls CPEN, but beware current surges during device
518 * connect. They can trigger transient overcurrent conditions
519 * that must be ignored.
520 */
521
522 prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);
523 conf = musb_readl(tbase, TUSB_DEV_CONF);
524 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
525
526 if (is_on) {
527 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
528 otg->default_a = 1;
529 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
530 devctl |= MUSB_DEVCTL_SESSION;
531
532 conf |= TUSB_DEV_CONF_USB_HOST_MODE;
533 MUSB_HST_MODE(musb);
534 } else {
535 u32 otg_stat;
536
537 timer = 0;
538
539 /* If ID pin is grounded, we want to be a_idle */
540 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
541 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
542 switch (musb->xceiv->state) {
543 case OTG_STATE_A_WAIT_VRISE:
544 case OTG_STATE_A_WAIT_BCON:
545 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
546 break;
547 case OTG_STATE_A_WAIT_VFALL:
548 musb->xceiv->state = OTG_STATE_A_IDLE;
549 break;
550 default:
551 musb->xceiv->state = OTG_STATE_A_IDLE;
552 }
553 musb->is_active = 0;
554 otg->default_a = 1;
555 MUSB_HST_MODE(musb);
556 } else {
557 musb->is_active = 0;
558 otg->default_a = 0;
559 musb->xceiv->state = OTG_STATE_B_IDLE;
560 MUSB_DEV_MODE(musb);
561 }
562
563 devctl &= ~MUSB_DEVCTL_SESSION;
564 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE;
565 }
566 prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
567
568 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm);
569 musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer);
570 musb_writel(tbase, TUSB_DEV_CONF, conf);
571 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
572
573 dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
574 otg_state_string(musb->xceiv->state),
575 musb_readb(musb->mregs, MUSB_DEVCTL),
576 musb_readl(tbase, TUSB_DEV_OTG_STAT),
577 conf, prcm);
578 }
579
580 /*
581 * Sets the mode to OTG, peripheral or host by changing the ID detection.
582 * Caller must take care of locking.
583 *
584 * Note that if a mini-A cable is plugged in the ID line will stay down as
585 * the weak ID pull-up is not able to pull the ID up.
586 *
587 * REVISIT: It would be possible to add support for changing between host
588 * and peripheral modes in non-OTG configurations by reconfiguring hardware
589 * and then setting musb->board_mode. For now, only support OTG mode.
590 */
591 static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode)
592 {
593 void __iomem *tbase = musb->ctrl_base;
594 u32 otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf;
595
596 if (musb->board_mode != MUSB_OTG) {
597 ERR("Changing mode currently only supported in OTG mode\n");
598 return -EINVAL;
599 }
600
601 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
602 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
603 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
604 dev_conf = musb_readl(tbase, TUSB_DEV_CONF);
605
606 switch (musb_mode) {
607
608 case MUSB_HOST: /* Disable PHY ID detect, ground ID */
609 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
610 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
611 dev_conf |= TUSB_DEV_CONF_ID_SEL;
612 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID;
613 break;
614 case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */
615 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
616 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
617 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
618 break;
619 case MUSB_OTG: /* Use PHY ID detection */
620 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
621 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
622 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
623 break;
624
625 default:
626 dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode);
627 return -EINVAL;
628 }
629
630 musb_writel(tbase, TUSB_PHY_OTG_CTRL,
631 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl);
632 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE,
633 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena);
634 musb_writel(tbase, TUSB_DEV_CONF, dev_conf);
635
636 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
637 if ((musb_mode == MUSB_PERIPHERAL) &&
638 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS))
639 INFO("Cannot be peripheral with mini-A cable "
640 "otg_stat: %08x\n", otg_stat);
641
642 return 0;
643 }
644
645 static inline unsigned long
646 tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
647 {
648 u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
649 unsigned long idle_timeout = 0;
650 struct usb_otg *otg = musb->xceiv->otg;
651
652 /* ID pin */
653 if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) {
654 int default_a;
655
656 if (is_otg_enabled(musb))
657 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
658 else
659 default_a = is_host_enabled(musb);
660 dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B');
661 otg->default_a = default_a;
662 tusb_musb_set_vbus(musb, default_a);
663
664 /* Don't allow idling immediately */
665 if (default_a)
666 idle_timeout = jiffies + (HZ * 3);
667 }
668
669 /* VBUS state change */
670 if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
671
672 /* B-dev state machine: no vbus ~= disconnect */
673 if ((is_otg_enabled(musb) && !otg->default_a)
674 || !is_host_enabled(musb)) {
675 /* ? musb_root_disconnect(musb); */
676 musb->port1_status &=
677 ~(USB_PORT_STAT_CONNECTION
678 | USB_PORT_STAT_ENABLE
679 | USB_PORT_STAT_LOW_SPEED
680 | USB_PORT_STAT_HIGH_SPEED
681 | USB_PORT_STAT_TEST
682 );
683
684 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
685 dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n");
686 if (musb->xceiv->state != OTG_STATE_B_IDLE) {
687 /* INTR_DISCONNECT can hide... */
688 musb->xceiv->state = OTG_STATE_B_IDLE;
689 musb->int_usb |= MUSB_INTR_DISCONNECT;
690 }
691 musb->is_active = 0;
692 }
693 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
694 otg_state_string(musb->xceiv->state), otg_stat);
695 idle_timeout = jiffies + (1 * HZ);
696 schedule_work(&musb->irq_work);
697
698 } else /* A-dev state machine */ {
699 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
700 otg_state_string(musb->xceiv->state), otg_stat);
701
702 switch (musb->xceiv->state) {
703 case OTG_STATE_A_IDLE:
704 dev_dbg(musb->controller, "Got SRP, turning on VBUS\n");
705 musb_platform_set_vbus(musb, 1);
706
707 /* CONNECT can wake if a_wait_bcon is set */
708 if (musb->a_wait_bcon != 0)
709 musb->is_active = 0;
710 else
711 musb->is_active = 1;
712
713 /*
714 * OPT FS A TD.4.6 needs few seconds for
715 * A_WAIT_VRISE
716 */
717 idle_timeout = jiffies + (2 * HZ);
718
719 break;
720 case OTG_STATE_A_WAIT_VRISE:
721 /* ignore; A-session-valid < VBUS_VALID/2,
722 * we monitor this with the timer
723 */
724 break;
725 case OTG_STATE_A_WAIT_VFALL:
726 /* REVISIT this irq triggers during short
727 * spikes caused by enumeration ...
728 */
729 if (musb->vbuserr_retry) {
730 musb->vbuserr_retry--;
731 tusb_musb_set_vbus(musb, 1);
732 } else {
733 musb->vbuserr_retry
734 = VBUSERR_RETRY_COUNT;
735 tusb_musb_set_vbus(musb, 0);
736 }
737 break;
738 default:
739 break;
740 }
741 }
742 }
743
744 /* OTG timer expiration */
745 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
746 u8 devctl;
747
748 dev_dbg(musb->controller, "%s timer, %03x\n",
749 otg_state_string(musb->xceiv->state), otg_stat);
750
751 switch (musb->xceiv->state) {
752 case OTG_STATE_A_WAIT_VRISE:
753 /* VBUS has probably been valid for a while now,
754 * but may well have bounced out of range a bit
755 */
756 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
757 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
758 if ((devctl & MUSB_DEVCTL_VBUS)
759 != MUSB_DEVCTL_VBUS) {
760 dev_dbg(musb->controller, "devctl %02x\n", devctl);
761 break;
762 }
763 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
764 musb->is_active = 0;
765 idle_timeout = jiffies
766 + msecs_to_jiffies(musb->a_wait_bcon);
767 } else {
768 /* REVISIT report overcurrent to hub? */
769 ERR("vbus too slow, devctl %02x\n", devctl);
770 tusb_musb_set_vbus(musb, 0);
771 }
772 break;
773 case OTG_STATE_A_WAIT_BCON:
774 if (musb->a_wait_bcon != 0)
775 idle_timeout = jiffies
776 + msecs_to_jiffies(musb->a_wait_bcon);
777 break;
778 case OTG_STATE_A_SUSPEND:
779 break;
780 case OTG_STATE_B_WAIT_ACON:
781 break;
782 default:
783 break;
784 }
785 }
786 schedule_work(&musb->irq_work);
787
788 return idle_timeout;
789 }
790
791 static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
792 {
793 struct musb *musb = __hci;
794 void __iomem *tbase = musb->ctrl_base;
795 unsigned long flags, idle_timeout = 0;
796 u32 int_mask, int_src;
797
798 spin_lock_irqsave(&musb->lock, flags);
799
800 /* Mask all interrupts to allow using both edge and level GPIO irq */
801 int_mask = musb_readl(tbase, TUSB_INT_MASK);
802 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
803
804 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
805 dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src);
806
807 musb->int_usb = (u8) int_src;
808
809 /* Acknowledge wake-up source interrupts */
810 if (int_src & TUSB_INT_SRC_DEV_WAKEUP) {
811 u32 reg;
812 u32 i;
813
814 if (tusb_get_revision(musb) == TUSB_REV_30)
815 tusb_wbus_quirk(musb, 0);
816
817 /* there are issues re-locking the PLL on wakeup ... */
818
819 /* work around issue 8 */
820 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) {
821 musb_writel(tbase, TUSB_SCRATCH_PAD, 0);
822 musb_writel(tbase, TUSB_SCRATCH_PAD, i);
823 reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
824 if (reg == i)
825 break;
826 dev_dbg(musb->controller, "TUSB NOR not ready\n");
827 }
828
829 /* work around issue 13 (2nd half) */
830 tusb_set_clock_source(musb, 1);
831
832 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);
833 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg);
834 if (reg & ~TUSB_PRCM_WNORCS) {
835 musb->is_active = 1;
836 schedule_work(&musb->irq_work);
837 }
838 dev_dbg(musb->controller, "wake %sactive %02x\n",
839 musb->is_active ? "" : "in", reg);
840
841 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
842 }
843
844 if (int_src & TUSB_INT_SRC_USB_IP_CONN)
845 del_timer(&musb_idle_timer);
846
847 /* OTG state change reports (annoyingly) not issued by Mentor core */
848 if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG
849 | TUSB_INT_SRC_OTG_TIMEOUT
850 | TUSB_INT_SRC_ID_STATUS_CHNG))
851 idle_timeout = tusb_otg_ints(musb, int_src, tbase);
852
853 /* TX dma callback must be handled here, RX dma callback is
854 * handled in tusb_omap_dma_cb.
855 */
856 if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) {
857 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
858 u32 real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK);
859
860 dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
861 real_dma_src = ~real_dma_src & dma_src;
862 if (tusb_dma_omap() && real_dma_src) {
863 int tx_source = (real_dma_src & 0xffff);
864 int i;
865
866 for (i = 1; i <= 15; i++) {
867 if (tx_source & (1 << i)) {
868 dev_dbg(musb->controller, "completing ep%i %s\n", i, "tx");
869 musb_dma_completion(musb, i, 1);
870 }
871 }
872 }
873 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src);
874 }
875
876 /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */
877 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) {
878 u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);
879
880 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src);
881 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1);
882 musb->int_tx = (musb_src & 0xffff);
883 } else {
884 musb->int_rx = 0;
885 musb->int_tx = 0;
886 }
887
888 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff))
889 musb_interrupt(musb);
890
891 /* Acknowledge TUSB interrupts. Clear only non-reserved bits */
892 musb_writel(tbase, TUSB_INT_SRC_CLEAR,
893 int_src & ~TUSB_INT_MASK_RESERVED_BITS);
894
895 tusb_musb_try_idle(musb, idle_timeout);
896
897 musb_writel(tbase, TUSB_INT_MASK, int_mask);
898 spin_unlock_irqrestore(&musb->lock, flags);
899
900 return IRQ_HANDLED;
901 }
902
903 static int dma_off;
904
905 /*
906 * Enables TUSB6010. Caller must take care of locking.
907 * REVISIT:
908 * - Check what is unnecessary in MGC_HdrcStart()
909 */
910 static void tusb_musb_enable(struct musb *musb)
911 {
912 void __iomem *tbase = musb->ctrl_base;
913
914 /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF.
915 * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */
916 musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
917
918 /* Setup TUSB interrupt, disable DMA and GPIO interrupts */
919 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0);
920 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
921 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
922
923 /* Clear all subsystem interrups */
924 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
925 musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff);
926 musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff);
927
928 /* Acknowledge pending interrupt(s) */
929 musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
930
931 /* Only 0 clock cycles for minimum interrupt de-assertion time and
932 * interrupt polarity active low seems to work reliably here */
933 musb_writel(tbase, TUSB_INT_CTRL_CONF,
934 TUSB_INT_CTRL_CONF_INT_RELCYC(0));
935
936 irq_set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW);
937
938 /* maybe force into the Default-A OTG state machine */
939 if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
940 & TUSB_DEV_OTG_STAT_ID_STATUS))
941 musb_writel(tbase, TUSB_INT_SRC_SET,
942 TUSB_INT_SRC_ID_STATUS_CHNG);
943
944 if (is_dma_capable() && dma_off)
945 printk(KERN_WARNING "%s %s: dma not reactivated\n",
946 __FILE__, __func__);
947 else
948 dma_off = 1;
949 }
950
951 /*
952 * Disables TUSB6010. Caller must take care of locking.
953 */
954 static void tusb_musb_disable(struct musb *musb)
955 {
956 void __iomem *tbase = musb->ctrl_base;
957
958 /* FIXME stop DMA, IRQs, timers, ... */
959
960 /* disable all IRQs */
961 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
962 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff);
963 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
964 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
965
966 del_timer(&musb_idle_timer);
967
968 if (is_dma_capable() && !dma_off) {
969 printk(KERN_WARNING "%s %s: dma still active\n",
970 __FILE__, __func__);
971 dma_off = 1;
972 }
973 }
974
975 /*
976 * Sets up TUSB6010 CPU interface specific signals and registers
977 * Note: Settings optimized for OMAP24xx
978 */
979 static void tusb_setup_cpu_interface(struct musb *musb)
980 {
981 void __iomem *tbase = musb->ctrl_base;
982
983 /*
984 * Disable GPIO[5:0] pullups (used as output DMA requests)
985 * Don't disable GPIO[7:6] as they are needed for wake-up.
986 */
987 musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F);
988
989 /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */
990 musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
991
992 /* Turn GPIO[5:0] to DMAREQ[5:0] signals */
993 musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
994
995 /* Burst size 16x16 bits, all six DMA requests enabled, DMA request
996 * de-assertion time 2 system clocks p 62 */
997 musb_writel(tbase, TUSB_DMA_REQ_CONF,
998 TUSB_DMA_REQ_CONF_BURST_SIZE(2) |
999 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) |
1000 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
1001
1002 /* Set 0 wait count for synchronous burst access */
1003 musb_writel(tbase, TUSB_WAIT_COUNT, 1);
1004 }
1005
1006 static int tusb_musb_start(struct musb *musb)
1007 {
1008 void __iomem *tbase = musb->ctrl_base;
1009 int ret = 0;
1010 unsigned long flags;
1011 u32 reg;
1012
1013 if (musb->board_set_power)
1014 ret = musb->board_set_power(1);
1015 if (ret != 0) {
1016 printk(KERN_ERR "tusb: Cannot enable TUSB6010\n");
1017 return ret;
1018 }
1019
1020 spin_lock_irqsave(&musb->lock, flags);
1021
1022 if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=
1023 TUSB_PROD_TEST_RESET_VAL) {
1024 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n");
1025 goto err;
1026 }
1027
1028 ret = tusb_print_revision(musb);
1029 if (ret < 2) {
1030 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n",
1031 ret);
1032 goto err;
1033 }
1034
1035 /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when
1036 * NOR FLASH interface is used */
1037 musb_writel(tbase, TUSB_VLYNQ_CTRL, 8);
1038
1039 /* Select PHY free running 60MHz as a system clock */
1040 tusb_set_clock_source(musb, 1);
1041
1042 /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for
1043 * power saving, enable VBus detect and session end comparators,
1044 * enable IDpullup, enable VBus charging */
1045 musb_writel(tbase, TUSB_PRCM_MNGMT,
1046 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) |
1047 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN |
1048 TUSB_PRCM_MNGMT_OTG_SESS_END_EN |
1049 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN |
1050 TUSB_PRCM_MNGMT_OTG_ID_PULLUP);
1051 tusb_setup_cpu_interface(musb);
1052
1053 /* simplify: always sense/pullup ID pins, as if in OTG mode */
1054 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
1055 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1056 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg);
1057
1058 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
1059 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1060 musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg);
1061
1062 spin_unlock_irqrestore(&musb->lock, flags);
1063
1064 return 0;
1065
1066 err:
1067 spin_unlock_irqrestore(&musb->lock, flags);
1068
1069 if (musb->board_set_power)
1070 musb->board_set_power(0);
1071
1072 return -ENODEV;
1073 }
1074
1075 static int tusb_musb_init(struct musb *musb)
1076 {
1077 struct platform_device *pdev;
1078 struct resource *mem;
1079 void __iomem *sync = NULL;
1080 int ret;
1081
1082 usb_nop_xceiv_register();
1083 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
1084 if (IS_ERR_OR_NULL(musb->xceiv))
1085 return -ENODEV;
1086
1087 pdev = to_platform_device(musb->controller);
1088
1089 /* dma address for async dma */
1090 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1091 musb->async = mem->start;
1092
1093 /* dma address for sync dma */
1094 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1095 if (!mem) {
1096 pr_debug("no sync dma resource?\n");
1097 ret = -ENODEV;
1098 goto done;
1099 }
1100 musb->sync = mem->start;
1101
1102 sync = ioremap(mem->start, resource_size(mem));
1103 if (!sync) {
1104 pr_debug("ioremap for sync failed\n");
1105 ret = -ENOMEM;
1106 goto done;
1107 }
1108 musb->sync_va = sync;
1109
1110 /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400,
1111 * FIFOs at 0x600, TUSB at 0x800
1112 */
1113 musb->mregs += TUSB_BASE_OFFSET;
1114
1115 ret = tusb_musb_start(musb);
1116 if (ret) {
1117 printk(KERN_ERR "Could not start tusb6010 (%d)\n",
1118 ret);
1119 goto done;
1120 }
1121 musb->isr = tusb_musb_interrupt;
1122
1123 if (is_peripheral_enabled(musb)) {
1124 musb->xceiv->set_power = tusb_draw_power;
1125 the_musb = musb;
1126 }
1127
1128 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
1129
1130 done:
1131 if (ret < 0) {
1132 if (sync)
1133 iounmap(sync);
1134
1135 usb_put_phy(musb->xceiv);
1136 usb_nop_xceiv_unregister();
1137 }
1138 return ret;
1139 }
1140
1141 static int tusb_musb_exit(struct musb *musb)
1142 {
1143 del_timer_sync(&musb_idle_timer);
1144 the_musb = NULL;
1145
1146 if (musb->board_set_power)
1147 musb->board_set_power(0);
1148
1149 iounmap(musb->sync_va);
1150
1151 usb_put_phy(musb->xceiv);
1152 usb_nop_xceiv_unregister();
1153 return 0;
1154 }
1155
1156 static const struct musb_platform_ops tusb_ops = {
1157 .init = tusb_musb_init,
1158 .exit = tusb_musb_exit,
1159
1160 .enable = tusb_musb_enable,
1161 .disable = tusb_musb_disable,
1162
1163 .set_mode = tusb_musb_set_mode,
1164 .try_idle = tusb_musb_try_idle,
1165
1166 .vbus_status = tusb_musb_vbus_status,
1167 .set_vbus = tusb_musb_set_vbus,
1168 };
1169
1170 static u64 tusb_dmamask = DMA_BIT_MASK(32);
1171
1172 static int __devinit tusb_probe(struct platform_device *pdev)
1173 {
1174 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
1175 struct platform_device *musb;
1176 struct tusb6010_glue *glue;
1177
1178 int ret = -ENOMEM;
1179
1180 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
1181 if (!glue) {
1182 dev_err(&pdev->dev, "failed to allocate glue context\n");
1183 goto err0;
1184 }
1185
1186 musb = platform_device_alloc("musb-hdrc", -1);
1187 if (!musb) {
1188 dev_err(&pdev->dev, "failed to allocate musb device\n");
1189 goto err1;
1190 }
1191
1192 musb->dev.parent = &pdev->dev;
1193 musb->dev.dma_mask = &tusb_dmamask;
1194 musb->dev.coherent_dma_mask = tusb_dmamask;
1195
1196 glue->dev = &pdev->dev;
1197 glue->musb = musb;
1198
1199 pdata->platform_ops = &tusb_ops;
1200
1201 platform_set_drvdata(pdev, glue);
1202
1203 ret = platform_device_add_resources(musb, pdev->resource,
1204 pdev->num_resources);
1205 if (ret) {
1206 dev_err(&pdev->dev, "failed to add resources\n");
1207 goto err2;
1208 }
1209
1210 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
1211 if (ret) {
1212 dev_err(&pdev->dev, "failed to add platform_data\n");
1213 goto err2;
1214 }
1215
1216 ret = platform_device_add(musb);
1217 if (ret) {
1218 dev_err(&pdev->dev, "failed to register musb device\n");
1219 goto err1;
1220 }
1221
1222 return 0;
1223
1224 err2:
1225 platform_device_put(musb);
1226
1227 err1:
1228 kfree(glue);
1229
1230 err0:
1231 return ret;
1232 }
1233
1234 static int __devexit tusb_remove(struct platform_device *pdev)
1235 {
1236 struct tusb6010_glue *glue = platform_get_drvdata(pdev);
1237
1238 platform_device_del(glue->musb);
1239 platform_device_put(glue->musb);
1240 kfree(glue);
1241
1242 return 0;
1243 }
1244
1245 static struct platform_driver tusb_driver = {
1246 .probe = tusb_probe,
1247 .remove = __devexit_p(tusb_remove),
1248 .driver = {
1249 .name = "musb-tusb",
1250 },
1251 };
1252
1253 MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer");
1254 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1255 MODULE_LICENSE("GPL v2");
1256
1257 static int __init tusb_init(void)
1258 {
1259 return platform_driver_register(&tusb_driver);
1260 }
1261 module_init(tusb_init);
1262
1263 static void __exit tusb_exit(void)
1264 {
1265 platform_driver_unregister(&tusb_driver);
1266 }
1267 module_exit(tusb_exit);
Ubuntu Jammy Linux kernel mirror